From 25b3221967e7e9e71f17dd6d6ae690b941c35578 Mon Sep 17 00:00:00 2001 From: Amin Karbas Date: Sun, 11 Jun 2023 19:48:21 +0000 Subject: [PATCH] First batch of runs --- labs/LAB5/aggregate.csv | 421 -- labs/LAB5/run_all.err | 1560 -------- labs/LAB5/run_all.sh | 4 - labs/LAB5/runs/deepsjeng-sms0/PARAMS.in | 226 ++ labs/LAB5/runs/deepsjeng-sms0/PARAMS.out | 908 +++++ labs/LAB5/runs/deepsjeng-sms0/bp.stat.0.out | 752 ++++ labs/LAB5/runs/deepsjeng-sms0/core.stat.0.out | 438 +++ .../LAB5/runs/deepsjeng-sms0/fetch.stat.0.out | 248 ++ labs/LAB5/runs/deepsjeng-sms0/inst.stat.0.out | 103 + .../runs/deepsjeng-sms0/l2l1pref.stat.0.out | 140 + .../runs/deepsjeng-sms0/memory.stat.0.out | 3416 +++++++++++++++++ .../LAB5/runs/deepsjeng-sms0/power.stat.0.out | 184 + labs/LAB5/runs/deepsjeng-sms0/pref.stat.0.out | 208 + .../runs/deepsjeng-sms0/ramulator.stat.out | 150 + .../deepsjeng-sms0/run.err} | 0 labs/LAB5/runs/deepsjeng-sms0/run.out | 107 + .../runs/deepsjeng-sms0/stream.stat.0.out | 188 + labs/LAB5/runs/deepsjeng-sms1/PARAMS.in | 226 ++ labs/LAB5/runs/deepsjeng-sms1/PARAMS.out | 908 +++++ labs/LAB5/runs/deepsjeng-sms1/bp.stat.0.out | 752 ++++ labs/LAB5/runs/deepsjeng-sms1/core.stat.0.out | 438 +++ .../LAB5/runs/deepsjeng-sms1/fetch.stat.0.out | 248 ++ labs/LAB5/runs/deepsjeng-sms1/inst.stat.0.out | 103 + .../runs/deepsjeng-sms1/l2l1pref.stat.0.out | 140 + .../runs/deepsjeng-sms1/memory.stat.0.out | 3416 +++++++++++++++++ .../LAB5/runs/deepsjeng-sms1/power.stat.0.out | 184 + labs/LAB5/runs/deepsjeng-sms1/pref.stat.0.out | 208 + .../runs/deepsjeng-sms1/ramulator.stat.out | 150 + labs/LAB5/runs/deepsjeng-sms1/run.err | 0 labs/LAB5/runs/deepsjeng-sms1/run.out | 107 + .../runs/deepsjeng-sms1/stream.stat.0.out | 188 + labs/LAB5/runs/exchange2-sms0/PARAMS.in | 226 ++ labs/LAB5/runs/exchange2-sms0/PARAMS.out | 908 +++++ labs/LAB5/runs/exchange2-sms0/bp.stat.0.out | 752 ++++ labs/LAB5/runs/exchange2-sms0/core.stat.0.out | 438 +++ .../LAB5/runs/exchange2-sms0/fetch.stat.0.out | 248 ++ labs/LAB5/runs/exchange2-sms0/inst.stat.0.out | 103 + .../runs/exchange2-sms0/l2l1pref.stat.0.out | 140 + .../runs/exchange2-sms0/memory.stat.0.out | 3416 +++++++++++++++++ .../LAB5/runs/exchange2-sms0/power.stat.0.out | 184 + labs/LAB5/runs/exchange2-sms0/pref.stat.0.out | 208 + .../runs/exchange2-sms0/ramulator.stat.out | 150 + labs/LAB5/runs/exchange2-sms0/run.err | 0 labs/LAB5/runs/exchange2-sms0/run.out | 107 + .../runs/exchange2-sms0/stream.stat.0.out | 188 + labs/LAB5/runs/exchange2-sms1/PARAMS.in | 226 ++ labs/LAB5/runs/exchange2-sms1/PARAMS.out | 908 +++++ labs/LAB5/runs/exchange2-sms1/bp.stat.0.out | 752 ++++ labs/LAB5/runs/exchange2-sms1/core.stat.0.out | 438 +++ .../LAB5/runs/exchange2-sms1/fetch.stat.0.out | 248 ++ labs/LAB5/runs/exchange2-sms1/inst.stat.0.out | 103 + .../runs/exchange2-sms1/l2l1pref.stat.0.out | 140 + .../runs/exchange2-sms1/memory.stat.0.out | 3416 +++++++++++++++++ .../LAB5/runs/exchange2-sms1/power.stat.0.out | 184 + labs/LAB5/runs/exchange2-sms1/pref.stat.0.out | 208 + .../runs/exchange2-sms1/ramulator.stat.out | 150 + labs/LAB5/runs/exchange2-sms1/run.err | 0 labs/LAB5/runs/exchange2-sms1/run.out | 107 + .../runs/exchange2-sms1/stream.stat.0.out | 188 + labs/LAB5/runs/leela_s_base-sms0/PARAMS.in | 226 ++ labs/LAB5/runs/leela_s_base-sms0/PARAMS.out | 908 +++++ .../LAB5/runs/leela_s_base-sms0/bp.stat.0.out | 752 ++++ .../runs/leela_s_base-sms0/core.stat.0.out | 438 +++ .../runs/leela_s_base-sms0/fetch.stat.0.out | 248 ++ .../runs/leela_s_base-sms0/inst.stat.0.out | 103 + .../leela_s_base-sms0/l2l1pref.stat.0.out | 140 + .../runs/leela_s_base-sms0/memory.stat.0.out | 3416 +++++++++++++++++ .../runs/leela_s_base-sms0/power.stat.0.out | 184 + .../runs/leela_s_base-sms0/pref.stat.0.out | 208 + .../runs/leela_s_base-sms0/ramulator.stat.out | 150 + labs/LAB5/runs/leela_s_base-sms0/run.err | 0 labs/LAB5/runs/leela_s_base-sms0/run.out | 107 + .../runs/leela_s_base-sms0/stream.stat.0.out | 188 + labs/LAB5/runs/leela_s_base-sms1/PARAMS.in | 226 ++ labs/LAB5/runs/leela_s_base-sms1/PARAMS.out | 908 +++++ .../LAB5/runs/leela_s_base-sms1/bp.stat.0.out | 752 ++++ .../runs/leela_s_base-sms1/core.stat.0.out | 438 +++ .../runs/leela_s_base-sms1/fetch.stat.0.out | 248 ++ .../runs/leela_s_base-sms1/inst.stat.0.out | 103 + .../leela_s_base-sms1/l2l1pref.stat.0.out | 140 + .../runs/leela_s_base-sms1/memory.stat.0.out | 3416 +++++++++++++++++ .../runs/leela_s_base-sms1/power.stat.0.out | 184 + .../runs/leela_s_base-sms1/pref.stat.0.out | 208 + .../runs/leela_s_base-sms1/ramulator.stat.out | 150 + labs/LAB5/runs/leela_s_base-sms1/run.err | 0 labs/LAB5/runs/leela_s_base-sms1/run.out | 107 + .../runs/leela_s_base-sms1/stream.stat.0.out | 188 + labs/LAB5/runs/mcf_s_base-sms0/PARAMS.in | 226 ++ labs/LAB5/runs/mcf_s_base-sms0/PARAMS.out | 908 +++++ labs/LAB5/runs/mcf_s_base-sms0/bp.stat.0.out | 752 ++++ .../LAB5/runs/mcf_s_base-sms0/core.stat.0.out | 438 +++ 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.../perlbench_s_base-sms1/power.stat.0.out | 184 + .../perlbench_s_base-sms1/pref.stat.0.out | 208 + .../perlbench_s_base-sms1/ramulator.stat.out | 150 + labs/LAB5/runs/perlbench_s_base-sms1/run.err | 0 labs/LAB5/runs/perlbench_s_base-sms1/run.out | 107 + .../perlbench_s_base-sms1/stream.stat.0.out | 188 + labs/LAB5/runs/sgcc_base-sms0/PARAMS.in | 226 ++ labs/LAB5/runs/sgcc_base-sms0/PARAMS.out | 908 +++++ labs/LAB5/runs/sgcc_base-sms0/bp.stat.0.out | 752 ++++ labs/LAB5/runs/sgcc_base-sms0/core.stat.0.out | 438 +++ .../LAB5/runs/sgcc_base-sms0/fetch.stat.0.out | 248 ++ labs/LAB5/runs/sgcc_base-sms0/inst.stat.0.out | 103 + .../runs/sgcc_base-sms0/l2l1pref.stat.0.out | 140 + .../runs/sgcc_base-sms0/memory.stat.0.out | 3416 +++++++++++++++++ .../LAB5/runs/sgcc_base-sms0/power.stat.0.out | 184 + labs/LAB5/runs/sgcc_base-sms0/pref.stat.0.out | 208 + .../runs/sgcc_base-sms0/ramulator.stat.out | 150 + labs/LAB5/runs/sgcc_base-sms0/run.err | 0 labs/LAB5/runs/sgcc_base-sms0/run.out | 107 + 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+++ .../runs/specrand_i-sms0/fetch.stat.0.out | 248 ++ .../LAB5/runs/specrand_i-sms0/inst.stat.0.out | 103 + .../runs/specrand_i-sms0/l2l1pref.stat.0.out | 140 + .../runs/specrand_i-sms0/memory.stat.0.out | 3416 +++++++++++++++++ .../runs/specrand_i-sms0/power.stat.0.out | 184 + .../LAB5/runs/specrand_i-sms0/pref.stat.0.out | 208 + .../runs/specrand_i-sms0/ramulator.stat.out | 150 + labs/LAB5/runs/specrand_i-sms0/run.err | 0 labs/LAB5/runs/specrand_i-sms0/run.out | 107 + .../runs/specrand_i-sms0/stream.stat.0.out | 188 + labs/LAB5/runs/specrand_i-sms1/PARAMS.in | 226 ++ labs/LAB5/runs/specrand_i-sms1/PARAMS.out | 908 +++++ labs/LAB5/runs/specrand_i-sms1/bp.stat.0.out | 752 ++++ .../LAB5/runs/specrand_i-sms1/core.stat.0.out | 438 +++ .../runs/specrand_i-sms1/fetch.stat.0.out | 248 ++ .../LAB5/runs/specrand_i-sms1/inst.stat.0.out | 103 + .../runs/specrand_i-sms1/l2l1pref.stat.0.out | 140 + .../runs/specrand_i-sms1/memory.stat.0.out | 3416 +++++++++++++++++ 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labs/LAB5/runs/x264-sms1/PARAMS.in | 226 ++ labs/LAB5/runs/x264-sms1/PARAMS.out | 908 +++++ labs/LAB5/runs/x264-sms1/bp.stat.0.out | 752 ++++ labs/LAB5/runs/x264-sms1/core.stat.0.out | 438 +++ labs/LAB5/runs/x264-sms1/fetch.stat.0.out | 248 ++ labs/LAB5/runs/x264-sms1/inst.stat.0.out | 103 + labs/LAB5/runs/x264-sms1/l2l1pref.stat.0.out | 140 + labs/LAB5/runs/x264-sms1/memory.stat.0.out | 3416 +++++++++++++++++ labs/LAB5/runs/x264-sms1/power.stat.0.out | 184 + labs/LAB5/runs/x264-sms1/pref.stat.0.out | 208 + labs/LAB5/runs/x264-sms1/ramulator.stat.out | 150 + labs/LAB5/runs/x264-sms1/run.err | 0 labs/LAB5/runs/x264-sms1/run.out | 107 + labs/LAB5/runs/x264-sms1/stream.stat.0.out | 188 + .../LAB5/runs/xalancbmk_s_base-sms0/PARAMS.in | 226 ++ .../runs/xalancbmk_s_base-sms0/PARAMS.out | 908 +++++ .../runs/xalancbmk_s_base-sms0/bp.stat.0.out | 752 ++++ .../xalancbmk_s_base-sms0/core.stat.0.out | 438 +++ .../xalancbmk_s_base-sms0/fetch.stat.0.out | 248 ++ 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labs/LAB5/runs/xalancbmk_s_base-sms1/stream.stat.0.out diff --git a/labs/LAB5/aggregate.csv b/labs/LAB5/aggregate.csv deleted file mode 100644 index 581620f1..00000000 --- a/labs/LAB5/aggregate.csv +++ /dev/null @@ -1,421 +0,0 @@ -run,metric,val -deepsjeng-0,ipc,1.96812 -deepsjeng-0,dcache_miss,1.048% -deepsjeng-0,dcache_miss_compulsory,0.0695 -deepsjeng-0,dcache_miss_capacity,0.9183 -deepsjeng-0,dcache_miss_conflict,0.0122 -deepsjeng-0,l1_hit,89.246% -deepsjeng-0,l1_miss,10.754% -deepsjeng-1,ipc,1.96687 -deepsjeng-1,dcache_miss,1.047% -deepsjeng-1,dcache_miss_compulsory,0.0695 -deepsjeng-1,dcache_miss_capacity,0.9183 -deepsjeng-1,dcache_miss_conflict,0.0122 -deepsjeng-1,l1_hit,89.250% -deepsjeng-1,l1_miss,10.750% -deepsjeng-10,ipc,1.96998 -deepsjeng-10,dcache_miss,1.048% -deepsjeng-10,dcache_miss_compulsory,0.0694 -deepsjeng-10,dcache_miss_capacity,0.9184 -deepsjeng-10,dcache_miss_conflict,0.0122 -deepsjeng-10,l1_hit,89.252% -deepsjeng-10,l1_miss,10.748% -deepsjeng-2,ipc,1.96881 -deepsjeng-2,dcache_miss,1.048% -deepsjeng-2,dcache_miss_compulsory,0.0694 -deepsjeng-2,dcache_miss_capacity,0.9184 -deepsjeng-2,dcache_miss_conflict,0.0122 -deepsjeng-2,l1_hit,89.250% -deepsjeng-2,l1_miss,10.750% -deepsjeng-20,ipc,1.96685 -deepsjeng-20,dcache_miss,1.048% -deepsjeng-20,dcache_miss_compulsory,0.0695 -deepsjeng-20,dcache_miss_capacity,0.9183 -deepsjeng-20,dcache_miss_conflict,0.0122 -deepsjeng-20,l1_hit,89.254% -deepsjeng-20,l1_miss,10.746% -deepsjeng-5,ipc,1.96754 -deepsjeng-5,dcache_miss,1.048% -deepsjeng-5,dcache_miss_compulsory,0.0695 -deepsjeng-5,dcache_miss_capacity,0.9183 -deepsjeng-5,dcache_miss_conflict,0.0122 -deepsjeng-5,l1_hit,89.251% -deepsjeng-5,l1_miss,10.749% -exchange2-0,ipc,2.44934 -exchange2-0,dcache_miss,0.001% -exchange2-0,dcache_miss_compulsory,0.3842 -exchange2-0,dcache_miss_capacity,0.0000 -exchange2-0,dcache_miss_conflict,0.6158 -exchange2-0,l1_hit,88.557% -exchange2-0,l1_miss,11.443% -exchange2-1,ipc,2.44934 -exchange2-1,dcache_miss,0.001% -exchange2-1,dcache_miss_compulsory,0.3842 -exchange2-1,dcache_miss_capacity,0.0000 -exchange2-1,dcache_miss_conflict,0.6158 -exchange2-1,l1_hit,88.557% -exchange2-1,l1_miss,11.443% -exchange2-10,ipc,2.44934 -exchange2-10,dcache_miss,0.001% -exchange2-10,dcache_miss_compulsory,0.3842 -exchange2-10,dcache_miss_capacity,0.0000 -exchange2-10,dcache_miss_conflict,0.6158 -exchange2-10,l1_hit,88.557% -exchange2-10,l1_miss,11.443% -exchange2-2,ipc,2.44934 -exchange2-2,dcache_miss,0.001% -exchange2-2,dcache_miss_compulsory,0.3842 -exchange2-2,dcache_miss_capacity,0.0000 -exchange2-2,dcache_miss_conflict,0.6158 -exchange2-2,l1_hit,88.557% -exchange2-2,l1_miss,11.443% -exchange2-20,ipc,2.44934 -exchange2-20,dcache_miss,0.001% -exchange2-20,dcache_miss_compulsory,0.3842 -exchange2-20,dcache_miss_capacity,0.0000 -exchange2-20,dcache_miss_conflict,0.6158 -exchange2-20,l1_hit,88.557% -exchange2-20,l1_miss,11.443% -exchange2-5,ipc,2.44934 -exchange2-5,dcache_miss,0.001% -exchange2-5,dcache_miss_compulsory,0.3842 -exchange2-5,dcache_miss_capacity,0.0000 -exchange2-5,dcache_miss_conflict,0.6158 -exchange2-5,l1_hit,88.557% -exchange2-5,l1_miss,11.443% -leela_s_base-0,ipc,1.60287 -leela_s_base-0,dcache_miss,1.067% -leela_s_base-0,dcache_miss_compulsory,0.0105 -leela_s_base-0,dcache_miss_capacity,0.9114 -leela_s_base-0,dcache_miss_conflict,0.0781 -leela_s_base-0,l1_hit,98.648% -leela_s_base-0,l1_miss,1.352% -leela_s_base-1,ipc,1.60460 -leela_s_base-1,dcache_miss,1.067% -leela_s_base-1,dcache_miss_compulsory,0.0105 -leela_s_base-1,dcache_miss_capacity,0.9114 -leela_s_base-1,dcache_miss_conflict,0.0781 -leela_s_base-1,l1_hit,98.655% -leela_s_base-1,l1_miss,1.345% -leela_s_base-10,ipc,1.60474 -leela_s_base-10,dcache_miss,1.067% -leela_s_base-10,dcache_miss_compulsory,0.0105 -leela_s_base-10,dcache_miss_capacity,0.9114 -leela_s_base-10,dcache_miss_conflict,0.0781 -leela_s_base-10,l1_hit,98.663% -leela_s_base-10,l1_miss,1.337% -leela_s_base-2,ipc,1.60422 -leela_s_base-2,dcache_miss,1.067% -leela_s_base-2,dcache_miss_compulsory,0.0105 -leela_s_base-2,dcache_miss_capacity,0.9114 -leela_s_base-2,dcache_miss_conflict,0.0781 -leela_s_base-2,l1_hit,98.657% -leela_s_base-2,l1_miss,1.343% -leela_s_base-20,ipc,1.60474 -leela_s_base-20,dcache_miss,1.067% -leela_s_base-20,dcache_miss_compulsory,0.0105 -leela_s_base-20,dcache_miss_capacity,0.9114 -leela_s_base-20,dcache_miss_conflict,0.0781 -leela_s_base-20,l1_hit,98.663% -leela_s_base-20,l1_miss,1.337% -leela_s_base-5,ipc,1.60503 -leela_s_base-5,dcache_miss,1.067% -leela_s_base-5,dcache_miss_compulsory,0.0105 -leela_s_base-5,dcache_miss_capacity,0.9114 -leela_s_base-5,dcache_miss_conflict,0.0781 -leela_s_base-5,l1_hit,98.661% -leela_s_base-5,l1_miss,1.339% -mcf_s_base-0,ipc,0.82272 -mcf_s_base-0,dcache_miss,23.753% -mcf_s_base-0,dcache_miss_compulsory,0.0342 -mcf_s_base-0,dcache_miss_capacity,0.9657 -mcf_s_base-0,dcache_miss_conflict,0.0001 -mcf_s_base-0,l1_hit,70.974% -mcf_s_base-0,l1_miss,29.026% -mcf_s_base-1,ipc,0.82554 -mcf_s_base-1,dcache_miss,23.763% -mcf_s_base-1,dcache_miss_compulsory,0.0341 -mcf_s_base-1,dcache_miss_capacity,0.9658 -mcf_s_base-1,dcache_miss_conflict,0.0001 -mcf_s_base-1,l1_hit,71.297% -mcf_s_base-1,l1_miss,28.703% -mcf_s_base-10,ipc,0.82888 -mcf_s_base-10,dcache_miss,23.772% -mcf_s_base-10,dcache_miss_compulsory,0.0341 -mcf_s_base-10,dcache_miss_capacity,0.9658 -mcf_s_base-10,dcache_miss_conflict,0.0001 -mcf_s_base-10,l1_hit,71.623% -mcf_s_base-10,l1_miss,28.377% -mcf_s_base-2,ipc,0.82661 -mcf_s_base-2,dcache_miss,23.764% -mcf_s_base-2,dcache_miss_compulsory,0.0341 -mcf_s_base-2,dcache_miss_capacity,0.9658 -mcf_s_base-2,dcache_miss_conflict,0.0001 -mcf_s_base-2,l1_hit,71.422% -mcf_s_base-2,l1_miss,28.578% -mcf_s_base-20,ipc,0.82986 -mcf_s_base-20,dcache_miss,23.781% -mcf_s_base-20,dcache_miss_compulsory,0.0341 -mcf_s_base-20,dcache_miss_capacity,0.9658 -mcf_s_base-20,dcache_miss_conflict,0.0001 -mcf_s_base-20,l1_hit,71.737% -mcf_s_base-20,l1_miss,28.263% -mcf_s_base-5,ipc,0.82785 -mcf_s_base-5,dcache_miss,23.774% -mcf_s_base-5,dcache_miss_compulsory,0.0341 -mcf_s_base-5,dcache_miss_capacity,0.9658 -mcf_s_base-5,dcache_miss_conflict,0.0001 -mcf_s_base-5,l1_hit,71.554% -mcf_s_base-5,l1_miss,28.446% -omnetpp-0,ipc,1.23755 -omnetpp-0,dcache_miss,6.485% -omnetpp-0,dcache_miss_compulsory,0.0949 -omnetpp-0,dcache_miss_capacity,0.9044 -omnetpp-0,dcache_miss_conflict,0.0007 -omnetpp-0,l1_hit,73.009% -omnetpp-0,l1_miss,26.991% -omnetpp-1,ipc,1.23859 -omnetpp-1,dcache_miss,6.483% -omnetpp-1,dcache_miss_compulsory,0.0949 -omnetpp-1,dcache_miss_capacity,0.9044 -omnetpp-1,dcache_miss_conflict,0.0007 -omnetpp-1,l1_hit,73.049% -omnetpp-1,l1_miss,26.951% -omnetpp-10,ipc,1.23956 -omnetpp-10,dcache_miss,6.485% -omnetpp-10,dcache_miss_compulsory,0.0949 -omnetpp-10,dcache_miss_capacity,0.9044 -omnetpp-10,dcache_miss_conflict,0.0007 -omnetpp-10,l1_hit,73.109% -omnetpp-10,l1_miss,26.891% -omnetpp-2,ipc,1.23880 -omnetpp-2,dcache_miss,6.487% -omnetpp-2,dcache_miss_compulsory,0.0949 -omnetpp-2,dcache_miss_capacity,0.9044 -omnetpp-2,dcache_miss_conflict,0.0007 -omnetpp-2,l1_hit,73.025% -omnetpp-2,l1_miss,26.975% -omnetpp-20,ipc,1.24098 -omnetpp-20,dcache_miss,6.487% -omnetpp-20,dcache_miss_compulsory,0.0949 -omnetpp-20,dcache_miss_capacity,0.9044 -omnetpp-20,dcache_miss_conflict,0.0007 -omnetpp-20,l1_hit,73.179% -omnetpp-20,l1_miss,26.821% -omnetpp-5,ipc,1.23790 -omnetpp-5,dcache_miss,6.481% -omnetpp-5,dcache_miss_compulsory,0.0950 -omnetpp-5,dcache_miss_capacity,0.9044 -omnetpp-5,dcache_miss_conflict,0.0007 -omnetpp-5,l1_hit,73.089% -omnetpp-5,l1_miss,26.911% -perlbench_s_base-0,ipc,1.29149 -perlbench_s_base-0,dcache_miss,4.259% -perlbench_s_base-0,dcache_miss_compulsory,0.0174 -perlbench_s_base-0,dcache_miss_capacity,0.9819 -perlbench_s_base-0,dcache_miss_conflict,0.0007 -perlbench_s_base-0,l1_hit,91.624% -perlbench_s_base-0,l1_miss,8.376% -perlbench_s_base-1,ipc,1.29090 -perlbench_s_base-1,dcache_miss,4.259% -perlbench_s_base-1,dcache_miss_compulsory,0.0174 -perlbench_s_base-1,dcache_miss_capacity,0.9819 -perlbench_s_base-1,dcache_miss_conflict,0.0007 -perlbench_s_base-1,l1_hit,91.642% -perlbench_s_base-1,l1_miss,8.358% -perlbench_s_base-10,ipc,1.29158 -perlbench_s_base-10,dcache_miss,4.259% -perlbench_s_base-10,dcache_miss_compulsory,0.0174 -perlbench_s_base-10,dcache_miss_capacity,0.9819 -perlbench_s_base-10,dcache_miss_conflict,0.0007 -perlbench_s_base-10,l1_hit,91.703% -perlbench_s_base-10,l1_miss,8.297% -perlbench_s_base-2,ipc,1.29131 -perlbench_s_base-2,dcache_miss,4.260% -perlbench_s_base-2,dcache_miss_compulsory,0.0174 -perlbench_s_base-2,dcache_miss_capacity,0.9820 -perlbench_s_base-2,dcache_miss_conflict,0.0007 -perlbench_s_base-2,l1_hit,91.690% -perlbench_s_base-2,l1_miss,8.310% -perlbench_s_base-20,ipc,1.29466 -perlbench_s_base-20,dcache_miss,4.259% -perlbench_s_base-20,dcache_miss_compulsory,0.0174 -perlbench_s_base-20,dcache_miss_capacity,0.9819 -perlbench_s_base-20,dcache_miss_conflict,0.0007 -perlbench_s_base-20,l1_hit,91.770% -perlbench_s_base-20,l1_miss,8.230% -perlbench_s_base-5,ipc,1.29131 -perlbench_s_base-5,dcache_miss,4.257% -perlbench_s_base-5,dcache_miss_compulsory,0.0174 -perlbench_s_base-5,dcache_miss_capacity,0.9819 -perlbench_s_base-5,dcache_miss_conflict,0.0007 -perlbench_s_base-5,l1_hit,91.684% -perlbench_s_base-5,l1_miss,8.316% -sgcc_base-0,ipc,1.23657 -sgcc_base-0,dcache_miss,2.878% -sgcc_base-0,dcache_miss_compulsory,0.0335 -sgcc_base-0,dcache_miss_capacity,0.9626 -sgcc_base-0,dcache_miss_conflict,0.0038 -sgcc_base-0,l1_hit,99.716% -sgcc_base-0,l1_miss,0.284% -sgcc_base-1,ipc,1.23649 -sgcc_base-1,dcache_miss,2.878% -sgcc_base-1,dcache_miss_compulsory,0.0335 -sgcc_base-1,dcache_miss_capacity,0.9626 -sgcc_base-1,dcache_miss_conflict,0.0038 -sgcc_base-1,l1_hit,99.716% -sgcc_base-1,l1_miss,0.284% -sgcc_base-10,ipc,1.23686 -sgcc_base-10,dcache_miss,2.878% -sgcc_base-10,dcache_miss_compulsory,0.0335 -sgcc_base-10,dcache_miss_capacity,0.9626 -sgcc_base-10,dcache_miss_conflict,0.0038 -sgcc_base-10,l1_hit,99.715% -sgcc_base-10,l1_miss,0.285% -sgcc_base-2,ipc,1.23661 -sgcc_base-2,dcache_miss,2.877% -sgcc_base-2,dcache_miss_compulsory,0.0335 -sgcc_base-2,dcache_miss_capacity,0.9626 -sgcc_base-2,dcache_miss_conflict,0.0038 -sgcc_base-2,l1_hit,99.716% -sgcc_base-2,l1_miss,0.284% -sgcc_base-20,ipc,1.23691 -sgcc_base-20,dcache_miss,2.878% -sgcc_base-20,dcache_miss_compulsory,0.0335 -sgcc_base-20,dcache_miss_capacity,0.9626 -sgcc_base-20,dcache_miss_conflict,0.0038 -sgcc_base-20,l1_hit,99.720% -sgcc_base-20,l1_miss,0.280% -sgcc_base-5,ipc,1.23668 -sgcc_base-5,dcache_miss,2.878% -sgcc_base-5,dcache_miss_compulsory,0.0335 -sgcc_base-5,dcache_miss_capacity,0.9626 -sgcc_base-5,dcache_miss_conflict,0.0038 -sgcc_base-5,l1_hit,99.714% -sgcc_base-5,l1_miss,0.286% -specrand_i-0,ipc,2.65955 -specrand_i-0,dcache_miss,0.002% -specrand_i-0,dcache_miss_compulsory,0.3115 -specrand_i-0,dcache_miss_capacity,0.0000 -specrand_i-0,dcache_miss_conflict,0.6885 -specrand_i-0,l1_hit,99.803% -specrand_i-0,l1_miss,0.197% -specrand_i-1,ipc,2.65955 -specrand_i-1,dcache_miss,0.002% -specrand_i-1,dcache_miss_compulsory,0.3115 -specrand_i-1,dcache_miss_capacity,0.0000 -specrand_i-1,dcache_miss_conflict,0.6885 -specrand_i-1,l1_hit,99.803% -specrand_i-1,l1_miss,0.197% -specrand_i-10,ipc,2.65955 -specrand_i-10,dcache_miss,0.002% -specrand_i-10,dcache_miss_compulsory,0.3115 -specrand_i-10,dcache_miss_capacity,0.0000 -specrand_i-10,dcache_miss_conflict,0.6885 -specrand_i-10,l1_hit,99.803% -specrand_i-10,l1_miss,0.197% -specrand_i-2,ipc,2.65955 -specrand_i-2,dcache_miss,0.002% -specrand_i-2,dcache_miss_compulsory,0.3115 -specrand_i-2,dcache_miss_capacity,0.0000 -specrand_i-2,dcache_miss_conflict,0.6885 -specrand_i-2,l1_hit,99.803% -specrand_i-2,l1_miss,0.197% -specrand_i-20,ipc,2.65955 -specrand_i-20,dcache_miss,0.002% -specrand_i-20,dcache_miss_compulsory,0.3115 -specrand_i-20,dcache_miss_capacity,0.0000 -specrand_i-20,dcache_miss_conflict,0.6885 -specrand_i-20,l1_hit,99.803% -specrand_i-20,l1_miss,0.197% -specrand_i-5,ipc,2.65955 -specrand_i-5,dcache_miss,0.002% -specrand_i-5,dcache_miss_compulsory,0.3115 -specrand_i-5,dcache_miss_capacity,0.0000 -specrand_i-5,dcache_miss_conflict,0.6885 -specrand_i-5,l1_hit,99.803% -specrand_i-5,l1_miss,0.197% -x264-0,ipc,2.93533 -x264-0,dcache_miss,2.745% -x264-0,dcache_miss_compulsory,0.0953 -x264-0,dcache_miss_capacity,0.9046 -x264-0,dcache_miss_conflict,0.0000 -x264-0,l1_hit,55.107% -x264-0,l1_miss,44.893% -x264-1,ipc,2.93626 -x264-1,dcache_miss,2.744% -x264-1,dcache_miss_compulsory,0.0954 -x264-1,dcache_miss_capacity,0.9046 -x264-1,dcache_miss_conflict,0.0000 -x264-1,l1_hit,55.330% -x264-1,l1_miss,44.670% -x264-10,ipc,2.93519 -x264-10,dcache_miss,2.746% -x264-10,dcache_miss_compulsory,0.0953 -x264-10,dcache_miss_capacity,0.9047 -x264-10,dcache_miss_conflict,0.0000 -x264-10,l1_hit,55.200% -x264-10,l1_miss,44.800% -x264-2,ipc,2.93502 -x264-2,dcache_miss,2.744% -x264-2,dcache_miss_compulsory,0.0954 -x264-2,dcache_miss_capacity,0.9046 -x264-2,dcache_miss_conflict,0.0000 -x264-2,l1_hit,54.987% -x264-2,l1_miss,45.013% -x264-20,ipc,2.93417 -x264-20,dcache_miss,2.741% -x264-20,dcache_miss_compulsory,0.0955 -x264-20,dcache_miss_capacity,0.9045 -x264-20,dcache_miss_conflict,0.0000 -x264-20,l1_hit,55.324% -x264-20,l1_miss,44.676% -x264-5,ipc,2.93545 -x264-5,dcache_miss,2.745% -x264-5,dcache_miss_compulsory,0.0953 -x264-5,dcache_miss_capacity,0.9046 -x264-5,dcache_miss_conflict,0.0000 -x264-5,l1_hit,55.056% -x264-5,l1_miss,44.944% -xalancbmk_s_base-0,ipc,1.00507 -xalancbmk_s_base-0,dcache_miss,18.918% -xalancbmk_s_base-0,dcache_miss_compulsory,0.0064 -xalancbmk_s_base-0,dcache_miss_capacity,0.9931 -xalancbmk_s_base-0,dcache_miss_conflict,0.0004 -xalancbmk_s_base-0,l1_hit,76.772% -xalancbmk_s_base-0,l1_miss,23.228% -xalancbmk_s_base-1,ipc,1.00594 -xalancbmk_s_base-1,dcache_miss,18.910% -xalancbmk_s_base-1,dcache_miss_compulsory,0.0064 -xalancbmk_s_base-1,dcache_miss_capacity,0.9931 -xalancbmk_s_base-1,dcache_miss_conflict,0.0004 -xalancbmk_s_base-1,l1_hit,76.800% -xalancbmk_s_base-1,l1_miss,23.200% -xalancbmk_s_base-10,ipc,1.00585 -xalancbmk_s_base-10,dcache_miss,18.908% -xalancbmk_s_base-10,dcache_miss_compulsory,0.0064 -xalancbmk_s_base-10,dcache_miss_capacity,0.9931 -xalancbmk_s_base-10,dcache_miss_conflict,0.0004 -xalancbmk_s_base-10,l1_hit,76.857% -xalancbmk_s_base-10,l1_miss,23.143% -xalancbmk_s_base-2,ipc,1.00831 -xalancbmk_s_base-2,dcache_miss,18.932% -xalancbmk_s_base-2,dcache_miss_compulsory,0.0064 -xalancbmk_s_base-2,dcache_miss_capacity,0.9932 -xalancbmk_s_base-2,dcache_miss_conflict,0.0004 -xalancbmk_s_base-2,l1_hit,76.911% -xalancbmk_s_base-2,l1_miss,23.089% -xalancbmk_s_base-20,ipc,1.00998 -xalancbmk_s_base-20,dcache_miss,18.898% -xalancbmk_s_base-20,dcache_miss_compulsory,0.0064 -xalancbmk_s_base-20,dcache_miss_capacity,0.9931 -xalancbmk_s_base-20,dcache_miss_conflict,0.0004 -xalancbmk_s_base-20,l1_hit,77.072% -xalancbmk_s_base-20,l1_miss,22.928% -xalancbmk_s_base-5,ipc,1.00804 -xalancbmk_s_base-5,dcache_miss,18.928% -xalancbmk_s_base-5,dcache_miss_compulsory,0.0064 -xalancbmk_s_base-5,dcache_miss_capacity,0.9932 -xalancbmk_s_base-5,dcache_miss_conflict,0.0004 -xalancbmk_s_base-5,l1_hit,76.895% -xalancbmk_s_base-5,l1_miss,23.105% diff --git a/labs/LAB5/run_all.err b/labs/LAB5/run_all.err deleted file mode 100644 index 45601854..00000000 --- a/labs/LAB5/run_all.err +++ /dev/null @@ -1,1560 +0,0 @@ -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=perlbench_s_base -+ VICTIM_CACHE_SIZE=0 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*perlbench_s_base*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir -type f -iname '*perlbench_s_base*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir/trace/drmemtrace.perlbench_s_base.mytest-m64.554262.9223.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/perlbench_s_base-0 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=0 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=0 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/perlbench_s_base-0 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/perlbench_s_base-0/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/perlbench_s_base-0 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir/trace/drmemtrace.perlbench_s_base.mytest-m64.554262.9223.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir/raw --VICTIM_CACHE_SIZE=0 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=perlbench_s_base -+ VICTIM_CACHE_SIZE=1 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*perlbench_s_base*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir -type f -iname '*perlbench_s_base*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir/trace/drmemtrace.perlbench_s_base.mytest-m64.554262.9223.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/perlbench_s_base-1 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=1' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=1 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=1 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/perlbench_s_base-1 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/perlbench_s_base-1/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/perlbench_s_base-1 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir/trace/drmemtrace.perlbench_s_base.mytest-m64.554262.9223.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir/raw --VICTIM_CACHE_SIZE=1 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=perlbench_s_base -+ VICTIM_CACHE_SIZE=2 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*perlbench_s_base*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir -type f -iname '*perlbench_s_base*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir/trace/drmemtrace.perlbench_s_base.mytest-m64.554262.9223.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/perlbench_s_base-2 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=2' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=2 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=2 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/perlbench_s_base-2 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/perlbench_s_base-2/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/perlbench_s_base-2 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir/trace/drmemtrace.perlbench_s_base.mytest-m64.554262.9223.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir/raw --VICTIM_CACHE_SIZE=2 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=perlbench_s_base -+ VICTIM_CACHE_SIZE=5 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*perlbench_s_base*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir -type f -iname '*perlbench_s_base*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir/trace/drmemtrace.perlbench_s_base.mytest-m64.554262.9223.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/perlbench_s_base-5 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=5' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=5 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=5 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/perlbench_s_base-5 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/perlbench_s_base-5/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/perlbench_s_base-5 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir/trace/drmemtrace.perlbench_s_base.mytest-m64.554262.9223.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir/raw --VICTIM_CACHE_SIZE=5 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=perlbench_s_base -+ VICTIM_CACHE_SIZE=10 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*perlbench_s_base*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir -type f -iname '*perlbench_s_base*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir/trace/drmemtrace.perlbench_s_base.mytest-m64.554262.9223.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/perlbench_s_base-10 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=10' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=10 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=10 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/perlbench_s_base-10 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/perlbench_s_base-10/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/perlbench_s_base-10 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir/trace/drmemtrace.perlbench_s_base.mytest-m64.554262.9223.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir/raw --VICTIM_CACHE_SIZE=10 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=perlbench_s_base -+ VICTIM_CACHE_SIZE=20 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*perlbench_s_base*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir -type f -iname '*perlbench_s_base*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir/trace/drmemtrace.perlbench_s_base.mytest-m64.554262.9223.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/perlbench_s_base-20 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=20' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=20 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=20 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/perlbench_s_base-20 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/perlbench_s_base-20/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/perlbench_s_base-20 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir/trace/drmemtrace.perlbench_s_base.mytest-m64.554262.9223.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir/raw --VICTIM_CACHE_SIZE=20 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=x264 -+ VICTIM_CACHE_SIZE=0 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*x264*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir -type f -iname '*x264*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir/trace/drmemtrace.x264.555077.8068.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/x264-0 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=0 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=0 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/x264-0 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/x264-0/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/x264-0 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir/trace/drmemtrace.x264.555077.8068.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir/raw --VICTIM_CACHE_SIZE=0 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=x264 -+ VICTIM_CACHE_SIZE=1 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*x264*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir -type f -iname '*x264*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir/trace/drmemtrace.x264.555077.8068.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/x264-1 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=1' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=1 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=1 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/x264-1 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/x264-1/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/x264-1 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir/trace/drmemtrace.x264.555077.8068.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir/raw --VICTIM_CACHE_SIZE=1 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=x264 -+ VICTIM_CACHE_SIZE=2 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*x264*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir -type f -iname '*x264*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir/trace/drmemtrace.x264.555077.8068.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/x264-2 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=2' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=2 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=2 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/x264-2 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/x264-2/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/x264-2 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir/trace/drmemtrace.x264.555077.8068.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir/raw --VICTIM_CACHE_SIZE=2 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=x264 -+ VICTIM_CACHE_SIZE=5 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*x264*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir -type f -iname '*x264*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir/trace/drmemtrace.x264.555077.8068.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/x264-5 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=5' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=5 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=5 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/x264-5 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/x264-5/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/x264-5 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir/trace/drmemtrace.x264.555077.8068.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir/raw --VICTIM_CACHE_SIZE=5 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=x264 -+ VICTIM_CACHE_SIZE=10 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*x264*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir -type f -iname '*x264*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir/trace/drmemtrace.x264.555077.8068.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/x264-10 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=10' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=10 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=10 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/x264-10 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/x264-10/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/x264-10 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir/trace/drmemtrace.x264.555077.8068.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir/raw --VICTIM_CACHE_SIZE=10 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=x264 -+ VICTIM_CACHE_SIZE=20 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*x264*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir -type f -iname '*x264*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir/trace/drmemtrace.x264.555077.8068.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/x264-20 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=20' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=20 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=20 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/x264-20 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/x264-20/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/x264-20 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir/trace/drmemtrace.x264.555077.8068.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir/raw --VICTIM_CACHE_SIZE=20 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=exchange2 -+ VICTIM_CACHE_SIZE=0 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*exchange2*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir -type f -iname '*exchange2*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir/trace/drmemtrace.exchange2.553888.0626.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/exchange2-0 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=0 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=0 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/exchange2-0 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/exchange2-0/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/exchange2-0 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir/trace/drmemtrace.exchange2.553888.0626.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir/raw --VICTIM_CACHE_SIZE=0 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=exchange2 -+ VICTIM_CACHE_SIZE=1 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*exchange2*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir -type f -iname '*exchange2*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir/trace/drmemtrace.exchange2.553888.0626.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/exchange2-1 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=1' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=1 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=1 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/exchange2-1 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/exchange2-1/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/exchange2-1 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir/trace/drmemtrace.exchange2.553888.0626.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir/raw --VICTIM_CACHE_SIZE=1 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=exchange2 -+ VICTIM_CACHE_SIZE=2 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*exchange2*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir -type f -iname '*exchange2*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir/trace/drmemtrace.exchange2.553888.0626.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/exchange2-2 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=2' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=2 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=2 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/exchange2-2 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/exchange2-2/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/exchange2-2 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir/trace/drmemtrace.exchange2.553888.0626.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir/raw --VICTIM_CACHE_SIZE=2 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=exchange2 -+ VICTIM_CACHE_SIZE=5 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*exchange2*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir -type f -iname '*exchange2*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir/trace/drmemtrace.exchange2.553888.0626.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/exchange2-5 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=5' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=5 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=5 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/exchange2-5 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/exchange2-5/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/exchange2-5 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir/trace/drmemtrace.exchange2.553888.0626.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir/raw --VICTIM_CACHE_SIZE=5 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=exchange2 -+ VICTIM_CACHE_SIZE=10 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*exchange2*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir -type f -iname '*exchange2*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir/trace/drmemtrace.exchange2.553888.0626.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/exchange2-10 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=10' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=10 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=10 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/exchange2-10 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/exchange2-10/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/exchange2-10 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir/trace/drmemtrace.exchange2.553888.0626.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir/raw --VICTIM_CACHE_SIZE=10 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=exchange2 -+ VICTIM_CACHE_SIZE=20 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*exchange2*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir -type f -iname '*exchange2*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir/trace/drmemtrace.exchange2.553888.0626.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/exchange2-20 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=20' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=20 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=20 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/exchange2-20 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/exchange2-20/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/exchange2-20 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir/trace/drmemtrace.exchange2.553888.0626.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir/raw --VICTIM_CACHE_SIZE=20 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=sgcc_base -+ VICTIM_CACHE_SIZE=0 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*sgcc_base*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir -type f -iname '*sgcc_base*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir/trace/drmemtrace.sgcc_base.mytest-m64.555062.3859.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/sgcc_base-0 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=0 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=0 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/sgcc_base-0 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/sgcc_base-0/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/sgcc_base-0 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir/trace/drmemtrace.sgcc_base.mytest-m64.555062.3859.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir/raw --VICTIM_CACHE_SIZE=0 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=sgcc_base -+ VICTIM_CACHE_SIZE=1 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*sgcc_base*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir -type f -iname '*sgcc_base*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir/trace/drmemtrace.sgcc_base.mytest-m64.555062.3859.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/sgcc_base-1 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=1' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=1 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=1 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/sgcc_base-1 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/sgcc_base-1/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/sgcc_base-1 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir/trace/drmemtrace.sgcc_base.mytest-m64.555062.3859.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir/raw --VICTIM_CACHE_SIZE=1 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=sgcc_base -+ VICTIM_CACHE_SIZE=2 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*sgcc_base*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir -type f -iname '*sgcc_base*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir/trace/drmemtrace.sgcc_base.mytest-m64.555062.3859.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/sgcc_base-2 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=2' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=2 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=2 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/sgcc_base-2 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/sgcc_base-2/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/sgcc_base-2 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir/trace/drmemtrace.sgcc_base.mytest-m64.555062.3859.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir/raw --VICTIM_CACHE_SIZE=2 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=sgcc_base -+ VICTIM_CACHE_SIZE=5 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*sgcc_base*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir -type f -iname '*sgcc_base*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir/trace/drmemtrace.sgcc_base.mytest-m64.555062.3859.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/sgcc_base-5 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=5' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=5 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=5 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/sgcc_base-5 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/sgcc_base-5/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/sgcc_base-5 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir/trace/drmemtrace.sgcc_base.mytest-m64.555062.3859.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir/raw --VICTIM_CACHE_SIZE=5 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=sgcc_base -+ VICTIM_CACHE_SIZE=10 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*sgcc_base*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir -type f -iname '*sgcc_base*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir/trace/drmemtrace.sgcc_base.mytest-m64.555062.3859.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/sgcc_base-10 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=10' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=10 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=10 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/sgcc_base-10 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/sgcc_base-10/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/sgcc_base-10 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir/trace/drmemtrace.sgcc_base.mytest-m64.555062.3859.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir/raw --VICTIM_CACHE_SIZE=10 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=sgcc_base -+ VICTIM_CACHE_SIZE=20 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*sgcc_base*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir -type f -iname '*sgcc_base*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir/trace/drmemtrace.sgcc_base.mytest-m64.555062.3859.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/sgcc_base-20 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=20' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=20 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=20 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/sgcc_base-20 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/sgcc_base-20/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/sgcc_base-20 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir/trace/drmemtrace.sgcc_base.mytest-m64.555062.3859.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir/raw --VICTIM_CACHE_SIZE=20 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=leela_s_base -+ VICTIM_CACHE_SIZE=0 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*leela_s_base*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir -type f -iname '*leela_s_base*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir/trace/drmemtrace.leela_s_base.mytest-m64.555086.2935.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/leela_s_base-0 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=0 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=0 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/leela_s_base-0 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/leela_s_base-0/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/leela_s_base-0 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir/trace/drmemtrace.leela_s_base.mytest-m64.555086.2935.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir/raw --VICTIM_CACHE_SIZE=0 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=leela_s_base -+ VICTIM_CACHE_SIZE=1 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*leela_s_base*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir -type f -iname '*leela_s_base*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir/trace/drmemtrace.leela_s_base.mytest-m64.555086.2935.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/leela_s_base-1 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=1' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=1 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=1 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/leela_s_base-1 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/leela_s_base-1/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/leela_s_base-1 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir/trace/drmemtrace.leela_s_base.mytest-m64.555086.2935.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir/raw --VICTIM_CACHE_SIZE=1 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=leela_s_base -+ VICTIM_CACHE_SIZE=2 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*leela_s_base*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir -type f -iname '*leela_s_base*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir/trace/drmemtrace.leela_s_base.mytest-m64.555086.2935.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/leela_s_base-2 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=2' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=2 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=2 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/leela_s_base-2 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/leela_s_base-2/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/leela_s_base-2 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir/trace/drmemtrace.leela_s_base.mytest-m64.555086.2935.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir/raw --VICTIM_CACHE_SIZE=2 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=leela_s_base -+ VICTIM_CACHE_SIZE=5 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*leela_s_base*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir -type f -iname '*leela_s_base*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir/trace/drmemtrace.leela_s_base.mytest-m64.555086.2935.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/leela_s_base-5 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=5' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=5 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=5 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/leela_s_base-5 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/leela_s_base-5/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/leela_s_base-5 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir/trace/drmemtrace.leela_s_base.mytest-m64.555086.2935.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir/raw --VICTIM_CACHE_SIZE=5 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=leela_s_base -+ VICTIM_CACHE_SIZE=10 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*leela_s_base*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir -type f -iname '*leela_s_base*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir/trace/drmemtrace.leela_s_base.mytest-m64.555086.2935.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/leela_s_base-10 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=10' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=10 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=10 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/leela_s_base-10 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/leela_s_base-10/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/leela_s_base-10 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir/trace/drmemtrace.leela_s_base.mytest-m64.555086.2935.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir/raw --VICTIM_CACHE_SIZE=10 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=leela_s_base -+ VICTIM_CACHE_SIZE=20 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*leela_s_base*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir -type f -iname '*leela_s_base*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir/trace/drmemtrace.leela_s_base.mytest-m64.555086.2935.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/leela_s_base-20 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=20' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=20 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=20 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/leela_s_base-20 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/leela_s_base-20/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/leela_s_base-20 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir/trace/drmemtrace.leela_s_base.mytest-m64.555086.2935.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir/raw --VICTIM_CACHE_SIZE=20 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=mcf_s_base -+ VICTIM_CACHE_SIZE=0 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*mcf_s_base*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir -type f -iname '*mcf_s_base*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir/trace/drmemtrace.mcf_s_base.mytest-m64.554166.7956.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/mcf_s_base-0 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=0 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=0 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/mcf_s_base-0 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/mcf_s_base-0/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/mcf_s_base-0 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir/trace/drmemtrace.mcf_s_base.mytest-m64.554166.7956.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir/raw --VICTIM_CACHE_SIZE=0 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=mcf_s_base -+ VICTIM_CACHE_SIZE=1 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*mcf_s_base*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir -type f -iname '*mcf_s_base*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir/trace/drmemtrace.mcf_s_base.mytest-m64.554166.7956.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/mcf_s_base-1 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=1' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=1 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=1 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/mcf_s_base-1 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/mcf_s_base-1/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/mcf_s_base-1 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir/trace/drmemtrace.mcf_s_base.mytest-m64.554166.7956.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir/raw --VICTIM_CACHE_SIZE=1 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=mcf_s_base -+ VICTIM_CACHE_SIZE=2 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*mcf_s_base*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir -type f -iname '*mcf_s_base*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir/trace/drmemtrace.mcf_s_base.mytest-m64.554166.7956.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/mcf_s_base-2 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=2' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=2 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=2 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/mcf_s_base-2 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/mcf_s_base-2/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/mcf_s_base-2 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir/trace/drmemtrace.mcf_s_base.mytest-m64.554166.7956.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir/raw --VICTIM_CACHE_SIZE=2 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=mcf_s_base -+ VICTIM_CACHE_SIZE=5 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*mcf_s_base*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir -type f -iname '*mcf_s_base*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir/trace/drmemtrace.mcf_s_base.mytest-m64.554166.7956.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/mcf_s_base-5 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=5' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=5 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=5 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/mcf_s_base-5 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/mcf_s_base-5/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/mcf_s_base-5 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir/trace/drmemtrace.mcf_s_base.mytest-m64.554166.7956.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir/raw --VICTIM_CACHE_SIZE=5 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=mcf_s_base -+ VICTIM_CACHE_SIZE=10 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*mcf_s_base*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir -type f -iname '*mcf_s_base*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir/trace/drmemtrace.mcf_s_base.mytest-m64.554166.7956.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/mcf_s_base-10 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=10' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=10 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=10 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/mcf_s_base-10 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/mcf_s_base-10/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/mcf_s_base-10 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir/trace/drmemtrace.mcf_s_base.mytest-m64.554166.7956.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir/raw --VICTIM_CACHE_SIZE=10 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=mcf_s_base -+ VICTIM_CACHE_SIZE=20 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*mcf_s_base*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir -type f -iname '*mcf_s_base*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir/trace/drmemtrace.mcf_s_base.mytest-m64.554166.7956.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/mcf_s_base-20 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=20' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=20 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=20 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/mcf_s_base-20 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/mcf_s_base-20/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/mcf_s_base-20 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir/trace/drmemtrace.mcf_s_base.mytest-m64.554166.7956.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir/raw --VICTIM_CACHE_SIZE=20 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=xalancbmk_s_base -+ VICTIM_CACHE_SIZE=0 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*xalancbmk_s_base*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir -type f -iname '*xalancbmk_s_base*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir/trace/drmemtrace.xalancbmk_s_base.mytest-m64.555084.7482.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/xalancbmk_s_base-0 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=0 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=0 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/xalancbmk_s_base-0 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/xalancbmk_s_base-0/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/xalancbmk_s_base-0 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir/trace/drmemtrace.xalancbmk_s_base.mytest-m64.555084.7482.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir/raw --VICTIM_CACHE_SIZE=0 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=xalancbmk_s_base -+ VICTIM_CACHE_SIZE=1 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*xalancbmk_s_base*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir -type f -iname '*xalancbmk_s_base*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir/trace/drmemtrace.xalancbmk_s_base.mytest-m64.555084.7482.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/xalancbmk_s_base-1 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=1' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=1 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=1 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/xalancbmk_s_base-1 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/xalancbmk_s_base-1/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/xalancbmk_s_base-1 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir/trace/drmemtrace.xalancbmk_s_base.mytest-m64.555084.7482.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir/raw --VICTIM_CACHE_SIZE=1 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=xalancbmk_s_base -+ VICTIM_CACHE_SIZE=2 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*xalancbmk_s_base*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir -type f -iname '*xalancbmk_s_base*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir/trace/drmemtrace.xalancbmk_s_base.mytest-m64.555084.7482.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/xalancbmk_s_base-2 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=2' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=2 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=2 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/xalancbmk_s_base-2 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/xalancbmk_s_base-2/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/xalancbmk_s_base-2 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir/trace/drmemtrace.xalancbmk_s_base.mytest-m64.555084.7482.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir/raw --VICTIM_CACHE_SIZE=2 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=xalancbmk_s_base -+ VICTIM_CACHE_SIZE=5 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*xalancbmk_s_base*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir -type f -iname '*xalancbmk_s_base*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir/trace/drmemtrace.xalancbmk_s_base.mytest-m64.555084.7482.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/xalancbmk_s_base-5 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=5' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=5 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=5 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/xalancbmk_s_base-5 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/xalancbmk_s_base-5/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/xalancbmk_s_base-5 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir/trace/drmemtrace.xalancbmk_s_base.mytest-m64.555084.7482.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir/raw --VICTIM_CACHE_SIZE=5 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=xalancbmk_s_base -+ VICTIM_CACHE_SIZE=10 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*xalancbmk_s_base*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir -type f -iname '*xalancbmk_s_base*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir/trace/drmemtrace.xalancbmk_s_base.mytest-m64.555084.7482.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/xalancbmk_s_base-10 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=10' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=10 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=10 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/xalancbmk_s_base-10 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/xalancbmk_s_base-10/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/xalancbmk_s_base-10 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir/trace/drmemtrace.xalancbmk_s_base.mytest-m64.555084.7482.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir/raw --VICTIM_CACHE_SIZE=10 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=xalancbmk_s_base -+ VICTIM_CACHE_SIZE=20 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*xalancbmk_s_base*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir -type f -iname '*xalancbmk_s_base*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir/trace/drmemtrace.xalancbmk_s_base.mytest-m64.555084.7482.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/xalancbmk_s_base-20 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=20' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=20 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=20 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/xalancbmk_s_base-20 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/xalancbmk_s_base-20/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/xalancbmk_s_base-20 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir/trace/drmemtrace.xalancbmk_s_base.mytest-m64.555084.7482.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir/raw --VICTIM_CACHE_SIZE=20 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=deepsjeng -+ VICTIM_CACHE_SIZE=0 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*deepsjeng*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir -type f -iname '*deepsjeng*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir/trace/drmemtrace.deepsjeng.553743.6815.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/deepsjeng-0 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=0 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=0 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/deepsjeng-0 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/deepsjeng-0/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/deepsjeng-0 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir/trace/drmemtrace.deepsjeng.553743.6815.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir/raw --VICTIM_CACHE_SIZE=0 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=deepsjeng -+ VICTIM_CACHE_SIZE=1 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*deepsjeng*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir -type f -iname '*deepsjeng*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir/trace/drmemtrace.deepsjeng.553743.6815.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/deepsjeng-1 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=1' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=1 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=1 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/deepsjeng-1 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/deepsjeng-1/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/deepsjeng-1 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir/trace/drmemtrace.deepsjeng.553743.6815.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir/raw --VICTIM_CACHE_SIZE=1 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=deepsjeng -+ VICTIM_CACHE_SIZE=2 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*deepsjeng*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir -type f -iname '*deepsjeng*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir/trace/drmemtrace.deepsjeng.553743.6815.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/deepsjeng-2 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=2' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=2 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=2 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/deepsjeng-2 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/deepsjeng-2/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/deepsjeng-2 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir/trace/drmemtrace.deepsjeng.553743.6815.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir/raw --VICTIM_CACHE_SIZE=2 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=deepsjeng -+ VICTIM_CACHE_SIZE=5 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*deepsjeng*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir -type f -iname '*deepsjeng*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir/trace/drmemtrace.deepsjeng.553743.6815.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/deepsjeng-5 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=5' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=5 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=5 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/deepsjeng-5 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/deepsjeng-5/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/deepsjeng-5 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir/trace/drmemtrace.deepsjeng.553743.6815.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir/raw --VICTIM_CACHE_SIZE=5 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=deepsjeng -+ VICTIM_CACHE_SIZE=10 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*deepsjeng*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir -type f -iname '*deepsjeng*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir/trace/drmemtrace.deepsjeng.553743.6815.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/deepsjeng-10 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=10' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=10 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=10 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/deepsjeng-10 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/deepsjeng-10/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/deepsjeng-10 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir/trace/drmemtrace.deepsjeng.553743.6815.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir/raw --VICTIM_CACHE_SIZE=10 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=deepsjeng -+ VICTIM_CACHE_SIZE=20 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*deepsjeng*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir -type f -iname '*deepsjeng*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir/trace/drmemtrace.deepsjeng.553743.6815.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/deepsjeng-20 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=20' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=20 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=20 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/deepsjeng-20 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/deepsjeng-20/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/deepsjeng-20 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir/trace/drmemtrace.deepsjeng.553743.6815.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir/raw --VICTIM_CACHE_SIZE=20 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=specrand_i -+ VICTIM_CACHE_SIZE=0 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*specrand_i*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir -type f -iname '*specrand_i*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir/trace/drmemtrace.specrand_i.553922.2837.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/specrand_i-0 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=0 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=0 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/specrand_i-0 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/specrand_i-0/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/specrand_i-0 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir/trace/drmemtrace.specrand_i.553922.2837.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir/raw --VICTIM_CACHE_SIZE=0 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=specrand_i -+ VICTIM_CACHE_SIZE=1 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*specrand_i*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir -type f -iname '*specrand_i*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir/trace/drmemtrace.specrand_i.553922.2837.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/specrand_i-1 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=1' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=1 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=1 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/specrand_i-1 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/specrand_i-1/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/specrand_i-1 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir/trace/drmemtrace.specrand_i.553922.2837.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir/raw --VICTIM_CACHE_SIZE=1 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=specrand_i -+ VICTIM_CACHE_SIZE=2 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*specrand_i*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir -type f -iname '*specrand_i*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir/trace/drmemtrace.specrand_i.553922.2837.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/specrand_i-2 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=2' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=2 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=2 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/specrand_i-2 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/specrand_i-2/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/specrand_i-2 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir/trace/drmemtrace.specrand_i.553922.2837.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir/raw --VICTIM_CACHE_SIZE=2 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=specrand_i -+ VICTIM_CACHE_SIZE=5 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*specrand_i*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir -type f -iname '*specrand_i*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir/trace/drmemtrace.specrand_i.553922.2837.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/specrand_i-5 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=5' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=5 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=5 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/specrand_i-5 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/specrand_i-5/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/specrand_i-5 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir/trace/drmemtrace.specrand_i.553922.2837.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir/raw --VICTIM_CACHE_SIZE=5 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=specrand_i -+ VICTIM_CACHE_SIZE=10 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*specrand_i*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir -type f -iname '*specrand_i*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir/trace/drmemtrace.specrand_i.553922.2837.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/specrand_i-10 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=10' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=10 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=10 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/specrand_i-10 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/specrand_i-10/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/specrand_i-10 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir/trace/drmemtrace.specrand_i.553922.2837.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir/raw --VICTIM_CACHE_SIZE=10 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=specrand_i -+ VICTIM_CACHE_SIZE=20 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*specrand_i*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir -type f -iname '*specrand_i*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir/trace/drmemtrace.specrand_i.553922.2837.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/specrand_i-20 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=20' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=20 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=20 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/specrand_i-20 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/specrand_i-20/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/specrand_i-20 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir/trace/drmemtrace.specrand_i.553922.2837.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir/raw --VICTIM_CACHE_SIZE=20 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=omnetpp -+ VICTIM_CACHE_SIZE=0 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*omnetpp*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir -type f -iname '*omnetpp*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir/trace/drmemtrace.omnetpp.552936.3514.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/omnetpp-0 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=0 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=0 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/omnetpp-0 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/omnetpp-0/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/omnetpp-0 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir/trace/drmemtrace.omnetpp.552936.3514.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir/raw --VICTIM_CACHE_SIZE=0 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=omnetpp -+ VICTIM_CACHE_SIZE=1 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*omnetpp*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir -type f -iname '*omnetpp*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir/trace/drmemtrace.omnetpp.552936.3514.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/omnetpp-1 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=1' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=1 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=1 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/omnetpp-1 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/omnetpp-1/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/omnetpp-1 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir/trace/drmemtrace.omnetpp.552936.3514.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir/raw --VICTIM_CACHE_SIZE=1 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=omnetpp -+ VICTIM_CACHE_SIZE=2 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*omnetpp*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir -type f -iname '*omnetpp*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir/trace/drmemtrace.omnetpp.552936.3514.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/omnetpp-2 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=2' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=2 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=2 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/omnetpp-2 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/omnetpp-2/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/omnetpp-2 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir/trace/drmemtrace.omnetpp.552936.3514.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir/raw --VICTIM_CACHE_SIZE=2 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=omnetpp -+ VICTIM_CACHE_SIZE=5 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*omnetpp*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir -type f -iname '*omnetpp*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir/trace/drmemtrace.omnetpp.552936.3514.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/omnetpp-5 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=5' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=5 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=5 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/omnetpp-5 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/omnetpp-5/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/omnetpp-5 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir/trace/drmemtrace.omnetpp.552936.3514.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir/raw --VICTIM_CACHE_SIZE=5 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=omnetpp -+ VICTIM_CACHE_SIZE=10 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*omnetpp*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir -type f -iname '*omnetpp*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir/trace/drmemtrace.omnetpp.552936.3514.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/omnetpp-10 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=10' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=10 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=10 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/omnetpp-10 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/omnetpp-10/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/omnetpp-10 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir/trace/drmemtrace.omnetpp.552936.3514.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir/raw --VICTIM_CACHE_SIZE=10 --fetch_off_path_ops=0 --inst_limit=100000000 -+ . vars.env -++ export ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ ALL_TRACES_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -++ export SCARAB_DIR=/scarab-dev/scarab/ -++ SCARAB_DIR=/scarab-dev/scarab/ -++ export DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -++ DEFAULT_PARAMS_IN=/scarab-dev/scarab//src/PARAMS.kaby_lake -+ TRACE_NAME=omnetpp -+ VICTIM_CACHE_SIZE=20 -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/ -type d -iname '*omnetpp*.dir' -+ TRACE_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir -++ find /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir -type f -iname '*omnetpp*.trace*' -+ TRACE_FILE=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir/trace/drmemtrace.omnetpp.552936.3514.trace.gz -+ TRACE_RAW_DIR=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir/raw -++ pwd -+ RUN_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/omnetpp-20 -+ EXTRA_ARGS= -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=20' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=20 --fetch_off_path_ops=0' -+ EXTRA_ARGS=' --VICTIM_CACHE_SIZE=20 --fetch_off_path_ops=0 --inst_limit=100000000' -++ pwd -+ START_DIR=/outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4 -+ mkdir -p /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/omnetpp-20 -+ cp /scarab-dev/scarab//src/PARAMS.kaby_lake /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/omnetpp-20/PARAMS.in -+ cd /outside/Development/ucsc/coursework/S23_CSE220/ucsc-s23-cse220/labs/LAB4/runs/omnetpp-20 -+ /scarab-dev/scarab//src/scarab --frontend memtrace --cbp_trace_r0=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir/trace/drmemtrace.omnetpp.552936.3514.trace.gz --memtrace_modules_log=/outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir/raw --VICTIM_CACHE_SIZE=20 --fetch_off_path_ops=0 --inst_limit=100000000 diff --git a/labs/LAB5/run_all.sh b/labs/LAB5/run_all.sh index 7bccd58e..abd4fb70 100755 --- a/labs/LAB5/run_all.sh +++ b/labs/LAB5/run_all.sh @@ -8,10 +8,6 @@ ALL_TRACE_NAMES=$(find "${ALL_TRACES_DIR}" -type d -iname "*.dir" | grep drmemtr ALL_RUN_CONFIGS=$(cat <<-END 0 1 - 2 - 5 - 10 - 20 END ) diff --git a/labs/LAB5/runs/deepsjeng-sms0/PARAMS.in b/labs/LAB5/runs/deepsjeng-sms0/PARAMS.in new file mode 100644 index 00000000..2593c2b8 --- /dev/null +++ b/labs/LAB5/runs/deepsjeng-sms0/PARAMS.in @@ -0,0 +1,226 @@ +# File : PARAMS.kaby_lake +# Date : 03/06/19 +# Description : Kaby Lake Configuration +# +# Based on documentation found here: +# https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake + +## Simulation Parameters +--mode full +--model cmp +--sim_limit none + +## Core Parameters + +# Femptoseconds, 3.2GHz, used for energy estimates. +--chip_cycle_time 312500 + + +### Fetch Stage +--fetch_off_path_ops 1 +--fetch_across_cache_lines 1 + +# Will break the packet upon a taken branch. +--fetch_break_on_taken 1 + +# Number of bubble cycles to wait after taken branch. +--fetch_taken_bubble_cycles 0 + + +#### ICache +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 + +### Branch Predictor +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_mech tagescl + + +#### BTB + +# BTB model to use. +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 + +# Allow the BTB to be updated by off path ops. +--btb_off_path_writes 1 + + +#### CRS + +# Enable return stack +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 + +### iBP +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged + # iBTB Model. tc_tagless, tc_tagged, tc_hybrid. +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 + +### Decode Stage +--decode_cycles 5 + + +### Map Stage +--map_cycles 5 + + +### Issue Stage + +# Max number of instructions to be fetched, decoded, renamed, and issued per cycle. +--issue_width 6 + +--rs_fill_width 0 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 + + +### Exec Stage + +### DCache +--dcache_size 32768 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--dcache_assoc 4 +--dcache_line_size 64 + +### Reorder/Retire Stage + +# Max number of instructions to be retired per cycle. +--node_ret_width 6 +--node_table_size 224 + +# Do not keep stores in RSVs on cache misses; TODO: confirm what this knob does +--stores_do_not_block_window 1 + +# TODO: confirm what this knob does +--prefs_do_not_block_window 1 + + +## Uncore + +### Mid-level cache + +# Enable use of a midlevel cache between i/d and L1 +--mlc_present 0 + +### LLC +--l1_size 1048576 +--l1_banks 1 +--l1_cycles 18 +--l1_assoc 8 +--l1_line_size 64 +--l1_interleave_factor 64 + + +### Prefetcher +--pref_framework_on 1 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--pref_shared_queues 0 +--pref_train_on_pref_misses 0 +--pref_oracle_train 0 +--pref_ul1req_queue_overwrite_on_full 1 + +--stream_length 64 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 + +--pref_throttlefb_on=1 +--pref_acc_thresh_1=0.75 +--pref_acc_thresh_2=0.4 +--pref_acc_thresh_3=0.4 +--pref_timely_thresh=0.01 +--pref_polpf_thresh=0.005 +--pref_update_interval=8192 + +--mem_req_buffer_pref_watermark 4 +--promote_to_higher_priority_mem_req_type 1 + +### Memory +--addr_translation random + +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 + +--mem_req_buffer_entries 32 +--mem_l1_fill_queue_entries 32 +--va_page_size_bytes 4096 +--bus_width_in_bytes 8 + +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 + +## Other + + +### Debug +--debug_inst_start 0 +--debug_inst_stop -1 +--debug_cycle_start 0 +--debug_cycle_stop -1 + + +## Stats and Params +--dump_params 1 +--dump_stats 1 +--dump_trace 0 + +#################################### +--set_off_path_confirmed 1 + +--order_beyond_bus 1 + +--mem_ooo_stores 1 +--mem_obey_store_dep 1 diff --git a/labs/LAB5/runs/deepsjeng-sms0/PARAMS.out b/labs/LAB5/runs/deepsjeng-sms0/PARAMS.out new file mode 100644 index 00000000..190da6ad --- /dev/null +++ b/labs/LAB5/runs/deepsjeng-sms0/PARAMS.out @@ -0,0 +1,908 @@ +--mode full +--model cmp +--frontend memtrace +--inst_limit 100000000 +--sim_limit none +--dump_params 1 +--dump_stats 1 +--dump_trace 0 +--mlc_present 0 +--l1_size 1048576 +--l1_assoc 8 +--l1_line_size 64 +--l1_cycles 18 +--l1_banks 1 +--l1_interleave_factor 64 +--va_page_size_bytes 4096 +--addr_translation random +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 +--dcache_size 32768 +--dcache_assoc 4 +--dcache_line_size 64 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--mem_ooo_stores 1 +--mem_obey_store_dep 1 +--mem_req_buffer_entries 32 +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 +--promote_to_higher_priority_mem_req_type 1 +--mem_req_buffer_pref_watermark 4 +--mem_l1_fill_queue_entries 32 +--order_beyond_bus 1 +--set_off_path_confirmed 1 +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--bus_width_in_bytes 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 +--chip_cycle_time 312500 +--issue_width 6 +--rs_fill_width 0 +--node_table_size 224 +--node_ret_width 6 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 +--decode_cycles 5 +--map_cycles 5 +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--fetch_across_cache_lines 1 +--fetch_off_path_ops 0 +--fetch_break_on_taken 1 +--fetch_taken_bubble_cycles 0 +--stores_do_not_block_window 1 +--prefs_do_not_block_window 1 +--cbp_trace_r0 /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir/trace/drmemtrace.deepsjeng.553743.6815.trace.gz +--memtrace_modules_log /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir/raw +--debug_cycle_start 0 +--debug_cycle_stop -1 +--debug_inst_start 0 +--debug_inst_stop -1 +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--bp_mech tagescl +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 +--btb_off_path_writes 1 +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_length 64 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 +--pref_framework_on 1 +--pref_shared_queues 0 +--pref_ul1req_queue_overwrite_on_full 1 +--pref_train_on_pref_misses 0 +--pref_oracle_train_on 0 +--pref_throttlefb_on 1 +--pref_acc_thresh_1 0.75 +--pref_acc_thresh_2 0.4 +--pref_acc_thresh_3 0.4 +--pref_update_interval 8192 +--pref_timely_thresh 0.01 +--pref_polpf_thresh 0.005 +--pref_sms_on 0 +1 1 1 1 1 1 1 + +--- Cut out everything below to use this file as PARAMS.in --- + +Parameter status at compile time and values supplied on the command line: + +SIM_MODE 0 full +SIM_MODEL 0 cmp +FRONTEND FE_PIN_EXEC_DRIVEN memtrace +INST_LIMIT NULL 100000000 +SIM_LIMIT "none" none +FORWARD_PROGRESS_LIMIT 100000000 +FORWARD_PROGRESS_INTERVAL 10000 +FAST_FORWARD 0 +FAST_FORWARD_UNTIL_ADDR 0 +FAST_FORWARD_TRACE_INS 0 +WARMUP 0 +HEARTBEAT_INTERVAL 1000000 +NUM_HEARTBEATS 0 +FILE_TAG "" +OUTPUT_DIR "." +STATUS_FILE NULL +BINDIR NULL +DUMP_PARAMS TRUE 1 +DUMP_STATS TRUE 1 +DUMP_TRACE FALSE 0 +CLEAR_STATS "never" +STATS_TO_TRACE NULL +STAT_TRACE_FILE "stats.trace" +STAT_TRACE_INTERVAL "i:100000" +PIPEVIEW FALSE +PIPEVIEW_FILE "pipeview" +MEMVIEW FALSE +MEMVIEW_FILE "memview.out" +MEMVIEW_START "never" +INST_HASH_TABLE_SIZE 500021 const +STDOUT_FILE NULL +STDERR_FILE NULL +PIN_EXEC_DRIVEN_FE_SOCKET "./pin_exec_driven_fe_socket.temp" +PRINT_PID FALSE +USE_UNSURE_FREE_LISTS FALSE +OPTIMIZER2_MAX_NUM_SLAVES 64 +OPTIMIZER2_PERFECT_MEMORYLESS FALSE +EXIT_COND 0 +ENABLE_SWPRF FALSE +MLC_PRESENT FALSE 0 +MLC_SIZE (512 * 1024) +MLC_ASSOC 4 +MLC_LINE_SIZE 64 +MLC_CYCLES 12 +PERFECT_MLC FALSE +MLC_READ_PORTS 1 +MLC_WRITE_PORTS 1 +MLC_BANKS 8 +MLC_INTERLEAVE_FACTOR 64 +MLC_CACHE_REPL_POLICY 0 +MLC_WRITE_THROUGH FALSE +PREFETCH_UPDATE_LRU_MLC TRUE +FORCE_L1_MISS FALSE +L1_SIZE (4 * 1024 * 1024) 1048576 +L1_ASSOC 8 8 +L1_LINE_SIZE 64 64 +L1_CYCLES 24 18 +PERFECT_L1 FALSE +PRIVATE_L1 FALSE +L1_READ_PORTS 1 +L1_WRITE_PORTS 1 +L1_BANKS 8 1 +L1_INTERLEAVE_FACTOR 64 64 +L1_CACHE_REPL_POLICY 0 +L1_WRITE_THROUGH FALSE +L1_IGNORE_WB FALSE +L1_USE_CORE_FREQ FALSE +MARK_L1_MISSES TRUE +PREFETCH_UPDATE_LRU_L1 TRUE +MEMORY_RANDOM_ADDR FALSE +VA_PAGE_SIZE_BYTES 4096 4096 +NUM_ADDR_NON_SIGN_EXTEND_BITS 48 +ADDR_TRANSLATION 0 random +CONSTANT_MEMORY_LATENCY FALSE +MEMORY_CYCLES 100 +STALL_MEM_REQS_ONLY FALSE +ICACHE_SIZE (64 * 1024) 32768 +ICACHE_ASSOC 4 4 +ICACHE_LINE_SIZE 64 64 +PERFECT_ICACHE FALSE +ICACHE_READ_PORTS 2 +ICACHE_WRITE_PORTS 1 +ICACHE_BANKS 8 +ICACHE_REPL 0 +DCACHE_SIZE (64 * 1024) 32768 +DCACHE_ASSOC 1 4 +DCACHE_LINE_SIZE 64 64 +DCACHE_CYCLES 2 +PERFECT_DCACHE FALSE +DCACHE_READ_PORTS 8 2 +DCACHE_WRITE_PORTS 1 1 +DCACHE_BANKS 1 1 +DCACHE_REPL 0 +DCACHE_REPL_PREF_THRESH 1 +MEM_OOO_STORES TRUE 1 +MEM_OBEY_STORE_DEP TRUE 1 +PREF_INSERT_LRU FALSE +PREF_INSERT_MIDDLE FALSE +PREF_INSERT_LOWQTR FALSE +PREF_INSERT_DYNACC FALSE +MEM_REQ_BUFFER_ENTRIES 32 32 +PRIVATE_MSHR_ON TRUE +MEM_PRIORITY_IFETCH 0 0 +MEM_PRIORITY_DFETCH 0 1 +MEM_PRIORITY_DSTORE 0 2 +MEM_PRIORITY_IPRF 9 3 +MEM_PRIORITY_DPRF 10 4 +MEM_PRIORITY_WB 0 5 +MEM_PRIORITY_WB_NODIRTY 0 5 +PROMOTE_TO_HIGHER_PRIORITY_MEM_REQ_TYPE FALSE 1 +MEM_REQ_BUFFER_PREF_WATERMARK 0 4 +MEM_REQ_BUFFER_WB_VALVE 2 +MEM_L1_FILL_QUEUE_ENTRIES 32 32 +MEM_BUS_OUT_QUEUE_PARTITION_ENABLE FALSE +MEM_MEM_QUEUE_PARTITION_ENABLE FALSE +MEM_BUS_OUT_QUEUE_AS_FIFO TRUE +OLDEST_FIRST_TO_MEM_QUEUE TRUE +ROUND_ROBIN_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE_TH 0 +L1_CYCLE_TIME 312500 +MLCQ_TO_L1Q_TRANSFER_LATENCY 1 +L1Q_TO_FSB_TRANSFER_LATENCY 1 +PRIORITIZE_PREFETCHES_WITH_UNIQUE FALSE +KICKOUT_PREFETCHES FALSE +KICKOUT_LOOK_FOR_OLDEST_FIRST FALSE +KICKOUT_OLDEST_PREFETCH FALSE +KICKOUT_OLDEST_PREFETCH_WITHIN_BANK FALSE +ORDER_BEYOND_BUS FALSE 1 +ALL_FIFO_QUEUES FALSE +QUEUE_MLC_SIZE 0 +QUEUE_L1_SIZE 0 +QUEUE_BUS_OUT_SIZE 0 +QUEUE_CORE_FILL_SIZE 0 +ALLOW_TYPE_MATCHES FALSE +STREAM_PREFETCH_ON FALSE +DC_PREF_CACHE_ENABLE FALSE +DC_PREF_CACHE_CYCLE 0 +PREF_INSERT_DCACHE_IMM TRUE +DC_PREF_CACHE_SIZE (64 * 1024) +DC_PREF_CACHE_ASSOC 4 +DC_PREF_ONLY_L1HIT FALSE +PREF_CACHE_USE_RDY_CYCLE FALSE +IC_PREF_CACHE_ENABLE FALSE +IC_PREF_CACHE_SIZE (64 * 1024) +IC_PREF_CACHE_ASSOC 4 +L1_PREF_CACHE_ENABLE FALSE +L1_PREF_CACHE_SIZE (1024 * 1024) +L1_PREF_CACHE_ASSOC 8 +SET_OFF_PATH_CONFIRMED FALSE 1 +USE_CONFIRMED_OFF FALSE +PREFCACHE_MOVE_OFFPATH FALSE +CACHE_STAT_ENABLE FALSE +PREF_DCACHE_HIT_FILL_L1 TRUE +PREF_ICACHE_HIT_FILL_L1 TRUE +CRITICAL_ACCESS_PLOT_ENABLE FALSE +CRITICAL_ACCESS_PLOT_FILE "critical_access_plot.dat" +ROUND_ROBIN_TO_L1 FALSE +PREF_I_TOGETHER FALSE +ONE_MORE_CACHE_LINE_ENABLE FALSE +L1_STATIC_PARTITION_ENABLE 0 +L1_STATIC_PARTITION NULL +L1_DYNAMIC_PARTITION_ENABLE FALSE +L1_DYNAMIC_PARTITION_POLICY 0 +PARTITION_UMON_DSS_PREF_ENABLE FALSE +L1_CACHE_HIT_POSITION_COLLECT FALSE +L1_PART_ON FALSE +L1_PART_TRIGGER "c:1000000" +L1_PART_START "t:0" +L1_PART_WARMUP FALSE +L1_PART_SHADOW_WARMUP FALSE +L1_PART_METRIC 0 +L1_PART_SEARCH 0 +L1_PART_USE_STALLING TRUE +L1_PART_FILL_DELAY 0 +L1_SHADOW_TAGS_MODULO 1 +HIER_MSHR_ON FALSE +PERF_PRED_ENABLE FALSE +PERF_PRED_MECH PERF_PRED_CP +PERF_PRED_REQ_LATENCY_MECH PERF_PRED_REQ_LATENCY_MECH_REQ_LATENCY +PERF_PRED_COUNT_ALL FALSE +PERF_PRED_COUNT_INST_MISSES TRUE +PERF_PRED_COUNT_PREFETCHES FALSE +PERF_PRED_COUNT_OFFPATH_REQS FALSE +PERF_PRED_COUNT_BW_REQS TRUE +PERF_PRED_UPDATE_MEM_REQ_TYPE FALSE +PERF_PRED_SLACK_PERIOD_SIZE 32 +PERF_PRED_REQS_FINISH_AT_FILL FALSE +PERF_PRED_MEM_UTIL_VIA_BUS_BW FALSE +PERF_PRED_CHIP_UTIL_VIA_MEM_STALL FALSE +DUMB_MODEL_AVG_REQ_DISTANCE 100 +DUMB_MODEL_RANDOMIZE_DISTANCE FALSE +DUMB_MODEL_AVG_REQ_DISTANCE_PER_CORE NULL +DUMB_MODEL_AVG_ROW_HITS 1 +DUMB_MODEL_AVG_ROW_HITS_PER_CORE NULL +DUMB_MODEL_MLP 1 +DUMB_MODEL_MLP_PER_CORE NULL +RAMULATOR_STANDARD "DDR4" DDR4 +RAMULATOR_SPEED "DDR4_2400R" DDR4_2400R +RAMULATOR_ORG "DDR4_8Gb_x8" DDR4_8Gb_x8 +RAMULATOR_CHANNELS 1 1 +RAMULATOR_RANKS 1 1 +RAMULATOR_BANKGROUPS 4 4 +RAMULATOR_BANKS 4 4 +RAMULATOR_CHIP_WIDTH 8 8 +BUS_WIDTH_IN_BYTES 8 8 +RAMULATOR_ROWS 65536 65536 +RAMULATOR_COLS 1024 1024 +RAMULATOR_SCHEDULING_POLICY "FRFCFS_Cap" FRFCFS_Cap +RAMULATOR_READQ_ENTRIES 32 32 +RAMULATOR_WRITEQ_ENTRIES 32 32 +RAMULATOR_REC_CMD_TRACE "off" FALSE +RAMULATOR_PRINT_CMD_TRACE "off" FALSE +RAMULATOR_USE_REST_OF_ADDR_AS_ROW_ADDR "on" +RAMULATOR_TCK 833333 833333 +RAMULATOR_TCL 16 16 +RAMULATOR_TCCD 6 6 +RAMULATOR_TCCDS 4 4 +RAMULATOR_TCCDL 6 6 +RAMULATOR_TCWL 12 12 +RAMULATOR_TBL 4 4 +RAMULATOR_TWTR 9 9 +RAMULATOR_TWTRS 3 3 +RAMULATOR_TWTRL 9 9 +RAMULATOR_TRP 16 16 +RAMULATOR_TRPpb 16 16 +RAMULATOR_TRPab 16 16 +RAMULATOR_TRCD 16 16 +RAMULATOR_TRCDR 16 16 +RAMULATOR_TRCDW 16 16 +RAMULATOR_TRAS 39 39 +DRAM_TECH_IN_NM 32 32 +DVFS_ON FALSE +DVFS_METRIC DVFS_METRIC_NUM_ELEMS +DVFS_CONFIGS NULL +DVFS_CONFIG_FILE NULL +DVFS_START "t:0" +DVFS_PERIOD "t:312500000000" +DVFS_LOG TRUE +DVFS_INDIVIDUAL_CORES FALSE +DVFS_CHIP_LEVEL FALSE +DVFS_STATIC NULL +DVFS_FORCE_CONFIG NULL +DVFS_REPLAY_CONFIG_TRACE NULL +DVFS_USE_ORACLE FALSE +DVFS_USE_BW_SHARING FALSE +DVFS_USE_DRAM_SHARING FALSE +DVFS_USE_STALL_TIME FALSE +DVFS_DRAM_SHARING_SOLVER_BIN NULL +DVFS_DRAM_SHARING_SOLVER_STRICT TRUE +DVFS_BW_SHARING_BUS_UTIL_THRESH 0.95 +DVFS_BW_SHARING_MAX_REQS 28.0 +DVFS_BW_SHARING_MAX_RW_COST 0.25 +DVFS_BW_SHARING_NO_PREF_STALL TRUE +DVFS_BW_SHARING_CRIT_STATS TRUE +DVFS_COUNT_L1_ACCESS_STALL FALSE +NUM_CORES 1 +CHIP_CYCLE_TIME 312500 312500 +CORE_0_CYCLE_TIME 312500 +CORE_1_CYCLE_TIME 312500 +CORE_2_CYCLE_TIME 312500 +CORE_3_CYCLE_TIME 312500 +CORE_4_CYCLE_TIME 312500 +CORE_5_CYCLE_TIME 312500 +CORE_6_CYCLE_TIME 312500 +CORE_7_CYCLE_TIME 312500 +CORE_8_CYCLE_TIME 312500 +CORE_9_CYCLE_TIME 312500 +CORE_10_CYCLE_TIME 312500 +CORE_11_CYCLE_TIME 312500 +CORE_12_CYCLE_TIME 312500 +CORE_13_CYCLE_TIME 312500 +CORE_14_CYCLE_TIME 312500 +CORE_15_CYCLE_TIME 312500 +CORE_16_CYCLE_TIME 312500 +CORE_17_CYCLE_TIME 312500 +CORE_18_CYCLE_TIME 312500 +CORE_19_CYCLE_TIME 312500 +CORE_20_CYCLE_TIME 312500 +CORE_21_CYCLE_TIME 312500 +CORE_22_CYCLE_TIME 312500 +CORE_23_CYCLE_TIME 312500 +CORE_24_CYCLE_TIME 312500 +CORE_25_CYCLE_TIME 312500 +CORE_26_CYCLE_TIME 312500 +CORE_27_CYCLE_TIME 312500 +CORE_28_CYCLE_TIME 312500 +CORE_29_CYCLE_TIME 312500 +CORE_30_CYCLE_TIME 312500 +CORE_31_CYCLE_TIME 312500 +CORE_32_CYCLE_TIME 312500 +CORE_33_CYCLE_TIME 312500 +CORE_34_CYCLE_TIME 312500 +CORE_35_CYCLE_TIME 312500 +CORE_36_CYCLE_TIME 312500 +CORE_37_CYCLE_TIME 312500 +CORE_38_CYCLE_TIME 312500 +CORE_39_CYCLE_TIME 312500 +CORE_40_CYCLE_TIME 312500 +CORE_41_CYCLE_TIME 312500 +CORE_42_CYCLE_TIME 312500 +CORE_43_CYCLE_TIME 312500 +CORE_44_CYCLE_TIME 312500 +CORE_45_CYCLE_TIME 312500 +CORE_46_CYCLE_TIME 312500 +CORE_47_CYCLE_TIME 312500 +CORE_48_CYCLE_TIME 312500 +CORE_49_CYCLE_TIME 312500 +CORE_50_CYCLE_TIME 312500 +CORE_51_CYCLE_TIME 312500 +CORE_52_CYCLE_TIME 312500 +CORE_53_CYCLE_TIME 312500 +CORE_54_CYCLE_TIME 312500 +CORE_55_CYCLE_TIME 312500 +CORE_56_CYCLE_TIME 312500 +CORE_57_CYCLE_TIME 312500 +CORE_58_CYCLE_TIME 312500 +CORE_59_CYCLE_TIME 312500 +CORE_60_CYCLE_TIME 312500 +CORE_61_CYCLE_TIME 312500 +CORE_62_CYCLE_TIME 312500 +CORE_63_CYCLE_TIME 312500 +ISSUE_WIDTH 4 6 +RS_FILL_WIDTH 8 0 +NODE_TABLE_SIZE 256 224 +NODE_RET_WIDTH 4 6 +NODE_RETIRE_RATE 10 +RS_SIZES "256" 97 +RS_CONNECTIONS "xF" 0 +FU_TYPES "0, 0, 0, 0" 0 0 0 0 0 0 0 0 +DECODE_CYCLES 1 5 +MAP_CYCLES 1 5 +EXTRA_RECOVERY_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after recovery. +EXTRA_REDIRECT_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after redirect. +EXTRA_CALLSYS_CYCLES 20 const +DIE_ON_CALLSYS FALSE +DIE_ON_RET_STALL_THRESH 0 +DIE_ON_RET_STALL_CORE 0 +DIE_ON_MEM_BLOCK_THRESH 0 +DIE_ON_MEM_BLOCK_CORE 0 +FETCH_ACROSS_CACHE_LINES FALSE 1 +FETCH_OFF_PATH_OPS TRUE 0 +FETCH_BREAK_ON_TAKEN FALSE 1 +FETCH_TAKEN_BUBBLE_CYCLES 0 0 +WP_COLLECT_STATS FALSE +SWITCH_IC_FETCH_ON_RECOVERY TRUE +OP_INV_DELAY 1 +OP_NOP_DELAY 1 +OP_CF_DELAY 1 +OP_MOV_DELAY 1 +OP_CMOV_DELAY 1 +OP_LDA_DELAY 1 +OP_IMEM_DELAY 1 +OP_IADD_DELAY 1 +OP_IMUL_DELAY 3 +OP_IDIV_DELAY -20 +OP_ICMP_DELAY 1 +OP_LOGIC_DELAY 1 +OP_SHIFT_DELAY 1 +OP_FMEM_DELAY 1 +OP_FCVT_DELAY 3 +OP_FADD_DELAY 3 +OP_FMUL_DELAY 5 +OP_FMA_DELAY 5 +OP_FDIV_DELAY -20 +OP_FCMP_DELAY 3 +OP_FCMOV_DELAY 1 +OP_GATHER_DELAY 12 +OP_SCATTER_DELAY 18 +OP_PIPELINED_FAST_DELAY 2 +OP_PIPELINED_MEDIUM_DELAY 5 +OP_PIPELINED_SLOW_DELAY 10 +OP_NOTPIPELINED_MEDIUM_DELAY -5 +OP_NOTPIPELINED_SLOW_DELAY -20 +OP_NOTPIPELINED_VERY_SLOW_DELAY -100 +UNIFORM_OP_DELAY 0 +STALL_ON_WAIT_MEM TRUE +STORES_DO_NOT_BLOCK_WINDOW FALSE 1 +PREFS_DO_NOT_BLOCK_WINDOW FALSE 1 +OBEY_REG_DEP TRUE +OLDEST_FIRST_SCHED FALSE +FIND_EMPTIEST_RS FALSE +TRACK_L1_MISS_DEPS FALSE +CBP_TRACE_R0 NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir/trace/drmemtrace.deepsjeng.553743.6815.trace.gz +CBP_TRACE_R1 NULL +CBP_TRACE_R2 NULL +CBP_TRACE_R3 NULL +CBP_TRACE_R4 NULL +CBP_TRACE_R5 NULL +CBP_TRACE_R6 NULL +CBP_TRACE_R7 NULL +CBP_TRACE_R8 NULL +CBP_TRACE_R9 NULL +CBP_TRACE_R10 NULL +CBP_TRACE_R11 NULL +CBP_TRACE_R12 NULL +CBP_TRACE_R13 NULL +CBP_TRACE_R14 NULL +CBP_TRACE_R15 NULL +CBP_TRACE_R16 NULL +CBP_TRACE_R17 NULL +CBP_TRACE_R18 NULL +CBP_TRACE_R19 NULL +CBP_TRACE_R20 NULL +CBP_TRACE_R21 NULL +CBP_TRACE_R22 NULL +CBP_TRACE_R23 NULL +CBP_TRACE_R24 NULL +CBP_TRACE_R25 NULL +CBP_TRACE_R26 NULL +CBP_TRACE_R27 NULL +CBP_TRACE_R28 NULL +CBP_TRACE_R29 NULL +CBP_TRACE_R30 NULL +CBP_TRACE_R31 NULL +CBP_TRACE_R32 NULL +CBP_TRACE_R33 NULL +CBP_TRACE_R34 NULL +CBP_TRACE_R35 NULL +CBP_TRACE_R36 NULL +CBP_TRACE_R37 NULL +CBP_TRACE_R38 NULL +CBP_TRACE_R39 NULL +CBP_TRACE_R40 NULL +CBP_TRACE_R41 NULL +CBP_TRACE_R42 NULL +CBP_TRACE_R43 NULL +CBP_TRACE_R44 NULL +CBP_TRACE_R45 NULL +CBP_TRACE_R46 NULL +CBP_TRACE_R47 NULL +CBP_TRACE_R48 NULL +CBP_TRACE_R49 NULL +CBP_TRACE_R50 NULL +CBP_TRACE_R51 NULL +CBP_TRACE_R52 NULL +CBP_TRACE_R53 NULL +CBP_TRACE_R54 NULL +CBP_TRACE_R55 NULL +CBP_TRACE_R56 NULL +CBP_TRACE_R57 NULL +CBP_TRACE_R58 NULL +CBP_TRACE_R59 NULL +CBP_TRACE_R60 NULL +CBP_TRACE_R61 NULL +CBP_TRACE_R62 NULL +CBP_TRACE_R63 NULL +MEMTRACE_MODULES_LOG NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir/raw +DUMB_CORE_ON FALSE +DUMB_CORE 1 +DEBUG_CYCLE_START 0 0 +DEBUG_CYCLE_STOP 0 -1 +DEBUG_TIME_START 0 +DEBUG_TIME_STOP 0 +DEBUG_INST_START 0 0 +DEBUG_INST_STOP 0 -1 +DEBUG_OP_START 0 +DEBUG_OP_STOP 0 +DEBUG_CACHE_LIB FALSE +DEBUG_HASH_LIB FALSE +DEBUG_LIST_LIB FALSE +DEBUG_PORT_LIB FALSE +DEBUG_BUS_LIB FALSE +DEBUG_OP_POOL FALSE +DEBUG_ORACLE FALSE +DEBUG_FRONTEND FALSE +DEBUG_ADDR_TRANS FALSE +DEBUG_BP FALSE +DEBUG_BP_DIR FALSE +DEBUG_BTB FALSE +DEBUG_CRS FALSE +DEBUG_MAP FALSE +DEBUG_MEMORY FALSE +DEBUG_REPLAY FALSE +DEBUG_FREQ FALSE +DEBUG_MODEL FALSE +DEBUG_THREAD FALSE +DEBUG_ICACHE_STAGE FALSE +DEBUG_DECODE_STAGE FALSE +DEBUG_MAP_STAGE FALSE +DEBUG_NODE_STAGE FALSE +DEBUG_EXEC_STAGE FALSE +DEBUG_DCACHE_STAGE FALSE +DEBUG_RETIRED_UOPS FALSE +DEBUG_EXC_INSERTS FALSE +DEBUG_BP_CONF FALSE +DEBUG_ONPATH_CONF FALSE +DEBUG_STREAM FALSE +DEBUG_STREAM_MEM FALSE +DEBUG_WAY FALSE +DEBUG_L2MARKV FALSE +DEBUG_L2L1PREF FALSE +DEBUG_PERF_PRED FALSE +DEBUG_POWER_UTILS FALSE +DEBUG_DVFS FALSE +DEBUG_TRACE_READ FALSE +DEBUG_INST_FIELDS FALSE +DEBUG_OP_FIELDS FALSE +DEBUG_PIN_EXEC_DRIVEN FALSE +DEBUG_CACHE_PART FALSE +DEBUG_OPTIMIZER2 FALSE +DEBUG_PREF FALSE +PERFECT_BP FALSE +PERFECT_BTB FALSE +PERFECT_IBP FALSE +PERFECT_CRS FALSE +PERFECT_CBR_BTB FALSE +PERFECT_NT_BTB FALSE +CFS_PER_CYCLE 3 6 # Number of branches that can be predicted in a single cycle +UPDATE_BP_OFF_PATH FALSE 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +BP_UPDATE_AT_RETIRE FALSE 0 # Update the BP at retire. If false, update at the end of exec. +BP_MECH 0 tagescl +LATE_BP_MECH NUM_BP +LATE_BP_LATENCY 5 +HIST_LENGTH 16 +PHT_CTR_BITS 2 const +BHT_ENTRIES (4 * 1024) +BHT_ASSOC 4 +HYBRIDS_INDEX_LENGTH 16 +HYBRIDG_HIST_LENGTH 16 +HYBRIDP_HIST_LENGTH 16 +FILTER_INDEX_LENGTH 16 +USE_FILTER FALSE +INF_HYBRIDGP FALSE +BP_HASH_TOS FALSE +IBTB_HASH_TOS FALSE +BTB_MECH 0 generic +BTB_ENTRIES (4 * 1024) 4096 +BTB_ASSOC 4 4 +BTB_OFF_PATH_WRITES TRUE 1 +ENABLE_CRS TRUE 1 +CRS_ENTRIES 32 32 +CRS_REALISTIC 0 1 +ENABLE_IBP TRUE 1 # Enable the indirect branch predictor +USE_PAT_HIST TRUE +IBTB_MECH 1 tc_tagged +IBTB_HIST_LENGTH 16 +IBTB_OFF_PATH_WRITES TRUE 1 # Allow off path ops to update the ibtb. +TARGETS_IN_HIST 4 +TC_ENTRIES (4 * 1024) 4096 +TC_ASSOC 4 4 +NUM_CORR_BRANCHES 3 +SEL_HIST_BP_ENTRIES 8192 +SEL_HIST_LENGTH 16 +SEL_HIST_DYN_CNT_TH 16 +SEL_HIST_MISPRED_TH 4 +ENABLE_BP_CONF FALSE +CONF_MECH 0 +PERF_BP_CONF_PRED FALSE +BPC_BITS 16 +BPC_MECH 1 +BPC_CTR_RESET TRUE +BPC_CIT_BITS 8 +BPC_CIT_TH 50 +BPC_CTR_BITS 3 +OPC_COUNT_ZEROS FALSE +OPC_COUNT_THRESH 10 +INF_LOOP FALSE +INF_LOOP_BUCKETS 811 +LOOP_ENTRIES (4 * 1024) +LOOP_ASSOC 4 +LOOP_COUNT_MAX 127 +LOOP_REPEAT_MAX 15 +KNOB_PRINT_BRINFO FALSE +BR_MISPRED_FILE NULL +CONF_PERCEPTRON_TH 0 +CONF_PERCEPTRON_CTR_BITS 8 +CONF_PERCEPTRON_ENTRIES 127 +CONF_PERCEPTRON_THRESH_OVRD 0 +CONF_HIST_LENGTH 32 +PERCEPTRON_CONF_USE_CONF FALSE +PERCEPTRON_CONF_TRAIN_HIS FALSE +PERCEPTRON_CONF_TRAIN_CONF FALSE +PERCEPTRON_CONF_TRAIN_OFFSET_CONF FALSE +PERCEPTRON_TRAIN_MISP_FACTOR 1 +PERCEPTRON_TRAIN_CORR_FACTOR 1 +PERCEPTRON_CONF_HIS_BOTH FALSE +PERCEPTRON_CONF_HIS_BOTH_LENGTH 4 +ENABLE_ICACHE_PACKET_BREAKING TRUE +NUM_LOAD_STORE_PER_PACKET 0 +PACKET_BREAK_ON_FUS FALSE +PACKET_BREAK_FU_TYPES "G,G,G,G,G,G,G,G,G,G,G,G" +POWER_INTF_ON FALSE +POWER_INTF_ENABLE_SCALING FALSE +POWER_INTF_EXEC "power/power_intf.py" +POWER_INTF_REF_CHIP_TECH_NM 22 +POWER_INTF_REF_CHIP_FREQ (3.2e9) +POWER_INTF_REF_MEMORY_FREQ (0.8e9) +POWER_OTHER (0.0) +PREF_STREAM_ON FALSE 1 +PREF_STREAM_PER_CORE_ENABLE FALSE 1 +STREAM_BUFFER_N 16 +STREAM_PREFETCH_N 2 4 +STREAM_START_DIS 5 1 +STREAM_LENGTH 16 64 +STREAM_FULL_N 1 +STREAM_TRAIN_LENGTH 16 +STREAM_TRAIN_NUM 1 4 +PREF_ACC_USE_CACHE FALSE +STREAM_STALL_ON_QUEUE_FULL FALSE +PREF_SCHEDULE_NUM 4 +TRAIN_FILTER_SIZE 32 +PREF_REQ_Q_SIZE 64 +STREAM_CREATE_ON_DC_MISS FALSE 0 +STREAM_CREATE_ON_L1_MISS TRUE 1 +STREAM_TRAIN_ON_WRONGPATH TRUE +STREAM_CREATE_ON_WRONGPATH TRUE +STREAM_PREF_INTO_DCACHE FALSE +REMOVE_REDUNDANT_STREAM FALSE +L2HIT_STREAM_SCHEDULE_NUM 4 +PREF_REQ_QUEUE_FILTER_ON FALSE +HW_PREF_HIT_TRAIN_STREAM FALSE +L2HIT_STREAM_BUFFER_N 32 +L2HIT_STREAM_PREFETCH_N 2 +L2HIT_STREAM_START_DIS 2 +L2HIT_STREAM_LENGTH 8 +L2HIT_PREF_REQ_Q_SIZE 128 +L2HIT_L2ACCESS_REQ_Q_SIZE 64 +PREF_STREAM_ACCPERSTREAM FALSE +PREF_ACC_DISTANCE_10 128 +PREF_FRAMEWORK_ON FALSE 1 +PREF_TRACE_ON FALSE +PREF_DL0REQ_QUEUE_SIZE 32 +PREF_UMLC_REQ_QUEUE_SIZE 64 +PREF_UL1REQ_QUEUE_SIZE 128 +PREF_SHARED_QUEUES TRUE 0 +PREF_DL0_MISS_ON TRUE +PREF_DL0_HIT_ON TRUE +PREF_DL0REQ_QUEUE_FILTER_ON TRUE +PREF_UMLC_REQ_QUEUE_FILTER_ON TRUE +PREF_UL1REQ_QUEUE_FILTER_ON TRUE +PREF_DL0REQ_ADD_FILTER_ON TRUE +PREF_UMLC_REQ_ADD_FILTER_ON TRUE +PREF_UL1REQ_ADD_FILTER_ON TRUE +PREF_DL0REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UMLC_REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UL1REQ_QUEUE_OVERWRITE_ON_FULL FALSE 1 +PREF_DL0SCHEDULE_NUM 4 +PREF_UMLC_SCHEDULE_NUM 4 +PREF_UL1SCHEDULE_NUM 4 +PREF_L1Q_DEMAND_RESERVE 0 +PREF_REPORT_PREF_MATCH_AS_MISS FALSE +PREF_REPORT_PREF_MATCH_AS_HIT TRUE +PREF_UPDATE_ON_WRONGPATH TRUE +PREF_TRAIN_ON_PREF_MISSES FALSE 0 +PREF_ORACLE_TRAIN_ON FALSE 0 +PREF_REQ_DROP FALSE +PREF_THROTTLE_ON FALSE +PREF_THROTTLEFB_ON FALSE 1 +PREF_ACC_THRESH_1 0.90 0.75 +PREF_ACC_THRESH_2 0.70 0.4 +PREF_ACC_THRESH_3 0.60 0.4 +PREF_ACC_THRESH_4 0.40 +PREF_UPDATE_INTERVAL 0 8192 +PREF_ANALYZE_LOAD FALSE +PREF_POL_THRESH_1 0.25 +PREF_POL_THRESH_2 0.10 +PREF_POLBV_ON FALSE +PREF_POLBV_SIZE 1024 +PREF_TIMELY_THRESH 0.05 0.01 +PREF_POLPF_THRESH 0.01 0.005 +PREF_DEGFB_USEONLYACC FALSE +PREF_DEGFB_USEONLYPOL FALSE +PREF_DEGFB_USEONLYLATE FALSE +PREF_TIMELY_THRESH_2 0.005 +PREF_DEGFB_STATPHASEFILE FALSE +PREF_MAX_DEGFB 4 +PREF_DHAL FALSE +PREF_DHAL_SENTTHRESH 16 +PREF_DHAL_USETHRESH_MAX 12 +PREF_DHAL_USETHRESH_MIN2 8 +PREF_DHAL_USETHRESH_MIN1 4 +PREF_DHAL_MAXDEG 64 +PREF_HFILTER_ON FALSE +PREF_HFILTER_INDEX_BITS 12 +PREF_HFILTER_USE_PC FALSE +PREF_HFILTER_PRED_USELESS_THRES 2 +PREF_HFILTER_RESET_ENABLE FALSE +PREF_HFILTER_RESET_INTERVAL 100000 +L2L1PREF_ON FALSE +L2WAY_PREF FALSE +L2MARKV_PREF_ON FALSE +L2NEXT_PREF_ON FALSE +L2HIT_STREAM_PREF_ON FALSE +L2L1_DC_HIT_TRAIN FALSE +L1_HIT_DUMP_FILE_ON FALSE +L1_HIT_DUMP_WO_TXT FALSE +L1_HIT_DUMPFILE "l1hit_dump.out" +IDEAL_L2_L1_PREFETCHER FALSE +IDEAL_L2_ICACHE_PREFETCHER FALSE +L1WAY_PREF_SEND_QUEUE 4 +L1PREF_REQ_QUEUE_SIZE 1024 +L1PREF_IMMEDIATE FALSE +L1WAY_PREF_TIMER_DIS 1000 +L1MARKV_PREF_SEND_QUEUE 4 +L1PREF_MARKV_REQ_QUEUE_SIZE 1024 +MARKV_L2ACCESS_REQ_Q_SIZE 64 +L1MARKV_PREF_IMMEDIATE FALSE +L1MARKV_PREF_TIMER_DIS 1 +L2L1_HIT_TRAIN TRUE +L1MARKV_REQ_TH 1 +L2L1_IMMEDIATE_PREF_CACHE FALSE +L2L1_FILL_PREF_CACHE FALSE +L2L1_L2_HIT_STAT FALSE +PREF_GHB_ON FALSE +DEBUG_PREF_GHB FALSE +PREF_GHB_BUFFER_N 1024 +PREF_GHB_INDEX_N 128 +PREF_GHB_CZONE_BITS 12 +PREF_GHB_DEGREE 16 +PREF_GHB_MAX_DEGREE 32 +PREF_STRIDE_ON FALSE +DEBUG_PREF_STRIDE FALSE +PREF_STRIDE_TABLE_N 1024 +PREF_STRIDE_REGION_BITS 16 +PREF_STRIDE_DEGREE 4 +PREF_STRIDE_DISTANCE 16 +PREF_STRIDE_STARTDISTANCE 1 +PREF_STRIDE_SINGLE_THRESH 6 +PREF_STRIDE_MULTI_THRESH 6 +PREF_STRIDE_SINGLE_STRIDE_MODE FALSE +PREF_STRIDEPC_ON FALSE +DEBUG_PREF_STRIDEPC FALSE +PREF_STRIDEPC_TABLE_N 1024 +PREF_STRIDEPC_DEGREE 4 +PREF_STRIDEPC_DISTANCE 16 +PREF_STRIDEPC_USELOADADDR FALSE +PREF_STRIDEPC_TRAINNUM 2 +PREF_STRIDEPC_STARTDIS 4 +PREF_PHASE_ON FALSE +PREF_PHASE_STUDY FALSE +DEBUG_PREF_PHASE FALSE +PREF_PHASE_PRIME_HASH 16381 +PREF_PHASE_INFOSIZE 16384 +PREF_PHASE_LOG2REGIONSIZE 12 +PREF_PHASE_REGIONENTRIES 64 +PREF_PHASE_TRACKEDREGIONS 32 +PREF_PHASE_INTERVAL 100000 +PREF_PHASE_TABLE_SIZE 64 +PREF_PHASE_MAXDIFF_THRESH 64 +PREF_PHASE_MIN_MISSES 64 +PREF_PHASE_MISSPER 0.4 +PREF_2DC_ON FALSE +DEBUG_PREF_2DC FALSE +PREF_2DC_CACHE_SIZE (1 * 1024) +PREF_2DC_CACHE_ASSOC 4 +PREF_2DC_CACHE_LINE_SIZE 1 +PREF_2DC_DEGREE 16 +PREF_2DC_ZONE_SHIFT 10 +PREF_2DC_TAG_SIZE 16 +PREF_2DC_NUM_REGIONS 64 +PREF_2DC_REGION_HASH 61 +PREF_MARKOV_ON FALSE +DEBUG_PREF_MARKOV FALSE +PREF_MARKOV_NUM_ENTRIES 65536 +PREF_MARKOV_NUM_NEXT_STATES 8 +PREF_MARKOV_SEND_ON_PREF_HIT TRUE +PREF_MARKOV_UPDATE_ON_PREF_HIT TRUE +PREF_MARKOV_TABLE_UPDATE_POLICY 0 +PREF_MARKOV_SEND_THRESHOLD 0 +PREF_SMS_ON FALSE 0 +PREF_SMS_AT_SIZE 64 +PREF_SMS_FT_SIZE 64 +PREF_SMS_PHT_SIZE 16384 +PREF_SMS_PRF_SIZE 1024 +PREF_SMS_REGION_SIZE 2048 diff --git a/labs/LAB5/runs/deepsjeng-sms0/bp.stat.0.out b/labs/LAB5/runs/deepsjeng-sms0/bp.stat.0.out new file mode 100644 index 00000000..45197d54 --- /dev/null +++ b/labs/LAB5/runs/deepsjeng-sms0/bp.stat.0.out @@ -0,0 +1,752 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 50809793 Instructions: 100000000 IPC: 1.96812 + +BTB_ON_PATH_MISS 50498 0.349% 50498 0.349% +BTB_ON_PATH_HIT 14409909 99.651% 14409909 99.651% + 14460407 100.000% 14460407 100.000% + 1.00 0.99 1.00 0.99 + +BTB_OFF_PATH_MISS 0 -nan% 0 -nan% +BTB_OFF_PATH_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BTB_ON_PATH_WRITE 50498 100.000% 50498 100.000% +BTB_OFF_PATH_WRITE 0 0.000% 0 0.000% + 50498 100.000% 50498 100.000% + 0.00 0.00 0.00 0.00 + +BP_ON_PATH_CORRECT 13251800 91.642% 13251800 91.642% +BP_ON_PATH_MISPREDICT 350831 2.426% 350831 2.426% +BP_ON_PATH_MISFETCH 857776 5.932% 857776 5.932% + 14460407 100.000% 14460407 100.000% + 0.14 0.47 0.14 0.47 + +BP_OFF_PATH_CORRECT 0 -nan% 0 -nan% +BP_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% +BP_OFF_PATH_MISFETCH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +LATE_BP_ON_PATH_CORRECT 14460407 100.000% 14460407 100.000% +LATE_BP_ON_PATH_MISPREDICT 0 0.000% 0 0.000% +LATE_BP_ON_PATH_MISFETCH 0 0.000% 0 0.000% + 14460407 100.000% 14460407 100.000% + 0.00 0.00 0.00 0.00 + +LATE_BP_OFF_PATH_CORRECT 0 -nan% 0 -nan% +LATE_BP_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% +LATE_BP_OFF_PATH_MISFETCH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_PVN 0 -nan% 0 -nan% +BP_ON_PATH_CONF_PVN_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_PVP 0 -nan% 0 -nan% +BP_ON_PATH_CONF_PVP_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_SPEC 0 -nan% 0 -nan% +BP_ON_PATH_CONF_SPEC_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CRS_MISS_ON_PATH 41724 2.069% 41724 2.069% +CRS_HIT_ON_PATH 1975105 97.931% 1975105 97.931% + 2016829 100.000% 2016829 100.000% + 0.98 0.97 0.98 0.97 + +CRS_MISS_OFF_PATH 0 -nan% 0 -nan% +CRS_HIT_OFF_PATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CRS_CLOBBER 0 0 + +TARG_ON_PATH_MISS 2362 29.956% 2362 29.956% +TARG_ON_PATH_HIT 5523 70.044% 5523 70.044% + 7885 100.000% 7885 100.000% + 0.70 0.64 0.70 0.64 + +TARG_OFF_PATH_MISS 0 -nan% 0 -nan% +TARG_OFF_PATH_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_ON_PATH_WRITE 7885 100.000% 7885 100.000% +TARG_OFF_PATH_WRITE 0 0.000% 0 0.000% + 7885 100.000% 7885 100.000% + 0.00 0.00 0.00 0.00 + +TARG_HYBRID_CORRECT_TAGLESS 0 -nan% 0 -nan% +TARG_HYBRID_CORRECT_TAGGED 0 -nan% 0 -nan% +TARG_HYBRID_MISPRED_TAGLESS 0 -nan% 0 -nan% +TARG_HYBRID_MISPRED_TAGGED 0 -nan% 0 -nan% +TARG_HYBRID_NO_PRED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_VP_INDIRECT_MISPRED 0 -nan% 0 -nan% +TARG_VP_INDIRECT_NOPRED 0 -nan% 0 -nan% +TARG_VP_INDIRECT_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CBR_ON_PATH_CORRECT 9066824 96.275% 9066824 96.275% +CBR_ON_PATH_MISPREDICT 350831 3.725% 350831 3.725% + 9417655 100.000% 9417655 100.000% + 0.04 0.19 0.04 0.19 + +CBR_ON_PATH_CORRECT_PER1000INST 9066824 90.6682 9066824 90.6682 + +CBR_ON_PATH_MISPREDICT_PER1000INST 350831 3.5083 350831 3.5083 + +CBR_OFF_PATH_CORRECT 0 -nan% 0 -nan% +CBR_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PRED_TO_UPDATE_CYCLES_0 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_1 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_2 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_3 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_4 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_5 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_6 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_7 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_8 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_9 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_10 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_11 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_12 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_13 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_14 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_15 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_16 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_17 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_18 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_19 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_20 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_21 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_22 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_23 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_24 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_25 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_26 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_27 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_28 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_29 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_30 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_CORRECTED 0 -nan% 0 -nan% +BP_NOT_CORRECTED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_CORRECTED 0 -nan% 0 -nan% +TARG_NOT_CORRECTED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_MISP_PENALTY 10101622 10101622 + +BP_ON_PATH_CONF_MISPRED 0 -nan% 0 -nan% +BP_ON_PATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_OFF_PATH_CONF_MISPRED 0 -nan% 0 -nan% +BP_OFF_PATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_PRED_MIS_CONF_MISPRED 0 -nan% 0 -nan% +BP_ON_PATH_PRED_MIS_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_PRED_COR_CONF_MISPRED 0 -nan% 0 -nan% +BP_ON_PATH_PRED_COR_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_OFF_PATH_PRED_MIS_CONF_MISPRED 0 -nan% 0 -nan% +BP_OFF_PATH_PRED_MIS_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_OFF_PATH_PRED_COR_CONF_MISPRED 0 -nan% 0 -nan% +BP_OFF_PATH_PRED_COR_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ONPATH_CONF_MISPRED 0 -nan% 0 -nan% +ONPATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ONPATH_ON_PATH_CONF_MISPRED 0 -nan% 0 -nan% +ONPATH_ON_PATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ONPATH_OFF_PATH_CONF_MISPRED 0 -nan% 0 -nan% +ONPATH_OFF_PATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PRED_ONPATH_CONF_MISPRED 0 -nan% 0 -nan% +PRED_ONPATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PRED_OFFPATH_CONF_MISPRED 0 -nan% 0 -nan% +PRED_OFFPATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +LONG_OVWT_MIS 0 -nan% 0 -nan% +LONG_OVWT_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_0_7_MIS 0 -nan% 0 -nan% +OPC_LENGTH_0_7_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_8_15_MIS 0 -nan% 0 -nan% +OPC_LENGTH_8_15_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_16_23_MIS 0 -nan% 0 -nan% +OPC_LENGTH_16_23_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_24_31_MIS 0 -nan% 0 -nan% +OPC_LENGTH_24_31_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_32_39_MIS 0 -nan% 0 -nan% +OPC_LENGTH_32_39_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_40_47_MIS 0 -nan% 0 -nan% +OPC_LENGTH_40_47_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_48_55_MIS 0 -nan% 0 -nan% +OPC_LENGTH_48_55_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_56_63_MIS 0 -nan% 0 -nan% +OPC_LENGTH_56_63_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_64_71_MIS 0 -nan% 0 -nan% +OPC_LENGTH_64_71_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_72_79_MIS 0 -nan% 0 -nan% +OPC_LENGTH_72_79_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_80_MIS 0 -nan% 0 -nan% +OPC_LENGTH_80_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ALL_ONES_MIS 0 -nan% 0 -nan% +ALL_ONES_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan 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--git a/labs/LAB5/runs/deepsjeng-sms0/inst.stat.0.out b/labs/LAB5/runs/deepsjeng-sms0/inst.stat.0.out new file mode 100644 index 00000000..82036087 --- /dev/null +++ b/labs/LAB5/runs/deepsjeng-sms0/inst.stat.0.out @@ -0,0 +1,103 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 50809793 Instructions: 100000000 IPC: 1.96812 + +ST_OP_INV 0 0.000% 0 0.000% +ST_OP_NOP 2324066 1.917% 2324066 1.917% +ST_OP_CF 14460410 11.931% 14460410 11.931% +ST_OP_MOV 14118958 11.649% 14118958 11.649% +ST_OP_CMOV 426561 0.352% 426561 0.352% +ST_OP_LDA 7123151 5.877% 7123151 5.877% +ST_OP_IMEM 37070597 30.585% 37070597 30.585% +ST_OP_IADD 14866594 12.266% 14866594 12.266% +ST_OP_IMUL 1367985 1.129% 1367985 1.129% +ST_OP_IDIV 46050 0.038% 46050 0.038% +ST_OP_ICMP 5955128 4.913% 5955128 4.913% +ST_OP_LOGIC 16705411 13.783% 16705411 13.783% +ST_OP_SHIFT 6328151 5.221% 6328151 5.221% +ST_OP_FMEM 155333 0.128% 155333 0.128% +ST_OP_FCVT 0 0.000% 0 0.000% +ST_OP_FADD 0 0.000% 0 0.000% +ST_OP_FMUL 0 0.000% 0 0.000% +ST_OP_FMA 0 0.000% 0 0.000% +ST_OP_FDIV 0 0.000% 0 0.000% +ST_OP_FCMP 0 0.000% 0 0.000% +ST_OP_FCMOV 0 0.000% 0 0.000% +ST_OP_GATHER 0 0.000% 0 0.000% +ST_OP_SCATTER 0 0.000% 0 0.000% +ST_OP_PIPELINED_FAST 176 0.000% 176 0.000% +ST_OP_PIPELINED_MEDIUM 255308 0.211% 255308 0.211% +ST_OP_PIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_MEDIUM 143 0.000% 143 0.000% +ST_OP_NOTPIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_VERY_SLOW 0 0.000% 0 0.000% + 121204022 100.000% 121204022 100.000% + 6.40 3.22 6.40 3.22 + +ST_NOT_CF 106743612 88.069% 106743612 88.069% +ST_CF_BR 1001317 0.826% 1001317 0.826% +ST_CF_CBR 9417655 7.770% 9417655 7.770% +ST_CF_CALL 2016721 1.664% 2016721 1.664% +ST_CF_IBR 7763 0.006% 7763 0.006% +ST_CF_ICALL 122 0.000% 122 0.000% +ST_CF_ICO 0 0.000% 0 0.000% +ST_CF_RET 2016829 1.664% 2016829 1.664% +ST_CF_SYS 3 0.000% 3 0.000% + 121204022 100.000% 121204022 100.000% + 0.33 1.04 0.33 1.04 + +ST_BAR_NONE 121204019 100.000% 121204019 100.000% +ST_BAR_FETCH 3 0.000% 3 0.000% +ST_BAR_ISSUE 0 0.000% 0 0.000% +ST_BAR_BOTH 0 0.000% 0 0.000% + 121204022 100.000% 121204022 100.000% + 0.00 0.00 0.00 0.00 + +ST_NOT_MEM 83978092 69.287% 83978092 69.287% +ST_MEM_LD 25106825 20.715% 25106825 20.715% +ST_MEM_ST 12119105 9.999% 12119105 9.999% +ST_MEM_PF 0 0.000% 0 0.000% +ST_MEM_WH 0 0.000% 0 0.000% +ST_MEM_EVICT 0 0.000% 0 0.000% + 121204022 100.000% 121204022 100.000% + 0.41 0.57 0.41 0.57 + +ST_NOT_MEM_OFFPATH 0 -nan% 0 -nan% +ST_MEM_LD_OFFPATH 0 -nan% 0 -nan% +ST_MEM_ST_OFFPATH 0 -nan% 0 -nan% +ST_MEM_PF_OFFPATH 0 -nan% 0 -nan% +ST_MEM_WH_OFFPATH 0 -nan% 0 -nan% +ST_MEM_EVIC_OFFPATHT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ST_OP_ONPATH 121204022 121204022 + +ST_OP_OFFPATH 0 0 + +ST_FAKE_OP_OFFPATH 0 -nan% 0 -nan% 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+#################################################################################################### +Cumulative: Cycles: 50809793 Instructions: 100000000 IPC: 1.96812 + +L2WAY_FILL_L1 0 0 + +L2WAY_WAY_HIT 0 -nan% 0 -nan% +L2WAY_WAY_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_PREF_REQ 0 0 + +L2WAY_PREF_HIT_DATA_IN_CACHE 0 -nan% 0 -nan% +L2WAY_PREF_HIT_DATA_REQ 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_TRAIN_HIT 0 -nan% 0 -nan% +L2WAY_TRAIN_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L1_HIT_REQ_TYPE_IFETCH 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DFETCH 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DSTORE 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_IPRF 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DPRF 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_WB 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2_ACCESS_INTERVAL__0 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__1 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__2 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__3 0 -nan% 0 -nan% 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b/labs/LAB5/runs/deepsjeng-sms0/memory.stat.0.out new file mode 100644 index 00000000..ee083ee1 --- /dev/null +++ b/labs/LAB5/runs/deepsjeng-sms0/memory.stat.0.out @@ -0,0 +1,3416 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 50809793 Instructions: 100000000 IPC: 1.96812 + +ICACHE_MISS 91279 0.322% 91279 0.322% +ICACHE_HIT 28284827 99.678% 28284827 99.678% + 28376106 100.000% 28376106 100.000% + 1.00 1.00 1.00 1.00 + +ICACHE_MISS_ONPATH 91279 100.000% 91279 100.000% +ICACHE_MISS_OFFPATH 0 0.000% 0 0.000% + 91279 100.000% 91279 100.000% + 0.00 0.00 0.00 0.00 + +ICACHE_HIT_ONPATH 28284827 100.000% 28284827 100.000% +ICACHE_HIT_OFFPATH 0 0.000% 0 0.000% + 28284827 100.000% 28284827 100.000% + 0.00 0.00 0.00 0.00 + +ICACHE_HIT_ONPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +ICACHE_HIT_ONPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ICACHE_HIT_OFFPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +ICACHE_HIT_OFFPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DCACHE_MISS 389969 1.048% 389969 1.048% +DCACHE_ST_BUFFER_HIT 38135 0.102% 38135 0.102% +DCACHE_HIT 36797803 98.850% 36797803 98.850% + 37225907 100.000% 37225907 100.000% + 1.98 1.97 1.98 1.97 + +DCACHE_MISS_COMPULSORY 27089 0.0695 27089 0.0695 + +DCACHE_MISS_CAPACITY 358122 0.9183 358122 0.9183 + +DCACHE_MISS_CONFLICT 4758 0.0122 4758 0.0122 + +DCACHE_MISS_ONPATH 389969 100.000% 389969 100.000% +DCACHE_MISS_OFFPATH 0 0.000% 0 0.000% + 389969 100.000% 389969 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_ST_BUFFER_HIT_ONPATH 38135 100.000% 38135 100.000% +DCACHE_ST_BUFFER_HIT_OFFPATH 0 0.000% 0 0.000% + 38135 100.000% 38135 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_HIT_ONPATH 36797803 100.000% 36797803 100.000% +DCACHE_HIT_OFFPATH 0 0.000% 0 0.000% + 36797803 100.000% 36797803 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_HIT_ONPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +DCACHE_HIT_ONPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DCACHE_HIT_OFFPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +DCACHE_HIT_OFFPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DCACHE_MISS_LD 225046 57.709% 225046 57.709% +DCACHE_MISS_ST 164923 42.291% 164923 42.291% + 389969 100.000% 389969 100.000% + 0.42 0.47 0.42 0.47 + +DCACHE_MISS_LD_ONPATH 225046 100.000% 225046 100.000% +DCACHE_MISS_LD_OFFPATH 0 0.000% 0 0.000% + 225046 100.000% 225046 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_MISS_ST_ONPATH 164923 100.000% 164923 100.000% +DCACHE_MISS_ST_OFFPATH 0 0.000% 0 0.000% + 164923 100.000% 164923 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_MISS_WAITMEM 0 0 + +MEM_REQ_ROW_BUFFER_HITS 0 -nan% 0 -nan% +MEM_REQ_ROW_BUFFER_MISSES 0 -nan% 0 -nan% +MEM_REQ_ROW_BUFFER_CONFLICTS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + 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+CORE_EVICTED_L1_DEMAND 11879 99.132% 11879 99.132% +CORE_EVICTED_L1_PREF_USED 34 0.284% 34 0.284% +CORE_EVICTED_L1_PREF_NOT_USED 70 0.584% 70 0.584% + 11983 100.000% 11983 100.000% + 0.01 0.16 0.01 0.16 + +CORE_EVICTED_MLC_DEMAND 0 -nan% 0 -nan% +CORE_EVICTED_MLC_PREF_USED 0 -nan% 0 -nan% +CORE_EVICTED_MLC_PREF_NOT_USED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CORE_MEM_LATENCY_AVE_DEMAND 1569854 132.1537 1569854 132.1537 + +CORE_MEM_LATENCY_AVE_PREF_USED 3331 97.9706 3331 97.9706 + +CORE_MEM_LATENCY_AVE_PREF_NOT_USED 7642 109.1714 7642 109.1714 + +DRAM_LATENCY 0 0 + +TOTAL_DRAM_LATENCY 0 0 + +DRAM_CLOSED_PAGE_POLICY_CMD 0 0 + +DRAM_ACTIVATE_STALLING 0 0 + +DRAM_PRECHARGE_STALLING 0 0 + +DRAM_PRECHARGE_STALLING_WAIT_CYCLES 0 0 + +L1_STAY_DEMAND 279929035093 23565033.6807 279929035093 23565033.6807 + +L1_STAY_PREF_USED 1211021204 35618270.7059 1211021204 35618270.7059 + +L1_STAY_PREF_NOT_USED 1649228963 23560413.7571 1649228963 23560413.7571 + +TOTAL_DATA_MISS_LATENCY 3572152 3572152 + +TOTAL_DATA_MISS_COUNT 26774 26774 + +CORE_PREF_L1_NOT_USED_LATENCY200 67 95.714% 67 95.714% +CORE_PREF_L1_NOT_USED_LATENCY400 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_LATENCY600 2 2.857% 2 2.857% +CORE_PREF_L1_NOT_USED_LATENCY800 1 1.429% 1 1.429% +CORE_PREF_L1_NOT_USED_LATENCY1000 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_LATENCY1200 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_LATENCY1400 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_LATENCY1600 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_LATENCY1600MORE 0 0.000% 0 0.000% + 70 100.000% 70 100.000% + 0.10 0.48 0.10 0.48 + +CORE_PREF_L1_NOT_USED_DISTANCE_1 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_DISTANCE_2 1 1.429% 1 1.429% +CORE_PREF_L1_NOT_USED_DISTANCE_4 5 7.143% 5 7.143% +CORE_PREF_L1_NOT_USED_DISTANCE_8 29 41.429% 29 41.429% +CORE_PREF_L1_NOT_USED_DISTANCE_16 35 50.000% 35 50.000% +CORE_PREF_L1_NOT_USED_DISTANCE_32 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_DISTANCE_MORE 0 0.000% 0 0.000% + 70 100.000% 70 100.000% + 3.40 0.69 3.40 0.69 + +CORE_PREF_L1_USED_LATENCY200 33 97.059% 33 97.059% +CORE_PREF_L1_USED_LATENCY400 0 0.000% 0 0.000% +CORE_PREF_L1_USED_LATENCY600 0 0.000% 0 0.000% +CORE_PREF_L1_USED_LATENCY800 1 2.941% 1 2.941% +CORE_PREF_L1_USED_LATENCY1000 0 0.000% 0 0.000% +CORE_PREF_L1_USED_LATENCY1200 0 0.000% 0 0.000% +CORE_PREF_L1_USED_LATENCY1400 0 0.000% 0 0.000% +CORE_PREF_L1_USED_LATENCY1600 0 0.000% 0 0.000% +CORE_PREF_L1_USED_LATENCY1600MORE 0 0.000% 0 0.000% + 34 100.000% 34 100.000% + 0.09 0.51 0.09 0.51 + +CORE_PREF_L1_USED_DISTANCE_1 0 0.000% 0 0.000% +CORE_PREF_L1_USED_DISTANCE_2 1 2.941% 1 2.941% +CORE_PREF_L1_USED_DISTANCE_4 15 44.118% 15 44.118% +CORE_PREF_L1_USED_DISTANCE_8 12 35.294% 12 35.294% +CORE_PREF_L1_USED_DISTANCE_16 6 17.647% 6 17.647% +CORE_PREF_L1_USED_DISTANCE_32 0 0.000% 0 0.000% +CORE_PREF_L1_USED_DISTANCE_MORE 0 0.000% 0 0.000% + 34 100.000% 34 100.000% + 2.68 0.81 2.68 0.81 + +CORE_PREF_L1_DEMAND_LATENCY300 11468 96.540% 11468 96.540% +CORE_PREF_L1_DEMAND_LATENCY400 38 0.320% 38 0.320% +CORE_PREF_L1_DEMAND_LATENCY500 29 0.244% 29 0.244% +CORE_PREF_L1_DEMAND_LATENCY600 40 0.337% 40 0.337% +CORE_PREF_L1_DEMAND_LATENCY700 45 0.379% 45 0.379% +CORE_PREF_L1_DEMAND_LATENCY800 49 0.412% 49 0.412% +CORE_PREF_L1_DEMAND_LATENCY900 40 0.337% 40 0.337% +CORE_PREF_L1_DEMAND_LATENCY1000 42 0.354% 42 0.354% +CORE_PREF_L1_DEMAND_LATENCY1000MORE 128 1.078% 128 1.078% + 11879 100.000% 11879 100.000% + 0.19 1.06 0.19 1.06 + +CORE_PREF_MLC_NOT_USED_LATENCY200 0 -nan% 0 -nan% +CORE_PREF_MLC_NOT_USED_LATENCY400 0 -nan% 0 -nan% +CORE_PREF_MLC_NOT_USED_LATENCY600 0 -nan% 0 -nan% +CORE_PREF_MLC_NOT_USED_LATENCY800 0 -nan% 0 -nan% +CORE_PREF_MLC_NOT_USED_LATENCY1000 0 -nan% 0 -nan% +CORE_PREF_MLC_NOT_USED_LATENCY1200 0 -nan% 0 -nan% +CORE_PREF_MLC_NOT_USED_LATENCY1400 0 -nan% 0 -nan% +CORE_PREF_MLC_NOT_USED_LATENCY1600 0 -nan% 0 -nan% +CORE_PREF_MLC_NOT_USED_LATENCY1600MORE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CORE_PREF_MLC_USED_LATENCY200 0 -nan% 0 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+DRAM_NUM_REQS_24_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_24_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_24_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_24_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_24_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_24_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_24_WB_NODIRTY 0 -nan 0 -nan + +DRAM_NUM_REQS_25_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_25_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_25_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_25_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_25_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_25_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_25_WB_NODIRTY 0 -nan 0 -nan + +DRAM_NUM_REQS_26_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_26_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_26_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_26_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_26_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_26_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_26_WB_NODIRTY 0 -nan 0 -nan + +DRAM_NUM_REQS_27_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_27_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_27_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_27_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_27_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_27_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_27_WB_NODIRTY 0 -nan 0 -nan + +DRAM_NUM_REQS_28_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_28_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_28_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_28_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_28_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_28_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_28_WB_NODIRTY 0 -nan 0 -nan + +DRAM_NUM_REQS_29_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_29_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_29_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_29_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_29_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_29_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_29_WB_NODIRTY 0 -nan 0 -nan + +DRAM_NUM_REQS_30_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_30_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_30_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_30_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_30_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_30_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_30_WB_NODIRTY 0 -nan 0 -nan + +DRAM_NUM_REQS_31_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_31_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_31_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_31_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_31_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_31_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_31_WB_NODIRTY 0 -nan 0 -nan + +DRAM_NUM_REQS_32_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_32_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_32_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_32_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_32_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_32_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_32_WB_NODIRTY 0 -nan 0 -nan + +DRAM_BOTTLENECK_BUS_0 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_10 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_20 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_30 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_40 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_50 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_60 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_70 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_80 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_90 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_100 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DRAM_BOTTLENECK_BANKS_0 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_10 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_20 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_30 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_40 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_50 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_60 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_70 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_80 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_90 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_100 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DRAM_BOTTLENECK_FAW_0 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_10 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_20 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_30 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_40 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_50 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_60 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_70 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_80 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_90 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_100 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DRAM_ROW_HIT_GEN_AFTER_ROW_OPEN_STALLING 0 0 + +KNOWN_BAD_ADDRESS 0 0.000% 0 0.000% +GOOD_ADDRESS 821598 100.000% 821598 100.000% + 821598 100.000% 821598 100.000% + 1.00 1.00 1.00 1.00 + + + diff --git a/labs/LAB5/runs/deepsjeng-sms0/power.stat.0.out b/labs/LAB5/runs/deepsjeng-sms0/power.stat.0.out new file mode 100644 index 00000000..26d23aa7 --- /dev/null +++ b/labs/LAB5/runs/deepsjeng-sms0/power.stat.0.out @@ -0,0 +1,184 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 50809793 Instructions: 100000000 IPC: 1.96812 + +POWER_STATS_BEGIN 0 0 + +POWER_TIME 15878060312500 15878060312500 + +POWER_CYCLE 50809793 50809793 + +POWER_ITLB_ACCESS 28376106 28376106 + +POWER_DTLB_ACCESS 12119092 12119092 + +POWER_ICACHE_ACCESS 28376106 28376106 + +POWER_ICACHE_MISS 91279 91279 + +POWER_BTB_READ 28376106 28376106 + +POWER_BTB_WRITE 1208606 1208606 + +POWER_ROB_READ 121203964 121203964 + +POWER_ROB_WRITE 121203964 121203964 + +POWER_RENAME_READ 242407928 242407928 + +POWER_RENAME_WRITE 121203964 121203964 + +POWER_FP_RENAME_READ 0 0 + +POWER_FP_RENAME_WRITE 0 0 + +POWER_FUNCTION_CALL 2016842 2016842 + +POWER_INST_WINDOW_READ 121203964 121203964 + +POWER_INST_WINDOW_WRITE 121203964 121203964 + +POWER_INT_REGFILE_READ 145540637 145540637 + +POWER_INT_REGFILE_WRITE 118366721 118366721 + +POWER_IALU_ACCESS 119789930 119789930 + +POWER_CDB_IALU_ACCESS 119789930 119789930 + +POWER_MUL_ACCESS 1414034 1414034 + +POWER_CDB_MUL_ACCESS 1414034 1414034 + +POWER_FP_INST_WINDOW_WRITE 0 0 + +POWER_FP_INST_WINDOW_READ 0 0 + +POWER_FP_REGFILE_READ 0 0 + +POWER_FP_REGFILE_WRITE 0 0 + +POWER_FPU_ACCESS 0 0 + +POWER_CDB_FPU_ACCESS 0 0 + +POWER_DCACHE_READ_ACCESS 25106816 25106816 + +POWER_DCACHE_WRITE_ACCESS 12119091 12119091 + +POWER_DCACHE_READ_MISS 263181 263181 + +POWER_DCACHE_WRITE_MISS 164923 164923 + +POWER_MLC_READ_ACCESS 0 0 + +POWER_MLC_WRITE_ACCESS 0 0 + +POWER_MLC_READ_MISS 0 0 + +POWER_MLC_WRITE_MISS 0 0 + +POWER_LLC_READ_ACCESS 258667 258667 + +POWER_LLC_WRITE_ACCESS 72787 72787 + +POWER_LLC_READ_MISS 28246 28246 + +POWER_LLC_WRITE_MISS 0 0 + +POWER_MEMORY_ACCESS 0 0 + +POWER_MEMORY_READ_ACCESS 0 0 + +POWER_MEMORY_WRITE_ACCESS 0 0 + +POWER_INST_WINDOW_WAKEUP_ACCESS 121203964 121203964 + +POWER_FP_INST_WINDOW_WAKEUP_ACCESS 0 0 + +POWER_L1DIREC_READ_ACCESS 0 0 + +POWER_L1DIREC_WRITE_ACCESS 0 0 + +POWER_L1DIREC_READ_MISS 0 0 + +POWER_L1DIREC_WRITE_MISS 0 0 + +POWER_L2DIREC_READ_ACCESS 0 0 + +POWER_L2DIREC_WRITE_ACCESS 0 0 + +POWER_L2DIREC_READ_MISS 0 0 + +POWER_L2DIREC_WRITE_MISS 0 0 + +POWER_MEMORY_CTRL_ACCESS 36147 36147 + +POWER_MEMORY_CTRL_READ 28246 28246 + +POWER_MEMORY_CTRL_WRITE 7901 7901 + +POWER_OP 121203964 121203964 + +POWER_INT_OP 118468939 118468939 + +POWER_FP_OP 410960 410960 + +POWER_LD_OP 25106816 25106816 + +POWER_ST_OP 12119092 12119092 + +POWER_BRANCH_MISPREDICT 1208606 1208606 + +POWER_COMMITTED_OP 121203964 121203964 + +POWER_COMMITTED_INT_OP 118468939 118468939 + +POWER_COMMITTED_FP_OP 2735025 2735025 + +POWER_BRANCH_OP 14460405 14460405 + +POWER_DRAM_PRECHARGE 12492 12492 + +POWER_DRAM_ACTIVATE 25752 25752 + +POWER_DRAM_READ 28244 28244 + +POWER_DRAM_WRITE 7892 7892 + +POWER_STATS_END 0 0 + +ENERGY 0.000000 0.000000 + +ENERGY_CORE 0.000000 0.000000 + +ENERGY_UNCORE 0.000000 0.000000 + +ENERGY_MEMORY 0.000000 0.000000 + +ENERGY_OTHER 0.000000 0.000000 + +ENERGY_CORE_STATIC 0.000000 0.000000 + +ENERGY_CORE_DYNAMIC 0.000000 0.000000 + +ENERGY_UNCORE_STATIC 0.000000 0.000000 + +ENERGY_UNCORE_DYNAMIC 0.000000 0.000000 + +ENERGY_MEMORY_STATIC 0.000000 0.000000 + +ENERGY_MEMORY_DYNAMIC 0.000000 0.000000 + +ENERGY_OTHER_STATIC 0.000000 0.000000 + +ENERGY_OTHER_DYNAMIC 0.000000 0.000000 + +TIME 0.000000 0.000000 + +ENERGY_STATS_END 0 0 + + + diff --git a/labs/LAB5/runs/deepsjeng-sms0/pref.stat.0.out b/labs/LAB5/runs/deepsjeng-sms0/pref.stat.0.out new file mode 100644 index 00000000..f7ad0b24 --- /dev/null +++ b/labs/LAB5/runs/deepsjeng-sms0/pref.stat.0.out @@ -0,0 +1,208 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 50809793 Instructions: 100000000 IPC: 1.96812 + +PREF_DL0REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UMLC_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UL1REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_DL0REQ_QUEUE_FULL 0 0 + +PREF_UMLC_REQ_QUEUE_FULL 0 0 + +PREF_UL1REQ_QUEUE_FULL 0 0 + +PREF_DC_HIT_NOSEND 0 0 + +PREF_WBQDC_HIT_NOSEND 0 0 + +PREF_MLCQ_STALL 0 0 + +PREF_L1Q_STALL 0 0 + +PREF_UMLC_REQ_SEND_QUEUE_STALL 0 0 + +PREF_UL1REQ_SEND_QUEUE_STALL 0 0 + +PREF_UMLC_REQ_QUEUE_SENTREQ 0 0 + +PREF_UL1REQ_QUEUE_SENTREQ 995 995 + +PREF_NEWREQ_MATCHED 23 23 + +PREF_UMLC_REQ_QUEUE_MATCHED_REQ 0 0 + +PREF_UL1REQ_QUEUE_MATCHED_REQ 152 152 + +PREF_DL0REQ_QUEUE_MATCHED_REQ 0 0 + +L1_PREF_HIT 27644 27644 + +L1_PREF_UNIQUE_HIT 408 408 + +L1_PREF_LATE 10 10 + +L1_LATE_PREF_CYCLES 3479 3479 + +L1_LATE_PREF_CYCLES_DIST_0 5 50.000% 5 50.000% +L1_LATE_PREF_CYCLES_DIST_100 1 10.000% 1 10.000% +L1_LATE_PREF_CYCLES_DIST_200 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_300 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_400 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_500 1 10.000% 1 10.000% +L1_LATE_PREF_CYCLES_DIST_600 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_700 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_800 3 30.000% 3 30.000% +L1_LATE_PREF_CYCLES_DIST_900 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1000 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1100 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1200 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1300 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1400 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1500 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1600 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1700 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1800 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1900 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_2000 0 0.000% 0 0.000% + 10 100.000% 10 100.000% + 3.00 3.04 3.00 3.04 + +MLC_PREF_HIT 0 0 + +MLC_PREF_UNIQUE_HIT 0 0 + +MLC_PREF_LATE 0 0 + +PREF_HYBRID_SEL_0 0 -nan% 0 -nan% +PREF_HYBRID_SEL_1 0 -nan% 0 -nan% +PREF_HYBRID_SEL_2 0 -nan% 0 -nan% +PREF_HYBRID_SEL_3 0 -nan% 0 -nan% +PREF_HYBRID_SEL_4 0 -nan% 0 -nan% +PREF_HYBRID_SEL_5 0 -nan% 0 -nan% +PREF_HYBRID_SEL_6 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_DISTANCE_1 0 0.000% 0 0.000% +PREF_DISTANCE_2 0 0.000% 0 0.000% +PREF_DISTANCE_3 0 0.000% 0 0.000% +PREF_DISTANCE_4 1 100.000% 1 100.000% +PREF_DISTANCE_5 0 0.000% 0 0.000% +PREF_DISTANCE_6 0 0.000% 0 0.000% +PREF_DISTANCE_7 0 0.000% 0 0.000% +PREF_DISTANCE_8 0 0.000% 0 0.000% +PREF_DISTANCE_9 0 0.000% 0 0.000% +PREF_DISTANCE_10 0 0.000% 0 0.000% + 1 100.000% 1 100.000% + 3.00 -nan 3.00 -nan + +PREF_REPL_MRU 0 -nan% 0 -nan% +PREF_REPL_MID 0 -nan% 0 -nan% +PREF_REPL_LOWQTR 0 -nan% 0 -nan% +PREF_REPL_LRU 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_REPL_MOVEDOWN 0 -nan% 0 -nan% +PREF_REPL_MOVEUP 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_COV_1 0 -nan% 0 -nan% +PREF_COV_2 0 -nan% 0 -nan% +PREF_COV_3 0 -nan% 0 -nan% +PREF_COV_4 0 -nan% 0 -nan% +PREF_COV_5 0 -nan% 0 -nan% +PREF_COV_6 0 -nan% 0 -nan% +PREF_COV_7 0 -nan% 0 -nan% +PREF_COV_8 0 -nan% 0 -nan% +PREF_COV_9 0 -nan% 0 -nan% +PREF_COV_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_POL_1 0 0.000% 0 0.000% +PREF_POL_2 0 0.000% 0 0.000% +PREF_POL_3 0 0.000% 0 0.000% +PREF_POL_4 0 0.000% 0 0.000% +PREF_POL_5 0 0.000% 0 0.000% +PREF_POL_6 0 0.000% 0 0.000% +PREF_POL_7 0 0.000% 0 0.000% +PREF_POL_8 0 0.000% 0 0.000% +PREF_POL_9 0 0.000% 0 0.000% +PREF_POL_10 1 100.000% 1 100.000% + 1 100.000% 1 100.000% + 9.00 inf 9.00 inf + +PREF_ACC_1 0 0.000% 0 0.000% +PREF_ACC_2 1 100.000% 1 100.000% +PREF_ACC_3 0 0.000% 0 0.000% +PREF_ACC_4 0 0.000% 0 0.000% +PREF_ACC_5 0 0.000% 0 0.000% +PREF_ACC_6 0 0.000% 0 0.000% +PREF_ACC_7 0 0.000% 0 0.000% +PREF_ACC_8 0 0.000% 0 0.000% +PREF_ACC_9 0 0.000% 0 0.000% +PREF_ACC_10 0 0.000% 0 0.000% + 1 100.000% 1 100.000% + 1.00 -nan 1.00 -nan + +PREF_TIMELY_1 0 0.000% 0 0.000% +PREF_TIMELY_2 0 0.000% 0 0.000% +PREF_TIMELY_3 0 0.000% 0 0.000% +PREF_TIMELY_4 0 0.000% 0 0.000% +PREF_TIMELY_5 0 0.000% 0 0.000% +PREF_TIMELY_6 0 0.000% 0 0.000% +PREF_TIMELY_7 0 0.000% 0 0.000% +PREF_TIMELY_8 0 0.000% 0 0.000% +PREF_TIMELY_9 0 0.000% 0 0.000% +PREF_TIMELY_10 1 100.000% 1 100.000% + 1 100.000% 1 100.000% + 9.00 inf 9.00 inf + +PREF_UNUSED_EVICT 70 70 + +PREF_REGION_SENT 0 0 + +PREF_REGION_USEFUL 0 0 + +PREF_REGION_EVICT 0 0 + +PREF_PFPOL 0 0 + +PREF_PHASE_NEWPHASE_DET 0 0 + +PREF_PHASE_NEWPHASE_NOTVALID 0 0 + +PREF_PHASE_SENTPREF 0 0 + +PREF_PHASE_OVERWRITE_PAGE 0 0 + +PREF_UPDATE_COUNT 1 1 + +PREF_ACC1_HT_HP 0 0.000% 0 0.000% +PREF_ACC1_HT_LP 0 0.000% 0 0.000% +PREF_ACC1_LT_HP 0 0.000% 0 0.000% +PREF_ACC1_LT_LP 1 100.000% 1 100.000% +PREF_ACC2_HT_HP 0 0.000% 0 0.000% +PREF_ACC2_HT_LP 0 0.000% 0 0.000% +PREF_ACC2_LT_HP 0 0.000% 0 0.000% +PREF_ACC2_LT_LP 0 0.000% 0 0.000% +PREF_ACC3_HT_HP 0 0.000% 0 0.000% +PREF_ACC3_HT_LP 0 0.000% 0 0.000% +PREF_ACC3_LT_HP 0 0.000% 0 0.000% +PREF_ACC3_LT_LP 0 0.000% 0 0.000% +PREF_ACC4_HT_HP 0 0.000% 0 0.000% +PREF_ACC4_HT_LP 0 0.000% 0 0.000% +PREF_ACC4_LT_HP 0 0.000% 0 0.000% +PREF_ACC4_LT_LP 0 0.000% 0 0.000% + 1 100.000% 1 100.000% + 3.00 -nan 3.00 -nan + + + diff --git a/labs/LAB5/runs/deepsjeng-sms0/ramulator.stat.out b/labs/LAB5/runs/deepsjeng-sms0/ramulator.stat.out new file mode 100644 index 00000000..472ea8b0 --- /dev/null +++ b/labs/LAB5/runs/deepsjeng-sms0/ramulator.stat.out @@ -0,0 +1,150 @@ + ramulator.active_cycles_0 2669484 # Total active cycles for level _0 + ramulator.busy_cycles_0 2669484 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0 + ramulator.serving_requests_0 3547863 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.average_serving_requests_0 0.186204 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.active_cycles_0_0 2669484 # Total active cycles for level _0_0 + ramulator.busy_cycles_0_0 3436824 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0 + ramulator.serving_requests_0_0 3547863 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.average_serving_requests_0_0 0.186204 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.active_cycles_0_0_0 526069 # Total active cycles for level _0_0_0 + ramulator.busy_cycles_0_0_0 526069 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0 + ramulator.serving_requests_0_0_0 574194 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 +ramulator.average_serving_requests_0_0_0 0.030136 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 + ramulator.active_cycles_0_0_0_0 134288 # Total active cycles for level _0_0_0_0 + ramulator.busy_cycles_0_0_0_0 134288 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_0 + ramulator.serving_requests_0_0_0_0 140441 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 +ramulator.average_serving_requests_0_0_0_0 0.007371 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 + ramulator.active_cycles_0_0_0_1 187976 # Total active cycles for level _0_0_0_1 + ramulator.busy_cycles_0_0_0_1 187976 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_1 + ramulator.serving_requests_0_0_0_1 193436 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 +ramulator.average_serving_requests_0_0_0_1 0.010152 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 + ramulator.active_cycles_0_0_0_2 102739 # Total active cycles for level _0_0_0_2 + ramulator.busy_cycles_0_0_0_2 102739 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_2 + ramulator.serving_requests_0_0_0_2 109176 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 +ramulator.average_serving_requests_0_0_0_2 0.005730 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 + ramulator.active_cycles_0_0_0_3 125083 # Total active cycles for level _0_0_0_3 + ramulator.busy_cycles_0_0_0_3 125083 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_3 + ramulator.serving_requests_0_0_0_3 131141 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 +ramulator.average_serving_requests_0_0_0_3 0.006883 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 + ramulator.active_cycles_0_0_1 889061 # Total active cycles for level _0_0_1 + ramulator.busy_cycles_0_0_1 889061 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1 + ramulator.serving_requests_0_0_1 991500 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 +ramulator.average_serving_requests_0_0_1 0.052037 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 + ramulator.active_cycles_0_0_1_0 208596 # Total active cycles for level _0_0_1_0 + ramulator.busy_cycles_0_0_1_0 208596 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_0 + ramulator.serving_requests_0_0_1_0 215434 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 +ramulator.average_serving_requests_0_0_1_0 0.011307 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 + ramulator.active_cycles_0_0_1_1 246333 # Total active cycles for level _0_0_1_1 + ramulator.busy_cycles_0_0_1_1 246333 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_1 + ramulator.serving_requests_0_0_1_1 252241 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 +ramulator.average_serving_requests_0_0_1_1 0.013238 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 + ramulator.active_cycles_0_0_1_2 248817 # Total active cycles for level _0_0_1_2 + ramulator.busy_cycles_0_0_1_2 248817 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_2 + ramulator.serving_requests_0_0_1_2 257010 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 +ramulator.average_serving_requests_0_0_1_2 0.013489 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 + ramulator.active_cycles_0_0_1_3 260070 # Total active cycles for level _0_0_1_3 + ramulator.busy_cycles_0_0_1_3 260070 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_3 + ramulator.serving_requests_0_0_1_3 266815 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 +ramulator.average_serving_requests_0_0_1_3 0.014003 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 + ramulator.active_cycles_0_0_2 930388 # Total active cycles for level _0_0_2 + ramulator.busy_cycles_0_0_2 930388 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2 + ramulator.serving_requests_0_0_2 1000511 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 +ramulator.average_serving_requests_0_0_2 0.052510 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 + ramulator.active_cycles_0_0_2_0 266104 # Total active cycles for level _0_0_2_0 + ramulator.busy_cycles_0_0_2_0 266104 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_0 + ramulator.serving_requests_0_0_2_0 272774 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 +ramulator.average_serving_requests_0_0_2_0 0.014316 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 + ramulator.active_cycles_0_0_2_1 278151 # Total active cycles for level _0_0_2_1 + ramulator.busy_cycles_0_0_2_1 278151 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_1 + ramulator.serving_requests_0_0_2_1 283531 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 +ramulator.average_serving_requests_0_0_2_1 0.014881 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 + ramulator.active_cycles_0_0_2_2 115857 # Total active cycles for level _0_0_2_2 + ramulator.busy_cycles_0_0_2_2 115857 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_2 + ramulator.serving_requests_0_0_2_2 122864 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 +ramulator.average_serving_requests_0_0_2_2 0.006448 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 + ramulator.active_cycles_0_0_2_3 314279 # Total active cycles for level _0_0_2_3 + ramulator.busy_cycles_0_0_2_3 314279 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_3 + ramulator.serving_requests_0_0_2_3 321342 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 +ramulator.average_serving_requests_0_0_2_3 0.016865 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 + ramulator.active_cycles_0_0_3 930288 # Total active cycles for level _0_0_3 + ramulator.busy_cycles_0_0_3 930288 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3 + ramulator.serving_requests_0_0_3 981658 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 +ramulator.average_serving_requests_0_0_3 0.051521 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 + ramulator.active_cycles_0_0_3_0 85453 # Total active cycles for level _0_0_3_0 + ramulator.busy_cycles_0_0_3_0 85453 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_0 + ramulator.serving_requests_0_0_3_0 91100 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 +ramulator.average_serving_requests_0_0_3_0 0.004781 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 + ramulator.active_cycles_0_0_3_1 163900 # Total active cycles for level _0_0_3_1 + ramulator.busy_cycles_0_0_3_1 163900 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_1 + ramulator.serving_requests_0_0_3_1 170076 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 +ramulator.average_serving_requests_0_0_3_1 0.008926 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 + ramulator.active_cycles_0_0_3_2 176512 # Total active cycles for level _0_0_3_2 + ramulator.busy_cycles_0_0_3_2 176512 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_2 + ramulator.serving_requests_0_0_3_2 182464 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 +ramulator.average_serving_requests_0_0_3_2 0.009576 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 + ramulator.active_cycles_0_0_3_3 529903 # Total active cycles for level _0_0_3_3 + ramulator.busy_cycles_0_0_3_3 529903 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_3 + ramulator.serving_requests_0_0_3_3 538018 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 +ramulator.average_serving_requests_0_0_3_3 0.028237 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 + ramulator.read_transaction_bytes_0 1807616 # The total byte of read transaction per channel + ramulator.write_transaction_bytes_0 505088 # The total byte of write transaction per channel + ramulator.row_hits_channel_0_core 10384 # Number of row hits per channel per core + ramulator.row_misses_channel_0_core 15294 # Number of row misses per channel per core + ramulator.row_conflicts_channel_0_core 10458 # Number of row conflicts per channel per core + ramulator.read_row_hits_channel_0_core 10309 # Number of row hits for read requests per channel per core + [0] 10309.0 # +ramulator.read_row_misses_channel_0_core 12515 # Number of row misses for read requests per channel per core + [0] 12515.0 # +ramulator.read_row_conflicts_channel_0_core 5420 # Number of row conflicts for read requests per channel per core + [0] 5420.0 # + ramulator.write_row_hits_channel_0_core 75 # Number of row hits for write requests per channel per core + [0] 75.0 # +ramulator.write_row_misses_channel_0_core 2779 # Number of row misses for write requests per channel per core + [0] 2779.0 # +ramulator.write_row_conflicts_channel_0_core 5038 # Number of row conflicts for write requests per channel per core + [0] 5038.0 # + ramulator.useless_activates_0_core 0 # Number of useless activations. E.g, ACT -> PRE w/o RD or WR + ramulator.read_latency_avg_0 49.763648 # The average memory latency cycles (in memory time domain) per request for all read requests in this channel + ramulator.read_latency_sum_0 1405624 # The memory latency cycles (in memory time domain) sum for all read requests in this channel + ramulator.req_queue_length_avg_0 10.715903 # Average of read and write queue length per memory cycle per channel. + ramulator.req_queue_length_sum_0 204177383 # Sum of read and write queue length per memory cycle per channel. + ramulator.read_req_queue_length_avg_0 0.058702 # Read queue length average per memory cycle per channel. + ramulator.read_req_queue_length_sum_0 1118492 # Read queue length sum per memory cycle per channel. + ramulator.write_req_queue_length_avg_0 10.657201 # Write queue length average per memory cycle per channel. + ramulator.write_req_queue_length_sum_0 203058891 # Write queue length sum per memory cycle per channel. + ramulator.record_read_hits 0.0 # record read hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_misses 0.0 # record_read_miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_conflicts 0.0 # record read conflict count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_hits 0.0 # record write hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_misses 0.0 # record write miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_conflicts 0.0 # record write conflict for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.dram_capacity 8589934592 # Number of bytes in simulated DRAM + ramulator.dram_cycles 19053679 # Number of DRAM cycles simulated + ramulator.incoming_requests 36147 # Number of incoming requests to DRAM + ramulator.read_requests 28246 # Number of incoming read requests to DRAM per core + [0] 28246.0 # + ramulator.write_requests 7901 # Number of incoming write requests to DRAM per core + [0] 7901.0 # + ramulator.ramulator_active_cycles 2669484 # The total number of cycles that the DRAM part is active (serving R/W) + ramulator.incoming_requests_per_channel 36147.0 # Number of incoming requests to each DRAM channel + [0] 36147.0 # +ramulator.incoming_read_reqs_per_channel 28246.0 # Number of incoming read requests to each DRAM channel + [0] 28246.0 # + ramulator.physical_page_replacement 0 # The number of times that physical page replacement happens. + ramulator.maximum_bandwidth 19200000000 # The theoretical maximum bandwidth (Bps) + ramulator.in_queue_req_num_sum 204177383 # Sum of read/write queue length + ramulator.in_queue_read_req_num_sum 1118492 # Sum of read queue length + ramulator.in_queue_write_req_num_sum 203058891 # Sum of write queue length + ramulator.in_queue_req_num_avg 10.715903 # Average of read/write queue length per memory cycle + ramulator.in_queue_read_req_num_avg 0.058702 # Average of read queue length per memory cycle + ramulator.in_queue_write_req_num_avg 10.657201 # Average of write queue length per memory cycle + ramulator.record_read_requests 0.0 # record read requests for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_requests 0.0 # record write requests for this core when it reaches request limit or to the end + [0] 0.0 # diff --git a/labs/LAB5/run_all.out b/labs/LAB5/runs/deepsjeng-sms0/run.err similarity index 100% rename from labs/LAB5/run_all.out rename to labs/LAB5/runs/deepsjeng-sms0/run.err diff --git a/labs/LAB5/runs/deepsjeng-sms0/run.out b/labs/LAB5/runs/deepsjeng-sms0/run.out new file mode 100644 index 00000000..44a4cff4 --- /dev/null +++ b/labs/LAB5/runs/deepsjeng-sms0/run.out @@ -0,0 +1,107 @@ +Scarab gitrev: 7ab9e17 +Scarab started at Sun Jun 11 08:08:38 2023 + +Initialized Ramulator. +** Heartbeat: 1% -- { 1000003 } -- 0.00 KIPS (500.00 KIPS) +** Heartbeat: 2% -- { 2000004 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 3% -- { 3000005 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 4% -- { 4000008 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 5% -- { 5000010 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 6% -- { 6000013 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 7% -- { 7000014 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 8% -- { 8000018 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 9% -- { 9000018 } -- 1000.00 KIPS (529.41 KIPS) +** Heartbeat: 10% -- { 10000019 } -- 500.00 KIPS (526.32 KIPS) +** Heartbeat: 11% -- { 11000020 } -- 500.00 KIPS (523.81 KIPS) +** Heartbeat: 12% -- { 12000021 } -- 500.00 KIPS (521.74 KIPS) +** Heartbeat: 13% -- { 13000024 } -- 500.00 KIPS (520.00 KIPS) +** Heartbeat: 14% -- { 14000025 } -- 500.00 KIPS (518.52 KIPS) +** Heartbeat: 15% -- { 15000025 } -- 500.00 KIPS (517.24 KIPS) +** Heartbeat: 16% -- { 16000030 } -- 500.00 KIPS (516.13 KIPS) +** Heartbeat: 17% -- { 17000030 } -- 1000.00 KIPS (531.25 KIPS) +** Heartbeat: 18% -- { 18000034 } -- 500.00 KIPS (529.41 KIPS) +** Heartbeat: 19% -- { 19000035 } -- 500.00 KIPS (527.78 KIPS) +** Heartbeat: 20% -- { 20000040 } -- 500.00 KIPS (526.32 KIPS) +** Heartbeat: 21% -- { 21000041 } -- 500.00 KIPS (525.00 KIPS) +** Heartbeat: 22% -- { 22000045 } -- 500.00 KIPS (523.81 KIPS) +** Heartbeat: 23% -- { 23000046 } -- 500.00 KIPS (522.73 KIPS) +** Heartbeat: 24% -- { 24000046 } -- 500.00 KIPS (521.74 KIPS) +** Heartbeat: 25% -- { 25000049 } -- 500.00 KIPS (520.83 KIPS) +** Heartbeat: 26% -- { 26000049 } -- 1000.00 KIPS (530.61 KIPS) +** Heartbeat: 27% -- { 27000051 } -- 500.00 KIPS (529.41 KIPS) +** Heartbeat: 28% -- { 28000053 } -- 500.00 KIPS (528.30 KIPS) +** Heartbeat: 29% -- { 29000054 } -- 500.00 KIPS (527.27 KIPS) +** Heartbeat: 30% -- { 30000059 } -- 500.00 KIPS (526.32 KIPS) +** Heartbeat: 31% -- { 31000059 } -- 500.00 KIPS (525.42 KIPS) +** Heartbeat: 32% -- { 32000060 } -- 1000.00 KIPS (533.33 KIPS) +** Heartbeat: 33% -- { 33000062 } -- 500.00 KIPS (532.26 KIPS) +** Heartbeat: 34% -- { 34000062 } -- 500.00 KIPS (531.25 KIPS) +** Heartbeat: 35% -- { 35000063 } -- 500.00 KIPS (530.30 KIPS) +** Heartbeat: 36% -- { 36000064 } -- 500.00 KIPS (529.41 KIPS) +** Heartbeat: 37% -- { 37000066 } -- 500.00 KIPS (528.57 KIPS) +** Heartbeat: 38% -- { 38000070 } -- 500.00 KIPS (527.78 KIPS) +** Heartbeat: 39% -- { 39000072 } -- 1000.00 KIPS (534.25 KIPS) +** Heartbeat: 40% -- { 40000074 } -- 500.00 KIPS (533.33 KIPS) +** Heartbeat: 41% -- { 41000074 } -- 500.00 KIPS (532.47 KIPS) +** Heartbeat: 42% -- { 42000077 } -- 500.00 KIPS (531.65 KIPS) +** Heartbeat: 43% -- { 43000081 } -- 500.00 KIPS (530.87 KIPS) +** Heartbeat: 44% -- { 44000081 } -- 500.00 KIPS (530.12 KIPS) +** Heartbeat: 45% -- { 45000085 } -- 1000.00 KIPS (535.72 KIPS) +** Heartbeat: 46% -- { 46000087 } -- 500.00 KIPS (534.88 KIPS) +** Heartbeat: 47% -- { 47000090 } -- 500.00 KIPS (534.09 KIPS) +** Heartbeat: 48% -- { 48000094 } -- 500.00 KIPS (533.33 KIPS) +** Heartbeat: 49% -- { 49000097 } -- 500.00 KIPS (532.61 KIPS) +** Heartbeat: 50% -- { 50000097 } -- 500.00 KIPS (531.92 KIPS) +** Heartbeat: 51% -- { 51000100 } -- 1000.00 KIPS (536.84 KIPS) +** Heartbeat: 52% -- { 52000101 } -- 500.00 KIPS (536.08 KIPS) +** Heartbeat: 53% -- { 53000104 } -- 500.00 KIPS (535.35 KIPS) +** Heartbeat: 54% -- { 54000106 } -- 500.00 KIPS (534.65 KIPS) +** Heartbeat: 55% -- { 55000107 } -- 500.00 KIPS (533.98 KIPS) +** Heartbeat: 56% -- { 56000107 } -- 1000.00 KIPS (538.46 KIPS) +** Heartbeat: 57% -- { 57000112 } -- 500.00 KIPS (537.74 KIPS) +** Heartbeat: 58% -- { 58000117 } -- 500.00 KIPS (537.04 KIPS) +** Heartbeat: 59% -- { 59000118 } -- 500.00 KIPS (536.36 KIPS) +** Heartbeat: 60% -- { 60000122 } -- 500.00 KIPS (535.72 KIPS) +** Heartbeat: 61% -- { 61000123 } -- 500.00 KIPS (535.09 KIPS) +** Heartbeat: 62% -- { 62000124 } -- 1000.00 KIPS (539.13 KIPS) +** Heartbeat: 63% -- { 63000124 } -- 500.00 KIPS (538.46 KIPS) +** Heartbeat: 64% -- { 64000125 } -- 500.00 KIPS (537.82 KIPS) +** Heartbeat: 65% -- { 65000125 } -- 500.00 KIPS (537.19 KIPS) +** Heartbeat: 66% -- { 66000125 } -- 500.00 KIPS (536.59 KIPS) +** Heartbeat: 67% -- { 67000127 } -- 500.00 KIPS (536.00 KIPS) +** Heartbeat: 68% -- { 68000131 } -- 1000.00 KIPS (539.68 KIPS) +** Heartbeat: 69% -- { 69000131 } -- 500.00 KIPS (539.06 KIPS) +** Heartbeat: 70% -- { 70000133 } -- 500.00 KIPS (538.46 KIPS) +** Heartbeat: 71% -- { 71000135 } -- 500.00 KIPS (537.88 KIPS) +** Heartbeat: 72% -- { 72000135 } -- 500.00 KIPS (537.31 KIPS) +** Heartbeat: 73% -- { 73000135 } -- 500.00 KIPS (536.77 KIPS) +** Heartbeat: 74% -- { 74000140 } -- 500.00 KIPS (536.23 KIPS) +** Heartbeat: 75% -- { 75000142 } -- 1000.00 KIPS (539.57 KIPS) +** Heartbeat: 76% -- { 76000145 } -- 500.00 KIPS (539.01 KIPS) +** Heartbeat: 77% -- { 77000145 } -- 500.00 KIPS (538.46 KIPS) +** Heartbeat: 78% -- { 78000148 } -- 500.00 KIPS (537.93 KIPS) +** Heartbeat: 79% -- { 79000150 } -- 500.00 KIPS (537.42 KIPS) +** Heartbeat: 80% -- { 80000150 } -- 500.00 KIPS (536.91 KIPS) +** Heartbeat: 81% -- { 81000150 } -- 500.00 KIPS (536.42 KIPS) +** Heartbeat: 82% -- { 82000151 } -- 1000.00 KIPS (539.47 KIPS) +** Heartbeat: 83% -- { 83000154 } -- 500.00 KIPS (538.96 KIPS) +** Heartbeat: 84% -- { 84000154 } -- 500.00 KIPS (538.46 KIPS) +** Heartbeat: 85% -- { 85000156 } -- 500.00 KIPS (537.98 KIPS) +** Heartbeat: 86% -- { 86000159 } -- 500.00 KIPS (537.50 KIPS) +** Heartbeat: 87% -- { 87000160 } -- 500.00 KIPS (537.04 KIPS) +** Heartbeat: 88% -- { 88000163 } -- 1000.00 KIPS (539.88 KIPS) +** Heartbeat: 89% -- { 89000163 } -- 500.00 KIPS (539.39 KIPS) +** Heartbeat: 90% -- { 90000166 } -- 500.00 KIPS (538.92 KIPS) +** Heartbeat: 91% -- { 91000167 } -- 500.00 KIPS (538.46 KIPS) +** Heartbeat: 92% -- { 92000170 } -- 500.00 KIPS (538.01 KIPS) +** Heartbeat: 93% -- { 93000172 } -- 500.00 KIPS (537.57 KIPS) +** Heartbeat: 94% -- { 94000176 } -- 500.00 KIPS (537.14 KIPS) +** Heartbeat: 95% -- { 95000181 } -- 1000.00 KIPS (539.77 KIPS) +** Heartbeat: 96% -- { 96000181 } -- 500.00 KIPS (539.33 KIPS) +** Heartbeat: 97% -- { 97000181 } -- 500.00 KIPS (538.89 KIPS) +** Heartbeat: 98% -- { 98000183 } -- 500.00 KIPS (538.46 KIPS) +** Heartbeat: 99% -- { 99000186 } -- 500.00 KIPS (538.04 KIPS) +** Core 0 Finished: insts:100000000 cycles:50809793 time:15878060312500 -- 1.97 IPC (1.97 IPC) -- N/A KIPS (537.63 KIPS) +done +Scarab finished at Sun Jun 11 08:11:44 2023 + diff --git a/labs/LAB5/runs/deepsjeng-sms0/stream.stat.0.out b/labs/LAB5/runs/deepsjeng-sms0/stream.stat.0.out new file mode 100644 index 00000000..0a765402 --- /dev/null +++ b/labs/LAB5/runs/deepsjeng-sms0/stream.stat.0.out @@ -0,0 +1,188 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 50809793 Instructions: 100000000 IPC: 1.96812 + +DCACHE_PREF_HIT 0 0 + +IFETCH_WB_FIRST_SCHEDULE 0 -nan% 0 -nan% +PREFETCH_LAST_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_PREF_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_LOW_OP_SCHEDULE 0 -nan% 0 -nan% +DEMAND_LAST_SCHEDULE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +SEND_MISS_REQ_QUEUE 28246 28246 + +L1_DATA_EVICT 11983 11983 + +STREAM_BUFFER_REQ 0 0 + +PREF_SEND_TO_MEM_REQ 0 -nan% 0 -nan% +PREF_SEND_TO_MEM_REQ_FAIL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +HIT_TRAIN_STREAM 574 2.084% 574 2.084% +MISS_TRAIN_STREAM 26974 97.916% 26974 97.916% + 27548 100.000% 27548 100.000% + 0.98 0.97 0.98 0.97 + +STREAM_TRAIN_CREATE 17351 17351 + +MEM_REQ_MISS_HWP_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_SW_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_IFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DSTORE_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DPRF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_WB_Q 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_BY_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_WB 0 -nan% 0 -nan% +PREF_HIT_BY_PREF 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_WB 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_L1_FILL 0 -nan% 0 -nan% +DEMAND_L1_FILL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TOUCH_L1_REPLACE 0 0.000% 0 0.000% +NO_TOUCH_L1_REPLACE 11983 100.000% 11983 100.000% + 11983 100.000% 11983 100.000% + 1.00 1.00 1.00 1.00 + +PREF_REQ_QUE_FULL 0 0 + +STREAM_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +L2HIT_STREAM_PREF_REQ_QUE_FULL 0 0 + +L2HIT_HIT_TRAIN_STREAM 0 -nan% 0 -nan% +L2HIT_MISS_TRAIN_STREAM 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_TRAIN_CREATE 0 0 + +L2HIT_STREAM_BUFFER_REQ 0 0 + +L2HIT_STREAM_PREF_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_STREAM_PREF_DCACHE_INSERT 0 -nan% 0 -nan% +L2HIT_STREAM_L2_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_DCACHE_PORT_FULL 0 0 + +L2HIT_STREAM_PREF_L1_PORT_FULL 0 0 + +L2HIT_TRAIN_HIT_DEMAND 0 -nan% 0 -nan% +L2HIT_TRAIN_MISS_REQ 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_TRAIN_FILTER_MISS 0 -nan% 0 -nan% +L2HIT_TRAIN_FILTER_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_PREF_REQ_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_PREF_REQ_DCACHE_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_L2SEND_Q_FULL 0 -nan% 0 -nan% +L2HIT_L2SEND_Q_ENTER 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_MEM_REQ 0 0 + +REMOVE_REDUNDANT_STREAM_STAT 0 0 + +REPLACE_OLD_STREAM 17335 17335 + +REQ_SEND_QUEUE_STALL 0 0 + +STREAM_ENTER_RA 0 0 + +CORE_STREAM_LENGTH_0 33 20.625% 33 20.625% +CORE_STREAM_LENGTH_10 73 45.625% 73 45.625% +CORE_STREAM_LENGTH_20 48 30.000% 48 30.000% +CORE_STREAM_LENGTH_30 4 2.500% 4 2.500% +CORE_STREAM_LENGTH_40 2 1.250% 2 1.250% +CORE_STREAM_LENGTH_50 0 0.000% 0 0.000% +CORE_STREAM_LENGTH_60 0 0.000% 0 0.000% +CORE_STREAM_LENGTH_70 0 0.000% 0 0.000% +CORE_STREAM_LENGTH_80 0 0.000% 0 0.000% +CORE_STREAM_LENGTH_90 0 0.000% 0 0.000% +CORE_STREAM_LENGTH_100_P 0 0.000% 0 0.000% + 160 100.000% 160 100.000% + 1.18 0.63 1.18 0.63 + +CORE_CUM_STREAM_LENGTH_0 222 8.679% 222 8.679% +CORE_CUM_STREAM_LENGTH_10 1042 40.735% 1042 40.735% +CORE_CUM_STREAM_LENGTH_20 1079 42.181% 1079 42.181% +CORE_CUM_STREAM_LENGTH_30 129 5.043% 129 5.043% +CORE_CUM_STREAM_LENGTH_40 86 3.362% 86 3.362% +CORE_CUM_STREAM_LENGTH_50 0 0.000% 0 0.000% +CORE_CUM_STREAM_LENGTH_60 0 0.000% 0 0.000% +CORE_CUM_STREAM_LENGTH_70 0 0.000% 0 0.000% +CORE_CUM_STREAM_LENGTH_80 0 0.000% 0 0.000% +CORE_CUM_STREAM_LENGTH_90 0 0.000% 0 0.000% +CORE_CUM_STREAM_LENGTH_100_P 0 0.000% 0 0.000% + 2558 100.000% 2558 100.000% + 1.54 0.72 1.54 0.72 + +CORE_STREAM_TRAIN_HITS_0 127 79.375% 127 79.375% +CORE_STREAM_TRAIN_HITS_10 31 19.375% 31 19.375% +CORE_STREAM_TRAIN_HITS_20 2 1.250% 2 1.250% +CORE_STREAM_TRAIN_HITS_30 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_40 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_50 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_60 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_70 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_80 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_90 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_100_P 0 0.000% 0 0.000% + 160 100.000% 160 100.000% + 0.22 0.40 0.22 0.40 + +CORE_CUM_STREAM_TRAIN_HITS_0 801 65.980% 801 65.980% +CORE_CUM_STREAM_TRAIN_HITS_10 372 30.643% 372 30.643% +CORE_CUM_STREAM_TRAIN_HITS_20 41 3.377% 41 3.377% +CORE_CUM_STREAM_TRAIN_HITS_30 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_40 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_50 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_60 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_70 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_80 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_90 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_100_P 0 0.000% 0 0.000% + 1214 100.000% 1214 100.000% + 0.37 0.46 0.37 0.46 + +CORE_STREAM_TRAIN_CREATE 17351 17351 + + + diff --git a/labs/LAB5/runs/deepsjeng-sms1/PARAMS.in b/labs/LAB5/runs/deepsjeng-sms1/PARAMS.in new file mode 100644 index 00000000..2593c2b8 --- /dev/null +++ b/labs/LAB5/runs/deepsjeng-sms1/PARAMS.in @@ -0,0 +1,226 @@ +# File : PARAMS.kaby_lake +# Date : 03/06/19 +# Description : Kaby Lake Configuration +# +# Based on documentation found here: +# https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake + +## Simulation Parameters +--mode full +--model cmp +--sim_limit none + +## Core Parameters + +# Femptoseconds, 3.2GHz, used for energy estimates. +--chip_cycle_time 312500 + + +### Fetch Stage +--fetch_off_path_ops 1 +--fetch_across_cache_lines 1 + +# Will break the packet upon a taken branch. +--fetch_break_on_taken 1 + +# Number of bubble cycles to wait after taken branch. +--fetch_taken_bubble_cycles 0 + + +#### ICache +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 + +### Branch Predictor +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_mech tagescl + + +#### BTB + +# BTB model to use. +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 + +# Allow the BTB to be updated by off path ops. +--btb_off_path_writes 1 + + +#### CRS + +# Enable return stack +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 + +### iBP +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged + # iBTB Model. tc_tagless, tc_tagged, tc_hybrid. +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 + +### Decode Stage +--decode_cycles 5 + + +### Map Stage +--map_cycles 5 + + +### Issue Stage + +# Max number of instructions to be fetched, decoded, renamed, and issued per cycle. +--issue_width 6 + +--rs_fill_width 0 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 + + +### Exec Stage + +### DCache +--dcache_size 32768 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--dcache_assoc 4 +--dcache_line_size 64 + +### Reorder/Retire Stage + +# Max number of instructions to be retired per cycle. +--node_ret_width 6 +--node_table_size 224 + +# Do not keep stores in RSVs on cache misses; TODO: confirm what this knob does +--stores_do_not_block_window 1 + +# TODO: confirm what this knob does +--prefs_do_not_block_window 1 + + +## Uncore + +### Mid-level cache + +# Enable use of a midlevel cache between i/d and L1 +--mlc_present 0 + +### LLC +--l1_size 1048576 +--l1_banks 1 +--l1_cycles 18 +--l1_assoc 8 +--l1_line_size 64 +--l1_interleave_factor 64 + + +### Prefetcher +--pref_framework_on 1 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--pref_shared_queues 0 +--pref_train_on_pref_misses 0 +--pref_oracle_train 0 +--pref_ul1req_queue_overwrite_on_full 1 + +--stream_length 64 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 + +--pref_throttlefb_on=1 +--pref_acc_thresh_1=0.75 +--pref_acc_thresh_2=0.4 +--pref_acc_thresh_3=0.4 +--pref_timely_thresh=0.01 +--pref_polpf_thresh=0.005 +--pref_update_interval=8192 + +--mem_req_buffer_pref_watermark 4 +--promote_to_higher_priority_mem_req_type 1 + +### Memory +--addr_translation random + +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 + +--mem_req_buffer_entries 32 +--mem_l1_fill_queue_entries 32 +--va_page_size_bytes 4096 +--bus_width_in_bytes 8 + +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 + +## Other + + +### Debug +--debug_inst_start 0 +--debug_inst_stop -1 +--debug_cycle_start 0 +--debug_cycle_stop -1 + + +## Stats and Params +--dump_params 1 +--dump_stats 1 +--dump_trace 0 + +#################################### +--set_off_path_confirmed 1 + +--order_beyond_bus 1 + +--mem_ooo_stores 1 +--mem_obey_store_dep 1 diff --git a/labs/LAB5/runs/deepsjeng-sms1/PARAMS.out b/labs/LAB5/runs/deepsjeng-sms1/PARAMS.out new file mode 100644 index 00000000..b91f7ebc --- /dev/null +++ b/labs/LAB5/runs/deepsjeng-sms1/PARAMS.out @@ -0,0 +1,908 @@ +--mode full +--model cmp +--frontend memtrace +--inst_limit 100000000 +--sim_limit none +--dump_params 1 +--dump_stats 1 +--dump_trace 0 +--mlc_present 0 +--l1_size 1048576 +--l1_assoc 8 +--l1_line_size 64 +--l1_cycles 18 +--l1_banks 1 +--l1_interleave_factor 64 +--va_page_size_bytes 4096 +--addr_translation random +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 +--dcache_size 32768 +--dcache_assoc 4 +--dcache_line_size 64 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--mem_ooo_stores 1 +--mem_obey_store_dep 1 +--mem_req_buffer_entries 32 +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 +--promote_to_higher_priority_mem_req_type 1 +--mem_req_buffer_pref_watermark 4 +--mem_l1_fill_queue_entries 32 +--order_beyond_bus 1 +--set_off_path_confirmed 1 +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--bus_width_in_bytes 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 +--chip_cycle_time 312500 +--issue_width 6 +--rs_fill_width 0 +--node_table_size 224 +--node_ret_width 6 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 +--decode_cycles 5 +--map_cycles 5 +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--fetch_across_cache_lines 1 +--fetch_off_path_ops 0 +--fetch_break_on_taken 1 +--fetch_taken_bubble_cycles 0 +--stores_do_not_block_window 1 +--prefs_do_not_block_window 1 +--cbp_trace_r0 /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir/trace/drmemtrace.deepsjeng.553743.6815.trace.gz +--memtrace_modules_log /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir/raw +--debug_cycle_start 0 +--debug_cycle_stop -1 +--debug_inst_start 0 +--debug_inst_stop -1 +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--bp_mech tagescl +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 +--btb_off_path_writes 1 +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_length 64 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 +--pref_framework_on 1 +--pref_shared_queues 0 +--pref_ul1req_queue_overwrite_on_full 1 +--pref_train_on_pref_misses 0 +--pref_oracle_train_on 0 +--pref_throttlefb_on 1 +--pref_acc_thresh_1 0.75 +--pref_acc_thresh_2 0.4 +--pref_acc_thresh_3 0.4 +--pref_update_interval 8192 +--pref_timely_thresh 0.01 +--pref_polpf_thresh 0.005 +--pref_sms_on 1 +1 1 1 1 1 1 1 + +--- Cut out everything below to use this file as PARAMS.in --- + +Parameter status at compile time and values supplied on the command line: + +SIM_MODE 0 full +SIM_MODEL 0 cmp +FRONTEND FE_PIN_EXEC_DRIVEN memtrace +INST_LIMIT NULL 100000000 +SIM_LIMIT "none" none +FORWARD_PROGRESS_LIMIT 100000000 +FORWARD_PROGRESS_INTERVAL 10000 +FAST_FORWARD 0 +FAST_FORWARD_UNTIL_ADDR 0 +FAST_FORWARD_TRACE_INS 0 +WARMUP 0 +HEARTBEAT_INTERVAL 1000000 +NUM_HEARTBEATS 0 +FILE_TAG "" +OUTPUT_DIR "." +STATUS_FILE NULL +BINDIR NULL +DUMP_PARAMS TRUE 1 +DUMP_STATS TRUE 1 +DUMP_TRACE FALSE 0 +CLEAR_STATS "never" +STATS_TO_TRACE NULL +STAT_TRACE_FILE "stats.trace" +STAT_TRACE_INTERVAL "i:100000" +PIPEVIEW FALSE +PIPEVIEW_FILE "pipeview" +MEMVIEW FALSE +MEMVIEW_FILE "memview.out" +MEMVIEW_START "never" +INST_HASH_TABLE_SIZE 500021 const +STDOUT_FILE NULL +STDERR_FILE NULL +PIN_EXEC_DRIVEN_FE_SOCKET "./pin_exec_driven_fe_socket.temp" +PRINT_PID FALSE +USE_UNSURE_FREE_LISTS FALSE +OPTIMIZER2_MAX_NUM_SLAVES 64 +OPTIMIZER2_PERFECT_MEMORYLESS FALSE +EXIT_COND 0 +ENABLE_SWPRF FALSE +MLC_PRESENT FALSE 0 +MLC_SIZE (512 * 1024) +MLC_ASSOC 4 +MLC_LINE_SIZE 64 +MLC_CYCLES 12 +PERFECT_MLC FALSE +MLC_READ_PORTS 1 +MLC_WRITE_PORTS 1 +MLC_BANKS 8 +MLC_INTERLEAVE_FACTOR 64 +MLC_CACHE_REPL_POLICY 0 +MLC_WRITE_THROUGH FALSE +PREFETCH_UPDATE_LRU_MLC TRUE +FORCE_L1_MISS FALSE +L1_SIZE (4 * 1024 * 1024) 1048576 +L1_ASSOC 8 8 +L1_LINE_SIZE 64 64 +L1_CYCLES 24 18 +PERFECT_L1 FALSE +PRIVATE_L1 FALSE +L1_READ_PORTS 1 +L1_WRITE_PORTS 1 +L1_BANKS 8 1 +L1_INTERLEAVE_FACTOR 64 64 +L1_CACHE_REPL_POLICY 0 +L1_WRITE_THROUGH FALSE +L1_IGNORE_WB FALSE +L1_USE_CORE_FREQ FALSE +MARK_L1_MISSES TRUE +PREFETCH_UPDATE_LRU_L1 TRUE +MEMORY_RANDOM_ADDR FALSE +VA_PAGE_SIZE_BYTES 4096 4096 +NUM_ADDR_NON_SIGN_EXTEND_BITS 48 +ADDR_TRANSLATION 0 random +CONSTANT_MEMORY_LATENCY FALSE +MEMORY_CYCLES 100 +STALL_MEM_REQS_ONLY FALSE +ICACHE_SIZE (64 * 1024) 32768 +ICACHE_ASSOC 4 4 +ICACHE_LINE_SIZE 64 64 +PERFECT_ICACHE FALSE +ICACHE_READ_PORTS 2 +ICACHE_WRITE_PORTS 1 +ICACHE_BANKS 8 +ICACHE_REPL 0 +DCACHE_SIZE (64 * 1024) 32768 +DCACHE_ASSOC 1 4 +DCACHE_LINE_SIZE 64 64 +DCACHE_CYCLES 2 +PERFECT_DCACHE FALSE +DCACHE_READ_PORTS 8 2 +DCACHE_WRITE_PORTS 1 1 +DCACHE_BANKS 1 1 +DCACHE_REPL 0 +DCACHE_REPL_PREF_THRESH 1 +MEM_OOO_STORES TRUE 1 +MEM_OBEY_STORE_DEP TRUE 1 +PREF_INSERT_LRU FALSE +PREF_INSERT_MIDDLE FALSE +PREF_INSERT_LOWQTR FALSE +PREF_INSERT_DYNACC FALSE +MEM_REQ_BUFFER_ENTRIES 32 32 +PRIVATE_MSHR_ON TRUE +MEM_PRIORITY_IFETCH 0 0 +MEM_PRIORITY_DFETCH 0 1 +MEM_PRIORITY_DSTORE 0 2 +MEM_PRIORITY_IPRF 9 3 +MEM_PRIORITY_DPRF 10 4 +MEM_PRIORITY_WB 0 5 +MEM_PRIORITY_WB_NODIRTY 0 5 +PROMOTE_TO_HIGHER_PRIORITY_MEM_REQ_TYPE FALSE 1 +MEM_REQ_BUFFER_PREF_WATERMARK 0 4 +MEM_REQ_BUFFER_WB_VALVE 2 +MEM_L1_FILL_QUEUE_ENTRIES 32 32 +MEM_BUS_OUT_QUEUE_PARTITION_ENABLE FALSE +MEM_MEM_QUEUE_PARTITION_ENABLE FALSE +MEM_BUS_OUT_QUEUE_AS_FIFO TRUE +OLDEST_FIRST_TO_MEM_QUEUE TRUE +ROUND_ROBIN_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE_TH 0 +L1_CYCLE_TIME 312500 +MLCQ_TO_L1Q_TRANSFER_LATENCY 1 +L1Q_TO_FSB_TRANSFER_LATENCY 1 +PRIORITIZE_PREFETCHES_WITH_UNIQUE FALSE +KICKOUT_PREFETCHES FALSE +KICKOUT_LOOK_FOR_OLDEST_FIRST FALSE +KICKOUT_OLDEST_PREFETCH FALSE +KICKOUT_OLDEST_PREFETCH_WITHIN_BANK FALSE +ORDER_BEYOND_BUS FALSE 1 +ALL_FIFO_QUEUES FALSE +QUEUE_MLC_SIZE 0 +QUEUE_L1_SIZE 0 +QUEUE_BUS_OUT_SIZE 0 +QUEUE_CORE_FILL_SIZE 0 +ALLOW_TYPE_MATCHES FALSE +STREAM_PREFETCH_ON FALSE +DC_PREF_CACHE_ENABLE FALSE +DC_PREF_CACHE_CYCLE 0 +PREF_INSERT_DCACHE_IMM TRUE +DC_PREF_CACHE_SIZE (64 * 1024) +DC_PREF_CACHE_ASSOC 4 +DC_PREF_ONLY_L1HIT FALSE +PREF_CACHE_USE_RDY_CYCLE FALSE +IC_PREF_CACHE_ENABLE FALSE +IC_PREF_CACHE_SIZE (64 * 1024) +IC_PREF_CACHE_ASSOC 4 +L1_PREF_CACHE_ENABLE FALSE +L1_PREF_CACHE_SIZE (1024 * 1024) +L1_PREF_CACHE_ASSOC 8 +SET_OFF_PATH_CONFIRMED FALSE 1 +USE_CONFIRMED_OFF FALSE +PREFCACHE_MOVE_OFFPATH FALSE +CACHE_STAT_ENABLE FALSE +PREF_DCACHE_HIT_FILL_L1 TRUE +PREF_ICACHE_HIT_FILL_L1 TRUE +CRITICAL_ACCESS_PLOT_ENABLE FALSE +CRITICAL_ACCESS_PLOT_FILE "critical_access_plot.dat" +ROUND_ROBIN_TO_L1 FALSE +PREF_I_TOGETHER FALSE +ONE_MORE_CACHE_LINE_ENABLE FALSE +L1_STATIC_PARTITION_ENABLE 0 +L1_STATIC_PARTITION NULL +L1_DYNAMIC_PARTITION_ENABLE FALSE +L1_DYNAMIC_PARTITION_POLICY 0 +PARTITION_UMON_DSS_PREF_ENABLE FALSE +L1_CACHE_HIT_POSITION_COLLECT FALSE +L1_PART_ON FALSE +L1_PART_TRIGGER "c:1000000" +L1_PART_START "t:0" +L1_PART_WARMUP FALSE +L1_PART_SHADOW_WARMUP FALSE +L1_PART_METRIC 0 +L1_PART_SEARCH 0 +L1_PART_USE_STALLING TRUE +L1_PART_FILL_DELAY 0 +L1_SHADOW_TAGS_MODULO 1 +HIER_MSHR_ON FALSE +PERF_PRED_ENABLE FALSE +PERF_PRED_MECH PERF_PRED_CP +PERF_PRED_REQ_LATENCY_MECH PERF_PRED_REQ_LATENCY_MECH_REQ_LATENCY +PERF_PRED_COUNT_ALL FALSE +PERF_PRED_COUNT_INST_MISSES TRUE +PERF_PRED_COUNT_PREFETCHES FALSE +PERF_PRED_COUNT_OFFPATH_REQS FALSE +PERF_PRED_COUNT_BW_REQS TRUE +PERF_PRED_UPDATE_MEM_REQ_TYPE FALSE +PERF_PRED_SLACK_PERIOD_SIZE 32 +PERF_PRED_REQS_FINISH_AT_FILL FALSE +PERF_PRED_MEM_UTIL_VIA_BUS_BW FALSE +PERF_PRED_CHIP_UTIL_VIA_MEM_STALL FALSE +DUMB_MODEL_AVG_REQ_DISTANCE 100 +DUMB_MODEL_RANDOMIZE_DISTANCE FALSE +DUMB_MODEL_AVG_REQ_DISTANCE_PER_CORE NULL +DUMB_MODEL_AVG_ROW_HITS 1 +DUMB_MODEL_AVG_ROW_HITS_PER_CORE NULL +DUMB_MODEL_MLP 1 +DUMB_MODEL_MLP_PER_CORE NULL +RAMULATOR_STANDARD "DDR4" DDR4 +RAMULATOR_SPEED "DDR4_2400R" DDR4_2400R +RAMULATOR_ORG "DDR4_8Gb_x8" DDR4_8Gb_x8 +RAMULATOR_CHANNELS 1 1 +RAMULATOR_RANKS 1 1 +RAMULATOR_BANKGROUPS 4 4 +RAMULATOR_BANKS 4 4 +RAMULATOR_CHIP_WIDTH 8 8 +BUS_WIDTH_IN_BYTES 8 8 +RAMULATOR_ROWS 65536 65536 +RAMULATOR_COLS 1024 1024 +RAMULATOR_SCHEDULING_POLICY "FRFCFS_Cap" FRFCFS_Cap +RAMULATOR_READQ_ENTRIES 32 32 +RAMULATOR_WRITEQ_ENTRIES 32 32 +RAMULATOR_REC_CMD_TRACE "off" FALSE +RAMULATOR_PRINT_CMD_TRACE "off" FALSE +RAMULATOR_USE_REST_OF_ADDR_AS_ROW_ADDR "on" +RAMULATOR_TCK 833333 833333 +RAMULATOR_TCL 16 16 +RAMULATOR_TCCD 6 6 +RAMULATOR_TCCDS 4 4 +RAMULATOR_TCCDL 6 6 +RAMULATOR_TCWL 12 12 +RAMULATOR_TBL 4 4 +RAMULATOR_TWTR 9 9 +RAMULATOR_TWTRS 3 3 +RAMULATOR_TWTRL 9 9 +RAMULATOR_TRP 16 16 +RAMULATOR_TRPpb 16 16 +RAMULATOR_TRPab 16 16 +RAMULATOR_TRCD 16 16 +RAMULATOR_TRCDR 16 16 +RAMULATOR_TRCDW 16 16 +RAMULATOR_TRAS 39 39 +DRAM_TECH_IN_NM 32 32 +DVFS_ON FALSE +DVFS_METRIC DVFS_METRIC_NUM_ELEMS +DVFS_CONFIGS NULL +DVFS_CONFIG_FILE NULL +DVFS_START "t:0" +DVFS_PERIOD "t:312500000000" +DVFS_LOG TRUE +DVFS_INDIVIDUAL_CORES FALSE +DVFS_CHIP_LEVEL FALSE +DVFS_STATIC NULL +DVFS_FORCE_CONFIG NULL +DVFS_REPLAY_CONFIG_TRACE NULL +DVFS_USE_ORACLE FALSE +DVFS_USE_BW_SHARING FALSE +DVFS_USE_DRAM_SHARING FALSE +DVFS_USE_STALL_TIME FALSE +DVFS_DRAM_SHARING_SOLVER_BIN NULL +DVFS_DRAM_SHARING_SOLVER_STRICT TRUE +DVFS_BW_SHARING_BUS_UTIL_THRESH 0.95 +DVFS_BW_SHARING_MAX_REQS 28.0 +DVFS_BW_SHARING_MAX_RW_COST 0.25 +DVFS_BW_SHARING_NO_PREF_STALL TRUE +DVFS_BW_SHARING_CRIT_STATS TRUE +DVFS_COUNT_L1_ACCESS_STALL FALSE +NUM_CORES 1 +CHIP_CYCLE_TIME 312500 312500 +CORE_0_CYCLE_TIME 312500 +CORE_1_CYCLE_TIME 312500 +CORE_2_CYCLE_TIME 312500 +CORE_3_CYCLE_TIME 312500 +CORE_4_CYCLE_TIME 312500 +CORE_5_CYCLE_TIME 312500 +CORE_6_CYCLE_TIME 312500 +CORE_7_CYCLE_TIME 312500 +CORE_8_CYCLE_TIME 312500 +CORE_9_CYCLE_TIME 312500 +CORE_10_CYCLE_TIME 312500 +CORE_11_CYCLE_TIME 312500 +CORE_12_CYCLE_TIME 312500 +CORE_13_CYCLE_TIME 312500 +CORE_14_CYCLE_TIME 312500 +CORE_15_CYCLE_TIME 312500 +CORE_16_CYCLE_TIME 312500 +CORE_17_CYCLE_TIME 312500 +CORE_18_CYCLE_TIME 312500 +CORE_19_CYCLE_TIME 312500 +CORE_20_CYCLE_TIME 312500 +CORE_21_CYCLE_TIME 312500 +CORE_22_CYCLE_TIME 312500 +CORE_23_CYCLE_TIME 312500 +CORE_24_CYCLE_TIME 312500 +CORE_25_CYCLE_TIME 312500 +CORE_26_CYCLE_TIME 312500 +CORE_27_CYCLE_TIME 312500 +CORE_28_CYCLE_TIME 312500 +CORE_29_CYCLE_TIME 312500 +CORE_30_CYCLE_TIME 312500 +CORE_31_CYCLE_TIME 312500 +CORE_32_CYCLE_TIME 312500 +CORE_33_CYCLE_TIME 312500 +CORE_34_CYCLE_TIME 312500 +CORE_35_CYCLE_TIME 312500 +CORE_36_CYCLE_TIME 312500 +CORE_37_CYCLE_TIME 312500 +CORE_38_CYCLE_TIME 312500 +CORE_39_CYCLE_TIME 312500 +CORE_40_CYCLE_TIME 312500 +CORE_41_CYCLE_TIME 312500 +CORE_42_CYCLE_TIME 312500 +CORE_43_CYCLE_TIME 312500 +CORE_44_CYCLE_TIME 312500 +CORE_45_CYCLE_TIME 312500 +CORE_46_CYCLE_TIME 312500 +CORE_47_CYCLE_TIME 312500 +CORE_48_CYCLE_TIME 312500 +CORE_49_CYCLE_TIME 312500 +CORE_50_CYCLE_TIME 312500 +CORE_51_CYCLE_TIME 312500 +CORE_52_CYCLE_TIME 312500 +CORE_53_CYCLE_TIME 312500 +CORE_54_CYCLE_TIME 312500 +CORE_55_CYCLE_TIME 312500 +CORE_56_CYCLE_TIME 312500 +CORE_57_CYCLE_TIME 312500 +CORE_58_CYCLE_TIME 312500 +CORE_59_CYCLE_TIME 312500 +CORE_60_CYCLE_TIME 312500 +CORE_61_CYCLE_TIME 312500 +CORE_62_CYCLE_TIME 312500 +CORE_63_CYCLE_TIME 312500 +ISSUE_WIDTH 4 6 +RS_FILL_WIDTH 8 0 +NODE_TABLE_SIZE 256 224 +NODE_RET_WIDTH 4 6 +NODE_RETIRE_RATE 10 +RS_SIZES "256" 97 +RS_CONNECTIONS "xF" 0 +FU_TYPES "0, 0, 0, 0" 0 0 0 0 0 0 0 0 +DECODE_CYCLES 1 5 +MAP_CYCLES 1 5 +EXTRA_RECOVERY_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after recovery. +EXTRA_REDIRECT_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after redirect. +EXTRA_CALLSYS_CYCLES 20 const +DIE_ON_CALLSYS FALSE +DIE_ON_RET_STALL_THRESH 0 +DIE_ON_RET_STALL_CORE 0 +DIE_ON_MEM_BLOCK_THRESH 0 +DIE_ON_MEM_BLOCK_CORE 0 +FETCH_ACROSS_CACHE_LINES FALSE 1 +FETCH_OFF_PATH_OPS TRUE 0 +FETCH_BREAK_ON_TAKEN FALSE 1 +FETCH_TAKEN_BUBBLE_CYCLES 0 0 +WP_COLLECT_STATS FALSE +SWITCH_IC_FETCH_ON_RECOVERY TRUE +OP_INV_DELAY 1 +OP_NOP_DELAY 1 +OP_CF_DELAY 1 +OP_MOV_DELAY 1 +OP_CMOV_DELAY 1 +OP_LDA_DELAY 1 +OP_IMEM_DELAY 1 +OP_IADD_DELAY 1 +OP_IMUL_DELAY 3 +OP_IDIV_DELAY -20 +OP_ICMP_DELAY 1 +OP_LOGIC_DELAY 1 +OP_SHIFT_DELAY 1 +OP_FMEM_DELAY 1 +OP_FCVT_DELAY 3 +OP_FADD_DELAY 3 +OP_FMUL_DELAY 5 +OP_FMA_DELAY 5 +OP_FDIV_DELAY -20 +OP_FCMP_DELAY 3 +OP_FCMOV_DELAY 1 +OP_GATHER_DELAY 12 +OP_SCATTER_DELAY 18 +OP_PIPELINED_FAST_DELAY 2 +OP_PIPELINED_MEDIUM_DELAY 5 +OP_PIPELINED_SLOW_DELAY 10 +OP_NOTPIPELINED_MEDIUM_DELAY -5 +OP_NOTPIPELINED_SLOW_DELAY -20 +OP_NOTPIPELINED_VERY_SLOW_DELAY -100 +UNIFORM_OP_DELAY 0 +STALL_ON_WAIT_MEM TRUE +STORES_DO_NOT_BLOCK_WINDOW FALSE 1 +PREFS_DO_NOT_BLOCK_WINDOW FALSE 1 +OBEY_REG_DEP TRUE +OLDEST_FIRST_SCHED FALSE +FIND_EMPTIEST_RS FALSE +TRACK_L1_MISS_DEPS FALSE +CBP_TRACE_R0 NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir/trace/drmemtrace.deepsjeng.553743.6815.trace.gz +CBP_TRACE_R1 NULL +CBP_TRACE_R2 NULL +CBP_TRACE_R3 NULL +CBP_TRACE_R4 NULL +CBP_TRACE_R5 NULL +CBP_TRACE_R6 NULL +CBP_TRACE_R7 NULL +CBP_TRACE_R8 NULL +CBP_TRACE_R9 NULL +CBP_TRACE_R10 NULL +CBP_TRACE_R11 NULL +CBP_TRACE_R12 NULL +CBP_TRACE_R13 NULL +CBP_TRACE_R14 NULL +CBP_TRACE_R15 NULL +CBP_TRACE_R16 NULL +CBP_TRACE_R17 NULL +CBP_TRACE_R18 NULL +CBP_TRACE_R19 NULL +CBP_TRACE_R20 NULL +CBP_TRACE_R21 NULL +CBP_TRACE_R22 NULL +CBP_TRACE_R23 NULL +CBP_TRACE_R24 NULL +CBP_TRACE_R25 NULL +CBP_TRACE_R26 NULL +CBP_TRACE_R27 NULL +CBP_TRACE_R28 NULL +CBP_TRACE_R29 NULL +CBP_TRACE_R30 NULL +CBP_TRACE_R31 NULL +CBP_TRACE_R32 NULL +CBP_TRACE_R33 NULL +CBP_TRACE_R34 NULL +CBP_TRACE_R35 NULL +CBP_TRACE_R36 NULL +CBP_TRACE_R37 NULL +CBP_TRACE_R38 NULL +CBP_TRACE_R39 NULL +CBP_TRACE_R40 NULL +CBP_TRACE_R41 NULL +CBP_TRACE_R42 NULL +CBP_TRACE_R43 NULL +CBP_TRACE_R44 NULL +CBP_TRACE_R45 NULL +CBP_TRACE_R46 NULL +CBP_TRACE_R47 NULL +CBP_TRACE_R48 NULL +CBP_TRACE_R49 NULL +CBP_TRACE_R50 NULL +CBP_TRACE_R51 NULL +CBP_TRACE_R52 NULL +CBP_TRACE_R53 NULL +CBP_TRACE_R54 NULL +CBP_TRACE_R55 NULL +CBP_TRACE_R56 NULL +CBP_TRACE_R57 NULL +CBP_TRACE_R58 NULL +CBP_TRACE_R59 NULL +CBP_TRACE_R60 NULL +CBP_TRACE_R61 NULL +CBP_TRACE_R62 NULL +CBP_TRACE_R63 NULL +MEMTRACE_MODULES_LOG NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.deepsjeng.553743.1618.dir/raw +DUMB_CORE_ON FALSE +DUMB_CORE 1 +DEBUG_CYCLE_START 0 0 +DEBUG_CYCLE_STOP 0 -1 +DEBUG_TIME_START 0 +DEBUG_TIME_STOP 0 +DEBUG_INST_START 0 0 +DEBUG_INST_STOP 0 -1 +DEBUG_OP_START 0 +DEBUG_OP_STOP 0 +DEBUG_CACHE_LIB FALSE +DEBUG_HASH_LIB FALSE +DEBUG_LIST_LIB FALSE +DEBUG_PORT_LIB FALSE +DEBUG_BUS_LIB FALSE +DEBUG_OP_POOL FALSE +DEBUG_ORACLE FALSE +DEBUG_FRONTEND FALSE +DEBUG_ADDR_TRANS FALSE +DEBUG_BP FALSE +DEBUG_BP_DIR FALSE +DEBUG_BTB FALSE +DEBUG_CRS FALSE +DEBUG_MAP FALSE +DEBUG_MEMORY FALSE +DEBUG_REPLAY FALSE +DEBUG_FREQ FALSE +DEBUG_MODEL FALSE +DEBUG_THREAD FALSE +DEBUG_ICACHE_STAGE FALSE +DEBUG_DECODE_STAGE FALSE +DEBUG_MAP_STAGE FALSE +DEBUG_NODE_STAGE FALSE +DEBUG_EXEC_STAGE FALSE +DEBUG_DCACHE_STAGE FALSE +DEBUG_RETIRED_UOPS FALSE +DEBUG_EXC_INSERTS FALSE +DEBUG_BP_CONF FALSE +DEBUG_ONPATH_CONF FALSE +DEBUG_STREAM FALSE +DEBUG_STREAM_MEM FALSE +DEBUG_WAY FALSE +DEBUG_L2MARKV FALSE +DEBUG_L2L1PREF FALSE +DEBUG_PERF_PRED FALSE +DEBUG_POWER_UTILS FALSE +DEBUG_DVFS FALSE +DEBUG_TRACE_READ FALSE +DEBUG_INST_FIELDS FALSE +DEBUG_OP_FIELDS FALSE +DEBUG_PIN_EXEC_DRIVEN FALSE +DEBUG_CACHE_PART FALSE +DEBUG_OPTIMIZER2 FALSE +DEBUG_PREF FALSE +PERFECT_BP FALSE +PERFECT_BTB FALSE +PERFECT_IBP FALSE +PERFECT_CRS FALSE +PERFECT_CBR_BTB FALSE +PERFECT_NT_BTB FALSE +CFS_PER_CYCLE 3 6 # Number of branches that can be predicted in a single cycle +UPDATE_BP_OFF_PATH FALSE 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +BP_UPDATE_AT_RETIRE FALSE 0 # Update the BP at retire. If false, update at the end of exec. +BP_MECH 0 tagescl +LATE_BP_MECH NUM_BP +LATE_BP_LATENCY 5 +HIST_LENGTH 16 +PHT_CTR_BITS 2 const +BHT_ENTRIES (4 * 1024) +BHT_ASSOC 4 +HYBRIDS_INDEX_LENGTH 16 +HYBRIDG_HIST_LENGTH 16 +HYBRIDP_HIST_LENGTH 16 +FILTER_INDEX_LENGTH 16 +USE_FILTER FALSE +INF_HYBRIDGP FALSE +BP_HASH_TOS FALSE +IBTB_HASH_TOS FALSE +BTB_MECH 0 generic +BTB_ENTRIES (4 * 1024) 4096 +BTB_ASSOC 4 4 +BTB_OFF_PATH_WRITES TRUE 1 +ENABLE_CRS TRUE 1 +CRS_ENTRIES 32 32 +CRS_REALISTIC 0 1 +ENABLE_IBP TRUE 1 # Enable the indirect branch predictor +USE_PAT_HIST TRUE +IBTB_MECH 1 tc_tagged +IBTB_HIST_LENGTH 16 +IBTB_OFF_PATH_WRITES TRUE 1 # Allow off path ops to update the ibtb. +TARGETS_IN_HIST 4 +TC_ENTRIES (4 * 1024) 4096 +TC_ASSOC 4 4 +NUM_CORR_BRANCHES 3 +SEL_HIST_BP_ENTRIES 8192 +SEL_HIST_LENGTH 16 +SEL_HIST_DYN_CNT_TH 16 +SEL_HIST_MISPRED_TH 4 +ENABLE_BP_CONF FALSE +CONF_MECH 0 +PERF_BP_CONF_PRED FALSE +BPC_BITS 16 +BPC_MECH 1 +BPC_CTR_RESET TRUE +BPC_CIT_BITS 8 +BPC_CIT_TH 50 +BPC_CTR_BITS 3 +OPC_COUNT_ZEROS FALSE +OPC_COUNT_THRESH 10 +INF_LOOP FALSE +INF_LOOP_BUCKETS 811 +LOOP_ENTRIES (4 * 1024) +LOOP_ASSOC 4 +LOOP_COUNT_MAX 127 +LOOP_REPEAT_MAX 15 +KNOB_PRINT_BRINFO FALSE +BR_MISPRED_FILE NULL +CONF_PERCEPTRON_TH 0 +CONF_PERCEPTRON_CTR_BITS 8 +CONF_PERCEPTRON_ENTRIES 127 +CONF_PERCEPTRON_THRESH_OVRD 0 +CONF_HIST_LENGTH 32 +PERCEPTRON_CONF_USE_CONF FALSE +PERCEPTRON_CONF_TRAIN_HIS FALSE +PERCEPTRON_CONF_TRAIN_CONF FALSE +PERCEPTRON_CONF_TRAIN_OFFSET_CONF FALSE +PERCEPTRON_TRAIN_MISP_FACTOR 1 +PERCEPTRON_TRAIN_CORR_FACTOR 1 +PERCEPTRON_CONF_HIS_BOTH FALSE +PERCEPTRON_CONF_HIS_BOTH_LENGTH 4 +ENABLE_ICACHE_PACKET_BREAKING TRUE +NUM_LOAD_STORE_PER_PACKET 0 +PACKET_BREAK_ON_FUS FALSE +PACKET_BREAK_FU_TYPES "G,G,G,G,G,G,G,G,G,G,G,G" +POWER_INTF_ON FALSE +POWER_INTF_ENABLE_SCALING FALSE +POWER_INTF_EXEC "power/power_intf.py" +POWER_INTF_REF_CHIP_TECH_NM 22 +POWER_INTF_REF_CHIP_FREQ (3.2e9) +POWER_INTF_REF_MEMORY_FREQ (0.8e9) +POWER_OTHER (0.0) +PREF_STREAM_ON FALSE 1 +PREF_STREAM_PER_CORE_ENABLE FALSE 1 +STREAM_BUFFER_N 16 +STREAM_PREFETCH_N 2 4 +STREAM_START_DIS 5 1 +STREAM_LENGTH 16 64 +STREAM_FULL_N 1 +STREAM_TRAIN_LENGTH 16 +STREAM_TRAIN_NUM 1 4 +PREF_ACC_USE_CACHE FALSE +STREAM_STALL_ON_QUEUE_FULL FALSE +PREF_SCHEDULE_NUM 4 +TRAIN_FILTER_SIZE 32 +PREF_REQ_Q_SIZE 64 +STREAM_CREATE_ON_DC_MISS FALSE 0 +STREAM_CREATE_ON_L1_MISS TRUE 1 +STREAM_TRAIN_ON_WRONGPATH TRUE +STREAM_CREATE_ON_WRONGPATH TRUE +STREAM_PREF_INTO_DCACHE FALSE +REMOVE_REDUNDANT_STREAM FALSE +L2HIT_STREAM_SCHEDULE_NUM 4 +PREF_REQ_QUEUE_FILTER_ON FALSE +HW_PREF_HIT_TRAIN_STREAM FALSE +L2HIT_STREAM_BUFFER_N 32 +L2HIT_STREAM_PREFETCH_N 2 +L2HIT_STREAM_START_DIS 2 +L2HIT_STREAM_LENGTH 8 +L2HIT_PREF_REQ_Q_SIZE 128 +L2HIT_L2ACCESS_REQ_Q_SIZE 64 +PREF_STREAM_ACCPERSTREAM FALSE +PREF_ACC_DISTANCE_10 128 +PREF_FRAMEWORK_ON FALSE 1 +PREF_TRACE_ON FALSE +PREF_DL0REQ_QUEUE_SIZE 32 +PREF_UMLC_REQ_QUEUE_SIZE 64 +PREF_UL1REQ_QUEUE_SIZE 128 +PREF_SHARED_QUEUES TRUE 0 +PREF_DL0_MISS_ON TRUE +PREF_DL0_HIT_ON TRUE +PREF_DL0REQ_QUEUE_FILTER_ON TRUE +PREF_UMLC_REQ_QUEUE_FILTER_ON TRUE +PREF_UL1REQ_QUEUE_FILTER_ON TRUE +PREF_DL0REQ_ADD_FILTER_ON TRUE +PREF_UMLC_REQ_ADD_FILTER_ON TRUE +PREF_UL1REQ_ADD_FILTER_ON TRUE +PREF_DL0REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UMLC_REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UL1REQ_QUEUE_OVERWRITE_ON_FULL FALSE 1 +PREF_DL0SCHEDULE_NUM 4 +PREF_UMLC_SCHEDULE_NUM 4 +PREF_UL1SCHEDULE_NUM 4 +PREF_L1Q_DEMAND_RESERVE 0 +PREF_REPORT_PREF_MATCH_AS_MISS FALSE +PREF_REPORT_PREF_MATCH_AS_HIT TRUE +PREF_UPDATE_ON_WRONGPATH TRUE +PREF_TRAIN_ON_PREF_MISSES FALSE 0 +PREF_ORACLE_TRAIN_ON FALSE 0 +PREF_REQ_DROP FALSE +PREF_THROTTLE_ON FALSE +PREF_THROTTLEFB_ON FALSE 1 +PREF_ACC_THRESH_1 0.90 0.75 +PREF_ACC_THRESH_2 0.70 0.4 +PREF_ACC_THRESH_3 0.60 0.4 +PREF_ACC_THRESH_4 0.40 +PREF_UPDATE_INTERVAL 0 8192 +PREF_ANALYZE_LOAD FALSE +PREF_POL_THRESH_1 0.25 +PREF_POL_THRESH_2 0.10 +PREF_POLBV_ON FALSE +PREF_POLBV_SIZE 1024 +PREF_TIMELY_THRESH 0.05 0.01 +PREF_POLPF_THRESH 0.01 0.005 +PREF_DEGFB_USEONLYACC FALSE +PREF_DEGFB_USEONLYPOL FALSE +PREF_DEGFB_USEONLYLATE FALSE +PREF_TIMELY_THRESH_2 0.005 +PREF_DEGFB_STATPHASEFILE FALSE +PREF_MAX_DEGFB 4 +PREF_DHAL FALSE +PREF_DHAL_SENTTHRESH 16 +PREF_DHAL_USETHRESH_MAX 12 +PREF_DHAL_USETHRESH_MIN2 8 +PREF_DHAL_USETHRESH_MIN1 4 +PREF_DHAL_MAXDEG 64 +PREF_HFILTER_ON FALSE +PREF_HFILTER_INDEX_BITS 12 +PREF_HFILTER_USE_PC FALSE +PREF_HFILTER_PRED_USELESS_THRES 2 +PREF_HFILTER_RESET_ENABLE FALSE +PREF_HFILTER_RESET_INTERVAL 100000 +L2L1PREF_ON FALSE +L2WAY_PREF FALSE +L2MARKV_PREF_ON FALSE +L2NEXT_PREF_ON FALSE +L2HIT_STREAM_PREF_ON FALSE +L2L1_DC_HIT_TRAIN FALSE +L1_HIT_DUMP_FILE_ON FALSE +L1_HIT_DUMP_WO_TXT FALSE +L1_HIT_DUMPFILE "l1hit_dump.out" +IDEAL_L2_L1_PREFETCHER FALSE +IDEAL_L2_ICACHE_PREFETCHER FALSE +L1WAY_PREF_SEND_QUEUE 4 +L1PREF_REQ_QUEUE_SIZE 1024 +L1PREF_IMMEDIATE FALSE +L1WAY_PREF_TIMER_DIS 1000 +L1MARKV_PREF_SEND_QUEUE 4 +L1PREF_MARKV_REQ_QUEUE_SIZE 1024 +MARKV_L2ACCESS_REQ_Q_SIZE 64 +L1MARKV_PREF_IMMEDIATE FALSE +L1MARKV_PREF_TIMER_DIS 1 +L2L1_HIT_TRAIN TRUE +L1MARKV_REQ_TH 1 +L2L1_IMMEDIATE_PREF_CACHE FALSE +L2L1_FILL_PREF_CACHE FALSE +L2L1_L2_HIT_STAT FALSE +PREF_GHB_ON FALSE +DEBUG_PREF_GHB FALSE +PREF_GHB_BUFFER_N 1024 +PREF_GHB_INDEX_N 128 +PREF_GHB_CZONE_BITS 12 +PREF_GHB_DEGREE 16 +PREF_GHB_MAX_DEGREE 32 +PREF_STRIDE_ON FALSE +DEBUG_PREF_STRIDE FALSE +PREF_STRIDE_TABLE_N 1024 +PREF_STRIDE_REGION_BITS 16 +PREF_STRIDE_DEGREE 4 +PREF_STRIDE_DISTANCE 16 +PREF_STRIDE_STARTDISTANCE 1 +PREF_STRIDE_SINGLE_THRESH 6 +PREF_STRIDE_MULTI_THRESH 6 +PREF_STRIDE_SINGLE_STRIDE_MODE FALSE +PREF_STRIDEPC_ON FALSE +DEBUG_PREF_STRIDEPC FALSE +PREF_STRIDEPC_TABLE_N 1024 +PREF_STRIDEPC_DEGREE 4 +PREF_STRIDEPC_DISTANCE 16 +PREF_STRIDEPC_USELOADADDR FALSE +PREF_STRIDEPC_TRAINNUM 2 +PREF_STRIDEPC_STARTDIS 4 +PREF_PHASE_ON FALSE +PREF_PHASE_STUDY FALSE +DEBUG_PREF_PHASE FALSE +PREF_PHASE_PRIME_HASH 16381 +PREF_PHASE_INFOSIZE 16384 +PREF_PHASE_LOG2REGIONSIZE 12 +PREF_PHASE_REGIONENTRIES 64 +PREF_PHASE_TRACKEDREGIONS 32 +PREF_PHASE_INTERVAL 100000 +PREF_PHASE_TABLE_SIZE 64 +PREF_PHASE_MAXDIFF_THRESH 64 +PREF_PHASE_MIN_MISSES 64 +PREF_PHASE_MISSPER 0.4 +PREF_2DC_ON FALSE +DEBUG_PREF_2DC FALSE +PREF_2DC_CACHE_SIZE (1 * 1024) +PREF_2DC_CACHE_ASSOC 4 +PREF_2DC_CACHE_LINE_SIZE 1 +PREF_2DC_DEGREE 16 +PREF_2DC_ZONE_SHIFT 10 +PREF_2DC_TAG_SIZE 16 +PREF_2DC_NUM_REGIONS 64 +PREF_2DC_REGION_HASH 61 +PREF_MARKOV_ON FALSE +DEBUG_PREF_MARKOV FALSE +PREF_MARKOV_NUM_ENTRIES 65536 +PREF_MARKOV_NUM_NEXT_STATES 8 +PREF_MARKOV_SEND_ON_PREF_HIT TRUE +PREF_MARKOV_UPDATE_ON_PREF_HIT TRUE +PREF_MARKOV_TABLE_UPDATE_POLICY 0 +PREF_MARKOV_SEND_THRESHOLD 0 +PREF_SMS_ON FALSE 1 +PREF_SMS_AT_SIZE 64 +PREF_SMS_FT_SIZE 64 +PREF_SMS_PHT_SIZE 16384 +PREF_SMS_PRF_SIZE 1024 +PREF_SMS_REGION_SIZE 2048 diff --git a/labs/LAB5/runs/deepsjeng-sms1/bp.stat.0.out b/labs/LAB5/runs/deepsjeng-sms1/bp.stat.0.out new file mode 100644 index 00000000..45197d54 --- /dev/null +++ b/labs/LAB5/runs/deepsjeng-sms1/bp.stat.0.out @@ -0,0 +1,752 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 50809793 Instructions: 100000000 IPC: 1.96812 + +BTB_ON_PATH_MISS 50498 0.349% 50498 0.349% +BTB_ON_PATH_HIT 14409909 99.651% 14409909 99.651% + 14460407 100.000% 14460407 100.000% + 1.00 0.99 1.00 0.99 + +BTB_OFF_PATH_MISS 0 -nan% 0 -nan% +BTB_OFF_PATH_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BTB_ON_PATH_WRITE 50498 100.000% 50498 100.000% +BTB_OFF_PATH_WRITE 0 0.000% 0 0.000% + 50498 100.000% 50498 100.000% + 0.00 0.00 0.00 0.00 + +BP_ON_PATH_CORRECT 13251800 91.642% 13251800 91.642% +BP_ON_PATH_MISPREDICT 350831 2.426% 350831 2.426% +BP_ON_PATH_MISFETCH 857776 5.932% 857776 5.932% + 14460407 100.000% 14460407 100.000% + 0.14 0.47 0.14 0.47 + +BP_OFF_PATH_CORRECT 0 -nan% 0 -nan% +BP_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% +BP_OFF_PATH_MISFETCH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +LATE_BP_ON_PATH_CORRECT 14460407 100.000% 14460407 100.000% +LATE_BP_ON_PATH_MISPREDICT 0 0.000% 0 0.000% +LATE_BP_ON_PATH_MISFETCH 0 0.000% 0 0.000% + 14460407 100.000% 14460407 100.000% + 0.00 0.00 0.00 0.00 + +LATE_BP_OFF_PATH_CORRECT 0 -nan% 0 -nan% +LATE_BP_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% +LATE_BP_OFF_PATH_MISFETCH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_PVN 0 -nan% 0 -nan% +BP_ON_PATH_CONF_PVN_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_PVP 0 -nan% 0 -nan% +BP_ON_PATH_CONF_PVP_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_SPEC 0 -nan% 0 -nan% +BP_ON_PATH_CONF_SPEC_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CRS_MISS_ON_PATH 41724 2.069% 41724 2.069% +CRS_HIT_ON_PATH 1975105 97.931% 1975105 97.931% + 2016829 100.000% 2016829 100.000% + 0.98 0.97 0.98 0.97 + +CRS_MISS_OFF_PATH 0 -nan% 0 -nan% +CRS_HIT_OFF_PATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CRS_CLOBBER 0 0 + +TARG_ON_PATH_MISS 2362 29.956% 2362 29.956% +TARG_ON_PATH_HIT 5523 70.044% 5523 70.044% + 7885 100.000% 7885 100.000% + 0.70 0.64 0.70 0.64 + +TARG_OFF_PATH_MISS 0 -nan% 0 -nan% +TARG_OFF_PATH_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_ON_PATH_WRITE 7885 100.000% 7885 100.000% +TARG_OFF_PATH_WRITE 0 0.000% 0 0.000% + 7885 100.000% 7885 100.000% + 0.00 0.00 0.00 0.00 + +TARG_HYBRID_CORRECT_TAGLESS 0 -nan% 0 -nan% +TARG_HYBRID_CORRECT_TAGGED 0 -nan% 0 -nan% +TARG_HYBRID_MISPRED_TAGLESS 0 -nan% 0 -nan% +TARG_HYBRID_MISPRED_TAGGED 0 -nan% 0 -nan% +TARG_HYBRID_NO_PRED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_VP_INDIRECT_MISPRED 0 -nan% 0 -nan% +TARG_VP_INDIRECT_NOPRED 0 -nan% 0 -nan% +TARG_VP_INDIRECT_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CBR_ON_PATH_CORRECT 9066824 96.275% 9066824 96.275% +CBR_ON_PATH_MISPREDICT 350831 3.725% 350831 3.725% + 9417655 100.000% 9417655 100.000% + 0.04 0.19 0.04 0.19 + +CBR_ON_PATH_CORRECT_PER1000INST 9066824 90.6682 9066824 90.6682 + +CBR_ON_PATH_MISPREDICT_PER1000INST 350831 3.5083 350831 3.5083 + +CBR_OFF_PATH_CORRECT 0 -nan% 0 -nan% +CBR_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PRED_TO_UPDATE_CYCLES_0 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_1 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_2 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_3 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_4 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_5 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_6 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_7 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_8 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_9 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_10 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_11 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_12 0 -nan% 0 -nan% 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--git a/labs/LAB5/runs/deepsjeng-sms1/inst.stat.0.out b/labs/LAB5/runs/deepsjeng-sms1/inst.stat.0.out new file mode 100644 index 00000000..82036087 --- /dev/null +++ b/labs/LAB5/runs/deepsjeng-sms1/inst.stat.0.out @@ -0,0 +1,103 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 50809793 Instructions: 100000000 IPC: 1.96812 + +ST_OP_INV 0 0.000% 0 0.000% +ST_OP_NOP 2324066 1.917% 2324066 1.917% +ST_OP_CF 14460410 11.931% 14460410 11.931% +ST_OP_MOV 14118958 11.649% 14118958 11.649% +ST_OP_CMOV 426561 0.352% 426561 0.352% +ST_OP_LDA 7123151 5.877% 7123151 5.877% +ST_OP_IMEM 37070597 30.585% 37070597 30.585% +ST_OP_IADD 14866594 12.266% 14866594 12.266% +ST_OP_IMUL 1367985 1.129% 1367985 1.129% +ST_OP_IDIV 46050 0.038% 46050 0.038% +ST_OP_ICMP 5955128 4.913% 5955128 4.913% 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+CORE_EVICTED_L1_DEMAND 11879 99.132% 11879 99.132% +CORE_EVICTED_L1_PREF_USED 34 0.284% 34 0.284% +CORE_EVICTED_L1_PREF_NOT_USED 70 0.584% 70 0.584% + 11983 100.000% 11983 100.000% + 0.01 0.16 0.01 0.16 + +CORE_EVICTED_MLC_DEMAND 0 -nan% 0 -nan% +CORE_EVICTED_MLC_PREF_USED 0 -nan% 0 -nan% +CORE_EVICTED_MLC_PREF_NOT_USED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CORE_MEM_LATENCY_AVE_DEMAND 1569854 132.1537 1569854 132.1537 + +CORE_MEM_LATENCY_AVE_PREF_USED 3331 97.9706 3331 97.9706 + +CORE_MEM_LATENCY_AVE_PREF_NOT_USED 7642 109.1714 7642 109.1714 + +DRAM_LATENCY 0 0 + +TOTAL_DRAM_LATENCY 0 0 + +DRAM_CLOSED_PAGE_POLICY_CMD 0 0 + +DRAM_ACTIVATE_STALLING 0 0 + +DRAM_PRECHARGE_STALLING 0 0 + +DRAM_PRECHARGE_STALLING_WAIT_CYCLES 0 0 + +L1_STAY_DEMAND 279929035093 23565033.6807 279929035093 23565033.6807 + +L1_STAY_PREF_USED 1211021204 35618270.7059 1211021204 35618270.7059 + +L1_STAY_PREF_NOT_USED 1649228963 23560413.7571 1649228963 23560413.7571 + +TOTAL_DATA_MISS_LATENCY 3572152 3572152 + +TOTAL_DATA_MISS_COUNT 26774 26774 + +CORE_PREF_L1_NOT_USED_LATENCY200 67 95.714% 67 95.714% +CORE_PREF_L1_NOT_USED_LATENCY400 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_LATENCY600 2 2.857% 2 2.857% +CORE_PREF_L1_NOT_USED_LATENCY800 1 1.429% 1 1.429% +CORE_PREF_L1_NOT_USED_LATENCY1000 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_LATENCY1200 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_LATENCY1400 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_LATENCY1600 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_LATENCY1600MORE 0 0.000% 0 0.000% + 70 100.000% 70 100.000% + 0.10 0.48 0.10 0.48 + +CORE_PREF_L1_NOT_USED_DISTANCE_1 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_DISTANCE_2 1 1.429% 1 1.429% +CORE_PREF_L1_NOT_USED_DISTANCE_4 5 7.143% 5 7.143% +CORE_PREF_L1_NOT_USED_DISTANCE_8 29 41.429% 29 41.429% +CORE_PREF_L1_NOT_USED_DISTANCE_16 35 50.000% 35 50.000% +CORE_PREF_L1_NOT_USED_DISTANCE_32 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_DISTANCE_MORE 0 0.000% 0 0.000% + 70 100.000% 70 100.000% + 3.40 0.69 3.40 0.69 + +CORE_PREF_L1_USED_LATENCY200 33 97.059% 33 97.059% +CORE_PREF_L1_USED_LATENCY400 0 0.000% 0 0.000% +CORE_PREF_L1_USED_LATENCY600 0 0.000% 0 0.000% +CORE_PREF_L1_USED_LATENCY800 1 2.941% 1 2.941% +CORE_PREF_L1_USED_LATENCY1000 0 0.000% 0 0.000% +CORE_PREF_L1_USED_LATENCY1200 0 0.000% 0 0.000% +CORE_PREF_L1_USED_LATENCY1400 0 0.000% 0 0.000% +CORE_PREF_L1_USED_LATENCY1600 0 0.000% 0 0.000% +CORE_PREF_L1_USED_LATENCY1600MORE 0 0.000% 0 0.000% + 34 100.000% 34 100.000% + 0.09 0.51 0.09 0.51 + +CORE_PREF_L1_USED_DISTANCE_1 0 0.000% 0 0.000% +CORE_PREF_L1_USED_DISTANCE_2 1 2.941% 1 2.941% +CORE_PREF_L1_USED_DISTANCE_4 15 44.118% 15 44.118% +CORE_PREF_L1_USED_DISTANCE_8 12 35.294% 12 35.294% +CORE_PREF_L1_USED_DISTANCE_16 6 17.647% 6 17.647% +CORE_PREF_L1_USED_DISTANCE_32 0 0.000% 0 0.000% +CORE_PREF_L1_USED_DISTANCE_MORE 0 0.000% 0 0.000% + 34 100.000% 34 100.000% + 2.68 0.81 2.68 0.81 + +CORE_PREF_L1_DEMAND_LATENCY300 11468 96.540% 11468 96.540% +CORE_PREF_L1_DEMAND_LATENCY400 38 0.320% 38 0.320% +CORE_PREF_L1_DEMAND_LATENCY500 29 0.244% 29 0.244% +CORE_PREF_L1_DEMAND_LATENCY600 40 0.337% 40 0.337% +CORE_PREF_L1_DEMAND_LATENCY700 45 0.379% 45 0.379% +CORE_PREF_L1_DEMAND_LATENCY800 49 0.412% 49 0.412% +CORE_PREF_L1_DEMAND_LATENCY900 40 0.337% 40 0.337% +CORE_PREF_L1_DEMAND_LATENCY1000 42 0.354% 42 0.354% +CORE_PREF_L1_DEMAND_LATENCY1000MORE 128 1.078% 128 1.078% + 11879 100.000% 11879 100.000% + 0.19 1.06 0.19 1.06 + +CORE_PREF_MLC_NOT_USED_LATENCY200 0 -nan% 0 -nan% +CORE_PREF_MLC_NOT_USED_LATENCY400 0 -nan% 0 -nan% +CORE_PREF_MLC_NOT_USED_LATENCY600 0 -nan% 0 -nan% +CORE_PREF_MLC_NOT_USED_LATENCY800 0 -nan% 0 -nan% +CORE_PREF_MLC_NOT_USED_LATENCY1000 0 -nan% 0 -nan% +CORE_PREF_MLC_NOT_USED_LATENCY1200 0 -nan% 0 -nan% +CORE_PREF_MLC_NOT_USED_LATENCY1400 0 -nan% 0 -nan% +CORE_PREF_MLC_NOT_USED_LATENCY1600 0 -nan% 0 -nan% +CORE_PREF_MLC_NOT_USED_LATENCY1600MORE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CORE_PREF_MLC_USED_LATENCY200 0 -nan% 0 -nan% +CORE_PREF_MLC_USED_LATENCY400 0 -nan% 0 -nan% +CORE_PREF_MLC_USED_LATENCY600 0 -nan% 0 -nan% +CORE_PREF_MLC_USED_LATENCY800 0 -nan% 0 -nan% +CORE_PREF_MLC_USED_LATENCY1000 0 -nan% 0 -nan% +CORE_PREF_MLC_USED_LATENCY1200 0 -nan% 0 -nan% +CORE_PREF_MLC_USED_LATENCY1400 0 -nan% 0 -nan% +CORE_PREF_MLC_USED_LATENCY1600 0 -nan% 0 -nan% +CORE_PREF_MLC_USED_LATENCY1600MORE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CORE_PREF_MLC_DEMAND_LATENCY300 0 -nan% 0 -nan% +CORE_PREF_MLC_DEMAND_LATENCY400 0 -nan% 0 -nan% +CORE_PREF_MLC_DEMAND_LATENCY500 0 -nan% 0 -nan% +CORE_PREF_MLC_DEMAND_LATENCY600 0 -nan% 0 -nan% +CORE_PREF_MLC_DEMAND_LATENCY700 0 -nan% 0 -nan% +CORE_PREF_MLC_DEMAND_LATENCY800 0 -nan% 0 -nan% +CORE_PREF_MLC_DEMAND_LATENCY900 0 -nan% 0 -nan% +CORE_PREF_MLC_DEMAND_LATENCY1000 0 -nan% 0 -nan% +CORE_PREF_MLC_DEMAND_LATENCY1000MORE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TOTAL_BATCH_FORMED 0 0 + +TOTAL_BATCH_MEM_REQ_MARKED 0 -nan 0 -nan + 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+NUM_DCACHE_MISSES_IN_WINDOW_3 11705 11.039% 11705 11.039% +NUM_DCACHE_MISSES_IN_WINDOW_4 5300 4.998% 5300 4.998% +NUM_DCACHE_MISSES_IN_WINDOW_5 2535 2.391% 2535 2.391% +NUM_DCACHE_MISSES_IN_WINDOW_6 1471 1.387% 1471 1.387% +NUM_DCACHE_MISSES_IN_WINDOW_7 959 0.904% 959 0.904% +NUM_DCACHE_MISSES_IN_WINDOW_8 593 0.559% 593 0.559% +NUM_DCACHE_MISSES_IN_WINDOW_9 351 0.331% 351 0.331% +NUM_DCACHE_MISSES_IN_WINDOW_10 217 0.205% 217 0.205% +NUM_DCACHE_MISSES_IN_WINDOW_11 116 0.109% 116 0.109% +NUM_DCACHE_MISSES_IN_WINDOW_12 56 0.053% 56 0.053% +NUM_DCACHE_MISSES_IN_WINDOW_13 22 0.021% 22 0.021% +NUM_DCACHE_MISSES_IN_WINDOW_14 17 0.016% 17 0.016% +NUM_DCACHE_MISSES_IN_WINDOW_15 8 0.008% 8 0.008% +NUM_DCACHE_MISSES_IN_WINDOW_16_OR_MORE 54 0.051% 54 0.051% + 106033 100.000% 106033 100.000% + 0.99 1.33 0.99 1.33 + +DCACHE_MLP_IN_WINDOW_1_0 79617 75.087% 79617 75.087% +DCACHE_MLP_IN_WINDOW_1_5 8821 8.319% 8821 8.319% +DCACHE_MLP_IN_WINDOW_2_0 15679 14.787% 15679 14.787% +DCACHE_MLP_IN_WINDOW_2_5 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-nan 0 -nan + +DRAM_NUM_REQS_27_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_27_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_27_WB_NODIRTY 0 -nan 0 -nan + +DRAM_NUM_REQS_28_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_28_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_28_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_28_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_28_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_28_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_28_WB_NODIRTY 0 -nan 0 -nan + +DRAM_NUM_REQS_29_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_29_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_29_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_29_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_29_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_29_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_29_WB_NODIRTY 0 -nan 0 -nan + +DRAM_NUM_REQS_30_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_30_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_30_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_30_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_30_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_30_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_30_WB_NODIRTY 0 -nan 0 -nan + +DRAM_NUM_REQS_31_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_31_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_31_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_31_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_31_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_31_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_31_WB_NODIRTY 0 -nan 0 -nan + +DRAM_NUM_REQS_32_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_32_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_32_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_32_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_32_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_32_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_32_WB_NODIRTY 0 -nan 0 -nan + +DRAM_BOTTLENECK_BUS_0 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_10 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_20 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_30 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_40 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_50 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_60 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_70 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_80 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_90 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_100 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DRAM_BOTTLENECK_BANKS_0 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_10 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_20 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_30 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_40 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_50 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_60 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_70 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_80 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_90 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_100 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DRAM_BOTTLENECK_FAW_0 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_10 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_20 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_30 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_40 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_50 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_60 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_70 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_80 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_90 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_100 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DRAM_ROW_HIT_GEN_AFTER_ROW_OPEN_STALLING 0 0 + +KNOWN_BAD_ADDRESS 0 0.000% 0 0.000% +GOOD_ADDRESS 821598 100.000% 821598 100.000% + 821598 100.000% 821598 100.000% + 1.00 1.00 1.00 1.00 + + + diff --git a/labs/LAB5/runs/deepsjeng-sms1/power.stat.0.out b/labs/LAB5/runs/deepsjeng-sms1/power.stat.0.out new file mode 100644 index 00000000..26d23aa7 --- /dev/null +++ b/labs/LAB5/runs/deepsjeng-sms1/power.stat.0.out @@ -0,0 +1,184 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 50809793 Instructions: 100000000 IPC: 1.96812 + +POWER_STATS_BEGIN 0 0 + +POWER_TIME 15878060312500 15878060312500 + +POWER_CYCLE 50809793 50809793 + +POWER_ITLB_ACCESS 28376106 28376106 + +POWER_DTLB_ACCESS 12119092 12119092 + +POWER_ICACHE_ACCESS 28376106 28376106 + +POWER_ICACHE_MISS 91279 91279 + +POWER_BTB_READ 28376106 28376106 + +POWER_BTB_WRITE 1208606 1208606 + +POWER_ROB_READ 121203964 121203964 + +POWER_ROB_WRITE 121203964 121203964 + +POWER_RENAME_READ 242407928 242407928 + +POWER_RENAME_WRITE 121203964 121203964 + +POWER_FP_RENAME_READ 0 0 + +POWER_FP_RENAME_WRITE 0 0 + +POWER_FUNCTION_CALL 2016842 2016842 + +POWER_INST_WINDOW_READ 121203964 121203964 + +POWER_INST_WINDOW_WRITE 121203964 121203964 + +POWER_INT_REGFILE_READ 145540637 145540637 + +POWER_INT_REGFILE_WRITE 118366721 118366721 + +POWER_IALU_ACCESS 119789930 119789930 + +POWER_CDB_IALU_ACCESS 119789930 119789930 + +POWER_MUL_ACCESS 1414034 1414034 + +POWER_CDB_MUL_ACCESS 1414034 1414034 + +POWER_FP_INST_WINDOW_WRITE 0 0 + +POWER_FP_INST_WINDOW_READ 0 0 + +POWER_FP_REGFILE_READ 0 0 + +POWER_FP_REGFILE_WRITE 0 0 + +POWER_FPU_ACCESS 0 0 + +POWER_CDB_FPU_ACCESS 0 0 + +POWER_DCACHE_READ_ACCESS 25106816 25106816 + +POWER_DCACHE_WRITE_ACCESS 12119091 12119091 + +POWER_DCACHE_READ_MISS 263181 263181 + +POWER_DCACHE_WRITE_MISS 164923 164923 + +POWER_MLC_READ_ACCESS 0 0 + +POWER_MLC_WRITE_ACCESS 0 0 + +POWER_MLC_READ_MISS 0 0 + +POWER_MLC_WRITE_MISS 0 0 + +POWER_LLC_READ_ACCESS 258667 258667 + +POWER_LLC_WRITE_ACCESS 72787 72787 + +POWER_LLC_READ_MISS 28246 28246 + +POWER_LLC_WRITE_MISS 0 0 + +POWER_MEMORY_ACCESS 0 0 + +POWER_MEMORY_READ_ACCESS 0 0 + +POWER_MEMORY_WRITE_ACCESS 0 0 + +POWER_INST_WINDOW_WAKEUP_ACCESS 121203964 121203964 + +POWER_FP_INST_WINDOW_WAKEUP_ACCESS 0 0 + +POWER_L1DIREC_READ_ACCESS 0 0 + +POWER_L1DIREC_WRITE_ACCESS 0 0 + +POWER_L1DIREC_READ_MISS 0 0 + +POWER_L1DIREC_WRITE_MISS 0 0 + +POWER_L2DIREC_READ_ACCESS 0 0 + +POWER_L2DIREC_WRITE_ACCESS 0 0 + +POWER_L2DIREC_READ_MISS 0 0 + +POWER_L2DIREC_WRITE_MISS 0 0 + +POWER_MEMORY_CTRL_ACCESS 36147 36147 + +POWER_MEMORY_CTRL_READ 28246 28246 + +POWER_MEMORY_CTRL_WRITE 7901 7901 + +POWER_OP 121203964 121203964 + +POWER_INT_OP 118468939 118468939 + +POWER_FP_OP 410960 410960 + +POWER_LD_OP 25106816 25106816 + +POWER_ST_OP 12119092 12119092 + +POWER_BRANCH_MISPREDICT 1208606 1208606 + +POWER_COMMITTED_OP 121203964 121203964 + +POWER_COMMITTED_INT_OP 118468939 118468939 + +POWER_COMMITTED_FP_OP 2735025 2735025 + +POWER_BRANCH_OP 14460405 14460405 + +POWER_DRAM_PRECHARGE 12492 12492 + +POWER_DRAM_ACTIVATE 25752 25752 + +POWER_DRAM_READ 28244 28244 + +POWER_DRAM_WRITE 7892 7892 + +POWER_STATS_END 0 0 + +ENERGY 0.000000 0.000000 + +ENERGY_CORE 0.000000 0.000000 + +ENERGY_UNCORE 0.000000 0.000000 + +ENERGY_MEMORY 0.000000 0.000000 + +ENERGY_OTHER 0.000000 0.000000 + +ENERGY_CORE_STATIC 0.000000 0.000000 + +ENERGY_CORE_DYNAMIC 0.000000 0.000000 + +ENERGY_UNCORE_STATIC 0.000000 0.000000 + +ENERGY_UNCORE_DYNAMIC 0.000000 0.000000 + +ENERGY_MEMORY_STATIC 0.000000 0.000000 + +ENERGY_MEMORY_DYNAMIC 0.000000 0.000000 + +ENERGY_OTHER_STATIC 0.000000 0.000000 + +ENERGY_OTHER_DYNAMIC 0.000000 0.000000 + +TIME 0.000000 0.000000 + +ENERGY_STATS_END 0 0 + + + diff --git a/labs/LAB5/runs/deepsjeng-sms1/pref.stat.0.out b/labs/LAB5/runs/deepsjeng-sms1/pref.stat.0.out new file mode 100644 index 00000000..f7ad0b24 --- /dev/null +++ b/labs/LAB5/runs/deepsjeng-sms1/pref.stat.0.out @@ -0,0 +1,208 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 50809793 Instructions: 100000000 IPC: 1.96812 + +PREF_DL0REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UMLC_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UL1REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_DL0REQ_QUEUE_FULL 0 0 + +PREF_UMLC_REQ_QUEUE_FULL 0 0 + +PREF_UL1REQ_QUEUE_FULL 0 0 + +PREF_DC_HIT_NOSEND 0 0 + +PREF_WBQDC_HIT_NOSEND 0 0 + +PREF_MLCQ_STALL 0 0 + +PREF_L1Q_STALL 0 0 + +PREF_UMLC_REQ_SEND_QUEUE_STALL 0 0 + +PREF_UL1REQ_SEND_QUEUE_STALL 0 0 + +PREF_UMLC_REQ_QUEUE_SENTREQ 0 0 + +PREF_UL1REQ_QUEUE_SENTREQ 995 995 + +PREF_NEWREQ_MATCHED 23 23 + +PREF_UMLC_REQ_QUEUE_MATCHED_REQ 0 0 + +PREF_UL1REQ_QUEUE_MATCHED_REQ 152 152 + +PREF_DL0REQ_QUEUE_MATCHED_REQ 0 0 + +L1_PREF_HIT 27644 27644 + +L1_PREF_UNIQUE_HIT 408 408 + +L1_PREF_LATE 10 10 + +L1_LATE_PREF_CYCLES 3479 3479 + +L1_LATE_PREF_CYCLES_DIST_0 5 50.000% 5 50.000% +L1_LATE_PREF_CYCLES_DIST_100 1 10.000% 1 10.000% +L1_LATE_PREF_CYCLES_DIST_200 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_300 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_400 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_500 1 10.000% 1 10.000% +L1_LATE_PREF_CYCLES_DIST_600 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_700 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_800 3 30.000% 3 30.000% +L1_LATE_PREF_CYCLES_DIST_900 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1000 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1100 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1200 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1300 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1400 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1500 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1600 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1700 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1800 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1900 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_2000 0 0.000% 0 0.000% + 10 100.000% 10 100.000% + 3.00 3.04 3.00 3.04 + +MLC_PREF_HIT 0 0 + +MLC_PREF_UNIQUE_HIT 0 0 + +MLC_PREF_LATE 0 0 + +PREF_HYBRID_SEL_0 0 -nan% 0 -nan% +PREF_HYBRID_SEL_1 0 -nan% 0 -nan% +PREF_HYBRID_SEL_2 0 -nan% 0 -nan% +PREF_HYBRID_SEL_3 0 -nan% 0 -nan% +PREF_HYBRID_SEL_4 0 -nan% 0 -nan% +PREF_HYBRID_SEL_5 0 -nan% 0 -nan% +PREF_HYBRID_SEL_6 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_DISTANCE_1 0 0.000% 0 0.000% +PREF_DISTANCE_2 0 0.000% 0 0.000% +PREF_DISTANCE_3 0 0.000% 0 0.000% +PREF_DISTANCE_4 1 100.000% 1 100.000% +PREF_DISTANCE_5 0 0.000% 0 0.000% +PREF_DISTANCE_6 0 0.000% 0 0.000% +PREF_DISTANCE_7 0 0.000% 0 0.000% +PREF_DISTANCE_8 0 0.000% 0 0.000% +PREF_DISTANCE_9 0 0.000% 0 0.000% +PREF_DISTANCE_10 0 0.000% 0 0.000% + 1 100.000% 1 100.000% + 3.00 -nan 3.00 -nan + +PREF_REPL_MRU 0 -nan% 0 -nan% +PREF_REPL_MID 0 -nan% 0 -nan% +PREF_REPL_LOWQTR 0 -nan% 0 -nan% +PREF_REPL_LRU 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_REPL_MOVEDOWN 0 -nan% 0 -nan% +PREF_REPL_MOVEUP 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_COV_1 0 -nan% 0 -nan% +PREF_COV_2 0 -nan% 0 -nan% +PREF_COV_3 0 -nan% 0 -nan% +PREF_COV_4 0 -nan% 0 -nan% +PREF_COV_5 0 -nan% 0 -nan% +PREF_COV_6 0 -nan% 0 -nan% +PREF_COV_7 0 -nan% 0 -nan% +PREF_COV_8 0 -nan% 0 -nan% +PREF_COV_9 0 -nan% 0 -nan% +PREF_COV_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_POL_1 0 0.000% 0 0.000% +PREF_POL_2 0 0.000% 0 0.000% +PREF_POL_3 0 0.000% 0 0.000% +PREF_POL_4 0 0.000% 0 0.000% +PREF_POL_5 0 0.000% 0 0.000% +PREF_POL_6 0 0.000% 0 0.000% +PREF_POL_7 0 0.000% 0 0.000% +PREF_POL_8 0 0.000% 0 0.000% +PREF_POL_9 0 0.000% 0 0.000% +PREF_POL_10 1 100.000% 1 100.000% + 1 100.000% 1 100.000% + 9.00 inf 9.00 inf + +PREF_ACC_1 0 0.000% 0 0.000% +PREF_ACC_2 1 100.000% 1 100.000% +PREF_ACC_3 0 0.000% 0 0.000% +PREF_ACC_4 0 0.000% 0 0.000% +PREF_ACC_5 0 0.000% 0 0.000% +PREF_ACC_6 0 0.000% 0 0.000% +PREF_ACC_7 0 0.000% 0 0.000% +PREF_ACC_8 0 0.000% 0 0.000% +PREF_ACC_9 0 0.000% 0 0.000% +PREF_ACC_10 0 0.000% 0 0.000% + 1 100.000% 1 100.000% + 1.00 -nan 1.00 -nan + +PREF_TIMELY_1 0 0.000% 0 0.000% +PREF_TIMELY_2 0 0.000% 0 0.000% +PREF_TIMELY_3 0 0.000% 0 0.000% +PREF_TIMELY_4 0 0.000% 0 0.000% +PREF_TIMELY_5 0 0.000% 0 0.000% +PREF_TIMELY_6 0 0.000% 0 0.000% +PREF_TIMELY_7 0 0.000% 0 0.000% +PREF_TIMELY_8 0 0.000% 0 0.000% +PREF_TIMELY_9 0 0.000% 0 0.000% +PREF_TIMELY_10 1 100.000% 1 100.000% + 1 100.000% 1 100.000% + 9.00 inf 9.00 inf + +PREF_UNUSED_EVICT 70 70 + +PREF_REGION_SENT 0 0 + +PREF_REGION_USEFUL 0 0 + +PREF_REGION_EVICT 0 0 + +PREF_PFPOL 0 0 + +PREF_PHASE_NEWPHASE_DET 0 0 + +PREF_PHASE_NEWPHASE_NOTVALID 0 0 + +PREF_PHASE_SENTPREF 0 0 + +PREF_PHASE_OVERWRITE_PAGE 0 0 + +PREF_UPDATE_COUNT 1 1 + +PREF_ACC1_HT_HP 0 0.000% 0 0.000% +PREF_ACC1_HT_LP 0 0.000% 0 0.000% +PREF_ACC1_LT_HP 0 0.000% 0 0.000% +PREF_ACC1_LT_LP 1 100.000% 1 100.000% +PREF_ACC2_HT_HP 0 0.000% 0 0.000% +PREF_ACC2_HT_LP 0 0.000% 0 0.000% +PREF_ACC2_LT_HP 0 0.000% 0 0.000% +PREF_ACC2_LT_LP 0 0.000% 0 0.000% +PREF_ACC3_HT_HP 0 0.000% 0 0.000% +PREF_ACC3_HT_LP 0 0.000% 0 0.000% +PREF_ACC3_LT_HP 0 0.000% 0 0.000% +PREF_ACC3_LT_LP 0 0.000% 0 0.000% +PREF_ACC4_HT_HP 0 0.000% 0 0.000% +PREF_ACC4_HT_LP 0 0.000% 0 0.000% +PREF_ACC4_LT_HP 0 0.000% 0 0.000% +PREF_ACC4_LT_LP 0 0.000% 0 0.000% + 1 100.000% 1 100.000% + 3.00 -nan 3.00 -nan + + + diff --git a/labs/LAB5/runs/deepsjeng-sms1/ramulator.stat.out b/labs/LAB5/runs/deepsjeng-sms1/ramulator.stat.out new file mode 100644 index 00000000..472ea8b0 --- /dev/null +++ b/labs/LAB5/runs/deepsjeng-sms1/ramulator.stat.out @@ -0,0 +1,150 @@ + ramulator.active_cycles_0 2669484 # Total active cycles for level _0 + ramulator.busy_cycles_0 2669484 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0 + ramulator.serving_requests_0 3547863 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.average_serving_requests_0 0.186204 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.active_cycles_0_0 2669484 # Total active cycles for level _0_0 + ramulator.busy_cycles_0_0 3436824 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0 + ramulator.serving_requests_0_0 3547863 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.average_serving_requests_0_0 0.186204 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.active_cycles_0_0_0 526069 # Total active cycles for level _0_0_0 + ramulator.busy_cycles_0_0_0 526069 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0 + ramulator.serving_requests_0_0_0 574194 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 +ramulator.average_serving_requests_0_0_0 0.030136 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 + ramulator.active_cycles_0_0_0_0 134288 # Total active cycles for level _0_0_0_0 + ramulator.busy_cycles_0_0_0_0 134288 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_0 + ramulator.serving_requests_0_0_0_0 140441 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 +ramulator.average_serving_requests_0_0_0_0 0.007371 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 + ramulator.active_cycles_0_0_0_1 187976 # Total active cycles for level _0_0_0_1 + ramulator.busy_cycles_0_0_0_1 187976 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_1 + ramulator.serving_requests_0_0_0_1 193436 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 +ramulator.average_serving_requests_0_0_0_1 0.010152 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 + ramulator.active_cycles_0_0_0_2 102739 # Total active cycles for level _0_0_0_2 + ramulator.busy_cycles_0_0_0_2 102739 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_2 + ramulator.serving_requests_0_0_0_2 109176 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 +ramulator.average_serving_requests_0_0_0_2 0.005730 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 + ramulator.active_cycles_0_0_0_3 125083 # Total active cycles for level _0_0_0_3 + ramulator.busy_cycles_0_0_0_3 125083 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_3 + ramulator.serving_requests_0_0_0_3 131141 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 +ramulator.average_serving_requests_0_0_0_3 0.006883 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 + ramulator.active_cycles_0_0_1 889061 # Total active cycles for level _0_0_1 + ramulator.busy_cycles_0_0_1 889061 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1 + ramulator.serving_requests_0_0_1 991500 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 +ramulator.average_serving_requests_0_0_1 0.052037 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 + ramulator.active_cycles_0_0_1_0 208596 # Total active cycles for level _0_0_1_0 + ramulator.busy_cycles_0_0_1_0 208596 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_0 + ramulator.serving_requests_0_0_1_0 215434 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 +ramulator.average_serving_requests_0_0_1_0 0.011307 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 + ramulator.active_cycles_0_0_1_1 246333 # Total active cycles for level _0_0_1_1 + ramulator.busy_cycles_0_0_1_1 246333 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_1 + ramulator.serving_requests_0_0_1_1 252241 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 +ramulator.average_serving_requests_0_0_1_1 0.013238 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 + ramulator.active_cycles_0_0_1_2 248817 # Total active cycles for level _0_0_1_2 + ramulator.busy_cycles_0_0_1_2 248817 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_2 + ramulator.serving_requests_0_0_1_2 257010 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 +ramulator.average_serving_requests_0_0_1_2 0.013489 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 + ramulator.active_cycles_0_0_1_3 260070 # Total active cycles for level _0_0_1_3 + ramulator.busy_cycles_0_0_1_3 260070 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_3 + ramulator.serving_requests_0_0_1_3 266815 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 +ramulator.average_serving_requests_0_0_1_3 0.014003 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 + ramulator.active_cycles_0_0_2 930388 # Total active cycles for level _0_0_2 + ramulator.busy_cycles_0_0_2 930388 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2 + ramulator.serving_requests_0_0_2 1000511 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 +ramulator.average_serving_requests_0_0_2 0.052510 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 + ramulator.active_cycles_0_0_2_0 266104 # Total active cycles for level _0_0_2_0 + ramulator.busy_cycles_0_0_2_0 266104 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_0 + ramulator.serving_requests_0_0_2_0 272774 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 +ramulator.average_serving_requests_0_0_2_0 0.014316 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 + ramulator.active_cycles_0_0_2_1 278151 # Total active cycles for level _0_0_2_1 + ramulator.busy_cycles_0_0_2_1 278151 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_1 + ramulator.serving_requests_0_0_2_1 283531 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 +ramulator.average_serving_requests_0_0_2_1 0.014881 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 + ramulator.active_cycles_0_0_2_2 115857 # Total active cycles for level _0_0_2_2 + ramulator.busy_cycles_0_0_2_2 115857 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_2 + ramulator.serving_requests_0_0_2_2 122864 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 +ramulator.average_serving_requests_0_0_2_2 0.006448 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 + ramulator.active_cycles_0_0_2_3 314279 # Total active cycles for level _0_0_2_3 + ramulator.busy_cycles_0_0_2_3 314279 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_3 + ramulator.serving_requests_0_0_2_3 321342 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 +ramulator.average_serving_requests_0_0_2_3 0.016865 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 + ramulator.active_cycles_0_0_3 930288 # Total active cycles for level _0_0_3 + ramulator.busy_cycles_0_0_3 930288 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3 + ramulator.serving_requests_0_0_3 981658 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 +ramulator.average_serving_requests_0_0_3 0.051521 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 + ramulator.active_cycles_0_0_3_0 85453 # Total active cycles for level _0_0_3_0 + ramulator.busy_cycles_0_0_3_0 85453 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_0 + ramulator.serving_requests_0_0_3_0 91100 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 +ramulator.average_serving_requests_0_0_3_0 0.004781 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 + ramulator.active_cycles_0_0_3_1 163900 # Total active cycles for level _0_0_3_1 + ramulator.busy_cycles_0_0_3_1 163900 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_1 + ramulator.serving_requests_0_0_3_1 170076 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 +ramulator.average_serving_requests_0_0_3_1 0.008926 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 + ramulator.active_cycles_0_0_3_2 176512 # Total active cycles for level _0_0_3_2 + ramulator.busy_cycles_0_0_3_2 176512 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_2 + ramulator.serving_requests_0_0_3_2 182464 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 +ramulator.average_serving_requests_0_0_3_2 0.009576 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 + ramulator.active_cycles_0_0_3_3 529903 # Total active cycles for level _0_0_3_3 + ramulator.busy_cycles_0_0_3_3 529903 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_3 + ramulator.serving_requests_0_0_3_3 538018 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 +ramulator.average_serving_requests_0_0_3_3 0.028237 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 + ramulator.read_transaction_bytes_0 1807616 # The total byte of read transaction per channel + ramulator.write_transaction_bytes_0 505088 # The total byte of write transaction per channel + ramulator.row_hits_channel_0_core 10384 # Number of row hits per channel per core + ramulator.row_misses_channel_0_core 15294 # Number of row misses per channel per core + ramulator.row_conflicts_channel_0_core 10458 # Number of row conflicts per channel per core + ramulator.read_row_hits_channel_0_core 10309 # Number of row hits for read requests per channel per core + [0] 10309.0 # +ramulator.read_row_misses_channel_0_core 12515 # Number of row misses for read requests per channel per core + [0] 12515.0 # +ramulator.read_row_conflicts_channel_0_core 5420 # Number of row conflicts for read requests per channel per core + [0] 5420.0 # + ramulator.write_row_hits_channel_0_core 75 # Number of row hits for write requests per channel per core + [0] 75.0 # +ramulator.write_row_misses_channel_0_core 2779 # Number of row misses for write requests per channel per core + [0] 2779.0 # +ramulator.write_row_conflicts_channel_0_core 5038 # Number of row conflicts for write requests per channel per core + [0] 5038.0 # + ramulator.useless_activates_0_core 0 # Number of useless activations. E.g, ACT -> PRE w/o RD or WR + ramulator.read_latency_avg_0 49.763648 # The average memory latency cycles (in memory time domain) per request for all read requests in this channel + ramulator.read_latency_sum_0 1405624 # The memory latency cycles (in memory time domain) sum for all read requests in this channel + ramulator.req_queue_length_avg_0 10.715903 # Average of read and write queue length per memory cycle per channel. + ramulator.req_queue_length_sum_0 204177383 # Sum of read and write queue length per memory cycle per channel. + ramulator.read_req_queue_length_avg_0 0.058702 # Read queue length average per memory cycle per channel. + ramulator.read_req_queue_length_sum_0 1118492 # Read queue length sum per memory cycle per channel. + ramulator.write_req_queue_length_avg_0 10.657201 # Write queue length average per memory cycle per channel. + ramulator.write_req_queue_length_sum_0 203058891 # Write queue length sum per memory cycle per channel. + ramulator.record_read_hits 0.0 # record read hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_misses 0.0 # record_read_miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_conflicts 0.0 # record read conflict count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_hits 0.0 # record write hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_misses 0.0 # record write miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_conflicts 0.0 # record write conflict for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.dram_capacity 8589934592 # Number of bytes in simulated DRAM + ramulator.dram_cycles 19053679 # Number of DRAM cycles simulated + ramulator.incoming_requests 36147 # Number of incoming requests to DRAM + ramulator.read_requests 28246 # Number of incoming read requests to DRAM per core + [0] 28246.0 # + ramulator.write_requests 7901 # Number of incoming write requests to DRAM per core + [0] 7901.0 # + ramulator.ramulator_active_cycles 2669484 # The total number of cycles that the DRAM part is active (serving R/W) + ramulator.incoming_requests_per_channel 36147.0 # Number of incoming requests to each DRAM channel + [0] 36147.0 # +ramulator.incoming_read_reqs_per_channel 28246.0 # Number of incoming read requests to each DRAM channel + [0] 28246.0 # + ramulator.physical_page_replacement 0 # The number of times that physical page replacement happens. + ramulator.maximum_bandwidth 19200000000 # The theoretical maximum bandwidth (Bps) + ramulator.in_queue_req_num_sum 204177383 # Sum of read/write queue length + ramulator.in_queue_read_req_num_sum 1118492 # Sum of read queue length + ramulator.in_queue_write_req_num_sum 203058891 # Sum of write queue length + ramulator.in_queue_req_num_avg 10.715903 # Average of read/write queue length per memory cycle + ramulator.in_queue_read_req_num_avg 0.058702 # Average of read queue length per memory cycle + ramulator.in_queue_write_req_num_avg 10.657201 # Average of write queue length per memory cycle + ramulator.record_read_requests 0.0 # record read requests for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_requests 0.0 # record write requests for this core when it reaches request limit or to the end + [0] 0.0 # diff --git a/labs/LAB5/runs/deepsjeng-sms1/run.err b/labs/LAB5/runs/deepsjeng-sms1/run.err new file mode 100644 index 00000000..e69de29b diff --git a/labs/LAB5/runs/deepsjeng-sms1/run.out b/labs/LAB5/runs/deepsjeng-sms1/run.out new file mode 100644 index 00000000..fdd04f59 --- /dev/null +++ b/labs/LAB5/runs/deepsjeng-sms1/run.out @@ -0,0 +1,107 @@ +Scarab gitrev: 7ab9e17 +Scarab started at Sun Jun 11 08:08:38 2023 + +Initialized Ramulator. +** Heartbeat: 1% -- { 1000003 } -- 0.00 KIPS (500.00 KIPS) +** Heartbeat: 2% -- { 2000004 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 3% -- { 3000005 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 4% -- { 4000008 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 5% -- { 5000010 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 6% -- { 6000013 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 7% -- { 7000014 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 8% -- { 8000018 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 9% -- { 9000018 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 10% -- { 10000019 } -- 1000.00 KIPS (526.32 KIPS) +** Heartbeat: 11% -- { 11000020 } -- 500.00 KIPS (523.81 KIPS) +** Heartbeat: 12% -- { 12000021 } -- 500.00 KIPS (521.74 KIPS) +** Heartbeat: 13% -- { 13000024 } -- 500.00 KIPS (520.00 KIPS) +** Heartbeat: 14% -- { 14000025 } -- 500.00 KIPS (518.52 KIPS) +** Heartbeat: 15% -- { 15000025 } -- 500.00 KIPS (517.24 KIPS) +** Heartbeat: 16% -- { 16000030 } -- 500.00 KIPS (516.13 KIPS) +** Heartbeat: 17% -- { 17000030 } -- 500.00 KIPS (515.15 KIPS) +** Heartbeat: 18% -- { 18000034 } -- 1000.00 KIPS (529.41 KIPS) +** Heartbeat: 19% -- { 19000035 } -- 500.00 KIPS (527.78 KIPS) +** Heartbeat: 20% -- { 20000040 } -- 500.00 KIPS (526.32 KIPS) +** Heartbeat: 21% -- { 21000041 } -- 500.00 KIPS (525.00 KIPS) +** Heartbeat: 22% -- { 22000045 } -- 500.00 KIPS (523.81 KIPS) +** Heartbeat: 23% -- { 23000046 } -- 500.00 KIPS (522.73 KIPS) +** Heartbeat: 24% -- { 24000046 } -- 500.00 KIPS (521.74 KIPS) +** Heartbeat: 25% -- { 25000049 } -- 500.00 KIPS (520.83 KIPS) +** Heartbeat: 26% -- { 26000049 } -- 500.00 KIPS (520.00 KIPS) +** Heartbeat: 27% -- { 27000051 } -- 500.00 KIPS (519.23 KIPS) +** Heartbeat: 28% -- { 28000053 } -- 500.00 KIPS (518.52 KIPS) +** Heartbeat: 29% -- { 29000054 } -- 500.00 KIPS (517.86 KIPS) +** Heartbeat: 30% -- { 30000059 } -- 500.00 KIPS (517.24 KIPS) +** Heartbeat: 31% -- { 31000059 } -- 500.00 KIPS (516.67 KIPS) +** Heartbeat: 32% -- { 32000060 } -- 500.00 KIPS (516.13 KIPS) +** Heartbeat: 33% -- { 33000062 } -- 500.00 KIPS (515.63 KIPS) +** Heartbeat: 34% -- { 34000062 } -- 500.00 KIPS (515.15 KIPS) +** Heartbeat: 35% -- { 35000063 } -- 500.00 KIPS (514.71 KIPS) +** Heartbeat: 36% -- { 36000064 } -- 1000.00 KIPS (521.74 KIPS) +** Heartbeat: 37% -- { 37000066 } -- 500.00 KIPS (521.13 KIPS) +** Heartbeat: 38% -- { 38000070 } -- 500.00 KIPS (520.55 KIPS) +** Heartbeat: 39% -- { 39000072 } -- 500.00 KIPS (520.00 KIPS) +** Heartbeat: 40% -- { 40000074 } -- 500.00 KIPS (519.48 KIPS) +** Heartbeat: 41% -- { 41000074 } -- 500.00 KIPS (518.99 KIPS) +** Heartbeat: 42% -- { 42000077 } -- 500.00 KIPS (518.52 KIPS) +** Heartbeat: 43% -- { 43000081 } -- 500.00 KIPS (518.07 KIPS) +** Heartbeat: 44% -- { 44000081 } -- 500.00 KIPS (517.65 KIPS) +** Heartbeat: 45% -- { 45000085 } -- 500.00 KIPS (517.24 KIPS) +** Heartbeat: 46% -- { 46000087 } -- 500.00 KIPS (516.85 KIPS) +** Heartbeat: 47% -- { 47000090 } -- 500.00 KIPS (516.48 KIPS) +** Heartbeat: 48% -- { 48000094 } -- 500.00 KIPS (516.13 KIPS) +** Heartbeat: 49% -- { 49000097 } -- 500.00 KIPS (515.79 KIPS) +** Heartbeat: 50% -- { 50000097 } -- 500.00 KIPS (515.46 KIPS) +** Heartbeat: 51% -- { 51000100 } -- 500.00 KIPS (515.15 KIPS) +** Heartbeat: 52% -- { 52000101 } -- 500.00 KIPS (514.85 KIPS) +** Heartbeat: 53% -- { 53000104 } -- 500.00 KIPS (514.56 KIPS) +** Heartbeat: 54% -- { 54000106 } -- 500.00 KIPS (514.29 KIPS) +** Heartbeat: 55% -- { 55000107 } -- 500.00 KIPS (514.02 KIPS) +** Heartbeat: 56% -- { 56000107 } -- 500.00 KIPS (513.76 KIPS) +** Heartbeat: 57% -- { 57000112 } -- 500.00 KIPS (513.51 KIPS) +** Heartbeat: 58% -- { 58000117 } -- 500.00 KIPS (513.28 KIPS) +** Heartbeat: 59% -- { 59000118 } -- 500.00 KIPS (513.04 KIPS) +** Heartbeat: 60% -- { 60000122 } -- 1000.00 KIPS (517.24 KIPS) +** Heartbeat: 61% -- { 61000123 } -- 500.00 KIPS (516.95 KIPS) +** Heartbeat: 62% -- { 62000124 } -- 500.00 KIPS (516.67 KIPS) +** Heartbeat: 63% -- { 63000124 } -- 500.00 KIPS (516.39 KIPS) +** Heartbeat: 64% -- { 64000125 } -- 500.00 KIPS (516.13 KIPS) +** Heartbeat: 65% -- { 65000125 } -- 500.00 KIPS (515.87 KIPS) +** Heartbeat: 66% -- { 66000125 } -- 500.00 KIPS (515.63 KIPS) +** Heartbeat: 67% -- { 67000127 } -- 500.00 KIPS (515.39 KIPS) +** Heartbeat: 68% -- { 68000131 } -- 500.00 KIPS (515.15 KIPS) +** Heartbeat: 69% -- { 69000131 } -- 500.00 KIPS (514.93 KIPS) +** Heartbeat: 70% -- { 70000133 } -- 500.00 KIPS (514.71 KIPS) +** Heartbeat: 71% -- { 71000135 } -- 500.00 KIPS (514.49 KIPS) +** Heartbeat: 72% -- { 72000135 } -- 500.00 KIPS (514.29 KIPS) +** Heartbeat: 73% -- { 73000135 } -- 500.00 KIPS (514.09 KIPS) +** Heartbeat: 74% -- { 74000140 } -- 500.00 KIPS (513.89 KIPS) +** Heartbeat: 75% -- { 75000142 } -- 500.00 KIPS (513.70 KIPS) +** Heartbeat: 76% -- { 76000145 } -- 500.00 KIPS (513.51 KIPS) +** Heartbeat: 77% -- { 77000145 } -- 500.00 KIPS (513.33 KIPS) +** Heartbeat: 78% -- { 78000148 } -- 500.00 KIPS (513.16 KIPS) +** Heartbeat: 79% -- { 79000150 } -- 500.00 KIPS (512.99 KIPS) +** Heartbeat: 80% -- { 80000150 } -- 500.00 KIPS (512.82 KIPS) +** Heartbeat: 81% -- { 81000150 } -- 500.00 KIPS (512.66 KIPS) +** Heartbeat: 82% -- { 82000151 } -- 500.00 KIPS (512.50 KIPS) +** Heartbeat: 83% -- { 83000154 } -- 500.00 KIPS (512.35 KIPS) +** Heartbeat: 84% -- { 84000154 } -- 500.00 KIPS (512.20 KIPS) +** Heartbeat: 85% -- { 85000156 } -- 500.00 KIPS (512.05 KIPS) +** Heartbeat: 86% -- { 86000159 } -- 500.00 KIPS (511.91 KIPS) +** Heartbeat: 87% -- { 87000160 } -- 500.00 KIPS (511.77 KIPS) +** Heartbeat: 88% -- { 88000163 } -- 500.00 KIPS (511.63 KIPS) +** Heartbeat: 89% -- { 89000163 } -- 500.00 KIPS (511.50 KIPS) +** Heartbeat: 90% -- { 90000166 } -- 500.00 KIPS (511.36 KIPS) +** Heartbeat: 91% -- { 91000167 } -- 1000.00 KIPS (514.13 KIPS) +** Heartbeat: 92% -- { 92000170 } -- 500.00 KIPS (513.97 KIPS) +** Heartbeat: 93% -- { 93000172 } -- 500.00 KIPS (513.81 KIPS) +** Heartbeat: 94% -- { 94000176 } -- 500.00 KIPS (513.66 KIPS) +** Heartbeat: 95% -- { 95000181 } -- 500.00 KIPS (513.51 KIPS) +** Heartbeat: 96% -- { 96000181 } -- 500.00 KIPS (513.37 KIPS) +** Heartbeat: 97% -- { 97000181 } -- 500.00 KIPS (513.23 KIPS) +** Heartbeat: 98% -- { 98000183 } -- 500.00 KIPS (513.09 KIPS) +** Heartbeat: 99% -- { 99000186 } -- 500.00 KIPS (512.95 KIPS) +** Core 0 Finished: insts:100000000 cycles:50809793 time:15878060312500 -- 1.97 IPC (1.97 IPC) -- N/A KIPS (512.82 KIPS) +done +Scarab finished at Sun Jun 11 08:11:53 2023 + diff --git a/labs/LAB5/runs/deepsjeng-sms1/stream.stat.0.out b/labs/LAB5/runs/deepsjeng-sms1/stream.stat.0.out new file mode 100644 index 00000000..0a765402 --- /dev/null +++ b/labs/LAB5/runs/deepsjeng-sms1/stream.stat.0.out @@ -0,0 +1,188 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 50809793 Instructions: 100000000 IPC: 1.96812 + +DCACHE_PREF_HIT 0 0 + +IFETCH_WB_FIRST_SCHEDULE 0 -nan% 0 -nan% +PREFETCH_LAST_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_PREF_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_LOW_OP_SCHEDULE 0 -nan% 0 -nan% +DEMAND_LAST_SCHEDULE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +SEND_MISS_REQ_QUEUE 28246 28246 + +L1_DATA_EVICT 11983 11983 + +STREAM_BUFFER_REQ 0 0 + +PREF_SEND_TO_MEM_REQ 0 -nan% 0 -nan% +PREF_SEND_TO_MEM_REQ_FAIL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +HIT_TRAIN_STREAM 574 2.084% 574 2.084% +MISS_TRAIN_STREAM 26974 97.916% 26974 97.916% + 27548 100.000% 27548 100.000% + 0.98 0.97 0.98 0.97 + +STREAM_TRAIN_CREATE 17351 17351 + +MEM_REQ_MISS_HWP_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_SW_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_IFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DSTORE_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DPRF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_WB_Q 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_BY_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_WB 0 -nan% 0 -nan% +PREF_HIT_BY_PREF 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_WB 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_L1_FILL 0 -nan% 0 -nan% +DEMAND_L1_FILL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TOUCH_L1_REPLACE 0 0.000% 0 0.000% +NO_TOUCH_L1_REPLACE 11983 100.000% 11983 100.000% + 11983 100.000% 11983 100.000% + 1.00 1.00 1.00 1.00 + +PREF_REQ_QUE_FULL 0 0 + +STREAM_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +L2HIT_STREAM_PREF_REQ_QUE_FULL 0 0 + +L2HIT_HIT_TRAIN_STREAM 0 -nan% 0 -nan% +L2HIT_MISS_TRAIN_STREAM 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_TRAIN_CREATE 0 0 + +L2HIT_STREAM_BUFFER_REQ 0 0 + +L2HIT_STREAM_PREF_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_STREAM_PREF_DCACHE_INSERT 0 -nan% 0 -nan% +L2HIT_STREAM_L2_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_DCACHE_PORT_FULL 0 0 + +L2HIT_STREAM_PREF_L1_PORT_FULL 0 0 + +L2HIT_TRAIN_HIT_DEMAND 0 -nan% 0 -nan% +L2HIT_TRAIN_MISS_REQ 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_TRAIN_FILTER_MISS 0 -nan% 0 -nan% +L2HIT_TRAIN_FILTER_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_PREF_REQ_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_PREF_REQ_DCACHE_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_L2SEND_Q_FULL 0 -nan% 0 -nan% +L2HIT_L2SEND_Q_ENTER 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_MEM_REQ 0 0 + +REMOVE_REDUNDANT_STREAM_STAT 0 0 + +REPLACE_OLD_STREAM 17335 17335 + +REQ_SEND_QUEUE_STALL 0 0 + +STREAM_ENTER_RA 0 0 + +CORE_STREAM_LENGTH_0 33 20.625% 33 20.625% +CORE_STREAM_LENGTH_10 73 45.625% 73 45.625% +CORE_STREAM_LENGTH_20 48 30.000% 48 30.000% +CORE_STREAM_LENGTH_30 4 2.500% 4 2.500% +CORE_STREAM_LENGTH_40 2 1.250% 2 1.250% +CORE_STREAM_LENGTH_50 0 0.000% 0 0.000% +CORE_STREAM_LENGTH_60 0 0.000% 0 0.000% +CORE_STREAM_LENGTH_70 0 0.000% 0 0.000% +CORE_STREAM_LENGTH_80 0 0.000% 0 0.000% +CORE_STREAM_LENGTH_90 0 0.000% 0 0.000% +CORE_STREAM_LENGTH_100_P 0 0.000% 0 0.000% + 160 100.000% 160 100.000% + 1.18 0.63 1.18 0.63 + +CORE_CUM_STREAM_LENGTH_0 222 8.679% 222 8.679% +CORE_CUM_STREAM_LENGTH_10 1042 40.735% 1042 40.735% +CORE_CUM_STREAM_LENGTH_20 1079 42.181% 1079 42.181% +CORE_CUM_STREAM_LENGTH_30 129 5.043% 129 5.043% +CORE_CUM_STREAM_LENGTH_40 86 3.362% 86 3.362% +CORE_CUM_STREAM_LENGTH_50 0 0.000% 0 0.000% +CORE_CUM_STREAM_LENGTH_60 0 0.000% 0 0.000% +CORE_CUM_STREAM_LENGTH_70 0 0.000% 0 0.000% +CORE_CUM_STREAM_LENGTH_80 0 0.000% 0 0.000% +CORE_CUM_STREAM_LENGTH_90 0 0.000% 0 0.000% +CORE_CUM_STREAM_LENGTH_100_P 0 0.000% 0 0.000% + 2558 100.000% 2558 100.000% + 1.54 0.72 1.54 0.72 + +CORE_STREAM_TRAIN_HITS_0 127 79.375% 127 79.375% +CORE_STREAM_TRAIN_HITS_10 31 19.375% 31 19.375% +CORE_STREAM_TRAIN_HITS_20 2 1.250% 2 1.250% +CORE_STREAM_TRAIN_HITS_30 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_40 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_50 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_60 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_70 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_80 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_90 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_100_P 0 0.000% 0 0.000% + 160 100.000% 160 100.000% + 0.22 0.40 0.22 0.40 + +CORE_CUM_STREAM_TRAIN_HITS_0 801 65.980% 801 65.980% +CORE_CUM_STREAM_TRAIN_HITS_10 372 30.643% 372 30.643% +CORE_CUM_STREAM_TRAIN_HITS_20 41 3.377% 41 3.377% +CORE_CUM_STREAM_TRAIN_HITS_30 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_40 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_50 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_60 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_70 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_80 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_90 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_100_P 0 0.000% 0 0.000% + 1214 100.000% 1214 100.000% + 0.37 0.46 0.37 0.46 + +CORE_STREAM_TRAIN_CREATE 17351 17351 + + + diff --git a/labs/LAB5/runs/exchange2-sms0/PARAMS.in b/labs/LAB5/runs/exchange2-sms0/PARAMS.in new file mode 100644 index 00000000..2593c2b8 --- /dev/null +++ b/labs/LAB5/runs/exchange2-sms0/PARAMS.in @@ -0,0 +1,226 @@ +# File : PARAMS.kaby_lake +# Date : 03/06/19 +# Description : Kaby Lake Configuration +# +# Based on documentation found here: +# https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake + +## Simulation Parameters +--mode full +--model cmp +--sim_limit none + +## Core Parameters + +# Femptoseconds, 3.2GHz, used for energy estimates. +--chip_cycle_time 312500 + + +### Fetch Stage +--fetch_off_path_ops 1 +--fetch_across_cache_lines 1 + +# Will break the packet upon a taken branch. +--fetch_break_on_taken 1 + +# Number of bubble cycles to wait after taken branch. +--fetch_taken_bubble_cycles 0 + + +#### ICache +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 + +### Branch Predictor +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_mech tagescl + + +#### BTB + +# BTB model to use. +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 + +# Allow the BTB to be updated by off path ops. +--btb_off_path_writes 1 + + +#### CRS + +# Enable return stack +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 + +### iBP +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged + # iBTB Model. tc_tagless, tc_tagged, tc_hybrid. +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 + +### Decode Stage +--decode_cycles 5 + + +### Map Stage +--map_cycles 5 + + +### Issue Stage + +# Max number of instructions to be fetched, decoded, renamed, and issued per cycle. +--issue_width 6 + +--rs_fill_width 0 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 + + +### Exec Stage + +### DCache +--dcache_size 32768 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--dcache_assoc 4 +--dcache_line_size 64 + +### Reorder/Retire Stage + +# Max number of instructions to be retired per cycle. +--node_ret_width 6 +--node_table_size 224 + +# Do not keep stores in RSVs on cache misses; TODO: confirm what this knob does +--stores_do_not_block_window 1 + +# TODO: confirm what this knob does +--prefs_do_not_block_window 1 + + +## Uncore + +### Mid-level cache + +# Enable use of a midlevel cache between i/d and L1 +--mlc_present 0 + +### LLC +--l1_size 1048576 +--l1_banks 1 +--l1_cycles 18 +--l1_assoc 8 +--l1_line_size 64 +--l1_interleave_factor 64 + + +### Prefetcher +--pref_framework_on 1 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--pref_shared_queues 0 +--pref_train_on_pref_misses 0 +--pref_oracle_train 0 +--pref_ul1req_queue_overwrite_on_full 1 + +--stream_length 64 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 + +--pref_throttlefb_on=1 +--pref_acc_thresh_1=0.75 +--pref_acc_thresh_2=0.4 +--pref_acc_thresh_3=0.4 +--pref_timely_thresh=0.01 +--pref_polpf_thresh=0.005 +--pref_update_interval=8192 + +--mem_req_buffer_pref_watermark 4 +--promote_to_higher_priority_mem_req_type 1 + +### Memory +--addr_translation random + +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 + +--mem_req_buffer_entries 32 +--mem_l1_fill_queue_entries 32 +--va_page_size_bytes 4096 +--bus_width_in_bytes 8 + +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 + +## Other + + +### Debug +--debug_inst_start 0 +--debug_inst_stop -1 +--debug_cycle_start 0 +--debug_cycle_stop -1 + + +## Stats and Params +--dump_params 1 +--dump_stats 1 +--dump_trace 0 + +#################################### +--set_off_path_confirmed 1 + +--order_beyond_bus 1 + +--mem_ooo_stores 1 +--mem_obey_store_dep 1 diff --git a/labs/LAB5/runs/exchange2-sms0/PARAMS.out b/labs/LAB5/runs/exchange2-sms0/PARAMS.out new file mode 100644 index 00000000..f5c53901 --- /dev/null +++ b/labs/LAB5/runs/exchange2-sms0/PARAMS.out @@ -0,0 +1,908 @@ +--mode full +--model cmp +--frontend memtrace +--inst_limit 100000000 +--sim_limit none +--dump_params 1 +--dump_stats 1 +--dump_trace 0 +--mlc_present 0 +--l1_size 1048576 +--l1_assoc 8 +--l1_line_size 64 +--l1_cycles 18 +--l1_banks 1 +--l1_interleave_factor 64 +--va_page_size_bytes 4096 +--addr_translation random +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 +--dcache_size 32768 +--dcache_assoc 4 +--dcache_line_size 64 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--mem_ooo_stores 1 +--mem_obey_store_dep 1 +--mem_req_buffer_entries 32 +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 +--promote_to_higher_priority_mem_req_type 1 +--mem_req_buffer_pref_watermark 4 +--mem_l1_fill_queue_entries 32 +--order_beyond_bus 1 +--set_off_path_confirmed 1 +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--bus_width_in_bytes 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 +--chip_cycle_time 312500 +--issue_width 6 +--rs_fill_width 0 +--node_table_size 224 +--node_ret_width 6 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 +--decode_cycles 5 +--map_cycles 5 +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--fetch_across_cache_lines 1 +--fetch_off_path_ops 0 +--fetch_break_on_taken 1 +--fetch_taken_bubble_cycles 0 +--stores_do_not_block_window 1 +--prefs_do_not_block_window 1 +--cbp_trace_r0 /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir/trace/drmemtrace.exchange2.553888.0626.trace.gz +--memtrace_modules_log /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir/raw +--debug_cycle_start 0 +--debug_cycle_stop -1 +--debug_inst_start 0 +--debug_inst_stop -1 +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--bp_mech tagescl +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 +--btb_off_path_writes 1 +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_length 64 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 +--pref_framework_on 1 +--pref_shared_queues 0 +--pref_ul1req_queue_overwrite_on_full 1 +--pref_train_on_pref_misses 0 +--pref_oracle_train_on 0 +--pref_throttlefb_on 1 +--pref_acc_thresh_1 0.75 +--pref_acc_thresh_2 0.4 +--pref_acc_thresh_3 0.4 +--pref_update_interval 8192 +--pref_timely_thresh 0.01 +--pref_polpf_thresh 0.005 +--pref_sms_on 0 +1 1 1 1 1 1 1 + +--- Cut out everything below to use this file as PARAMS.in --- + +Parameter status at compile time and values supplied on the command line: + +SIM_MODE 0 full +SIM_MODEL 0 cmp +FRONTEND FE_PIN_EXEC_DRIVEN memtrace +INST_LIMIT NULL 100000000 +SIM_LIMIT "none" none +FORWARD_PROGRESS_LIMIT 100000000 +FORWARD_PROGRESS_INTERVAL 10000 +FAST_FORWARD 0 +FAST_FORWARD_UNTIL_ADDR 0 +FAST_FORWARD_TRACE_INS 0 +WARMUP 0 +HEARTBEAT_INTERVAL 1000000 +NUM_HEARTBEATS 0 +FILE_TAG "" +OUTPUT_DIR "." +STATUS_FILE NULL +BINDIR NULL +DUMP_PARAMS TRUE 1 +DUMP_STATS TRUE 1 +DUMP_TRACE FALSE 0 +CLEAR_STATS "never" +STATS_TO_TRACE NULL +STAT_TRACE_FILE "stats.trace" +STAT_TRACE_INTERVAL "i:100000" +PIPEVIEW FALSE +PIPEVIEW_FILE "pipeview" +MEMVIEW FALSE +MEMVIEW_FILE "memview.out" +MEMVIEW_START "never" +INST_HASH_TABLE_SIZE 500021 const +STDOUT_FILE NULL +STDERR_FILE NULL +PIN_EXEC_DRIVEN_FE_SOCKET "./pin_exec_driven_fe_socket.temp" +PRINT_PID FALSE +USE_UNSURE_FREE_LISTS FALSE +OPTIMIZER2_MAX_NUM_SLAVES 64 +OPTIMIZER2_PERFECT_MEMORYLESS FALSE +EXIT_COND 0 +ENABLE_SWPRF FALSE +MLC_PRESENT FALSE 0 +MLC_SIZE (512 * 1024) +MLC_ASSOC 4 +MLC_LINE_SIZE 64 +MLC_CYCLES 12 +PERFECT_MLC FALSE +MLC_READ_PORTS 1 +MLC_WRITE_PORTS 1 +MLC_BANKS 8 +MLC_INTERLEAVE_FACTOR 64 +MLC_CACHE_REPL_POLICY 0 +MLC_WRITE_THROUGH FALSE +PREFETCH_UPDATE_LRU_MLC TRUE +FORCE_L1_MISS FALSE +L1_SIZE (4 * 1024 * 1024) 1048576 +L1_ASSOC 8 8 +L1_LINE_SIZE 64 64 +L1_CYCLES 24 18 +PERFECT_L1 FALSE +PRIVATE_L1 FALSE +L1_READ_PORTS 1 +L1_WRITE_PORTS 1 +L1_BANKS 8 1 +L1_INTERLEAVE_FACTOR 64 64 +L1_CACHE_REPL_POLICY 0 +L1_WRITE_THROUGH FALSE +L1_IGNORE_WB FALSE +L1_USE_CORE_FREQ FALSE +MARK_L1_MISSES TRUE +PREFETCH_UPDATE_LRU_L1 TRUE +MEMORY_RANDOM_ADDR FALSE +VA_PAGE_SIZE_BYTES 4096 4096 +NUM_ADDR_NON_SIGN_EXTEND_BITS 48 +ADDR_TRANSLATION 0 random +CONSTANT_MEMORY_LATENCY FALSE +MEMORY_CYCLES 100 +STALL_MEM_REQS_ONLY FALSE +ICACHE_SIZE (64 * 1024) 32768 +ICACHE_ASSOC 4 4 +ICACHE_LINE_SIZE 64 64 +PERFECT_ICACHE FALSE +ICACHE_READ_PORTS 2 +ICACHE_WRITE_PORTS 1 +ICACHE_BANKS 8 +ICACHE_REPL 0 +DCACHE_SIZE (64 * 1024) 32768 +DCACHE_ASSOC 1 4 +DCACHE_LINE_SIZE 64 64 +DCACHE_CYCLES 2 +PERFECT_DCACHE FALSE +DCACHE_READ_PORTS 8 2 +DCACHE_WRITE_PORTS 1 1 +DCACHE_BANKS 1 1 +DCACHE_REPL 0 +DCACHE_REPL_PREF_THRESH 1 +MEM_OOO_STORES TRUE 1 +MEM_OBEY_STORE_DEP TRUE 1 +PREF_INSERT_LRU FALSE +PREF_INSERT_MIDDLE FALSE +PREF_INSERT_LOWQTR FALSE +PREF_INSERT_DYNACC FALSE +MEM_REQ_BUFFER_ENTRIES 32 32 +PRIVATE_MSHR_ON TRUE +MEM_PRIORITY_IFETCH 0 0 +MEM_PRIORITY_DFETCH 0 1 +MEM_PRIORITY_DSTORE 0 2 +MEM_PRIORITY_IPRF 9 3 +MEM_PRIORITY_DPRF 10 4 +MEM_PRIORITY_WB 0 5 +MEM_PRIORITY_WB_NODIRTY 0 5 +PROMOTE_TO_HIGHER_PRIORITY_MEM_REQ_TYPE FALSE 1 +MEM_REQ_BUFFER_PREF_WATERMARK 0 4 +MEM_REQ_BUFFER_WB_VALVE 2 +MEM_L1_FILL_QUEUE_ENTRIES 32 32 +MEM_BUS_OUT_QUEUE_PARTITION_ENABLE FALSE +MEM_MEM_QUEUE_PARTITION_ENABLE FALSE +MEM_BUS_OUT_QUEUE_AS_FIFO TRUE +OLDEST_FIRST_TO_MEM_QUEUE TRUE +ROUND_ROBIN_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE_TH 0 +L1_CYCLE_TIME 312500 +MLCQ_TO_L1Q_TRANSFER_LATENCY 1 +L1Q_TO_FSB_TRANSFER_LATENCY 1 +PRIORITIZE_PREFETCHES_WITH_UNIQUE FALSE +KICKOUT_PREFETCHES FALSE +KICKOUT_LOOK_FOR_OLDEST_FIRST FALSE +KICKOUT_OLDEST_PREFETCH FALSE +KICKOUT_OLDEST_PREFETCH_WITHIN_BANK FALSE +ORDER_BEYOND_BUS FALSE 1 +ALL_FIFO_QUEUES FALSE +QUEUE_MLC_SIZE 0 +QUEUE_L1_SIZE 0 +QUEUE_BUS_OUT_SIZE 0 +QUEUE_CORE_FILL_SIZE 0 +ALLOW_TYPE_MATCHES FALSE +STREAM_PREFETCH_ON FALSE +DC_PREF_CACHE_ENABLE FALSE +DC_PREF_CACHE_CYCLE 0 +PREF_INSERT_DCACHE_IMM TRUE +DC_PREF_CACHE_SIZE (64 * 1024) +DC_PREF_CACHE_ASSOC 4 +DC_PREF_ONLY_L1HIT FALSE +PREF_CACHE_USE_RDY_CYCLE FALSE +IC_PREF_CACHE_ENABLE FALSE +IC_PREF_CACHE_SIZE (64 * 1024) +IC_PREF_CACHE_ASSOC 4 +L1_PREF_CACHE_ENABLE FALSE +L1_PREF_CACHE_SIZE (1024 * 1024) +L1_PREF_CACHE_ASSOC 8 +SET_OFF_PATH_CONFIRMED FALSE 1 +USE_CONFIRMED_OFF FALSE +PREFCACHE_MOVE_OFFPATH FALSE +CACHE_STAT_ENABLE FALSE +PREF_DCACHE_HIT_FILL_L1 TRUE +PREF_ICACHE_HIT_FILL_L1 TRUE +CRITICAL_ACCESS_PLOT_ENABLE FALSE +CRITICAL_ACCESS_PLOT_FILE "critical_access_plot.dat" +ROUND_ROBIN_TO_L1 FALSE +PREF_I_TOGETHER FALSE +ONE_MORE_CACHE_LINE_ENABLE FALSE +L1_STATIC_PARTITION_ENABLE 0 +L1_STATIC_PARTITION NULL +L1_DYNAMIC_PARTITION_ENABLE FALSE +L1_DYNAMIC_PARTITION_POLICY 0 +PARTITION_UMON_DSS_PREF_ENABLE FALSE +L1_CACHE_HIT_POSITION_COLLECT FALSE +L1_PART_ON FALSE +L1_PART_TRIGGER "c:1000000" +L1_PART_START "t:0" +L1_PART_WARMUP FALSE +L1_PART_SHADOW_WARMUP FALSE +L1_PART_METRIC 0 +L1_PART_SEARCH 0 +L1_PART_USE_STALLING TRUE +L1_PART_FILL_DELAY 0 +L1_SHADOW_TAGS_MODULO 1 +HIER_MSHR_ON FALSE +PERF_PRED_ENABLE FALSE +PERF_PRED_MECH PERF_PRED_CP +PERF_PRED_REQ_LATENCY_MECH PERF_PRED_REQ_LATENCY_MECH_REQ_LATENCY +PERF_PRED_COUNT_ALL FALSE +PERF_PRED_COUNT_INST_MISSES TRUE +PERF_PRED_COUNT_PREFETCHES FALSE +PERF_PRED_COUNT_OFFPATH_REQS FALSE +PERF_PRED_COUNT_BW_REQS TRUE +PERF_PRED_UPDATE_MEM_REQ_TYPE FALSE +PERF_PRED_SLACK_PERIOD_SIZE 32 +PERF_PRED_REQS_FINISH_AT_FILL FALSE +PERF_PRED_MEM_UTIL_VIA_BUS_BW FALSE +PERF_PRED_CHIP_UTIL_VIA_MEM_STALL FALSE +DUMB_MODEL_AVG_REQ_DISTANCE 100 +DUMB_MODEL_RANDOMIZE_DISTANCE FALSE +DUMB_MODEL_AVG_REQ_DISTANCE_PER_CORE NULL +DUMB_MODEL_AVG_ROW_HITS 1 +DUMB_MODEL_AVG_ROW_HITS_PER_CORE NULL +DUMB_MODEL_MLP 1 +DUMB_MODEL_MLP_PER_CORE NULL +RAMULATOR_STANDARD "DDR4" DDR4 +RAMULATOR_SPEED "DDR4_2400R" DDR4_2400R +RAMULATOR_ORG "DDR4_8Gb_x8" DDR4_8Gb_x8 +RAMULATOR_CHANNELS 1 1 +RAMULATOR_RANKS 1 1 +RAMULATOR_BANKGROUPS 4 4 +RAMULATOR_BANKS 4 4 +RAMULATOR_CHIP_WIDTH 8 8 +BUS_WIDTH_IN_BYTES 8 8 +RAMULATOR_ROWS 65536 65536 +RAMULATOR_COLS 1024 1024 +RAMULATOR_SCHEDULING_POLICY "FRFCFS_Cap" FRFCFS_Cap +RAMULATOR_READQ_ENTRIES 32 32 +RAMULATOR_WRITEQ_ENTRIES 32 32 +RAMULATOR_REC_CMD_TRACE "off" FALSE +RAMULATOR_PRINT_CMD_TRACE "off" FALSE +RAMULATOR_USE_REST_OF_ADDR_AS_ROW_ADDR "on" +RAMULATOR_TCK 833333 833333 +RAMULATOR_TCL 16 16 +RAMULATOR_TCCD 6 6 +RAMULATOR_TCCDS 4 4 +RAMULATOR_TCCDL 6 6 +RAMULATOR_TCWL 12 12 +RAMULATOR_TBL 4 4 +RAMULATOR_TWTR 9 9 +RAMULATOR_TWTRS 3 3 +RAMULATOR_TWTRL 9 9 +RAMULATOR_TRP 16 16 +RAMULATOR_TRPpb 16 16 +RAMULATOR_TRPab 16 16 +RAMULATOR_TRCD 16 16 +RAMULATOR_TRCDR 16 16 +RAMULATOR_TRCDW 16 16 +RAMULATOR_TRAS 39 39 +DRAM_TECH_IN_NM 32 32 +DVFS_ON FALSE +DVFS_METRIC DVFS_METRIC_NUM_ELEMS +DVFS_CONFIGS NULL +DVFS_CONFIG_FILE NULL +DVFS_START "t:0" +DVFS_PERIOD "t:312500000000" +DVFS_LOG TRUE +DVFS_INDIVIDUAL_CORES FALSE +DVFS_CHIP_LEVEL FALSE +DVFS_STATIC NULL +DVFS_FORCE_CONFIG NULL +DVFS_REPLAY_CONFIG_TRACE NULL +DVFS_USE_ORACLE FALSE +DVFS_USE_BW_SHARING FALSE +DVFS_USE_DRAM_SHARING FALSE +DVFS_USE_STALL_TIME FALSE +DVFS_DRAM_SHARING_SOLVER_BIN NULL +DVFS_DRAM_SHARING_SOLVER_STRICT TRUE +DVFS_BW_SHARING_BUS_UTIL_THRESH 0.95 +DVFS_BW_SHARING_MAX_REQS 28.0 +DVFS_BW_SHARING_MAX_RW_COST 0.25 +DVFS_BW_SHARING_NO_PREF_STALL TRUE +DVFS_BW_SHARING_CRIT_STATS TRUE +DVFS_COUNT_L1_ACCESS_STALL FALSE +NUM_CORES 1 +CHIP_CYCLE_TIME 312500 312500 +CORE_0_CYCLE_TIME 312500 +CORE_1_CYCLE_TIME 312500 +CORE_2_CYCLE_TIME 312500 +CORE_3_CYCLE_TIME 312500 +CORE_4_CYCLE_TIME 312500 +CORE_5_CYCLE_TIME 312500 +CORE_6_CYCLE_TIME 312500 +CORE_7_CYCLE_TIME 312500 +CORE_8_CYCLE_TIME 312500 +CORE_9_CYCLE_TIME 312500 +CORE_10_CYCLE_TIME 312500 +CORE_11_CYCLE_TIME 312500 +CORE_12_CYCLE_TIME 312500 +CORE_13_CYCLE_TIME 312500 +CORE_14_CYCLE_TIME 312500 +CORE_15_CYCLE_TIME 312500 +CORE_16_CYCLE_TIME 312500 +CORE_17_CYCLE_TIME 312500 +CORE_18_CYCLE_TIME 312500 +CORE_19_CYCLE_TIME 312500 +CORE_20_CYCLE_TIME 312500 +CORE_21_CYCLE_TIME 312500 +CORE_22_CYCLE_TIME 312500 +CORE_23_CYCLE_TIME 312500 +CORE_24_CYCLE_TIME 312500 +CORE_25_CYCLE_TIME 312500 +CORE_26_CYCLE_TIME 312500 +CORE_27_CYCLE_TIME 312500 +CORE_28_CYCLE_TIME 312500 +CORE_29_CYCLE_TIME 312500 +CORE_30_CYCLE_TIME 312500 +CORE_31_CYCLE_TIME 312500 +CORE_32_CYCLE_TIME 312500 +CORE_33_CYCLE_TIME 312500 +CORE_34_CYCLE_TIME 312500 +CORE_35_CYCLE_TIME 312500 +CORE_36_CYCLE_TIME 312500 +CORE_37_CYCLE_TIME 312500 +CORE_38_CYCLE_TIME 312500 +CORE_39_CYCLE_TIME 312500 +CORE_40_CYCLE_TIME 312500 +CORE_41_CYCLE_TIME 312500 +CORE_42_CYCLE_TIME 312500 +CORE_43_CYCLE_TIME 312500 +CORE_44_CYCLE_TIME 312500 +CORE_45_CYCLE_TIME 312500 +CORE_46_CYCLE_TIME 312500 +CORE_47_CYCLE_TIME 312500 +CORE_48_CYCLE_TIME 312500 +CORE_49_CYCLE_TIME 312500 +CORE_50_CYCLE_TIME 312500 +CORE_51_CYCLE_TIME 312500 +CORE_52_CYCLE_TIME 312500 +CORE_53_CYCLE_TIME 312500 +CORE_54_CYCLE_TIME 312500 +CORE_55_CYCLE_TIME 312500 +CORE_56_CYCLE_TIME 312500 +CORE_57_CYCLE_TIME 312500 +CORE_58_CYCLE_TIME 312500 +CORE_59_CYCLE_TIME 312500 +CORE_60_CYCLE_TIME 312500 +CORE_61_CYCLE_TIME 312500 +CORE_62_CYCLE_TIME 312500 +CORE_63_CYCLE_TIME 312500 +ISSUE_WIDTH 4 6 +RS_FILL_WIDTH 8 0 +NODE_TABLE_SIZE 256 224 +NODE_RET_WIDTH 4 6 +NODE_RETIRE_RATE 10 +RS_SIZES "256" 97 +RS_CONNECTIONS "xF" 0 +FU_TYPES "0, 0, 0, 0" 0 0 0 0 0 0 0 0 +DECODE_CYCLES 1 5 +MAP_CYCLES 1 5 +EXTRA_RECOVERY_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after recovery. +EXTRA_REDIRECT_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after redirect. +EXTRA_CALLSYS_CYCLES 20 const +DIE_ON_CALLSYS FALSE +DIE_ON_RET_STALL_THRESH 0 +DIE_ON_RET_STALL_CORE 0 +DIE_ON_MEM_BLOCK_THRESH 0 +DIE_ON_MEM_BLOCK_CORE 0 +FETCH_ACROSS_CACHE_LINES FALSE 1 +FETCH_OFF_PATH_OPS TRUE 0 +FETCH_BREAK_ON_TAKEN FALSE 1 +FETCH_TAKEN_BUBBLE_CYCLES 0 0 +WP_COLLECT_STATS FALSE +SWITCH_IC_FETCH_ON_RECOVERY TRUE +OP_INV_DELAY 1 +OP_NOP_DELAY 1 +OP_CF_DELAY 1 +OP_MOV_DELAY 1 +OP_CMOV_DELAY 1 +OP_LDA_DELAY 1 +OP_IMEM_DELAY 1 +OP_IADD_DELAY 1 +OP_IMUL_DELAY 3 +OP_IDIV_DELAY -20 +OP_ICMP_DELAY 1 +OP_LOGIC_DELAY 1 +OP_SHIFT_DELAY 1 +OP_FMEM_DELAY 1 +OP_FCVT_DELAY 3 +OP_FADD_DELAY 3 +OP_FMUL_DELAY 5 +OP_FMA_DELAY 5 +OP_FDIV_DELAY -20 +OP_FCMP_DELAY 3 +OP_FCMOV_DELAY 1 +OP_GATHER_DELAY 12 +OP_SCATTER_DELAY 18 +OP_PIPELINED_FAST_DELAY 2 +OP_PIPELINED_MEDIUM_DELAY 5 +OP_PIPELINED_SLOW_DELAY 10 +OP_NOTPIPELINED_MEDIUM_DELAY -5 +OP_NOTPIPELINED_SLOW_DELAY -20 +OP_NOTPIPELINED_VERY_SLOW_DELAY -100 +UNIFORM_OP_DELAY 0 +STALL_ON_WAIT_MEM TRUE +STORES_DO_NOT_BLOCK_WINDOW FALSE 1 +PREFS_DO_NOT_BLOCK_WINDOW FALSE 1 +OBEY_REG_DEP TRUE +OLDEST_FIRST_SCHED FALSE +FIND_EMPTIEST_RS FALSE +TRACK_L1_MISS_DEPS FALSE +CBP_TRACE_R0 NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir/trace/drmemtrace.exchange2.553888.0626.trace.gz +CBP_TRACE_R1 NULL +CBP_TRACE_R2 NULL +CBP_TRACE_R3 NULL +CBP_TRACE_R4 NULL +CBP_TRACE_R5 NULL +CBP_TRACE_R6 NULL +CBP_TRACE_R7 NULL +CBP_TRACE_R8 NULL +CBP_TRACE_R9 NULL +CBP_TRACE_R10 NULL +CBP_TRACE_R11 NULL +CBP_TRACE_R12 NULL +CBP_TRACE_R13 NULL +CBP_TRACE_R14 NULL +CBP_TRACE_R15 NULL +CBP_TRACE_R16 NULL +CBP_TRACE_R17 NULL +CBP_TRACE_R18 NULL +CBP_TRACE_R19 NULL +CBP_TRACE_R20 NULL +CBP_TRACE_R21 NULL +CBP_TRACE_R22 NULL +CBP_TRACE_R23 NULL +CBP_TRACE_R24 NULL +CBP_TRACE_R25 NULL +CBP_TRACE_R26 NULL +CBP_TRACE_R27 NULL +CBP_TRACE_R28 NULL +CBP_TRACE_R29 NULL +CBP_TRACE_R30 NULL +CBP_TRACE_R31 NULL +CBP_TRACE_R32 NULL +CBP_TRACE_R33 NULL +CBP_TRACE_R34 NULL +CBP_TRACE_R35 NULL +CBP_TRACE_R36 NULL +CBP_TRACE_R37 NULL +CBP_TRACE_R38 NULL +CBP_TRACE_R39 NULL +CBP_TRACE_R40 NULL +CBP_TRACE_R41 NULL +CBP_TRACE_R42 NULL +CBP_TRACE_R43 NULL +CBP_TRACE_R44 NULL +CBP_TRACE_R45 NULL +CBP_TRACE_R46 NULL +CBP_TRACE_R47 NULL +CBP_TRACE_R48 NULL +CBP_TRACE_R49 NULL +CBP_TRACE_R50 NULL +CBP_TRACE_R51 NULL +CBP_TRACE_R52 NULL +CBP_TRACE_R53 NULL +CBP_TRACE_R54 NULL +CBP_TRACE_R55 NULL +CBP_TRACE_R56 NULL +CBP_TRACE_R57 NULL +CBP_TRACE_R58 NULL +CBP_TRACE_R59 NULL +CBP_TRACE_R60 NULL +CBP_TRACE_R61 NULL +CBP_TRACE_R62 NULL +CBP_TRACE_R63 NULL +MEMTRACE_MODULES_LOG NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir/raw +DUMB_CORE_ON FALSE +DUMB_CORE 1 +DEBUG_CYCLE_START 0 0 +DEBUG_CYCLE_STOP 0 -1 +DEBUG_TIME_START 0 +DEBUG_TIME_STOP 0 +DEBUG_INST_START 0 0 +DEBUG_INST_STOP 0 -1 +DEBUG_OP_START 0 +DEBUG_OP_STOP 0 +DEBUG_CACHE_LIB FALSE +DEBUG_HASH_LIB FALSE +DEBUG_LIST_LIB FALSE +DEBUG_PORT_LIB FALSE +DEBUG_BUS_LIB FALSE +DEBUG_OP_POOL FALSE +DEBUG_ORACLE FALSE +DEBUG_FRONTEND FALSE +DEBUG_ADDR_TRANS FALSE +DEBUG_BP FALSE +DEBUG_BP_DIR FALSE +DEBUG_BTB FALSE +DEBUG_CRS FALSE +DEBUG_MAP FALSE +DEBUG_MEMORY FALSE +DEBUG_REPLAY FALSE +DEBUG_FREQ FALSE +DEBUG_MODEL FALSE +DEBUG_THREAD FALSE +DEBUG_ICACHE_STAGE FALSE +DEBUG_DECODE_STAGE FALSE +DEBUG_MAP_STAGE FALSE +DEBUG_NODE_STAGE FALSE +DEBUG_EXEC_STAGE FALSE +DEBUG_DCACHE_STAGE FALSE +DEBUG_RETIRED_UOPS FALSE +DEBUG_EXC_INSERTS FALSE +DEBUG_BP_CONF FALSE +DEBUG_ONPATH_CONF FALSE +DEBUG_STREAM FALSE +DEBUG_STREAM_MEM FALSE +DEBUG_WAY FALSE +DEBUG_L2MARKV FALSE +DEBUG_L2L1PREF FALSE +DEBUG_PERF_PRED FALSE +DEBUG_POWER_UTILS FALSE +DEBUG_DVFS FALSE +DEBUG_TRACE_READ FALSE +DEBUG_INST_FIELDS FALSE +DEBUG_OP_FIELDS FALSE +DEBUG_PIN_EXEC_DRIVEN FALSE +DEBUG_CACHE_PART FALSE +DEBUG_OPTIMIZER2 FALSE +DEBUG_PREF FALSE +PERFECT_BP FALSE +PERFECT_BTB FALSE +PERFECT_IBP FALSE +PERFECT_CRS FALSE +PERFECT_CBR_BTB FALSE +PERFECT_NT_BTB FALSE +CFS_PER_CYCLE 3 6 # Number of branches that can be predicted in a single cycle +UPDATE_BP_OFF_PATH FALSE 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +BP_UPDATE_AT_RETIRE FALSE 0 # Update the BP at retire. If false, update at the end of exec. +BP_MECH 0 tagescl +LATE_BP_MECH NUM_BP +LATE_BP_LATENCY 5 +HIST_LENGTH 16 +PHT_CTR_BITS 2 const +BHT_ENTRIES (4 * 1024) +BHT_ASSOC 4 +HYBRIDS_INDEX_LENGTH 16 +HYBRIDG_HIST_LENGTH 16 +HYBRIDP_HIST_LENGTH 16 +FILTER_INDEX_LENGTH 16 +USE_FILTER FALSE +INF_HYBRIDGP FALSE +BP_HASH_TOS FALSE +IBTB_HASH_TOS FALSE +BTB_MECH 0 generic +BTB_ENTRIES (4 * 1024) 4096 +BTB_ASSOC 4 4 +BTB_OFF_PATH_WRITES TRUE 1 +ENABLE_CRS TRUE 1 +CRS_ENTRIES 32 32 +CRS_REALISTIC 0 1 +ENABLE_IBP TRUE 1 # Enable the indirect branch predictor +USE_PAT_HIST TRUE +IBTB_MECH 1 tc_tagged +IBTB_HIST_LENGTH 16 +IBTB_OFF_PATH_WRITES TRUE 1 # Allow off path ops to update the ibtb. +TARGETS_IN_HIST 4 +TC_ENTRIES (4 * 1024) 4096 +TC_ASSOC 4 4 +NUM_CORR_BRANCHES 3 +SEL_HIST_BP_ENTRIES 8192 +SEL_HIST_LENGTH 16 +SEL_HIST_DYN_CNT_TH 16 +SEL_HIST_MISPRED_TH 4 +ENABLE_BP_CONF FALSE +CONF_MECH 0 +PERF_BP_CONF_PRED FALSE +BPC_BITS 16 +BPC_MECH 1 +BPC_CTR_RESET TRUE +BPC_CIT_BITS 8 +BPC_CIT_TH 50 +BPC_CTR_BITS 3 +OPC_COUNT_ZEROS FALSE +OPC_COUNT_THRESH 10 +INF_LOOP FALSE +INF_LOOP_BUCKETS 811 +LOOP_ENTRIES (4 * 1024) +LOOP_ASSOC 4 +LOOP_COUNT_MAX 127 +LOOP_REPEAT_MAX 15 +KNOB_PRINT_BRINFO FALSE +BR_MISPRED_FILE NULL +CONF_PERCEPTRON_TH 0 +CONF_PERCEPTRON_CTR_BITS 8 +CONF_PERCEPTRON_ENTRIES 127 +CONF_PERCEPTRON_THRESH_OVRD 0 +CONF_HIST_LENGTH 32 +PERCEPTRON_CONF_USE_CONF FALSE +PERCEPTRON_CONF_TRAIN_HIS FALSE +PERCEPTRON_CONF_TRAIN_CONF FALSE +PERCEPTRON_CONF_TRAIN_OFFSET_CONF FALSE +PERCEPTRON_TRAIN_MISP_FACTOR 1 +PERCEPTRON_TRAIN_CORR_FACTOR 1 +PERCEPTRON_CONF_HIS_BOTH FALSE +PERCEPTRON_CONF_HIS_BOTH_LENGTH 4 +ENABLE_ICACHE_PACKET_BREAKING TRUE +NUM_LOAD_STORE_PER_PACKET 0 +PACKET_BREAK_ON_FUS FALSE +PACKET_BREAK_FU_TYPES "G,G,G,G,G,G,G,G,G,G,G,G" +POWER_INTF_ON FALSE +POWER_INTF_ENABLE_SCALING FALSE +POWER_INTF_EXEC "power/power_intf.py" +POWER_INTF_REF_CHIP_TECH_NM 22 +POWER_INTF_REF_CHIP_FREQ (3.2e9) +POWER_INTF_REF_MEMORY_FREQ (0.8e9) +POWER_OTHER (0.0) +PREF_STREAM_ON FALSE 1 +PREF_STREAM_PER_CORE_ENABLE FALSE 1 +STREAM_BUFFER_N 16 +STREAM_PREFETCH_N 2 4 +STREAM_START_DIS 5 1 +STREAM_LENGTH 16 64 +STREAM_FULL_N 1 +STREAM_TRAIN_LENGTH 16 +STREAM_TRAIN_NUM 1 4 +PREF_ACC_USE_CACHE FALSE +STREAM_STALL_ON_QUEUE_FULL FALSE +PREF_SCHEDULE_NUM 4 +TRAIN_FILTER_SIZE 32 +PREF_REQ_Q_SIZE 64 +STREAM_CREATE_ON_DC_MISS FALSE 0 +STREAM_CREATE_ON_L1_MISS TRUE 1 +STREAM_TRAIN_ON_WRONGPATH TRUE +STREAM_CREATE_ON_WRONGPATH TRUE +STREAM_PREF_INTO_DCACHE FALSE +REMOVE_REDUNDANT_STREAM FALSE +L2HIT_STREAM_SCHEDULE_NUM 4 +PREF_REQ_QUEUE_FILTER_ON FALSE +HW_PREF_HIT_TRAIN_STREAM FALSE +L2HIT_STREAM_BUFFER_N 32 +L2HIT_STREAM_PREFETCH_N 2 +L2HIT_STREAM_START_DIS 2 +L2HIT_STREAM_LENGTH 8 +L2HIT_PREF_REQ_Q_SIZE 128 +L2HIT_L2ACCESS_REQ_Q_SIZE 64 +PREF_STREAM_ACCPERSTREAM FALSE +PREF_ACC_DISTANCE_10 128 +PREF_FRAMEWORK_ON FALSE 1 +PREF_TRACE_ON FALSE +PREF_DL0REQ_QUEUE_SIZE 32 +PREF_UMLC_REQ_QUEUE_SIZE 64 +PREF_UL1REQ_QUEUE_SIZE 128 +PREF_SHARED_QUEUES TRUE 0 +PREF_DL0_MISS_ON TRUE +PREF_DL0_HIT_ON TRUE +PREF_DL0REQ_QUEUE_FILTER_ON TRUE +PREF_UMLC_REQ_QUEUE_FILTER_ON TRUE +PREF_UL1REQ_QUEUE_FILTER_ON TRUE +PREF_DL0REQ_ADD_FILTER_ON TRUE +PREF_UMLC_REQ_ADD_FILTER_ON TRUE +PREF_UL1REQ_ADD_FILTER_ON TRUE +PREF_DL0REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UMLC_REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UL1REQ_QUEUE_OVERWRITE_ON_FULL FALSE 1 +PREF_DL0SCHEDULE_NUM 4 +PREF_UMLC_SCHEDULE_NUM 4 +PREF_UL1SCHEDULE_NUM 4 +PREF_L1Q_DEMAND_RESERVE 0 +PREF_REPORT_PREF_MATCH_AS_MISS FALSE +PREF_REPORT_PREF_MATCH_AS_HIT TRUE +PREF_UPDATE_ON_WRONGPATH TRUE +PREF_TRAIN_ON_PREF_MISSES FALSE 0 +PREF_ORACLE_TRAIN_ON FALSE 0 +PREF_REQ_DROP FALSE +PREF_THROTTLE_ON FALSE +PREF_THROTTLEFB_ON FALSE 1 +PREF_ACC_THRESH_1 0.90 0.75 +PREF_ACC_THRESH_2 0.70 0.4 +PREF_ACC_THRESH_3 0.60 0.4 +PREF_ACC_THRESH_4 0.40 +PREF_UPDATE_INTERVAL 0 8192 +PREF_ANALYZE_LOAD FALSE +PREF_POL_THRESH_1 0.25 +PREF_POL_THRESH_2 0.10 +PREF_POLBV_ON FALSE +PREF_POLBV_SIZE 1024 +PREF_TIMELY_THRESH 0.05 0.01 +PREF_POLPF_THRESH 0.01 0.005 +PREF_DEGFB_USEONLYACC FALSE +PREF_DEGFB_USEONLYPOL FALSE +PREF_DEGFB_USEONLYLATE FALSE +PREF_TIMELY_THRESH_2 0.005 +PREF_DEGFB_STATPHASEFILE FALSE +PREF_MAX_DEGFB 4 +PREF_DHAL FALSE +PREF_DHAL_SENTTHRESH 16 +PREF_DHAL_USETHRESH_MAX 12 +PREF_DHAL_USETHRESH_MIN2 8 +PREF_DHAL_USETHRESH_MIN1 4 +PREF_DHAL_MAXDEG 64 +PREF_HFILTER_ON FALSE +PREF_HFILTER_INDEX_BITS 12 +PREF_HFILTER_USE_PC FALSE +PREF_HFILTER_PRED_USELESS_THRES 2 +PREF_HFILTER_RESET_ENABLE FALSE +PREF_HFILTER_RESET_INTERVAL 100000 +L2L1PREF_ON FALSE +L2WAY_PREF FALSE +L2MARKV_PREF_ON FALSE +L2NEXT_PREF_ON FALSE +L2HIT_STREAM_PREF_ON FALSE +L2L1_DC_HIT_TRAIN FALSE +L1_HIT_DUMP_FILE_ON FALSE +L1_HIT_DUMP_WO_TXT FALSE +L1_HIT_DUMPFILE "l1hit_dump.out" +IDEAL_L2_L1_PREFETCHER FALSE +IDEAL_L2_ICACHE_PREFETCHER FALSE +L1WAY_PREF_SEND_QUEUE 4 +L1PREF_REQ_QUEUE_SIZE 1024 +L1PREF_IMMEDIATE FALSE +L1WAY_PREF_TIMER_DIS 1000 +L1MARKV_PREF_SEND_QUEUE 4 +L1PREF_MARKV_REQ_QUEUE_SIZE 1024 +MARKV_L2ACCESS_REQ_Q_SIZE 64 +L1MARKV_PREF_IMMEDIATE FALSE +L1MARKV_PREF_TIMER_DIS 1 +L2L1_HIT_TRAIN TRUE +L1MARKV_REQ_TH 1 +L2L1_IMMEDIATE_PREF_CACHE FALSE +L2L1_FILL_PREF_CACHE FALSE +L2L1_L2_HIT_STAT FALSE +PREF_GHB_ON FALSE +DEBUG_PREF_GHB FALSE +PREF_GHB_BUFFER_N 1024 +PREF_GHB_INDEX_N 128 +PREF_GHB_CZONE_BITS 12 +PREF_GHB_DEGREE 16 +PREF_GHB_MAX_DEGREE 32 +PREF_STRIDE_ON FALSE +DEBUG_PREF_STRIDE FALSE +PREF_STRIDE_TABLE_N 1024 +PREF_STRIDE_REGION_BITS 16 +PREF_STRIDE_DEGREE 4 +PREF_STRIDE_DISTANCE 16 +PREF_STRIDE_STARTDISTANCE 1 +PREF_STRIDE_SINGLE_THRESH 6 +PREF_STRIDE_MULTI_THRESH 6 +PREF_STRIDE_SINGLE_STRIDE_MODE FALSE +PREF_STRIDEPC_ON FALSE +DEBUG_PREF_STRIDEPC FALSE +PREF_STRIDEPC_TABLE_N 1024 +PREF_STRIDEPC_DEGREE 4 +PREF_STRIDEPC_DISTANCE 16 +PREF_STRIDEPC_USELOADADDR FALSE +PREF_STRIDEPC_TRAINNUM 2 +PREF_STRIDEPC_STARTDIS 4 +PREF_PHASE_ON FALSE +PREF_PHASE_STUDY FALSE +DEBUG_PREF_PHASE FALSE +PREF_PHASE_PRIME_HASH 16381 +PREF_PHASE_INFOSIZE 16384 +PREF_PHASE_LOG2REGIONSIZE 12 +PREF_PHASE_REGIONENTRIES 64 +PREF_PHASE_TRACKEDREGIONS 32 +PREF_PHASE_INTERVAL 100000 +PREF_PHASE_TABLE_SIZE 64 +PREF_PHASE_MAXDIFF_THRESH 64 +PREF_PHASE_MIN_MISSES 64 +PREF_PHASE_MISSPER 0.4 +PREF_2DC_ON FALSE +DEBUG_PREF_2DC FALSE +PREF_2DC_CACHE_SIZE (1 * 1024) +PREF_2DC_CACHE_ASSOC 4 +PREF_2DC_CACHE_LINE_SIZE 1 +PREF_2DC_DEGREE 16 +PREF_2DC_ZONE_SHIFT 10 +PREF_2DC_TAG_SIZE 16 +PREF_2DC_NUM_REGIONS 64 +PREF_2DC_REGION_HASH 61 +PREF_MARKOV_ON FALSE +DEBUG_PREF_MARKOV FALSE +PREF_MARKOV_NUM_ENTRIES 65536 +PREF_MARKOV_NUM_NEXT_STATES 8 +PREF_MARKOV_SEND_ON_PREF_HIT TRUE +PREF_MARKOV_UPDATE_ON_PREF_HIT TRUE +PREF_MARKOV_TABLE_UPDATE_POLICY 0 +PREF_MARKOV_SEND_THRESHOLD 0 +PREF_SMS_ON FALSE 0 +PREF_SMS_AT_SIZE 64 +PREF_SMS_FT_SIZE 64 +PREF_SMS_PHT_SIZE 16384 +PREF_SMS_PRF_SIZE 1024 +PREF_SMS_REGION_SIZE 2048 diff --git a/labs/LAB5/runs/exchange2-sms0/bp.stat.0.out b/labs/LAB5/runs/exchange2-sms0/bp.stat.0.out new file mode 100644 index 00000000..1cad164e --- /dev/null +++ b/labs/LAB5/runs/exchange2-sms0/bp.stat.0.out @@ -0,0 +1,752 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 40827371 Instructions: 100000000 IPC: 2.44934 + +BTB_ON_PATH_MISS 6923 0.040% 6923 0.040% +BTB_ON_PATH_HIT 17250203 99.960% 17250203 99.960% + 17257126 100.000% 17257126 100.000% + 1.00 1.00 1.00 1.00 + +BTB_OFF_PATH_MISS 0 -nan% 0 -nan% +BTB_OFF_PATH_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BTB_ON_PATH_WRITE 6923 100.000% 6923 100.000% +BTB_OFF_PATH_WRITE 0 0.000% 0 0.000% + 6923 100.000% 6923 100.000% + 0.00 0.00 0.00 0.00 + +BP_ON_PATH_CORRECT 16391289 94.983% 16391289 94.983% +BP_ON_PATH_MISPREDICT 102150 0.592% 102150 0.592% +BP_ON_PATH_MISFETCH 763687 4.425% 763687 4.425% + 17257126 100.000% 17257126 100.000% + 0.09 0.41 0.09 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+CHIP_UTILIZATION_UNDER_CRITICAL_MEM_REQ 0 -nan 0 -nan + +CHIP_UTILIZATION_UNDER_NONCRITICAL_MEM_REQ 0 -nan 0 -nan + +CYCLES_NOT_WAITING_FOR_OFF_CHIP 0 0.0000 0 0.0000 + +FUS_BUSY_NOT_WAITING_FOR_OFF_CHIP 0 -nan 0 -nan + +CYCLES_WAITING_FOR_OFF_CHIP 0 0.0000 0 0.0000 + +FUS_BUSY_WAITING_FOR_OFF_CHIP 0 -nan 0 -nan + +TOTAL_OFF_CHIP_DELAYS_LEFT 0 0 + +WRONG_IO_SCHED 0 0 + +DVFS_CONFIG_SWITCH 0 0 + + + diff --git a/labs/LAB5/runs/exchange2-sms0/fetch.stat.0.out b/labs/LAB5/runs/exchange2-sms0/fetch.stat.0.out new file mode 100644 index 00000000..7ba2242c --- /dev/null +++ b/labs/LAB5/runs/exchange2-sms0/fetch.stat.0.out @@ -0,0 +1,248 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 40827371 Instructions: 100000000 IPC: 2.44934 + +ICACHE_CYCLE 40827371 40827371 + +TCACHE_CYCLE 0 0 + +ICACHE_CYCLE_ONPATH 24115132 59.066% 24115132 59.066% +ICACHE_CYCLE_OFFPATH 16712239 40.934% 16712239 40.934% + 40827371 100.000% 40827371 100.000% + 0.41 0.46 0.41 0.46 + +FETCH_ON_PATH 24570155 100.000% 24570155 100.000% +FETCH_OFF_PATH 0 0.000% 0 0.000% + 24570155 100.000% 24570155 100.000% + 0.00 0.00 0.00 0.00 + +FETCHED_OPS_ON_PATH 0 -nan% 0 -nan% +FETCHED_OPS_OFF_PATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +INST_LOST_WAIT_FOR_MISP_RECOVERY 0 0.000% 0 0.000% +INST_LOST_WAIT_FOR_TIMER 0 0.000% 0 0.000% +INST_LOST_WAIT_FOR_EMPTY_ROB 0 0.000% 0 0.000% +INST_LOST_WAIT_FOR_REDIRECT 216810 0.145% 216810 0.145% +INST_LOST_FETCH 128408890 85.644% 128408890 85.644% +INST_LOST_OFF_PATH 0 0.000% 0 0.000% +INST_LOST_FULL_WINDOW 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_OTHER 130326 0.087% 130326 0.087% +INST_LOST_ROB_STALL_WAIT_FOR_RECOVERY 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_REDIRECT 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_GAP_FILL 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_L1_MISS 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_MEMORY 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_DC_MISS 40584 0.027% 40584 0.027% +INST_LOST_ROB_BLOCK_ISSUE_FULL 0 0.000% 0 0.000% +INST_LOST_ROB_BLOCK_ISSUE_GAP_TOO_LARGE 0 0.000% 0 0.000% +INST_LOST_BREAK_DONT 0 0.000% 0 0.000% +INST_LOST_BREAK_ISSUE_WIDTH 0 0.000% 0 0.000% +INST_LOST_BREAK_CF 0 0.000% 0 0.000% +INST_LOST_BREAK_BTB_MISS 18373 0.012% 18373 0.012% +INST_LOST_BREAK_ICACHE_MISS 2204412 1.470% 2204412 1.470% +INST_LOST_BREAK_LINE_END 0 0.000% 0 0.000% +INST_LOST_BREAK_STALL 0 0.000% 0 0.000% +INST_LOST_BREAK_BARRIER 0 0.000% 0 0.000% +INST_LOST_BREAK_OFFPATH 115538 0.077% 115538 0.077% +INST_LOST_BREAK_ALIGNMENT 0 0.000% 0 0.000% +INST_LOST_BREAK_TAKEN 18797687 12.537% 18797687 12.537% +INST_LOST_BREAK_MODEL_BEFORE 0 0.000% 0 0.000% +INST_LOST_BREAK_MODEL_AFTER 0 0.000% 0 0.000% + 149932620 100.000% 149932620 100.000% + 7.01 7.46 7.01 7.46 + +INST_LOST_TOTAL 244964226 244964226 + +FETCH_0_OPS 431675 1.727% 431675 1.727% +FETCH_1_OPS 1261739 5.049% 1261739 5.049% +FETCH_2_OPS 1046350 4.187% 1046350 4.187% +FETCH_3_OPS 1337381 5.352% 1337381 5.352% +FETCH_4_OPS 963564 3.856% 963564 3.856% +FETCH_5_OPS 2500314 10.006% 2500314 10.006% +FETCH_6_OPS 17447747 69.822% 17447747 69.822% +FETCH_7_OPS 0 0.000% 0 0.000% +FETCH_8_OPS 0 0.000% 0 0.000% +FETCH_9_OPS 0 0.000% 0 0.000% +FETCH_10_OPS 0 0.000% 0 0.000% +FETCH_11_OPS 0 0.000% 0 0.000% +FETCH_12_OPS 0 0.000% 0 0.000% +FETCH_13_OPS 0 0.000% 0 0.000% +FETCH_14_OPS 0 0.000% 0 0.000% +FETCH_15_OPS 0 0.000% 0 0.000% +FETCH_16_OPS 0 0.000% 0 0.000% + 24988770 100.000% 24988770 100.000% + 5.14 1.45 5.14 1.45 + +ST_BREAK_DONT 0 0.000% 0 0.000% +ST_BREAK_ISSUE_WIDTH 15550257 63.289% 15550257 63.289% +ST_BREAK_CF 0 0.000% 0 0.000% +ST_BREAK_BTB_MISS 6923 0.028% 6923 0.028% +ST_BREAK_ICACHE_MISS 13867 0.056% 13867 0.056% +ST_BREAK_LINE_END 0 0.000% 0 0.000% +ST_BREAK_STALL 0 0.000% 0 0.000% +ST_BREAK_BARRIER 0 0.000% 0 0.000% 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-nan% 0 -nan% +ICACHE_CYCLE_OFFPATH_RA 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +INACCURATE_OFFPATH_CYCLES 0 0.0000 0 0.0000 + +FETCH_ALL_INST 128408890 128408890 + +EXEC_ALL_INST 128408799 128408799 + +RET_ALL_INST 128408750 128408750 + +EXEC_ON_PATH_INST 128408799 100.000% 128408799 100.000% +EXEC_OFF_PATH_INST 0 0.000% 0 0.000% + 128408799 100.000% 128408799 100.000% + 0.00 0.00 0.00 0.00 + +EXEC_ON_PATH_INST_MEM 45194849 35.196% 45194849 35.196% +EXEC_ON_PATH_INST_NOTMEM 83213950 64.804% 83213950 64.804% +EXEC_OFF_PATH_INST_MEM 0 0.000% 0 0.000% +EXEC_OFF_PATH_INST_NOTMEM 0 0.000% 0 0.000% + 128408799 100.000% 128408799 100.000% + 0.65 0.28 0.65 0.28 + +EXEC_RA_INST 0 -nan% 0 -nan% +EXEC_NONRA_INST 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +EXEC_ON_PATH_INST_RA 0 -nan% 0 -nan% +EXEC_OFF_PATH_INST_RA 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +EXEC_ON_PATH_INST_NONRA 0 -nan% 0 -nan% +EXEC_OFF_PATH_INST_NONRA 0 -nan% 0 -nan% + 0 -nan% 0 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-nan% 0 -nan% +FETCH_TH_ADJUST_DOWN 0 -nan% 0 -nan% +FETCH_TH_ADJUST_SAME 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +THROTTLE_ADJUST_CACHE_MISS_INFO 0 0 + +LOW_CONF_COUNT_BP_MIS_0 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_1 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_2 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_3 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_4 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_5 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_6 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_7 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_8 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_9 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_10 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_11 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_12 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_13 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_14 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_15 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_16 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_17 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_18 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_19 0 -nan% 0 -nan% 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b/labs/LAB5/runs/exchange2-sms0/inst.stat.0.out new file mode 100644 index 00000000..3cbda967 --- /dev/null +++ b/labs/LAB5/runs/exchange2-sms0/inst.stat.0.out @@ -0,0 +1,103 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 40827371 Instructions: 100000000 IPC: 2.44934 + +ST_OP_INV 0 0.000% 0 0.000% +ST_OP_NOP 1224808 0.954% 1224808 0.954% +ST_OP_CF 17257126 13.439% 17257126 13.439% +ST_OP_MOV 8789711 6.845% 8789711 6.845% +ST_OP_CMOV 27636 0.022% 27636 0.022% +ST_OP_LDA 6908184 5.380% 6908184 5.380% +ST_OP_IMEM 45193492 35.195% 45193492 35.195% +ST_OP_IADD 30143783 23.475% 30143783 23.475% +ST_OP_IMUL 1090225 0.849% 1090225 0.849% +ST_OP_IDIV 921 0.001% 921 0.001% +ST_OP_ICMP 12337271 9.608% 12337271 9.608% +ST_OP_LOGIC 5287019 4.117% 5287019 4.117% +ST_OP_SHIFT 147316 0.115% 147316 0.115% +ST_OP_FMEM 1398 0.001% 1398 0.001% +ST_OP_FCVT 0 0.000% 0 0.000% +ST_OP_FADD 0 0.000% 0 0.000% +ST_OP_FMUL 0 0.000% 0 0.000% +ST_OP_FMA 0 0.000% 0 0.000% +ST_OP_FDIV 0 0.000% 0 0.000% +ST_OP_FCMP 0 0.000% 0 0.000% +ST_OP_FCMOV 0 0.000% 0 0.000% +ST_OP_GATHER 0 0.000% 0 0.000% +ST_OP_SCATTER 0 0.000% 0 0.000% +ST_OP_PIPELINED_FAST 0 0.000% 0 0.000% +ST_OP_PIPELINED_MEDIUM 0 0.000% 0 0.000% +ST_OP_PIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_MEDIUM 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_VERY_SLOW 0 0.000% 0 0.000% + 128408890 100.000% 128408890 100.000% + 6.00 2.44 6.00 2.44 + +ST_NOT_CF 111151764 86.561% 111151764 86.561% +ST_CF_BR 1114568 0.868% 1114568 0.868% +ST_CF_CBR 16018157 12.474% 16018157 12.474% +ST_CF_CALL 47888 0.037% 47888 0.037% +ST_CF_IBR 28627 0.022% 28627 0.022% +ST_CF_ICALL 0 0.000% 0 0.000% +ST_CF_ICO 0 0.000% 0 0.000% +ST_CF_RET 47886 0.037% 47886 0.037% +ST_CF_SYS 0 0.000% 0 0.000% + 128408890 100.000% 128408890 100.000% + 0.26 0.64 0.26 0.64 + +ST_BAR_NONE 128408890 100.000% 128408890 100.000% +ST_BAR_FETCH 0 0.000% 0 0.000% +ST_BAR_ISSUE 0 0.000% 0 0.000% +ST_BAR_BOTH 0 0.000% 0 0.000% + 128408890 100.000% 128408890 100.000% + 0.00 0.00 0.00 0.00 + +ST_NOT_MEM 83214000 64.804% 83214000 64.804% +ST_MEM_LD 28723490 22.369% 28723490 22.369% +ST_MEM_ST 16471400 12.827% 16471400 12.827% +ST_MEM_PF 0 0.000% 0 0.000% +ST_MEM_WH 0 0.000% 0 0.000% +ST_MEM_EVICT 0 0.000% 0 0.000% + 128408890 100.000% 128408890 100.000% + 0.48 0.60 0.48 0.60 + +ST_NOT_MEM_OFFPATH 0 -nan% 0 -nan% +ST_MEM_LD_OFFPATH 0 -nan% 0 -nan% +ST_MEM_ST_OFFPATH 0 -nan% 0 -nan% +ST_MEM_PF_OFFPATH 0 -nan% 0 -nan% +ST_MEM_WH_OFFPATH 0 -nan% 0 -nan% +ST_MEM_EVIC_OFFPATHT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ST_OP_ONPATH 128408890 128408890 + +ST_OP_OFFPATH 0 0 + +ST_FAKE_OP_OFFPATH 0 -nan% 0 -nan% +ST_NOT_FAKE_OP_OFFPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ST_FAKE_REASON_NOT_FAKE 0 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@@ -0,0 +1,3416 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 40827371 Instructions: 100000000 IPC: 2.44934 + +ICACHE_MISS 13867 0.045% 13867 0.045% +ICACHE_HIT 31098999 99.955% 31098999 99.955% + 31112866 100.000% 31112866 100.000% + 1.00 1.00 1.00 1.00 + +ICACHE_MISS_ONPATH 13867 100.000% 13867 100.000% +ICACHE_MISS_OFFPATH 0 0.000% 0 0.000% + 13867 100.000% 13867 100.000% + 0.00 0.00 0.00 0.00 + +ICACHE_HIT_ONPATH 31098999 100.000% 31098999 100.000% +ICACHE_HIT_OFFPATH 0 0.000% 0 0.000% + 31098999 100.000% 31098999 100.000% + 0.00 0.00 0.00 0.00 + +ICACHE_HIT_ONPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +ICACHE_HIT_ONPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ICACHE_HIT_OFFPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +ICACHE_HIT_OFFPATH_SAT_BY_ONPATH 0 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+ +POWER_L1DIREC_READ_ACCESS 0 0 + +POWER_L1DIREC_WRITE_ACCESS 0 0 + +POWER_L1DIREC_READ_MISS 0 0 + +POWER_L1DIREC_WRITE_MISS 0 0 + +POWER_L2DIREC_READ_ACCESS 0 0 + +POWER_L2DIREC_WRITE_ACCESS 0 0 + +POWER_L2DIREC_READ_MISS 0 0 + +POWER_L2DIREC_WRITE_MISS 0 0 + +POWER_MEMORY_CTRL_ACCESS 1782 1782 + +POWER_MEMORY_CTRL_READ 1782 1782 + +POWER_MEMORY_CTRL_WRITE 0 0 + +POWER_OP 128408799 128408799 + +POWER_INT_OP 127182594 127182594 + +POWER_FP_OP 1398 1398 + +POWER_LD_OP 28723467 28723467 + +POWER_ST_OP 16471382 16471382 + +POWER_BRANCH_MISPREDICT 865837 865837 + +POWER_COMMITTED_OP 128408799 128408799 + +POWER_COMMITTED_INT_OP 127182594 127182594 + +POWER_COMMITTED_FP_OP 1226205 1226205 + +POWER_BRANCH_OP 17257115 17257115 + +POWER_DRAM_PRECHARGE 103 103 + +POWER_DRAM_ACTIVATE 205 205 + +POWER_DRAM_READ 1782 1782 + +POWER_DRAM_WRITE 0 0 + +POWER_STATS_END 0 0 + +ENERGY 0.000000 0.000000 + +ENERGY_CORE 0.000000 0.000000 + +ENERGY_UNCORE 0.000000 0.000000 + +ENERGY_MEMORY 0.000000 0.000000 + +ENERGY_OTHER 0.000000 0.000000 + +ENERGY_CORE_STATIC 0.000000 0.000000 + +ENERGY_CORE_DYNAMIC 0.000000 0.000000 + +ENERGY_UNCORE_STATIC 0.000000 0.000000 + +ENERGY_UNCORE_DYNAMIC 0.000000 0.000000 + +ENERGY_MEMORY_STATIC 0.000000 0.000000 + +ENERGY_MEMORY_DYNAMIC 0.000000 0.000000 + +ENERGY_OTHER_STATIC 0.000000 0.000000 + +ENERGY_OTHER_DYNAMIC 0.000000 0.000000 + +TIME 0.000000 0.000000 + +ENERGY_STATS_END 0 0 + + + diff --git a/labs/LAB5/runs/exchange2-sms0/pref.stat.0.out b/labs/LAB5/runs/exchange2-sms0/pref.stat.0.out new file mode 100644 index 00000000..eb2fe3d4 --- /dev/null +++ b/labs/LAB5/runs/exchange2-sms0/pref.stat.0.out @@ -0,0 +1,208 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 40827371 Instructions: 100000000 IPC: 2.44934 + +PREF_DL0REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UMLC_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UL1REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_DL0REQ_QUEUE_FULL 0 0 + +PREF_UMLC_REQ_QUEUE_FULL 0 0 + +PREF_UL1REQ_QUEUE_FULL 0 0 + +PREF_DC_HIT_NOSEND 0 0 + +PREF_WBQDC_HIT_NOSEND 0 0 + +PREF_MLCQ_STALL 0 0 + +PREF_L1Q_STALL 0 0 + +PREF_UMLC_REQ_SEND_QUEUE_STALL 0 0 + +PREF_UL1REQ_SEND_QUEUE_STALL 0 0 + +PREF_UMLC_REQ_QUEUE_SENTREQ 0 0 + +PREF_UL1REQ_QUEUE_SENTREQ 225 225 + +PREF_NEWREQ_MATCHED 7 7 + +PREF_UMLC_REQ_QUEUE_MATCHED_REQ 0 0 + +PREF_UL1REQ_QUEUE_MATCHED_REQ 27 27 + +PREF_DL0REQ_QUEUE_MATCHED_REQ 0 0 + +L1_PREF_HIT 121 121 + +L1_PREF_UNIQUE_HIT 121 121 + +L1_PREF_LATE 2 2 + +L1_LATE_PREF_CYCLES 80 80 + +L1_LATE_PREF_CYCLES_DIST_0 2 100.000% 2 100.000% +L1_LATE_PREF_CYCLES_DIST_100 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_200 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_300 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_400 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_500 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_600 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_700 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_800 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_900 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1000 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1100 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1200 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1300 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1400 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1500 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1600 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1700 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1800 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1900 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_2000 0 0.000% 0 0.000% + 2 100.000% 2 100.000% + 0.00 0.00 0.00 0.00 + +MLC_PREF_HIT 0 0 + +MLC_PREF_UNIQUE_HIT 0 0 + +MLC_PREF_LATE 0 0 + +PREF_HYBRID_SEL_0 0 -nan% 0 -nan% +PREF_HYBRID_SEL_1 0 -nan% 0 -nan% +PREF_HYBRID_SEL_2 0 -nan% 0 -nan% +PREF_HYBRID_SEL_3 0 -nan% 0 -nan% +PREF_HYBRID_SEL_4 0 -nan% 0 -nan% +PREF_HYBRID_SEL_5 0 -nan% 0 -nan% +PREF_HYBRID_SEL_6 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_DISTANCE_1 0 -nan% 0 -nan% +PREF_DISTANCE_2 0 -nan% 0 -nan% +PREF_DISTANCE_3 0 -nan% 0 -nan% +PREF_DISTANCE_4 0 -nan% 0 -nan% +PREF_DISTANCE_5 0 -nan% 0 -nan% +PREF_DISTANCE_6 0 -nan% 0 -nan% +PREF_DISTANCE_7 0 -nan% 0 -nan% +PREF_DISTANCE_8 0 -nan% 0 -nan% +PREF_DISTANCE_9 0 -nan% 0 -nan% +PREF_DISTANCE_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_REPL_MRU 0 -nan% 0 -nan% +PREF_REPL_MID 0 -nan% 0 -nan% +PREF_REPL_LOWQTR 0 -nan% 0 -nan% +PREF_REPL_LRU 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_REPL_MOVEDOWN 0 -nan% 0 -nan% +PREF_REPL_MOVEUP 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_COV_1 0 -nan% 0 -nan% +PREF_COV_2 0 -nan% 0 -nan% +PREF_COV_3 0 -nan% 0 -nan% +PREF_COV_4 0 -nan% 0 -nan% +PREF_COV_5 0 -nan% 0 -nan% +PREF_COV_6 0 -nan% 0 -nan% +PREF_COV_7 0 -nan% 0 -nan% +PREF_COV_8 0 -nan% 0 -nan% +PREF_COV_9 0 -nan% 0 -nan% +PREF_COV_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_POL_1 0 -nan% 0 -nan% +PREF_POL_2 0 -nan% 0 -nan% +PREF_POL_3 0 -nan% 0 -nan% +PREF_POL_4 0 -nan% 0 -nan% +PREF_POL_5 0 -nan% 0 -nan% +PREF_POL_6 0 -nan% 0 -nan% +PREF_POL_7 0 -nan% 0 -nan% +PREF_POL_8 0 -nan% 0 -nan% +PREF_POL_9 0 -nan% 0 -nan% +PREF_POL_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_ACC_1 0 -nan% 0 -nan% +PREF_ACC_2 0 -nan% 0 -nan% +PREF_ACC_3 0 -nan% 0 -nan% +PREF_ACC_4 0 -nan% 0 -nan% +PREF_ACC_5 0 -nan% 0 -nan% +PREF_ACC_6 0 -nan% 0 -nan% +PREF_ACC_7 0 -nan% 0 -nan% +PREF_ACC_8 0 -nan% 0 -nan% +PREF_ACC_9 0 -nan% 0 -nan% +PREF_ACC_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_TIMELY_1 0 -nan% 0 -nan% +PREF_TIMELY_2 0 -nan% 0 -nan% +PREF_TIMELY_3 0 -nan% 0 -nan% +PREF_TIMELY_4 0 -nan% 0 -nan% +PREF_TIMELY_5 0 -nan% 0 -nan% +PREF_TIMELY_6 0 -nan% 0 -nan% +PREF_TIMELY_7 0 -nan% 0 -nan% +PREF_TIMELY_8 0 -nan% 0 -nan% +PREF_TIMELY_9 0 -nan% 0 -nan% +PREF_TIMELY_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_UNUSED_EVICT 0 0 + +PREF_REGION_SENT 0 0 + +PREF_REGION_USEFUL 0 0 + +PREF_REGION_EVICT 0 0 + +PREF_PFPOL 0 0 + +PREF_PHASE_NEWPHASE_DET 0 0 + +PREF_PHASE_NEWPHASE_NOTVALID 0 0 + +PREF_PHASE_SENTPREF 0 0 + +PREF_PHASE_OVERWRITE_PAGE 0 0 + +PREF_UPDATE_COUNT 0 0 + +PREF_ACC1_HT_HP 0 -nan% 0 -nan% +PREF_ACC1_HT_LP 0 -nan% 0 -nan% +PREF_ACC1_LT_HP 0 -nan% 0 -nan% +PREF_ACC1_LT_LP 0 -nan% 0 -nan% +PREF_ACC2_HT_HP 0 -nan% 0 -nan% +PREF_ACC2_HT_LP 0 -nan% 0 -nan% +PREF_ACC2_LT_HP 0 -nan% 0 -nan% +PREF_ACC2_LT_LP 0 -nan% 0 -nan% +PREF_ACC3_HT_HP 0 -nan% 0 -nan% +PREF_ACC3_HT_LP 0 -nan% 0 -nan% +PREF_ACC3_LT_HP 0 -nan% 0 -nan% +PREF_ACC3_LT_LP 0 -nan% 0 -nan% +PREF_ACC4_HT_HP 0 -nan% 0 -nan% +PREF_ACC4_HT_LP 0 -nan% 0 -nan% +PREF_ACC4_LT_HP 0 -nan% 0 -nan% +PREF_ACC4_LT_LP 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + + + diff --git a/labs/LAB5/runs/exchange2-sms0/ramulator.stat.out b/labs/LAB5/runs/exchange2-sms0/ramulator.stat.out new file mode 100644 index 00000000..f4056969 --- /dev/null +++ b/labs/LAB5/runs/exchange2-sms0/ramulator.stat.out @@ -0,0 +1,150 @@ + ramulator.active_cycles_0 35872 # Total active cycles for level _0 + ramulator.busy_cycles_0 35872 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0 + ramulator.serving_requests_0 39841 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.average_serving_requests_0 0.002602 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.active_cycles_0_0 35872 # Total active cycles for level _0_0 + ramulator.busy_cycles_0_0 722572 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0 + ramulator.serving_requests_0_0 39841 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.average_serving_requests_0_0 0.002602 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.active_cycles_0_0_0 9332 # Total active cycles for level _0_0_0 + ramulator.busy_cycles_0_0_0 9332 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0 + ramulator.serving_requests_0_0_0 9436 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 +ramulator.average_serving_requests_0_0_0 0.000616 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 + ramulator.active_cycles_0_0_0_0 188 # Total active cycles for level _0_0_0_0 + ramulator.busy_cycles_0_0_0_0 188 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_0 + ramulator.serving_requests_0_0_0_0 188 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 +ramulator.average_serving_requests_0_0_0_0 0.000012 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 + ramulator.active_cycles_0_0_0_1 2560 # Total active cycles for level _0_0_0_1 + ramulator.busy_cycles_0_0_0_1 2560 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_1 + ramulator.serving_requests_0_0_0_1 2560 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 +ramulator.average_serving_requests_0_0_0_1 0.000167 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 + ramulator.active_cycles_0_0_0_2 4548 # Total active cycles for level _0_0_0_2 + ramulator.busy_cycles_0_0_0_2 4548 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_2 + ramulator.serving_requests_0_0_0_2 4548 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 +ramulator.average_serving_requests_0_0_0_2 0.000297 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 + ramulator.active_cycles_0_0_0_3 2070 # Total active cycles for level _0_0_0_3 + ramulator.busy_cycles_0_0_0_3 2070 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_3 + ramulator.serving_requests_0_0_0_3 2140 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 +ramulator.average_serving_requests_0_0_0_3 0.000140 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 + ramulator.active_cycles_0_0_1 6915 # Total active cycles for level _0_0_1 + ramulator.busy_cycles_0_0_1 6915 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1 + ramulator.serving_requests_0_0_1 7514 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 +ramulator.average_serving_requests_0_0_1 0.000491 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 + ramulator.active_cycles_0_0_1_0 1628 # Total active cycles for level _0_0_1_0 + ramulator.busy_cycles_0_0_1_0 1628 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_0 + ramulator.serving_requests_0_0_1_0 1628 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 +ramulator.average_serving_requests_0_0_1_0 0.000106 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 + ramulator.active_cycles_0_0_1_1 1490 # Total active cycles for level _0_0_1_1 + ramulator.busy_cycles_0_0_1_1 1490 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_1 + ramulator.serving_requests_0_0_1_1 2036 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 +ramulator.average_serving_requests_0_0_1_1 0.000133 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 + ramulator.active_cycles_0_0_1_2 2316 # Total active cycles for level _0_0_1_2 + ramulator.busy_cycles_0_0_1_2 2316 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_2 + ramulator.serving_requests_0_0_1_2 2316 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 +ramulator.average_serving_requests_0_0_1_2 0.000151 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 + ramulator.active_cycles_0_0_1_3 1514 # Total active cycles for level _0_0_1_3 + ramulator.busy_cycles_0_0_1_3 1514 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_3 + ramulator.serving_requests_0_0_1_3 1534 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 +ramulator.average_serving_requests_0_0_1_3 0.000100 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 + ramulator.active_cycles_0_0_2 6886 # Total active cycles for level _0_0_2 + ramulator.busy_cycles_0_0_2 6886 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2 + ramulator.serving_requests_0_0_2 8223 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 +ramulator.average_serving_requests_0_0_2 0.000537 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 + ramulator.active_cycles_0_0_2_0 1442 # Total active cycles for level _0_0_2_0 + ramulator.busy_cycles_0_0_2_0 1442 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_0 + ramulator.serving_requests_0_0_2_0 2079 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 +ramulator.average_serving_requests_0_0_2_0 0.000136 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 + ramulator.active_cycles_0_0_2_1 1390 # Total active cycles for level _0_0_2_1 + ramulator.busy_cycles_0_0_2_1 1390 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_1 + ramulator.serving_requests_0_0_2_1 1390 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 +ramulator.average_serving_requests_0_0_2_1 0.000091 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 + ramulator.active_cycles_0_0_2_2 1264 # Total active cycles for level _0_0_2_2 + ramulator.busy_cycles_0_0_2_2 1264 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_2 + ramulator.serving_requests_0_0_2_2 1264 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 +ramulator.average_serving_requests_0_0_2_2 0.000083 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 + ramulator.active_cycles_0_0_2_3 2818 # Total active cycles for level _0_0_2_3 + ramulator.busy_cycles_0_0_2_3 2818 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_3 + ramulator.serving_requests_0_0_2_3 3490 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 +ramulator.average_serving_requests_0_0_2_3 0.000228 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 + ramulator.active_cycles_0_0_3 14175 # Total active cycles for level _0_0_3 + ramulator.busy_cycles_0_0_3 14175 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3 + ramulator.serving_requests_0_0_3 14668 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 +ramulator.average_serving_requests_0_0_3 0.000958 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 + ramulator.active_cycles_0_0_3_0 5376 # Total active cycles for level _0_0_3_0 + ramulator.busy_cycles_0_0_3_0 5376 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_0 + ramulator.serving_requests_0_0_3_0 5376 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 +ramulator.average_serving_requests_0_0_3_0 0.000351 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 + ramulator.active_cycles_0_0_3_1 3777 # Total active cycles for level _0_0_3_1 + ramulator.busy_cycles_0_0_3_1 3777 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_1 + ramulator.serving_requests_0_0_3_1 4256 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 +ramulator.average_serving_requests_0_0_3_1 0.000278 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 + ramulator.active_cycles_0_0_3_2 4980 # Total active cycles for level _0_0_3_2 + ramulator.busy_cycles_0_0_3_2 4980 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_2 + ramulator.serving_requests_0_0_3_2 4980 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 +ramulator.average_serving_requests_0_0_3_2 0.000325 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 + ramulator.active_cycles_0_0_3_3 42 # Total active cycles for level _0_0_3_3 + ramulator.busy_cycles_0_0_3_3 42 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_3 + ramulator.serving_requests_0_0_3_3 56 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 +ramulator.average_serving_requests_0_0_3_3 0.000004 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 + ramulator.read_transaction_bytes_0 114048 # The total byte of read transaction per channel + ramulator.write_transaction_bytes_0 0 # The total byte of write transaction per channel + ramulator.row_hits_channel_0_core 1577 # Number of row hits per channel per core + ramulator.row_misses_channel_0_core 148 # Number of row misses per channel per core + ramulator.row_conflicts_channel_0_core 57 # Number of row conflicts per channel per core + ramulator.read_row_hits_channel_0_core 1577 # Number of row hits for read requests per channel per core + [0] 1577.0 # +ramulator.read_row_misses_channel_0_core 148 # Number of row misses for read requests per channel per core + [0] 148.0 # +ramulator.read_row_conflicts_channel_0_core 57 # Number of row conflicts for read requests per channel per core + [0] 57.0 # + ramulator.write_row_hits_channel_0_core 0 # Number of row hits for write requests per channel per core + [0] 0.0 # +ramulator.write_row_misses_channel_0_core 0 # Number of row misses for write requests per channel per core + [0] 0.0 # +ramulator.write_row_conflicts_channel_0_core 0 # Number of row conflicts for write requests per channel per core + [0] 0.0 # + ramulator.useless_activates_0_core 0 # Number of useless activations. E.g, ACT -> PRE w/o RD or WR + ramulator.read_latency_avg_0 27.787318 # The average memory latency cycles (in memory time domain) per request for all read requests in this channel + ramulator.read_latency_sum_0 49517 # The memory latency cycles (in memory time domain) sum for all read requests in this channel + ramulator.req_queue_length_avg_0 0.003019 # Average of read and write queue length per memory cycle per channel. + ramulator.req_queue_length_sum_0 46228 # Sum of read and write queue length per memory cycle per channel. + ramulator.read_req_queue_length_avg_0 0.003019 # Read queue length average per memory cycle per channel. + ramulator.read_req_queue_length_sum_0 46228 # Read queue length sum per memory cycle per channel. + ramulator.write_req_queue_length_avg_0 0.000000 # Write queue length average per memory cycle per channel. + ramulator.write_req_queue_length_sum_0 0 # Write queue length sum per memory cycle per channel. + ramulator.record_read_hits 0.0 # record read hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_misses 0.0 # record_read_miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_conflicts 0.0 # record read conflict count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_hits 0.0 # record write hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_misses 0.0 # record write miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_conflicts 0.0 # record write conflict for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.dram_capacity 8589934592 # Number of bytes in simulated DRAM + ramulator.dram_cycles 15310270 # Number of DRAM cycles simulated + ramulator.incoming_requests 1782 # Number of incoming requests to DRAM + ramulator.read_requests 1782 # Number of incoming read requests to DRAM per core + [0] 1782.0 # + ramulator.write_requests 0 # Number of incoming write requests to DRAM per core + [0] 0.0 # + ramulator.ramulator_active_cycles 35872 # The total number of cycles that the DRAM part is active (serving R/W) + ramulator.incoming_requests_per_channel 1782.0 # Number of incoming requests to each DRAM channel + [0] 1782.0 # +ramulator.incoming_read_reqs_per_channel 1782.0 # Number of incoming read requests to each DRAM channel + [0] 1782.0 # + ramulator.physical_page_replacement 0 # The number of times that physical page replacement happens. + ramulator.maximum_bandwidth 19200000000 # The theoretical maximum bandwidth (Bps) + ramulator.in_queue_req_num_sum 46228 # Sum of read/write queue length + ramulator.in_queue_read_req_num_sum 46228 # Sum of read queue length + ramulator.in_queue_write_req_num_sum 0 # Sum of write queue length + ramulator.in_queue_req_num_avg 0.003019 # Average of read/write queue length per memory cycle + ramulator.in_queue_read_req_num_avg 0.003019 # Average of read queue length per memory cycle + ramulator.in_queue_write_req_num_avg 0.000000 # Average of write queue length per memory cycle + ramulator.record_read_requests 0.0 # record read requests for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_requests 0.0 # record write requests for this core when it reaches request limit or to the end + [0] 0.0 # diff --git a/labs/LAB5/runs/exchange2-sms0/run.err b/labs/LAB5/runs/exchange2-sms0/run.err new file mode 100644 index 00000000..e69de29b diff --git a/labs/LAB5/runs/exchange2-sms0/run.out b/labs/LAB5/runs/exchange2-sms0/run.out new file mode 100644 index 00000000..f56a7cf7 --- /dev/null +++ b/labs/LAB5/runs/exchange2-sms0/run.out @@ -0,0 +1,107 @@ +Scarab gitrev: 7ab9e17 +Scarab started at Sun Jun 11 08:08:38 2023 + +Initialized Ramulator. +** Heartbeat: 1% -- { 1000001 } -- 0.00 KIPS (500.00 KIPS) +** Heartbeat: 2% -- { 2000003 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 3% -- { 3000003 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 4% -- { 4000003 } -- 1000.00 KIPS (571.43 KIPS) +** Heartbeat: 5% -- { 5000006 } -- 500.00 KIPS (555.56 KIPS) +** Heartbeat: 6% -- { 6000008 } -- 1000.00 KIPS (600.00 KIPS) +** Heartbeat: 7% -- { 7000009 } -- 500.00 KIPS (583.33 KIPS) +** Heartbeat: 8% -- { 8000009 } -- 500.00 KIPS (571.43 KIPS) +** Heartbeat: 9% -- { 9000013 } -- 1000.00 KIPS (600.00 KIPS) +** Heartbeat: 10% -- { 10000015 } -- 500.00 KIPS (588.24 KIPS) +** Heartbeat: 11% -- { 11000016 } -- 500.00 KIPS (578.95 KIPS) +** Heartbeat: 12% -- { 12000021 } -- 1000.00 KIPS (600.00 KIPS) +** Heartbeat: 13% -- { 13000024 } -- 500.00 KIPS (590.91 KIPS) +** Heartbeat: 14% -- { 14000029 } -- 500.00 KIPS (583.33 KIPS) +** Heartbeat: 15% -- { 15000034 } -- 1000.00 KIPS (600.00 KIPS) +** Heartbeat: 16% -- { 16000037 } -- 500.00 KIPS (592.59 KIPS) +** Heartbeat: 17% -- { 17000037 } -- 1000.00 KIPS (607.14 KIPS) +** Heartbeat: 18% -- { 18000042 } -- 500.00 KIPS (600.00 KIPS) +** Heartbeat: 19% -- { 19000042 } -- 500.00 KIPS (593.75 KIPS) +** Heartbeat: 20% -- { 20000047 } -- 1000.00 KIPS (606.06 KIPS) +** Heartbeat: 21% -- { 21000052 } -- 500.00 KIPS (600.00 KIPS) +** Heartbeat: 22% -- { 22000053 } -- 500.00 KIPS (594.60 KIPS) +** Heartbeat: 23% -- { 23000055 } -- 500.00 KIPS (589.75 KIPS) +** Heartbeat: 24% -- { 24000058 } -- 500.00 KIPS (585.37 KIPS) +** Heartbeat: 25% -- { 25000062 } -- 500.00 KIPS (581.40 KIPS) +** Heartbeat: 26% -- { 26000064 } -- 500.00 KIPS (577.78 KIPS) +** Heartbeat: 27% -- { 27000065 } -- 500.00 KIPS (574.47 KIPS) +** Heartbeat: 28% -- { 28000065 } -- 500.00 KIPS (571.43 KIPS) +** Heartbeat: 29% -- { 29000067 } -- 500.00 KIPS (568.63 KIPS) +** Heartbeat: 30% -- { 30000068 } -- 1000.00 KIPS (576.92 KIPS) +** Heartbeat: 31% -- { 31000073 } -- 500.00 KIPS (574.08 KIPS) +** Heartbeat: 32% -- { 32000074 } -- 500.00 KIPS (571.43 KIPS) +** Heartbeat: 33% -- { 33000079 } -- 500.00 KIPS (568.97 KIPS) +** Heartbeat: 34% -- { 34000079 } -- 500.00 KIPS (566.67 KIPS) +** Heartbeat: 35% -- { 35000081 } -- 500.00 KIPS (564.52 KIPS) +** Heartbeat: 36% -- { 36000082 } -- 500.00 KIPS (562.50 KIPS) +** Heartbeat: 37% -- { 37000087 } -- 500.00 KIPS (560.61 KIPS) +** Heartbeat: 38% -- { 38000089 } -- 1000.00 KIPS (567.17 KIPS) +** Heartbeat: 39% -- { 39000090 } -- 500.00 KIPS (565.22 KIPS) +** Heartbeat: 40% -- { 40000092 } -- 500.00 KIPS (563.38 KIPS) +** Heartbeat: 41% -- { 41000095 } -- 500.00 KIPS (561.65 KIPS) +** Heartbeat: 42% -- { 42000097 } -- 500.00 KIPS (560.00 KIPS) +** Heartbeat: 43% -- { 43000099 } -- 500.00 KIPS (558.44 KIPS) +** Heartbeat: 44% -- { 44000099 } -- 500.00 KIPS (556.96 KIPS) +** Heartbeat: 45% -- { 45000099 } -- 500.00 KIPS (555.56 KIPS) +** Heartbeat: 46% -- { 46000103 } -- 1000.00 KIPS (560.98 KIPS) +** Heartbeat: 47% -- { 47000103 } -- 500.00 KIPS (559.53 KIPS) +** Heartbeat: 48% -- { 48000103 } -- 500.00 KIPS (558.14 KIPS) +** Heartbeat: 49% -- { 49000107 } -- 500.00 KIPS (556.82 KIPS) +** Heartbeat: 50% -- { 50000107 } -- 500.00 KIPS (555.56 KIPS) +** Heartbeat: 51% -- { 51000108 } -- 500.00 KIPS (554.35 KIPS) +** Heartbeat: 52% -- { 52000108 } -- 500.00 KIPS (553.19 KIPS) +** Heartbeat: 53% -- { 53000111 } -- 500.00 KIPS (552.08 KIPS) +** Heartbeat: 54% -- { 54000112 } -- 1000.00 KIPS (556.70 KIPS) +** Heartbeat: 55% -- { 55000117 } -- 500.00 KIPS (555.56 KIPS) +** Heartbeat: 56% -- { 56000119 } -- 500.00 KIPS (554.46 KIPS) +** Heartbeat: 57% -- { 57000122 } -- 500.00 KIPS (553.40 KIPS) +** Heartbeat: 58% -- { 58000125 } -- 500.00 KIPS (552.38 KIPS) +** Heartbeat: 59% -- { 59000125 } -- 500.00 KIPS (551.40 KIPS) +** Heartbeat: 60% -- { 60000128 } -- 500.00 KIPS (550.46 KIPS) +** Heartbeat: 61% -- { 61000128 } -- 500.00 KIPS (549.55 KIPS) +** Heartbeat: 62% -- { 62000130 } -- 1000.00 KIPS (553.57 KIPS) +** Heartbeat: 63% -- { 63000135 } -- 500.00 KIPS (552.63 KIPS) +** Heartbeat: 64% -- { 64000139 } -- 500.00 KIPS (551.73 KIPS) +** Heartbeat: 65% -- { 65000144 } -- 500.00 KIPS (550.85 KIPS) +** Heartbeat: 66% -- { 66000148 } -- 500.00 KIPS (550.00 KIPS) +** Heartbeat: 67% -- { 67000153 } -- 500.00 KIPS (549.18 KIPS) +** Heartbeat: 68% -- { 68000156 } -- 500.00 KIPS (548.39 KIPS) +** Heartbeat: 69% -- { 69000157 } -- 1000.00 KIPS (552.00 KIPS) +** Heartbeat: 70% -- { 70000161 } -- 500.00 KIPS (551.18 KIPS) +** Heartbeat: 71% -- { 71000163 } -- 500.00 KIPS (550.39 KIPS) +** Heartbeat: 72% -- { 72000164 } -- 500.00 KIPS (549.62 KIPS) +** Heartbeat: 73% -- { 73000169 } -- 500.00 KIPS (548.87 KIPS) +** Heartbeat: 74% -- { 74000171 } -- 500.00 KIPS (548.15 KIPS) +** Heartbeat: 75% -- { 75000173 } -- 500.00 KIPS (547.45 KIPS) +** Heartbeat: 76% -- { 76000177 } -- 500.00 KIPS (546.76 KIPS) +** Heartbeat: 77% -- { 77000180 } -- 1000.00 KIPS (550.00 KIPS) +** Heartbeat: 78% -- { 78000183 } -- 500.00 KIPS (549.30 KIPS) +** Heartbeat: 79% -- { 79000186 } -- 500.00 KIPS (548.61 KIPS) +** Heartbeat: 80% -- { 80000188 } -- 500.00 KIPS (547.95 KIPS) +** Heartbeat: 81% -- { 81000188 } -- 500.00 KIPS (547.30 KIPS) +** Heartbeat: 82% -- { 82000189 } -- 500.00 KIPS (546.67 KIPS) +** Heartbeat: 83% -- { 83000190 } -- 500.00 KIPS (546.05 KIPS) +** Heartbeat: 84% -- { 84000194 } -- 500.00 KIPS (545.46 KIPS) +** Heartbeat: 85% -- { 85000195 } -- 1000.00 KIPS (548.39 KIPS) +** Heartbeat: 86% -- { 86000195 } -- 500.00 KIPS (547.77 KIPS) +** Heartbeat: 87% -- { 87000196 } -- 500.00 KIPS (547.17 KIPS) +** Heartbeat: 88% -- { 88000197 } -- 500.00 KIPS (546.59 KIPS) +** Heartbeat: 89% -- { 89000198 } -- 500.00 KIPS (546.01 KIPS) +** Heartbeat: 90% -- { 90000198 } -- 500.00 KIPS (545.46 KIPS) +** Heartbeat: 91% -- { 91000199 } -- 500.00 KIPS (544.91 KIPS) +** Heartbeat: 92% -- { 92000199 } -- 500.00 KIPS (544.38 KIPS) +** Heartbeat: 93% -- { 93000201 } -- 1000.00 KIPS (547.06 KIPS) +** Heartbeat: 94% -- { 94000201 } -- 500.00 KIPS (546.51 KIPS) +** Heartbeat: 95% -- { 95000204 } -- 500.00 KIPS (545.98 KIPS) +** Heartbeat: 96% -- { 96000207 } -- 500.00 KIPS (545.46 KIPS) +** Heartbeat: 97% -- { 97000207 } -- 500.00 KIPS (544.94 KIPS) +** Heartbeat: 98% -- { 98000207 } -- 500.00 KIPS (544.45 KIPS) +** Heartbeat: 99% -- { 99000207 } -- 500.00 KIPS (543.96 KIPS) +** Core 0 Finished: insts:100000000 cycles:40827371 time:12758553437500 -- 2.45 IPC (2.45 IPC) -- N/A KIPS (543.48 KIPS) +done +Scarab finished at Sun Jun 11 08:11:42 2023 + diff --git a/labs/LAB5/runs/exchange2-sms0/stream.stat.0.out b/labs/LAB5/runs/exchange2-sms0/stream.stat.0.out new file mode 100644 index 00000000..5ee40bab --- /dev/null +++ b/labs/LAB5/runs/exchange2-sms0/stream.stat.0.out @@ -0,0 +1,188 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 40827371 Instructions: 100000000 IPC: 2.44934 + +DCACHE_PREF_HIT 0 0 + +IFETCH_WB_FIRST_SCHEDULE 0 -nan% 0 -nan% +PREFETCH_LAST_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_PREF_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_LOW_OP_SCHEDULE 0 -nan% 0 -nan% +DEMAND_LAST_SCHEDULE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +SEND_MISS_REQ_QUEUE 1782 1782 + +L1_DATA_EVICT 0 0 + +STREAM_BUFFER_REQ 0 0 + +PREF_SEND_TO_MEM_REQ 0 -nan% 0 -nan% +PREF_SEND_TO_MEM_REQ_FAIL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +HIT_TRAIN_STREAM 135 62.500% 135 62.500% +MISS_TRAIN_STREAM 81 37.500% 81 37.500% + 216 100.000% 216 100.000% + 0.38 0.45 0.38 0.45 + +STREAM_TRAIN_CREATE 29 29 + +MEM_REQ_MISS_HWP_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_SW_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_IFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DSTORE_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DPRF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_WB_Q 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_BY_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_WB 0 -nan% 0 -nan% +PREF_HIT_BY_PREF 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_WB 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_L1_FILL 0 -nan% 0 -nan% +DEMAND_L1_FILL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TOUCH_L1_REPLACE 0 -nan% 0 -nan% +NO_TOUCH_L1_REPLACE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_REQ_QUE_FULL 0 0 + +STREAM_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +L2HIT_STREAM_PREF_REQ_QUE_FULL 0 0 + +L2HIT_HIT_TRAIN_STREAM 0 -nan% 0 -nan% +L2HIT_MISS_TRAIN_STREAM 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_TRAIN_CREATE 0 0 + +L2HIT_STREAM_BUFFER_REQ 0 0 + +L2HIT_STREAM_PREF_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_STREAM_PREF_DCACHE_INSERT 0 -nan% 0 -nan% +L2HIT_STREAM_L2_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_DCACHE_PORT_FULL 0 0 + +L2HIT_STREAM_PREF_L1_PORT_FULL 0 0 + +L2HIT_TRAIN_HIT_DEMAND 0 -nan% 0 -nan% +L2HIT_TRAIN_MISS_REQ 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_TRAIN_FILTER_MISS 0 -nan% 0 -nan% +L2HIT_TRAIN_FILTER_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_PREF_REQ_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_PREF_REQ_DCACHE_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_L2SEND_Q_FULL 0 -nan% 0 -nan% +L2HIT_L2SEND_Q_ENTER 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_MEM_REQ 0 0 + +REMOVE_REDUNDANT_STREAM_STAT 0 0 + +REPLACE_OLD_STREAM 13 13 + +REQ_SEND_QUEUE_STALL 0 0 + +STREAM_ENTER_RA 0 0 + +CORE_STREAM_LENGTH_0 5 38.462% 5 38.462% +CORE_STREAM_LENGTH_10 2 15.385% 2 15.385% +CORE_STREAM_LENGTH_20 1 7.692% 1 7.692% +CORE_STREAM_LENGTH_30 3 23.077% 3 23.077% +CORE_STREAM_LENGTH_40 0 0.000% 0 0.000% +CORE_STREAM_LENGTH_50 0 0.000% 0 0.000% +CORE_STREAM_LENGTH_60 0 0.000% 0 0.000% +CORE_STREAM_LENGTH_70 1 7.692% 1 7.692% +CORE_STREAM_LENGTH_80 0 0.000% 0 0.000% +CORE_STREAM_LENGTH_90 0 0.000% 0 0.000% +CORE_STREAM_LENGTH_100_P 1 7.692% 1 7.692% + 13 100.000% 13 100.000% + 2.31 2.76 2.31 2.76 + +CORE_CUM_STREAM_LENGTH_0 38 10.053% 38 10.053% +CORE_CUM_STREAM_LENGTH_10 33 8.730% 33 8.730% +CORE_CUM_STREAM_LENGTH_20 23 6.085% 23 6.085% +CORE_CUM_STREAM_LENGTH_30 104 27.513% 104 27.513% +CORE_CUM_STREAM_LENGTH_40 0 0.000% 0 0.000% +CORE_CUM_STREAM_LENGTH_50 0 0.000% 0 0.000% +CORE_CUM_STREAM_LENGTH_60 0 0.000% 0 0.000% +CORE_CUM_STREAM_LENGTH_70 77 20.370% 77 20.370% +CORE_CUM_STREAM_LENGTH_80 0 0.000% 0 0.000% +CORE_CUM_STREAM_LENGTH_90 0 0.000% 0 0.000% +CORE_CUM_STREAM_LENGTH_100_P 103 27.249% 103 27.249% + 378 100.000% 378 100.000% + 5.19 4.22 5.19 4.22 + +CORE_STREAM_TRAIN_HITS_0 8 61.538% 8 61.538% +CORE_STREAM_TRAIN_HITS_10 3 23.077% 3 23.077% +CORE_STREAM_TRAIN_HITS_20 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_30 1 7.692% 1 7.692% +CORE_STREAM_TRAIN_HITS_40 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_50 1 7.692% 1 7.692% +CORE_STREAM_TRAIN_HITS_60 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_70 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_80 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_90 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_100_P 0 0.000% 0 0.000% + 13 100.000% 13 100.000% + 0.85 1.35 0.85 1.35 + +CORE_CUM_STREAM_TRAIN_HITS_0 49 26.203% 49 26.203% +CORE_CUM_STREAM_TRAIN_HITS_10 48 25.668% 48 25.668% +CORE_CUM_STREAM_TRAIN_HITS_20 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_30 36 19.251% 36 19.251% +CORE_CUM_STREAM_TRAIN_HITS_40 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_50 54 28.877% 54 28.877% +CORE_CUM_STREAM_TRAIN_HITS_60 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_70 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_80 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_90 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_100_P 0 0.000% 0 0.000% + 187 100.000% 187 100.000% + 2.28 1.64 2.28 1.64 + +CORE_STREAM_TRAIN_CREATE 29 29 + + + diff --git a/labs/LAB5/runs/exchange2-sms1/PARAMS.in b/labs/LAB5/runs/exchange2-sms1/PARAMS.in new file mode 100644 index 00000000..2593c2b8 --- /dev/null +++ b/labs/LAB5/runs/exchange2-sms1/PARAMS.in @@ -0,0 +1,226 @@ +# File : PARAMS.kaby_lake +# Date : 03/06/19 +# Description : Kaby Lake Configuration +# +# Based on documentation found here: +# https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake + +## Simulation Parameters +--mode full +--model cmp +--sim_limit none + +## Core Parameters + +# Femptoseconds, 3.2GHz, used for energy estimates. +--chip_cycle_time 312500 + + +### Fetch Stage +--fetch_off_path_ops 1 +--fetch_across_cache_lines 1 + +# Will break the packet upon a taken branch. +--fetch_break_on_taken 1 + +# Number of bubble cycles to wait after taken branch. +--fetch_taken_bubble_cycles 0 + + +#### ICache +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 + +### Branch Predictor +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_mech tagescl + + +#### BTB + +# BTB model to use. +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 + +# Allow the BTB to be updated by off path ops. +--btb_off_path_writes 1 + + +#### CRS + +# Enable return stack +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 + +### iBP +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged + # iBTB Model. tc_tagless, tc_tagged, tc_hybrid. +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 + +### Decode Stage +--decode_cycles 5 + + +### Map Stage +--map_cycles 5 + + +### Issue Stage + +# Max number of instructions to be fetched, decoded, renamed, and issued per cycle. +--issue_width 6 + +--rs_fill_width 0 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 + + +### Exec Stage + +### DCache +--dcache_size 32768 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--dcache_assoc 4 +--dcache_line_size 64 + +### Reorder/Retire Stage + +# Max number of instructions to be retired per cycle. +--node_ret_width 6 +--node_table_size 224 + +# Do not keep stores in RSVs on cache misses; TODO: confirm what this knob does +--stores_do_not_block_window 1 + +# TODO: confirm what this knob does +--prefs_do_not_block_window 1 + + +## Uncore + +### Mid-level cache + +# Enable use of a midlevel cache between i/d and L1 +--mlc_present 0 + +### LLC +--l1_size 1048576 +--l1_banks 1 +--l1_cycles 18 +--l1_assoc 8 +--l1_line_size 64 +--l1_interleave_factor 64 + + +### Prefetcher +--pref_framework_on 1 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--pref_shared_queues 0 +--pref_train_on_pref_misses 0 +--pref_oracle_train 0 +--pref_ul1req_queue_overwrite_on_full 1 + +--stream_length 64 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 + +--pref_throttlefb_on=1 +--pref_acc_thresh_1=0.75 +--pref_acc_thresh_2=0.4 +--pref_acc_thresh_3=0.4 +--pref_timely_thresh=0.01 +--pref_polpf_thresh=0.005 +--pref_update_interval=8192 + +--mem_req_buffer_pref_watermark 4 +--promote_to_higher_priority_mem_req_type 1 + +### Memory +--addr_translation random + +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 + +--mem_req_buffer_entries 32 +--mem_l1_fill_queue_entries 32 +--va_page_size_bytes 4096 +--bus_width_in_bytes 8 + +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 + +## Other + + +### Debug +--debug_inst_start 0 +--debug_inst_stop -1 +--debug_cycle_start 0 +--debug_cycle_stop -1 + + +## Stats and Params +--dump_params 1 +--dump_stats 1 +--dump_trace 0 + +#################################### +--set_off_path_confirmed 1 + +--order_beyond_bus 1 + +--mem_ooo_stores 1 +--mem_obey_store_dep 1 diff --git a/labs/LAB5/runs/exchange2-sms1/PARAMS.out b/labs/LAB5/runs/exchange2-sms1/PARAMS.out new file mode 100644 index 00000000..5033cfbc --- /dev/null +++ b/labs/LAB5/runs/exchange2-sms1/PARAMS.out @@ -0,0 +1,908 @@ +--mode full +--model cmp +--frontend memtrace +--inst_limit 100000000 +--sim_limit none +--dump_params 1 +--dump_stats 1 +--dump_trace 0 +--mlc_present 0 +--l1_size 1048576 +--l1_assoc 8 +--l1_line_size 64 +--l1_cycles 18 +--l1_banks 1 +--l1_interleave_factor 64 +--va_page_size_bytes 4096 +--addr_translation random +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 +--dcache_size 32768 +--dcache_assoc 4 +--dcache_line_size 64 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--mem_ooo_stores 1 +--mem_obey_store_dep 1 +--mem_req_buffer_entries 32 +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 +--promote_to_higher_priority_mem_req_type 1 +--mem_req_buffer_pref_watermark 4 +--mem_l1_fill_queue_entries 32 +--order_beyond_bus 1 +--set_off_path_confirmed 1 +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--bus_width_in_bytes 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 +--chip_cycle_time 312500 +--issue_width 6 +--rs_fill_width 0 +--node_table_size 224 +--node_ret_width 6 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 +--decode_cycles 5 +--map_cycles 5 +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--fetch_across_cache_lines 1 +--fetch_off_path_ops 0 +--fetch_break_on_taken 1 +--fetch_taken_bubble_cycles 0 +--stores_do_not_block_window 1 +--prefs_do_not_block_window 1 +--cbp_trace_r0 /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir/trace/drmemtrace.exchange2.553888.0626.trace.gz +--memtrace_modules_log /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir/raw +--debug_cycle_start 0 +--debug_cycle_stop -1 +--debug_inst_start 0 +--debug_inst_stop -1 +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--bp_mech tagescl +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 +--btb_off_path_writes 1 +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_length 64 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 +--pref_framework_on 1 +--pref_shared_queues 0 +--pref_ul1req_queue_overwrite_on_full 1 +--pref_train_on_pref_misses 0 +--pref_oracle_train_on 0 +--pref_throttlefb_on 1 +--pref_acc_thresh_1 0.75 +--pref_acc_thresh_2 0.4 +--pref_acc_thresh_3 0.4 +--pref_update_interval 8192 +--pref_timely_thresh 0.01 +--pref_polpf_thresh 0.005 +--pref_sms_on 1 +1 1 1 1 1 1 1 + +--- Cut out everything below to use this file as PARAMS.in --- + +Parameter status at compile time and values supplied on the command line: + +SIM_MODE 0 full +SIM_MODEL 0 cmp +FRONTEND FE_PIN_EXEC_DRIVEN memtrace +INST_LIMIT NULL 100000000 +SIM_LIMIT "none" none +FORWARD_PROGRESS_LIMIT 100000000 +FORWARD_PROGRESS_INTERVAL 10000 +FAST_FORWARD 0 +FAST_FORWARD_UNTIL_ADDR 0 +FAST_FORWARD_TRACE_INS 0 +WARMUP 0 +HEARTBEAT_INTERVAL 1000000 +NUM_HEARTBEATS 0 +FILE_TAG "" +OUTPUT_DIR "." +STATUS_FILE NULL +BINDIR NULL +DUMP_PARAMS TRUE 1 +DUMP_STATS TRUE 1 +DUMP_TRACE FALSE 0 +CLEAR_STATS "never" +STATS_TO_TRACE NULL +STAT_TRACE_FILE "stats.trace" +STAT_TRACE_INTERVAL "i:100000" +PIPEVIEW FALSE +PIPEVIEW_FILE "pipeview" +MEMVIEW FALSE +MEMVIEW_FILE "memview.out" +MEMVIEW_START "never" +INST_HASH_TABLE_SIZE 500021 const +STDOUT_FILE NULL +STDERR_FILE NULL +PIN_EXEC_DRIVEN_FE_SOCKET "./pin_exec_driven_fe_socket.temp" +PRINT_PID FALSE +USE_UNSURE_FREE_LISTS FALSE +OPTIMIZER2_MAX_NUM_SLAVES 64 +OPTIMIZER2_PERFECT_MEMORYLESS FALSE +EXIT_COND 0 +ENABLE_SWPRF FALSE +MLC_PRESENT FALSE 0 +MLC_SIZE (512 * 1024) +MLC_ASSOC 4 +MLC_LINE_SIZE 64 +MLC_CYCLES 12 +PERFECT_MLC FALSE +MLC_READ_PORTS 1 +MLC_WRITE_PORTS 1 +MLC_BANKS 8 +MLC_INTERLEAVE_FACTOR 64 +MLC_CACHE_REPL_POLICY 0 +MLC_WRITE_THROUGH FALSE +PREFETCH_UPDATE_LRU_MLC TRUE +FORCE_L1_MISS FALSE +L1_SIZE (4 * 1024 * 1024) 1048576 +L1_ASSOC 8 8 +L1_LINE_SIZE 64 64 +L1_CYCLES 24 18 +PERFECT_L1 FALSE +PRIVATE_L1 FALSE +L1_READ_PORTS 1 +L1_WRITE_PORTS 1 +L1_BANKS 8 1 +L1_INTERLEAVE_FACTOR 64 64 +L1_CACHE_REPL_POLICY 0 +L1_WRITE_THROUGH FALSE +L1_IGNORE_WB FALSE +L1_USE_CORE_FREQ FALSE +MARK_L1_MISSES TRUE +PREFETCH_UPDATE_LRU_L1 TRUE +MEMORY_RANDOM_ADDR FALSE +VA_PAGE_SIZE_BYTES 4096 4096 +NUM_ADDR_NON_SIGN_EXTEND_BITS 48 +ADDR_TRANSLATION 0 random +CONSTANT_MEMORY_LATENCY FALSE +MEMORY_CYCLES 100 +STALL_MEM_REQS_ONLY FALSE +ICACHE_SIZE (64 * 1024) 32768 +ICACHE_ASSOC 4 4 +ICACHE_LINE_SIZE 64 64 +PERFECT_ICACHE FALSE +ICACHE_READ_PORTS 2 +ICACHE_WRITE_PORTS 1 +ICACHE_BANKS 8 +ICACHE_REPL 0 +DCACHE_SIZE (64 * 1024) 32768 +DCACHE_ASSOC 1 4 +DCACHE_LINE_SIZE 64 64 +DCACHE_CYCLES 2 +PERFECT_DCACHE FALSE +DCACHE_READ_PORTS 8 2 +DCACHE_WRITE_PORTS 1 1 +DCACHE_BANKS 1 1 +DCACHE_REPL 0 +DCACHE_REPL_PREF_THRESH 1 +MEM_OOO_STORES TRUE 1 +MEM_OBEY_STORE_DEP TRUE 1 +PREF_INSERT_LRU FALSE +PREF_INSERT_MIDDLE FALSE +PREF_INSERT_LOWQTR FALSE +PREF_INSERT_DYNACC FALSE +MEM_REQ_BUFFER_ENTRIES 32 32 +PRIVATE_MSHR_ON TRUE +MEM_PRIORITY_IFETCH 0 0 +MEM_PRIORITY_DFETCH 0 1 +MEM_PRIORITY_DSTORE 0 2 +MEM_PRIORITY_IPRF 9 3 +MEM_PRIORITY_DPRF 10 4 +MEM_PRIORITY_WB 0 5 +MEM_PRIORITY_WB_NODIRTY 0 5 +PROMOTE_TO_HIGHER_PRIORITY_MEM_REQ_TYPE FALSE 1 +MEM_REQ_BUFFER_PREF_WATERMARK 0 4 +MEM_REQ_BUFFER_WB_VALVE 2 +MEM_L1_FILL_QUEUE_ENTRIES 32 32 +MEM_BUS_OUT_QUEUE_PARTITION_ENABLE FALSE +MEM_MEM_QUEUE_PARTITION_ENABLE FALSE +MEM_BUS_OUT_QUEUE_AS_FIFO TRUE +OLDEST_FIRST_TO_MEM_QUEUE TRUE +ROUND_ROBIN_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE_TH 0 +L1_CYCLE_TIME 312500 +MLCQ_TO_L1Q_TRANSFER_LATENCY 1 +L1Q_TO_FSB_TRANSFER_LATENCY 1 +PRIORITIZE_PREFETCHES_WITH_UNIQUE FALSE +KICKOUT_PREFETCHES FALSE +KICKOUT_LOOK_FOR_OLDEST_FIRST FALSE +KICKOUT_OLDEST_PREFETCH FALSE +KICKOUT_OLDEST_PREFETCH_WITHIN_BANK FALSE +ORDER_BEYOND_BUS FALSE 1 +ALL_FIFO_QUEUES FALSE +QUEUE_MLC_SIZE 0 +QUEUE_L1_SIZE 0 +QUEUE_BUS_OUT_SIZE 0 +QUEUE_CORE_FILL_SIZE 0 +ALLOW_TYPE_MATCHES FALSE +STREAM_PREFETCH_ON FALSE +DC_PREF_CACHE_ENABLE FALSE +DC_PREF_CACHE_CYCLE 0 +PREF_INSERT_DCACHE_IMM TRUE +DC_PREF_CACHE_SIZE (64 * 1024) +DC_PREF_CACHE_ASSOC 4 +DC_PREF_ONLY_L1HIT FALSE +PREF_CACHE_USE_RDY_CYCLE FALSE +IC_PREF_CACHE_ENABLE FALSE +IC_PREF_CACHE_SIZE (64 * 1024) +IC_PREF_CACHE_ASSOC 4 +L1_PREF_CACHE_ENABLE FALSE +L1_PREF_CACHE_SIZE (1024 * 1024) +L1_PREF_CACHE_ASSOC 8 +SET_OFF_PATH_CONFIRMED FALSE 1 +USE_CONFIRMED_OFF FALSE +PREFCACHE_MOVE_OFFPATH FALSE +CACHE_STAT_ENABLE FALSE +PREF_DCACHE_HIT_FILL_L1 TRUE +PREF_ICACHE_HIT_FILL_L1 TRUE +CRITICAL_ACCESS_PLOT_ENABLE FALSE +CRITICAL_ACCESS_PLOT_FILE "critical_access_plot.dat" +ROUND_ROBIN_TO_L1 FALSE +PREF_I_TOGETHER FALSE +ONE_MORE_CACHE_LINE_ENABLE FALSE +L1_STATIC_PARTITION_ENABLE 0 +L1_STATIC_PARTITION NULL +L1_DYNAMIC_PARTITION_ENABLE FALSE +L1_DYNAMIC_PARTITION_POLICY 0 +PARTITION_UMON_DSS_PREF_ENABLE FALSE +L1_CACHE_HIT_POSITION_COLLECT FALSE +L1_PART_ON FALSE +L1_PART_TRIGGER "c:1000000" +L1_PART_START "t:0" +L1_PART_WARMUP FALSE +L1_PART_SHADOW_WARMUP FALSE +L1_PART_METRIC 0 +L1_PART_SEARCH 0 +L1_PART_USE_STALLING TRUE +L1_PART_FILL_DELAY 0 +L1_SHADOW_TAGS_MODULO 1 +HIER_MSHR_ON FALSE +PERF_PRED_ENABLE FALSE +PERF_PRED_MECH PERF_PRED_CP +PERF_PRED_REQ_LATENCY_MECH PERF_PRED_REQ_LATENCY_MECH_REQ_LATENCY +PERF_PRED_COUNT_ALL FALSE +PERF_PRED_COUNT_INST_MISSES TRUE +PERF_PRED_COUNT_PREFETCHES FALSE +PERF_PRED_COUNT_OFFPATH_REQS FALSE +PERF_PRED_COUNT_BW_REQS TRUE +PERF_PRED_UPDATE_MEM_REQ_TYPE FALSE +PERF_PRED_SLACK_PERIOD_SIZE 32 +PERF_PRED_REQS_FINISH_AT_FILL FALSE +PERF_PRED_MEM_UTIL_VIA_BUS_BW FALSE +PERF_PRED_CHIP_UTIL_VIA_MEM_STALL FALSE +DUMB_MODEL_AVG_REQ_DISTANCE 100 +DUMB_MODEL_RANDOMIZE_DISTANCE FALSE +DUMB_MODEL_AVG_REQ_DISTANCE_PER_CORE NULL +DUMB_MODEL_AVG_ROW_HITS 1 +DUMB_MODEL_AVG_ROW_HITS_PER_CORE NULL +DUMB_MODEL_MLP 1 +DUMB_MODEL_MLP_PER_CORE NULL +RAMULATOR_STANDARD "DDR4" DDR4 +RAMULATOR_SPEED "DDR4_2400R" DDR4_2400R +RAMULATOR_ORG "DDR4_8Gb_x8" DDR4_8Gb_x8 +RAMULATOR_CHANNELS 1 1 +RAMULATOR_RANKS 1 1 +RAMULATOR_BANKGROUPS 4 4 +RAMULATOR_BANKS 4 4 +RAMULATOR_CHIP_WIDTH 8 8 +BUS_WIDTH_IN_BYTES 8 8 +RAMULATOR_ROWS 65536 65536 +RAMULATOR_COLS 1024 1024 +RAMULATOR_SCHEDULING_POLICY "FRFCFS_Cap" FRFCFS_Cap +RAMULATOR_READQ_ENTRIES 32 32 +RAMULATOR_WRITEQ_ENTRIES 32 32 +RAMULATOR_REC_CMD_TRACE "off" FALSE +RAMULATOR_PRINT_CMD_TRACE "off" FALSE +RAMULATOR_USE_REST_OF_ADDR_AS_ROW_ADDR "on" +RAMULATOR_TCK 833333 833333 +RAMULATOR_TCL 16 16 +RAMULATOR_TCCD 6 6 +RAMULATOR_TCCDS 4 4 +RAMULATOR_TCCDL 6 6 +RAMULATOR_TCWL 12 12 +RAMULATOR_TBL 4 4 +RAMULATOR_TWTR 9 9 +RAMULATOR_TWTRS 3 3 +RAMULATOR_TWTRL 9 9 +RAMULATOR_TRP 16 16 +RAMULATOR_TRPpb 16 16 +RAMULATOR_TRPab 16 16 +RAMULATOR_TRCD 16 16 +RAMULATOR_TRCDR 16 16 +RAMULATOR_TRCDW 16 16 +RAMULATOR_TRAS 39 39 +DRAM_TECH_IN_NM 32 32 +DVFS_ON FALSE +DVFS_METRIC DVFS_METRIC_NUM_ELEMS +DVFS_CONFIGS NULL +DVFS_CONFIG_FILE NULL +DVFS_START "t:0" +DVFS_PERIOD "t:312500000000" +DVFS_LOG TRUE +DVFS_INDIVIDUAL_CORES FALSE +DVFS_CHIP_LEVEL FALSE +DVFS_STATIC NULL +DVFS_FORCE_CONFIG NULL +DVFS_REPLAY_CONFIG_TRACE NULL +DVFS_USE_ORACLE FALSE +DVFS_USE_BW_SHARING FALSE +DVFS_USE_DRAM_SHARING FALSE +DVFS_USE_STALL_TIME FALSE +DVFS_DRAM_SHARING_SOLVER_BIN NULL +DVFS_DRAM_SHARING_SOLVER_STRICT TRUE +DVFS_BW_SHARING_BUS_UTIL_THRESH 0.95 +DVFS_BW_SHARING_MAX_REQS 28.0 +DVFS_BW_SHARING_MAX_RW_COST 0.25 +DVFS_BW_SHARING_NO_PREF_STALL TRUE +DVFS_BW_SHARING_CRIT_STATS TRUE +DVFS_COUNT_L1_ACCESS_STALL FALSE +NUM_CORES 1 +CHIP_CYCLE_TIME 312500 312500 +CORE_0_CYCLE_TIME 312500 +CORE_1_CYCLE_TIME 312500 +CORE_2_CYCLE_TIME 312500 +CORE_3_CYCLE_TIME 312500 +CORE_4_CYCLE_TIME 312500 +CORE_5_CYCLE_TIME 312500 +CORE_6_CYCLE_TIME 312500 +CORE_7_CYCLE_TIME 312500 +CORE_8_CYCLE_TIME 312500 +CORE_9_CYCLE_TIME 312500 +CORE_10_CYCLE_TIME 312500 +CORE_11_CYCLE_TIME 312500 +CORE_12_CYCLE_TIME 312500 +CORE_13_CYCLE_TIME 312500 +CORE_14_CYCLE_TIME 312500 +CORE_15_CYCLE_TIME 312500 +CORE_16_CYCLE_TIME 312500 +CORE_17_CYCLE_TIME 312500 +CORE_18_CYCLE_TIME 312500 +CORE_19_CYCLE_TIME 312500 +CORE_20_CYCLE_TIME 312500 +CORE_21_CYCLE_TIME 312500 +CORE_22_CYCLE_TIME 312500 +CORE_23_CYCLE_TIME 312500 +CORE_24_CYCLE_TIME 312500 +CORE_25_CYCLE_TIME 312500 +CORE_26_CYCLE_TIME 312500 +CORE_27_CYCLE_TIME 312500 +CORE_28_CYCLE_TIME 312500 +CORE_29_CYCLE_TIME 312500 +CORE_30_CYCLE_TIME 312500 +CORE_31_CYCLE_TIME 312500 +CORE_32_CYCLE_TIME 312500 +CORE_33_CYCLE_TIME 312500 +CORE_34_CYCLE_TIME 312500 +CORE_35_CYCLE_TIME 312500 +CORE_36_CYCLE_TIME 312500 +CORE_37_CYCLE_TIME 312500 +CORE_38_CYCLE_TIME 312500 +CORE_39_CYCLE_TIME 312500 +CORE_40_CYCLE_TIME 312500 +CORE_41_CYCLE_TIME 312500 +CORE_42_CYCLE_TIME 312500 +CORE_43_CYCLE_TIME 312500 +CORE_44_CYCLE_TIME 312500 +CORE_45_CYCLE_TIME 312500 +CORE_46_CYCLE_TIME 312500 +CORE_47_CYCLE_TIME 312500 +CORE_48_CYCLE_TIME 312500 +CORE_49_CYCLE_TIME 312500 +CORE_50_CYCLE_TIME 312500 +CORE_51_CYCLE_TIME 312500 +CORE_52_CYCLE_TIME 312500 +CORE_53_CYCLE_TIME 312500 +CORE_54_CYCLE_TIME 312500 +CORE_55_CYCLE_TIME 312500 +CORE_56_CYCLE_TIME 312500 +CORE_57_CYCLE_TIME 312500 +CORE_58_CYCLE_TIME 312500 +CORE_59_CYCLE_TIME 312500 +CORE_60_CYCLE_TIME 312500 +CORE_61_CYCLE_TIME 312500 +CORE_62_CYCLE_TIME 312500 +CORE_63_CYCLE_TIME 312500 +ISSUE_WIDTH 4 6 +RS_FILL_WIDTH 8 0 +NODE_TABLE_SIZE 256 224 +NODE_RET_WIDTH 4 6 +NODE_RETIRE_RATE 10 +RS_SIZES "256" 97 +RS_CONNECTIONS "xF" 0 +FU_TYPES "0, 0, 0, 0" 0 0 0 0 0 0 0 0 +DECODE_CYCLES 1 5 +MAP_CYCLES 1 5 +EXTRA_RECOVERY_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after recovery. +EXTRA_REDIRECT_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after redirect. +EXTRA_CALLSYS_CYCLES 20 const +DIE_ON_CALLSYS FALSE +DIE_ON_RET_STALL_THRESH 0 +DIE_ON_RET_STALL_CORE 0 +DIE_ON_MEM_BLOCK_THRESH 0 +DIE_ON_MEM_BLOCK_CORE 0 +FETCH_ACROSS_CACHE_LINES FALSE 1 +FETCH_OFF_PATH_OPS TRUE 0 +FETCH_BREAK_ON_TAKEN FALSE 1 +FETCH_TAKEN_BUBBLE_CYCLES 0 0 +WP_COLLECT_STATS FALSE +SWITCH_IC_FETCH_ON_RECOVERY TRUE +OP_INV_DELAY 1 +OP_NOP_DELAY 1 +OP_CF_DELAY 1 +OP_MOV_DELAY 1 +OP_CMOV_DELAY 1 +OP_LDA_DELAY 1 +OP_IMEM_DELAY 1 +OP_IADD_DELAY 1 +OP_IMUL_DELAY 3 +OP_IDIV_DELAY -20 +OP_ICMP_DELAY 1 +OP_LOGIC_DELAY 1 +OP_SHIFT_DELAY 1 +OP_FMEM_DELAY 1 +OP_FCVT_DELAY 3 +OP_FADD_DELAY 3 +OP_FMUL_DELAY 5 +OP_FMA_DELAY 5 +OP_FDIV_DELAY -20 +OP_FCMP_DELAY 3 +OP_FCMOV_DELAY 1 +OP_GATHER_DELAY 12 +OP_SCATTER_DELAY 18 +OP_PIPELINED_FAST_DELAY 2 +OP_PIPELINED_MEDIUM_DELAY 5 +OP_PIPELINED_SLOW_DELAY 10 +OP_NOTPIPELINED_MEDIUM_DELAY -5 +OP_NOTPIPELINED_SLOW_DELAY -20 +OP_NOTPIPELINED_VERY_SLOW_DELAY -100 +UNIFORM_OP_DELAY 0 +STALL_ON_WAIT_MEM TRUE +STORES_DO_NOT_BLOCK_WINDOW FALSE 1 +PREFS_DO_NOT_BLOCK_WINDOW FALSE 1 +OBEY_REG_DEP TRUE +OLDEST_FIRST_SCHED FALSE +FIND_EMPTIEST_RS FALSE +TRACK_L1_MISS_DEPS FALSE +CBP_TRACE_R0 NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir/trace/drmemtrace.exchange2.553888.0626.trace.gz +CBP_TRACE_R1 NULL +CBP_TRACE_R2 NULL +CBP_TRACE_R3 NULL +CBP_TRACE_R4 NULL +CBP_TRACE_R5 NULL +CBP_TRACE_R6 NULL +CBP_TRACE_R7 NULL +CBP_TRACE_R8 NULL +CBP_TRACE_R9 NULL +CBP_TRACE_R10 NULL +CBP_TRACE_R11 NULL +CBP_TRACE_R12 NULL +CBP_TRACE_R13 NULL +CBP_TRACE_R14 NULL +CBP_TRACE_R15 NULL +CBP_TRACE_R16 NULL +CBP_TRACE_R17 NULL +CBP_TRACE_R18 NULL +CBP_TRACE_R19 NULL +CBP_TRACE_R20 NULL +CBP_TRACE_R21 NULL +CBP_TRACE_R22 NULL +CBP_TRACE_R23 NULL +CBP_TRACE_R24 NULL +CBP_TRACE_R25 NULL +CBP_TRACE_R26 NULL +CBP_TRACE_R27 NULL +CBP_TRACE_R28 NULL +CBP_TRACE_R29 NULL +CBP_TRACE_R30 NULL +CBP_TRACE_R31 NULL +CBP_TRACE_R32 NULL +CBP_TRACE_R33 NULL +CBP_TRACE_R34 NULL +CBP_TRACE_R35 NULL +CBP_TRACE_R36 NULL +CBP_TRACE_R37 NULL +CBP_TRACE_R38 NULL +CBP_TRACE_R39 NULL +CBP_TRACE_R40 NULL +CBP_TRACE_R41 NULL +CBP_TRACE_R42 NULL +CBP_TRACE_R43 NULL +CBP_TRACE_R44 NULL +CBP_TRACE_R45 NULL +CBP_TRACE_R46 NULL +CBP_TRACE_R47 NULL +CBP_TRACE_R48 NULL +CBP_TRACE_R49 NULL +CBP_TRACE_R50 NULL +CBP_TRACE_R51 NULL +CBP_TRACE_R52 NULL +CBP_TRACE_R53 NULL +CBP_TRACE_R54 NULL +CBP_TRACE_R55 NULL +CBP_TRACE_R56 NULL +CBP_TRACE_R57 NULL +CBP_TRACE_R58 NULL +CBP_TRACE_R59 NULL +CBP_TRACE_R60 NULL +CBP_TRACE_R61 NULL +CBP_TRACE_R62 NULL +CBP_TRACE_R63 NULL +MEMTRACE_MODULES_LOG NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.exchange2.553888.1738.dir/raw +DUMB_CORE_ON FALSE +DUMB_CORE 1 +DEBUG_CYCLE_START 0 0 +DEBUG_CYCLE_STOP 0 -1 +DEBUG_TIME_START 0 +DEBUG_TIME_STOP 0 +DEBUG_INST_START 0 0 +DEBUG_INST_STOP 0 -1 +DEBUG_OP_START 0 +DEBUG_OP_STOP 0 +DEBUG_CACHE_LIB FALSE +DEBUG_HASH_LIB FALSE +DEBUG_LIST_LIB FALSE +DEBUG_PORT_LIB FALSE +DEBUG_BUS_LIB FALSE +DEBUG_OP_POOL FALSE +DEBUG_ORACLE FALSE +DEBUG_FRONTEND FALSE +DEBUG_ADDR_TRANS FALSE +DEBUG_BP FALSE +DEBUG_BP_DIR FALSE +DEBUG_BTB FALSE +DEBUG_CRS FALSE +DEBUG_MAP FALSE +DEBUG_MEMORY FALSE +DEBUG_REPLAY FALSE +DEBUG_FREQ FALSE +DEBUG_MODEL FALSE +DEBUG_THREAD FALSE +DEBUG_ICACHE_STAGE FALSE +DEBUG_DECODE_STAGE FALSE +DEBUG_MAP_STAGE FALSE +DEBUG_NODE_STAGE FALSE +DEBUG_EXEC_STAGE FALSE +DEBUG_DCACHE_STAGE FALSE +DEBUG_RETIRED_UOPS FALSE +DEBUG_EXC_INSERTS FALSE +DEBUG_BP_CONF FALSE +DEBUG_ONPATH_CONF FALSE +DEBUG_STREAM FALSE +DEBUG_STREAM_MEM FALSE +DEBUG_WAY FALSE +DEBUG_L2MARKV FALSE +DEBUG_L2L1PREF FALSE +DEBUG_PERF_PRED FALSE +DEBUG_POWER_UTILS FALSE +DEBUG_DVFS FALSE +DEBUG_TRACE_READ FALSE +DEBUG_INST_FIELDS FALSE +DEBUG_OP_FIELDS FALSE +DEBUG_PIN_EXEC_DRIVEN FALSE +DEBUG_CACHE_PART FALSE +DEBUG_OPTIMIZER2 FALSE +DEBUG_PREF FALSE +PERFECT_BP FALSE +PERFECT_BTB FALSE +PERFECT_IBP FALSE +PERFECT_CRS FALSE +PERFECT_CBR_BTB FALSE +PERFECT_NT_BTB FALSE +CFS_PER_CYCLE 3 6 # Number of branches that can be predicted in a single cycle +UPDATE_BP_OFF_PATH FALSE 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +BP_UPDATE_AT_RETIRE FALSE 0 # Update the BP at retire. If false, update at the end of exec. +BP_MECH 0 tagescl +LATE_BP_MECH NUM_BP +LATE_BP_LATENCY 5 +HIST_LENGTH 16 +PHT_CTR_BITS 2 const +BHT_ENTRIES (4 * 1024) +BHT_ASSOC 4 +HYBRIDS_INDEX_LENGTH 16 +HYBRIDG_HIST_LENGTH 16 +HYBRIDP_HIST_LENGTH 16 +FILTER_INDEX_LENGTH 16 +USE_FILTER FALSE +INF_HYBRIDGP FALSE +BP_HASH_TOS FALSE +IBTB_HASH_TOS FALSE +BTB_MECH 0 generic +BTB_ENTRIES (4 * 1024) 4096 +BTB_ASSOC 4 4 +BTB_OFF_PATH_WRITES TRUE 1 +ENABLE_CRS TRUE 1 +CRS_ENTRIES 32 32 +CRS_REALISTIC 0 1 +ENABLE_IBP TRUE 1 # Enable the indirect branch predictor +USE_PAT_HIST TRUE +IBTB_MECH 1 tc_tagged +IBTB_HIST_LENGTH 16 +IBTB_OFF_PATH_WRITES TRUE 1 # Allow off path ops to update the ibtb. +TARGETS_IN_HIST 4 +TC_ENTRIES (4 * 1024) 4096 +TC_ASSOC 4 4 +NUM_CORR_BRANCHES 3 +SEL_HIST_BP_ENTRIES 8192 +SEL_HIST_LENGTH 16 +SEL_HIST_DYN_CNT_TH 16 +SEL_HIST_MISPRED_TH 4 +ENABLE_BP_CONF FALSE +CONF_MECH 0 +PERF_BP_CONF_PRED FALSE +BPC_BITS 16 +BPC_MECH 1 +BPC_CTR_RESET TRUE +BPC_CIT_BITS 8 +BPC_CIT_TH 50 +BPC_CTR_BITS 3 +OPC_COUNT_ZEROS FALSE +OPC_COUNT_THRESH 10 +INF_LOOP FALSE +INF_LOOP_BUCKETS 811 +LOOP_ENTRIES (4 * 1024) +LOOP_ASSOC 4 +LOOP_COUNT_MAX 127 +LOOP_REPEAT_MAX 15 +KNOB_PRINT_BRINFO FALSE +BR_MISPRED_FILE NULL +CONF_PERCEPTRON_TH 0 +CONF_PERCEPTRON_CTR_BITS 8 +CONF_PERCEPTRON_ENTRIES 127 +CONF_PERCEPTRON_THRESH_OVRD 0 +CONF_HIST_LENGTH 32 +PERCEPTRON_CONF_USE_CONF FALSE +PERCEPTRON_CONF_TRAIN_HIS FALSE +PERCEPTRON_CONF_TRAIN_CONF FALSE +PERCEPTRON_CONF_TRAIN_OFFSET_CONF FALSE +PERCEPTRON_TRAIN_MISP_FACTOR 1 +PERCEPTRON_TRAIN_CORR_FACTOR 1 +PERCEPTRON_CONF_HIS_BOTH FALSE +PERCEPTRON_CONF_HIS_BOTH_LENGTH 4 +ENABLE_ICACHE_PACKET_BREAKING TRUE +NUM_LOAD_STORE_PER_PACKET 0 +PACKET_BREAK_ON_FUS FALSE +PACKET_BREAK_FU_TYPES "G,G,G,G,G,G,G,G,G,G,G,G" +POWER_INTF_ON FALSE +POWER_INTF_ENABLE_SCALING FALSE +POWER_INTF_EXEC "power/power_intf.py" +POWER_INTF_REF_CHIP_TECH_NM 22 +POWER_INTF_REF_CHIP_FREQ (3.2e9) +POWER_INTF_REF_MEMORY_FREQ (0.8e9) +POWER_OTHER (0.0) +PREF_STREAM_ON FALSE 1 +PREF_STREAM_PER_CORE_ENABLE FALSE 1 +STREAM_BUFFER_N 16 +STREAM_PREFETCH_N 2 4 +STREAM_START_DIS 5 1 +STREAM_LENGTH 16 64 +STREAM_FULL_N 1 +STREAM_TRAIN_LENGTH 16 +STREAM_TRAIN_NUM 1 4 +PREF_ACC_USE_CACHE FALSE +STREAM_STALL_ON_QUEUE_FULL FALSE +PREF_SCHEDULE_NUM 4 +TRAIN_FILTER_SIZE 32 +PREF_REQ_Q_SIZE 64 +STREAM_CREATE_ON_DC_MISS FALSE 0 +STREAM_CREATE_ON_L1_MISS TRUE 1 +STREAM_TRAIN_ON_WRONGPATH TRUE +STREAM_CREATE_ON_WRONGPATH TRUE +STREAM_PREF_INTO_DCACHE FALSE +REMOVE_REDUNDANT_STREAM FALSE +L2HIT_STREAM_SCHEDULE_NUM 4 +PREF_REQ_QUEUE_FILTER_ON FALSE +HW_PREF_HIT_TRAIN_STREAM FALSE +L2HIT_STREAM_BUFFER_N 32 +L2HIT_STREAM_PREFETCH_N 2 +L2HIT_STREAM_START_DIS 2 +L2HIT_STREAM_LENGTH 8 +L2HIT_PREF_REQ_Q_SIZE 128 +L2HIT_L2ACCESS_REQ_Q_SIZE 64 +PREF_STREAM_ACCPERSTREAM FALSE +PREF_ACC_DISTANCE_10 128 +PREF_FRAMEWORK_ON FALSE 1 +PREF_TRACE_ON FALSE +PREF_DL0REQ_QUEUE_SIZE 32 +PREF_UMLC_REQ_QUEUE_SIZE 64 +PREF_UL1REQ_QUEUE_SIZE 128 +PREF_SHARED_QUEUES TRUE 0 +PREF_DL0_MISS_ON TRUE +PREF_DL0_HIT_ON TRUE +PREF_DL0REQ_QUEUE_FILTER_ON TRUE +PREF_UMLC_REQ_QUEUE_FILTER_ON TRUE +PREF_UL1REQ_QUEUE_FILTER_ON TRUE +PREF_DL0REQ_ADD_FILTER_ON TRUE +PREF_UMLC_REQ_ADD_FILTER_ON TRUE +PREF_UL1REQ_ADD_FILTER_ON TRUE +PREF_DL0REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UMLC_REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UL1REQ_QUEUE_OVERWRITE_ON_FULL FALSE 1 +PREF_DL0SCHEDULE_NUM 4 +PREF_UMLC_SCHEDULE_NUM 4 +PREF_UL1SCHEDULE_NUM 4 +PREF_L1Q_DEMAND_RESERVE 0 +PREF_REPORT_PREF_MATCH_AS_MISS FALSE +PREF_REPORT_PREF_MATCH_AS_HIT TRUE +PREF_UPDATE_ON_WRONGPATH TRUE +PREF_TRAIN_ON_PREF_MISSES FALSE 0 +PREF_ORACLE_TRAIN_ON FALSE 0 +PREF_REQ_DROP FALSE +PREF_THROTTLE_ON FALSE +PREF_THROTTLEFB_ON FALSE 1 +PREF_ACC_THRESH_1 0.90 0.75 +PREF_ACC_THRESH_2 0.70 0.4 +PREF_ACC_THRESH_3 0.60 0.4 +PREF_ACC_THRESH_4 0.40 +PREF_UPDATE_INTERVAL 0 8192 +PREF_ANALYZE_LOAD FALSE +PREF_POL_THRESH_1 0.25 +PREF_POL_THRESH_2 0.10 +PREF_POLBV_ON FALSE +PREF_POLBV_SIZE 1024 +PREF_TIMELY_THRESH 0.05 0.01 +PREF_POLPF_THRESH 0.01 0.005 +PREF_DEGFB_USEONLYACC FALSE +PREF_DEGFB_USEONLYPOL FALSE +PREF_DEGFB_USEONLYLATE FALSE +PREF_TIMELY_THRESH_2 0.005 +PREF_DEGFB_STATPHASEFILE FALSE +PREF_MAX_DEGFB 4 +PREF_DHAL FALSE +PREF_DHAL_SENTTHRESH 16 +PREF_DHAL_USETHRESH_MAX 12 +PREF_DHAL_USETHRESH_MIN2 8 +PREF_DHAL_USETHRESH_MIN1 4 +PREF_DHAL_MAXDEG 64 +PREF_HFILTER_ON FALSE +PREF_HFILTER_INDEX_BITS 12 +PREF_HFILTER_USE_PC FALSE +PREF_HFILTER_PRED_USELESS_THRES 2 +PREF_HFILTER_RESET_ENABLE FALSE +PREF_HFILTER_RESET_INTERVAL 100000 +L2L1PREF_ON FALSE +L2WAY_PREF FALSE +L2MARKV_PREF_ON FALSE +L2NEXT_PREF_ON FALSE +L2HIT_STREAM_PREF_ON FALSE +L2L1_DC_HIT_TRAIN FALSE +L1_HIT_DUMP_FILE_ON FALSE +L1_HIT_DUMP_WO_TXT FALSE +L1_HIT_DUMPFILE "l1hit_dump.out" +IDEAL_L2_L1_PREFETCHER FALSE +IDEAL_L2_ICACHE_PREFETCHER FALSE +L1WAY_PREF_SEND_QUEUE 4 +L1PREF_REQ_QUEUE_SIZE 1024 +L1PREF_IMMEDIATE FALSE +L1WAY_PREF_TIMER_DIS 1000 +L1MARKV_PREF_SEND_QUEUE 4 +L1PREF_MARKV_REQ_QUEUE_SIZE 1024 +MARKV_L2ACCESS_REQ_Q_SIZE 64 +L1MARKV_PREF_IMMEDIATE FALSE +L1MARKV_PREF_TIMER_DIS 1 +L2L1_HIT_TRAIN TRUE +L1MARKV_REQ_TH 1 +L2L1_IMMEDIATE_PREF_CACHE FALSE +L2L1_FILL_PREF_CACHE FALSE +L2L1_L2_HIT_STAT FALSE +PREF_GHB_ON FALSE +DEBUG_PREF_GHB FALSE +PREF_GHB_BUFFER_N 1024 +PREF_GHB_INDEX_N 128 +PREF_GHB_CZONE_BITS 12 +PREF_GHB_DEGREE 16 +PREF_GHB_MAX_DEGREE 32 +PREF_STRIDE_ON FALSE +DEBUG_PREF_STRIDE FALSE +PREF_STRIDE_TABLE_N 1024 +PREF_STRIDE_REGION_BITS 16 +PREF_STRIDE_DEGREE 4 +PREF_STRIDE_DISTANCE 16 +PREF_STRIDE_STARTDISTANCE 1 +PREF_STRIDE_SINGLE_THRESH 6 +PREF_STRIDE_MULTI_THRESH 6 +PREF_STRIDE_SINGLE_STRIDE_MODE FALSE +PREF_STRIDEPC_ON FALSE +DEBUG_PREF_STRIDEPC FALSE +PREF_STRIDEPC_TABLE_N 1024 +PREF_STRIDEPC_DEGREE 4 +PREF_STRIDEPC_DISTANCE 16 +PREF_STRIDEPC_USELOADADDR FALSE +PREF_STRIDEPC_TRAINNUM 2 +PREF_STRIDEPC_STARTDIS 4 +PREF_PHASE_ON FALSE +PREF_PHASE_STUDY FALSE +DEBUG_PREF_PHASE FALSE +PREF_PHASE_PRIME_HASH 16381 +PREF_PHASE_INFOSIZE 16384 +PREF_PHASE_LOG2REGIONSIZE 12 +PREF_PHASE_REGIONENTRIES 64 +PREF_PHASE_TRACKEDREGIONS 32 +PREF_PHASE_INTERVAL 100000 +PREF_PHASE_TABLE_SIZE 64 +PREF_PHASE_MAXDIFF_THRESH 64 +PREF_PHASE_MIN_MISSES 64 +PREF_PHASE_MISSPER 0.4 +PREF_2DC_ON FALSE +DEBUG_PREF_2DC FALSE +PREF_2DC_CACHE_SIZE (1 * 1024) +PREF_2DC_CACHE_ASSOC 4 +PREF_2DC_CACHE_LINE_SIZE 1 +PREF_2DC_DEGREE 16 +PREF_2DC_ZONE_SHIFT 10 +PREF_2DC_TAG_SIZE 16 +PREF_2DC_NUM_REGIONS 64 +PREF_2DC_REGION_HASH 61 +PREF_MARKOV_ON FALSE +DEBUG_PREF_MARKOV FALSE +PREF_MARKOV_NUM_ENTRIES 65536 +PREF_MARKOV_NUM_NEXT_STATES 8 +PREF_MARKOV_SEND_ON_PREF_HIT TRUE +PREF_MARKOV_UPDATE_ON_PREF_HIT TRUE +PREF_MARKOV_TABLE_UPDATE_POLICY 0 +PREF_MARKOV_SEND_THRESHOLD 0 +PREF_SMS_ON FALSE 1 +PREF_SMS_AT_SIZE 64 +PREF_SMS_FT_SIZE 64 +PREF_SMS_PHT_SIZE 16384 +PREF_SMS_PRF_SIZE 1024 +PREF_SMS_REGION_SIZE 2048 diff --git a/labs/LAB5/runs/exchange2-sms1/bp.stat.0.out b/labs/LAB5/runs/exchange2-sms1/bp.stat.0.out new file mode 100644 index 00000000..1cad164e --- /dev/null +++ b/labs/LAB5/runs/exchange2-sms1/bp.stat.0.out @@ -0,0 +1,752 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 40827371 Instructions: 100000000 IPC: 2.44934 + +BTB_ON_PATH_MISS 6923 0.040% 6923 0.040% +BTB_ON_PATH_HIT 17250203 99.960% 17250203 99.960% + 17257126 100.000% 17257126 100.000% + 1.00 1.00 1.00 1.00 + +BTB_OFF_PATH_MISS 0 -nan% 0 -nan% +BTB_OFF_PATH_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BTB_ON_PATH_WRITE 6923 100.000% 6923 100.000% +BTB_OFF_PATH_WRITE 0 0.000% 0 0.000% + 6923 100.000% 6923 100.000% + 0.00 0.00 0.00 0.00 + +BP_ON_PATH_CORRECT 16391289 94.983% 16391289 94.983% +BP_ON_PATH_MISPREDICT 102150 0.592% 102150 0.592% +BP_ON_PATH_MISFETCH 763687 4.425% 763687 4.425% + 17257126 100.000% 17257126 100.000% + 0.09 0.41 0.09 0.41 + +BP_OFF_PATH_CORRECT 0 -nan% 0 -nan% +BP_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% +BP_OFF_PATH_MISFETCH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +LATE_BP_ON_PATH_CORRECT 17257126 100.000% 17257126 100.000% +LATE_BP_ON_PATH_MISPREDICT 0 0.000% 0 0.000% +LATE_BP_ON_PATH_MISFETCH 0 0.000% 0 0.000% + 17257126 100.000% 17257126 100.000% + 0.00 0.00 0.00 0.00 + +LATE_BP_OFF_PATH_CORRECT 0 -nan% 0 -nan% +LATE_BP_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% +LATE_BP_OFF_PATH_MISFETCH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_PVN 0 -nan% 0 -nan% +BP_ON_PATH_CONF_PVN_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_PVP 0 -nan% 0 -nan% +BP_ON_PATH_CONF_PVP_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_SPEC 0 -nan% 0 -nan% +BP_ON_PATH_CONF_SPEC_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CRS_MISS_ON_PATH 32 0.067% 32 0.067% +CRS_HIT_ON_PATH 47854 99.933% 47854 99.933% + 47886 100.000% 47886 100.000% + 1.00 1.00 1.00 1.00 + +CRS_MISS_OFF_PATH 0 -nan% 0 -nan% +CRS_HIT_OFF_PATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CRS_CLOBBER 0 0 + +TARG_ON_PATH_MISS 4813 16.813% 4813 16.813% +TARG_ON_PATH_HIT 23814 83.187% 23814 83.187% + 28627 100.000% 28627 100.000% + 0.83 0.77 0.83 0.77 + +TARG_OFF_PATH_MISS 0 -nan% 0 -nan% +TARG_OFF_PATH_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_ON_PATH_WRITE 28627 100.000% 28627 100.000% +TARG_OFF_PATH_WRITE 0 0.000% 0 0.000% + 28627 100.000% 28627 100.000% + 0.00 0.00 0.00 0.00 + +TARG_HYBRID_CORRECT_TAGLESS 0 -nan% 0 -nan% +TARG_HYBRID_CORRECT_TAGGED 0 -nan% 0 -nan% +TARG_HYBRID_MISPRED_TAGLESS 0 -nan% 0 -nan% +TARG_HYBRID_MISPRED_TAGGED 0 -nan% 0 -nan% +TARG_HYBRID_NO_PRED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_VP_INDIRECT_MISPRED 0 -nan% 0 -nan% +TARG_VP_INDIRECT_NOPRED 0 -nan% 0 -nan% +TARG_VP_INDIRECT_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan 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+CHIP_UTILIZATION_UNDER_CRITICAL_MEM_REQ 0 -nan 0 -nan + +CHIP_UTILIZATION_UNDER_NONCRITICAL_MEM_REQ 0 -nan 0 -nan + +CYCLES_NOT_WAITING_FOR_OFF_CHIP 0 0.0000 0 0.0000 + +FUS_BUSY_NOT_WAITING_FOR_OFF_CHIP 0 -nan 0 -nan + +CYCLES_WAITING_FOR_OFF_CHIP 0 0.0000 0 0.0000 + +FUS_BUSY_WAITING_FOR_OFF_CHIP 0 -nan 0 -nan + +TOTAL_OFF_CHIP_DELAYS_LEFT 0 0 + +WRONG_IO_SCHED 0 0 + +DVFS_CONFIG_SWITCH 0 0 + + + diff --git a/labs/LAB5/runs/exchange2-sms1/fetch.stat.0.out b/labs/LAB5/runs/exchange2-sms1/fetch.stat.0.out new file mode 100644 index 00000000..7ba2242c --- /dev/null +++ b/labs/LAB5/runs/exchange2-sms1/fetch.stat.0.out @@ -0,0 +1,248 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 40827371 Instructions: 100000000 IPC: 2.44934 + +ICACHE_CYCLE 40827371 40827371 + +TCACHE_CYCLE 0 0 + +ICACHE_CYCLE_ONPATH 24115132 59.066% 24115132 59.066% +ICACHE_CYCLE_OFFPATH 16712239 40.934% 16712239 40.934% + 40827371 100.000% 40827371 100.000% + 0.41 0.46 0.41 0.46 + +FETCH_ON_PATH 24570155 100.000% 24570155 100.000% +FETCH_OFF_PATH 0 0.000% 0 0.000% + 24570155 100.000% 24570155 100.000% + 0.00 0.00 0.00 0.00 + +FETCHED_OPS_ON_PATH 0 -nan% 0 -nan% +FETCHED_OPS_OFF_PATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +INST_LOST_WAIT_FOR_MISP_RECOVERY 0 0.000% 0 0.000% +INST_LOST_WAIT_FOR_TIMER 0 0.000% 0 0.000% +INST_LOST_WAIT_FOR_EMPTY_ROB 0 0.000% 0 0.000% +INST_LOST_WAIT_FOR_REDIRECT 216810 0.145% 216810 0.145% +INST_LOST_FETCH 128408890 85.644% 128408890 85.644% +INST_LOST_OFF_PATH 0 0.000% 0 0.000% +INST_LOST_FULL_WINDOW 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_OTHER 130326 0.087% 130326 0.087% +INST_LOST_ROB_STALL_WAIT_FOR_RECOVERY 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_REDIRECT 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_GAP_FILL 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_L1_MISS 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_MEMORY 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_DC_MISS 40584 0.027% 40584 0.027% +INST_LOST_ROB_BLOCK_ISSUE_FULL 0 0.000% 0 0.000% +INST_LOST_ROB_BLOCK_ISSUE_GAP_TOO_LARGE 0 0.000% 0 0.000% +INST_LOST_BREAK_DONT 0 0.000% 0 0.000% +INST_LOST_BREAK_ISSUE_WIDTH 0 0.000% 0 0.000% +INST_LOST_BREAK_CF 0 0.000% 0 0.000% +INST_LOST_BREAK_BTB_MISS 18373 0.012% 18373 0.012% +INST_LOST_BREAK_ICACHE_MISS 2204412 1.470% 2204412 1.470% +INST_LOST_BREAK_LINE_END 0 0.000% 0 0.000% +INST_LOST_BREAK_STALL 0 0.000% 0 0.000% +INST_LOST_BREAK_BARRIER 0 0.000% 0 0.000% +INST_LOST_BREAK_OFFPATH 115538 0.077% 115538 0.077% +INST_LOST_BREAK_ALIGNMENT 0 0.000% 0 0.000% +INST_LOST_BREAK_TAKEN 18797687 12.537% 18797687 12.537% +INST_LOST_BREAK_MODEL_BEFORE 0 0.000% 0 0.000% +INST_LOST_BREAK_MODEL_AFTER 0 0.000% 0 0.000% + 149932620 100.000% 149932620 100.000% + 7.01 7.46 7.01 7.46 + +INST_LOST_TOTAL 244964226 244964226 + +FETCH_0_OPS 431675 1.727% 431675 1.727% +FETCH_1_OPS 1261739 5.049% 1261739 5.049% +FETCH_2_OPS 1046350 4.187% 1046350 4.187% +FETCH_3_OPS 1337381 5.352% 1337381 5.352% +FETCH_4_OPS 963564 3.856% 963564 3.856% +FETCH_5_OPS 2500314 10.006% 2500314 10.006% +FETCH_6_OPS 17447747 69.822% 17447747 69.822% +FETCH_7_OPS 0 0.000% 0 0.000% +FETCH_8_OPS 0 0.000% 0 0.000% +FETCH_9_OPS 0 0.000% 0 0.000% +FETCH_10_OPS 0 0.000% 0 0.000% +FETCH_11_OPS 0 0.000% 0 0.000% +FETCH_12_OPS 0 0.000% 0 0.000% +FETCH_13_OPS 0 0.000% 0 0.000% +FETCH_14_OPS 0 0.000% 0 0.000% +FETCH_15_OPS 0 0.000% 0 0.000% +FETCH_16_OPS 0 0.000% 0 0.000% + 24988770 100.000% 24988770 100.000% + 5.14 1.45 5.14 1.45 + +ST_BREAK_DONT 0 0.000% 0 0.000% +ST_BREAK_ISSUE_WIDTH 15550257 63.289% 15550257 63.289% +ST_BREAK_CF 0 0.000% 0 0.000% +ST_BREAK_BTB_MISS 6923 0.028% 6923 0.028% +ST_BREAK_ICACHE_MISS 13867 0.056% 13867 0.056% +ST_BREAK_LINE_END 0 0.000% 0 0.000% +ST_BREAK_STALL 0 0.000% 0 0.000% +ST_BREAK_BARRIER 0 0.000% 0 0.000% +ST_BREAK_OFFPATH 65496 0.267% 65496 0.267% +ST_BREAK_ALIGNMENT 0 0.000% 0 0.000% +ST_BREAK_TAKEN 8933612 36.360% 8933612 36.360% + 24570155 100.000% 24570155 100.000% + 4.29 5.04 4.29 5.04 + +ORACLE_ON_PATH_INST 128408890 100.000% 128408890 100.000% +ORACLE_OFF_PATH_INST 0 0.000% 0 0.000% + 128408890 100.000% 128408890 100.000% + 0.00 0.00 0.00 0.00 + +ORACLE_ON_PATH_INST_MEM 45194890 35.196% 45194890 35.196% +ORACLE_ON_PATH_INST_NOTMEM 83214000 64.804% 83214000 64.804% +ORACLE_OFF_PATH_INST_MEM 0 0.000% 0 0.000% +ORACLE_OFF_PATH_INST_NOTMEM 0 0.000% 0 0.000% + 128408890 100.000% 128408890 100.000% + 0.65 0.28 0.65 0.28 + +ICACHE_CYCLE_NONRA_ONPATH 0 -nan% 0 -nan% +ICACHE_CYCLE_NONRA_OFFPATH 0 -nan% 0 -nan% +ICACHE_CYCLE_RA_ONPATH 0 -nan% 0 -nan% +ICACHE_CYCLE_RA_OFFPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ICACHE_CYCLE_ONPATH_NONRA 0 -nan% 0 -nan% +ICACHE_CYCLE_OFFPATH_NONRA 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ICACHE_CYCLE_ONPATH_RA 0 -nan% 0 -nan% +ICACHE_CYCLE_OFFPATH_RA 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +INACCURATE_OFFPATH_CYCLES 0 0.0000 0 0.0000 + +FETCH_ALL_INST 128408890 128408890 + +EXEC_ALL_INST 128408799 128408799 + +RET_ALL_INST 128408750 128408750 + +EXEC_ON_PATH_INST 128408799 100.000% 128408799 100.000% +EXEC_OFF_PATH_INST 0 0.000% 0 0.000% + 128408799 100.000% 128408799 100.000% + 0.00 0.00 0.00 0.00 + +EXEC_ON_PATH_INST_MEM 45194849 35.196% 45194849 35.196% +EXEC_ON_PATH_INST_NOTMEM 83213950 64.804% 83213950 64.804% +EXEC_OFF_PATH_INST_MEM 0 0.000% 0 0.000% +EXEC_OFF_PATH_INST_NOTMEM 0 0.000% 0 0.000% + 128408799 100.000% 128408799 100.000% + 0.65 0.28 0.65 0.28 + +EXEC_RA_INST 0 -nan% 0 -nan% +EXEC_NONRA_INST 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +EXEC_ON_PATH_INST_RA 0 -nan% 0 -nan% +EXEC_OFF_PATH_INST_RA 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +EXEC_ON_PATH_INST_NONRA 0 -nan% 0 -nan% +EXEC_OFF_PATH_INST_NONRA 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +EXEC_RA_ON_PATH_INST 0 -nan% 0 -nan% +EXEC_RA_OFF_PATH_INST 0 -nan% 0 -nan% +EXEC_NONRA_ON_PATH_INST 0 -nan% 0 -nan% +EXEC_NONRA_OFF_PATH_INST 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ICACHE_THROTTLE_CYCLE 0 0 + +FETCH_ENABLE_THROTTLE_OFF_PATH 0 -nan% 0 -nan% +FETCH_ENABLE_THROTTLE_ON_PATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +FETCH_DISABLE_THROTTLE_OFF_PATH 0 -nan% 0 -nan% +FETCH_DISABLE_THROTTLE_ON_PATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +FETCH_TH_ADJUST__0 0 -nan% 0 -nan% +FETCH_TH_ADJUST__1 0 -nan% 0 -nan% +FETCH_TH_ADJUST__2 0 -nan% 0 -nan% +FETCH_TH_ADJUST__3 0 -nan% 0 -nan% +FETCH_TH_ADJUST__4 0 -nan% 0 -nan% +FETCH_TH_ADJUST__5 0 -nan% 0 -nan% +FETCH_TH_ADJUST__6 0 -nan% 0 -nan% +FETCH_TH_ADJUST__7 0 -nan% 0 -nan% +FETCH_TH_ADJUST__8 0 -nan% 0 -nan% +FETCH_TH_ADJUST__9 0 -nan% 0 -nan% +FETCH_TH_ADJUST__MAX 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +FETCH_TH_ADJUST_UP 0 -nan% 0 -nan% +FETCH_TH_ADJUST_DOWN 0 -nan% 0 -nan% +FETCH_TH_ADJUST_SAME 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +THROTTLE_ADJUST_CACHE_MISS_INFO 0 0 + +LOW_CONF_COUNT_BP_MIS_0 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_1 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_2 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_3 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_4 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_5 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_6 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_7 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_8 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_9 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_10 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_11 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_12 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_13 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_14 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_15 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_16 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_17 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_18 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_19 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_20 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +LOW_CONF_COUNT_RET_0 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_1 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_2 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_3 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_4 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_5 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_6 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_7 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_8 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_9 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_10 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_11 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_12 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_13 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_14 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_15 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_16 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_17 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_18 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_19 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_20 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + + + diff --git a/labs/LAB5/runs/exchange2-sms1/inst.stat.0.out b/labs/LAB5/runs/exchange2-sms1/inst.stat.0.out new file mode 100644 index 00000000..3cbda967 --- /dev/null +++ b/labs/LAB5/runs/exchange2-sms1/inst.stat.0.out @@ -0,0 +1,103 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 40827371 Instructions: 100000000 IPC: 2.44934 + +ST_OP_INV 0 0.000% 0 0.000% +ST_OP_NOP 1224808 0.954% 1224808 0.954% +ST_OP_CF 17257126 13.439% 17257126 13.439% +ST_OP_MOV 8789711 6.845% 8789711 6.845% +ST_OP_CMOV 27636 0.022% 27636 0.022% +ST_OP_LDA 6908184 5.380% 6908184 5.380% +ST_OP_IMEM 45193492 35.195% 45193492 35.195% +ST_OP_IADD 30143783 23.475% 30143783 23.475% +ST_OP_IMUL 1090225 0.849% 1090225 0.849% +ST_OP_IDIV 921 0.001% 921 0.001% +ST_OP_ICMP 12337271 9.608% 12337271 9.608% +ST_OP_LOGIC 5287019 4.117% 5287019 4.117% +ST_OP_SHIFT 147316 0.115% 147316 0.115% +ST_OP_FMEM 1398 0.001% 1398 0.001% +ST_OP_FCVT 0 0.000% 0 0.000% +ST_OP_FADD 0 0.000% 0 0.000% +ST_OP_FMUL 0 0.000% 0 0.000% +ST_OP_FMA 0 0.000% 0 0.000% +ST_OP_FDIV 0 0.000% 0 0.000% +ST_OP_FCMP 0 0.000% 0 0.000% +ST_OP_FCMOV 0 0.000% 0 0.000% +ST_OP_GATHER 0 0.000% 0 0.000% +ST_OP_SCATTER 0 0.000% 0 0.000% +ST_OP_PIPELINED_FAST 0 0.000% 0 0.000% +ST_OP_PIPELINED_MEDIUM 0 0.000% 0 0.000% +ST_OP_PIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_MEDIUM 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_VERY_SLOW 0 0.000% 0 0.000% + 128408890 100.000% 128408890 100.000% + 6.00 2.44 6.00 2.44 + +ST_NOT_CF 111151764 86.561% 111151764 86.561% +ST_CF_BR 1114568 0.868% 1114568 0.868% +ST_CF_CBR 16018157 12.474% 16018157 12.474% +ST_CF_CALL 47888 0.037% 47888 0.037% +ST_CF_IBR 28627 0.022% 28627 0.022% +ST_CF_ICALL 0 0.000% 0 0.000% +ST_CF_ICO 0 0.000% 0 0.000% +ST_CF_RET 47886 0.037% 47886 0.037% +ST_CF_SYS 0 0.000% 0 0.000% + 128408890 100.000% 128408890 100.000% + 0.26 0.64 0.26 0.64 + +ST_BAR_NONE 128408890 100.000% 128408890 100.000% +ST_BAR_FETCH 0 0.000% 0 0.000% +ST_BAR_ISSUE 0 0.000% 0 0.000% +ST_BAR_BOTH 0 0.000% 0 0.000% + 128408890 100.000% 128408890 100.000% + 0.00 0.00 0.00 0.00 + +ST_NOT_MEM 83214000 64.804% 83214000 64.804% +ST_MEM_LD 28723490 22.369% 28723490 22.369% +ST_MEM_ST 16471400 12.827% 16471400 12.827% +ST_MEM_PF 0 0.000% 0 0.000% +ST_MEM_WH 0 0.000% 0 0.000% +ST_MEM_EVICT 0 0.000% 0 0.000% + 128408890 100.000% 128408890 100.000% + 0.48 0.60 0.48 0.60 + +ST_NOT_MEM_OFFPATH 0 -nan% 0 -nan% +ST_MEM_LD_OFFPATH 0 -nan% 0 -nan% +ST_MEM_ST_OFFPATH 0 -nan% 0 -nan% +ST_MEM_PF_OFFPATH 0 -nan% 0 -nan% +ST_MEM_WH_OFFPATH 0 -nan% 0 -nan% +ST_MEM_EVIC_OFFPATHT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ST_OP_ONPATH 128408890 128408890 + +ST_OP_OFFPATH 0 0 + +ST_FAKE_OP_OFFPATH 0 -nan% 0 -nan% +ST_NOT_FAKE_OP_OFFPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ST_FAKE_REASON_NOT_FAKE 0 -nan% 0 -nan% +ST_FAKE_REASON_REDIRECT_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_RETURN_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_NONRET_CF_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_NOT_TAKEN_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_WRONG_PATH_STORE_TO_NEW_REGION 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ST_INST_ONPATH 100000090 100000090 + +ST_INST_OFFPATH 0 0 + +STATIC_PIN_NOP 0 0 + +DYNAMIC_PIN_REP_GREATER_256 0 0 + + + diff --git a/labs/LAB5/runs/exchange2-sms1/l2l1pref.stat.0.out b/labs/LAB5/runs/exchange2-sms1/l2l1pref.stat.0.out new file mode 100644 index 00000000..3bedb52d --- /dev/null +++ b/labs/LAB5/runs/exchange2-sms1/l2l1pref.stat.0.out @@ -0,0 +1,140 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 40827371 Instructions: 100000000 IPC: 2.44934 + +L2WAY_FILL_L1 0 0 + +L2WAY_WAY_HIT 0 -nan% 0 -nan% +L2WAY_WAY_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_PREF_REQ 0 0 + +L2WAY_PREF_HIT_DATA_IN_CACHE 0 -nan% 0 -nan% +L2WAY_PREF_HIT_DATA_REQ 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_TRAIN_HIT 0 -nan% 0 -nan% +L2WAY_TRAIN_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L1_HIT_REQ_TYPE_IFETCH 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DFETCH 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DSTORE 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_IPRF 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DPRF 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_WB 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2_ACCESS_INTERVAL__0 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__1 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__2 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__3 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__4 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__5 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__6 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__7 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__8 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_L1INSERT_PORT_FULL 0 -nan% 0 -nan% +L2WAY_L1INSERT_PORT_READY 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2MARKV_NEXT_ADDR_HIT 0 -nan% 0 -nan% +L2MARKV_NEXT_ADDR_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2MARKV_LAST_ADDR_HIT 0 -nan% 0 -nan% +L2MARKV_LAST_ADDR_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +MARKV_L2_TIME_DIFF__0 0 -nan% 0 -nan% +MARKV_L2_TIME_DIFF__1 0 -nan% 0 -nan% +MARKV_L2_TIME_DIFF__2 0 -nan% 0 -nan% +MARKV_L2_TIME_DIFF__3 0 -nan% 0 -nan% +MARKV_L2_TIME_DIFF__4 0 -nan% 0 -nan% +MARKV_L2_TIME_DIFF__5 0 -nan% 0 -nan% +MARKV_L2_TIME_DIFF__6 0 -nan% 0 -nan% +MARKV_L2_TIME_DIFF__7 0 -nan% 0 -nan% +MARKV_L2_TIME_DIFF__8 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2MARKV_PREF_REQ 0 0 + +L2MARKV_PREF_TRAIN 0 0 + +L2MARKV_PREF_HIT_DATA_REQ 0 -nan% 0 -nan% +L2MARKV_PREF_HIT_DATA_IN_CACHE 0 -nan% 0 -nan% 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-*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 40827371 Instructions: 100000000 IPC: 2.44934 + +POWER_STATS_BEGIN 0 0 + +POWER_TIME 12758553437500 12758553437500 + +POWER_CYCLE 40827371 40827371 + +POWER_ITLB_ACCESS 31112866 31112866 + +POWER_DTLB_ACCESS 16471382 16471382 + +POWER_ICACHE_ACCESS 31112866 31112866 + +POWER_ICACHE_MISS 13867 13867 + +POWER_BTB_READ 31112866 31112866 + +POWER_BTB_WRITE 865837 865837 + +POWER_ROB_READ 128408799 128408799 + +POWER_ROB_WRITE 128408799 128408799 + +POWER_RENAME_READ 256817598 256817598 + +POWER_RENAME_WRITE 128408799 128408799 + +POWER_FP_RENAME_READ 0 0 + +POWER_FP_RENAME_WRITE 0 0 + +POWER_FUNCTION_CALL 47888 47888 + +POWER_INST_WINDOW_READ 128408799 128408799 + +POWER_INST_WINDOW_WRITE 128408799 128408799 + +POWER_INT_REGFILE_READ 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0.000% +L1_LATE_PREF_CYCLES_DIST_700 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_800 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_900 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1000 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1100 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1200 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1300 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1400 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1500 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1600 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1700 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1800 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1900 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_2000 0 0.000% 0 0.000% + 2 100.000% 2 100.000% + 0.00 0.00 0.00 0.00 + +MLC_PREF_HIT 0 0 + +MLC_PREF_UNIQUE_HIT 0 0 + +MLC_PREF_LATE 0 0 + +PREF_HYBRID_SEL_0 0 -nan% 0 -nan% +PREF_HYBRID_SEL_1 0 -nan% 0 -nan% +PREF_HYBRID_SEL_2 0 -nan% 0 -nan% +PREF_HYBRID_SEL_3 0 -nan% 0 -nan% +PREF_HYBRID_SEL_4 0 -nan% 0 -nan% +PREF_HYBRID_SEL_5 0 -nan% 0 -nan% +PREF_HYBRID_SEL_6 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_DISTANCE_1 0 -nan% 0 -nan% +PREF_DISTANCE_2 0 -nan% 0 -nan% +PREF_DISTANCE_3 0 -nan% 0 -nan% +PREF_DISTANCE_4 0 -nan% 0 -nan% +PREF_DISTANCE_5 0 -nan% 0 -nan% +PREF_DISTANCE_6 0 -nan% 0 -nan% +PREF_DISTANCE_7 0 -nan% 0 -nan% +PREF_DISTANCE_8 0 -nan% 0 -nan% +PREF_DISTANCE_9 0 -nan% 0 -nan% +PREF_DISTANCE_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_REPL_MRU 0 -nan% 0 -nan% +PREF_REPL_MID 0 -nan% 0 -nan% +PREF_REPL_LOWQTR 0 -nan% 0 -nan% +PREF_REPL_LRU 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_REPL_MOVEDOWN 0 -nan% 0 -nan% +PREF_REPL_MOVEUP 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_COV_1 0 -nan% 0 -nan% +PREF_COV_2 0 -nan% 0 -nan% +PREF_COV_3 0 -nan% 0 -nan% +PREF_COV_4 0 -nan% 0 -nan% +PREF_COV_5 0 -nan% 0 -nan% +PREF_COV_6 0 -nan% 0 -nan% +PREF_COV_7 0 -nan% 0 -nan% +PREF_COV_8 0 -nan% 0 -nan% +PREF_COV_9 0 -nan% 0 -nan% +PREF_COV_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_POL_1 0 -nan% 0 -nan% +PREF_POL_2 0 -nan% 0 -nan% +PREF_POL_3 0 -nan% 0 -nan% +PREF_POL_4 0 -nan% 0 -nan% +PREF_POL_5 0 -nan% 0 -nan% +PREF_POL_6 0 -nan% 0 -nan% +PREF_POL_7 0 -nan% 0 -nan% +PREF_POL_8 0 -nan% 0 -nan% +PREF_POL_9 0 -nan% 0 -nan% +PREF_POL_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_ACC_1 0 -nan% 0 -nan% +PREF_ACC_2 0 -nan% 0 -nan% +PREF_ACC_3 0 -nan% 0 -nan% +PREF_ACC_4 0 -nan% 0 -nan% +PREF_ACC_5 0 -nan% 0 -nan% +PREF_ACC_6 0 -nan% 0 -nan% +PREF_ACC_7 0 -nan% 0 -nan% +PREF_ACC_8 0 -nan% 0 -nan% +PREF_ACC_9 0 -nan% 0 -nan% +PREF_ACC_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_TIMELY_1 0 -nan% 0 -nan% +PREF_TIMELY_2 0 -nan% 0 -nan% +PREF_TIMELY_3 0 -nan% 0 -nan% +PREF_TIMELY_4 0 -nan% 0 -nan% +PREF_TIMELY_5 0 -nan% 0 -nan% +PREF_TIMELY_6 0 -nan% 0 -nan% +PREF_TIMELY_7 0 -nan% 0 -nan% +PREF_TIMELY_8 0 -nan% 0 -nan% +PREF_TIMELY_9 0 -nan% 0 -nan% +PREF_TIMELY_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_UNUSED_EVICT 0 0 + +PREF_REGION_SENT 0 0 + +PREF_REGION_USEFUL 0 0 + +PREF_REGION_EVICT 0 0 + +PREF_PFPOL 0 0 + +PREF_PHASE_NEWPHASE_DET 0 0 + +PREF_PHASE_NEWPHASE_NOTVALID 0 0 + +PREF_PHASE_SENTPREF 0 0 + +PREF_PHASE_OVERWRITE_PAGE 0 0 + +PREF_UPDATE_COUNT 0 0 + +PREF_ACC1_HT_HP 0 -nan% 0 -nan% +PREF_ACC1_HT_LP 0 -nan% 0 -nan% +PREF_ACC1_LT_HP 0 -nan% 0 -nan% +PREF_ACC1_LT_LP 0 -nan% 0 -nan% +PREF_ACC2_HT_HP 0 -nan% 0 -nan% +PREF_ACC2_HT_LP 0 -nan% 0 -nan% +PREF_ACC2_LT_HP 0 -nan% 0 -nan% +PREF_ACC2_LT_LP 0 -nan% 0 -nan% +PREF_ACC3_HT_HP 0 -nan% 0 -nan% +PREF_ACC3_HT_LP 0 -nan% 0 -nan% +PREF_ACC3_LT_HP 0 -nan% 0 -nan% +PREF_ACC3_LT_LP 0 -nan% 0 -nan% +PREF_ACC4_HT_HP 0 -nan% 0 -nan% +PREF_ACC4_HT_LP 0 -nan% 0 -nan% +PREF_ACC4_LT_HP 0 -nan% 0 -nan% +PREF_ACC4_LT_LP 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + + + diff --git a/labs/LAB5/runs/exchange2-sms1/ramulator.stat.out b/labs/LAB5/runs/exchange2-sms1/ramulator.stat.out new file mode 100644 index 00000000..f4056969 --- /dev/null +++ b/labs/LAB5/runs/exchange2-sms1/ramulator.stat.out @@ -0,0 +1,150 @@ + ramulator.active_cycles_0 35872 # Total active cycles for level _0 + ramulator.busy_cycles_0 35872 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0 + ramulator.serving_requests_0 39841 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.average_serving_requests_0 0.002602 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.active_cycles_0_0 35872 # Total active cycles for level _0_0 + ramulator.busy_cycles_0_0 722572 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0 + ramulator.serving_requests_0_0 39841 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.average_serving_requests_0_0 0.002602 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.active_cycles_0_0_0 9332 # Total active cycles for level _0_0_0 + ramulator.busy_cycles_0_0_0 9332 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0 + ramulator.serving_requests_0_0_0 9436 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 +ramulator.average_serving_requests_0_0_0 0.000616 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 + ramulator.active_cycles_0_0_0_0 188 # Total active cycles for level _0_0_0_0 + ramulator.busy_cycles_0_0_0_0 188 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_0 + ramulator.serving_requests_0_0_0_0 188 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 +ramulator.average_serving_requests_0_0_0_0 0.000012 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 + ramulator.active_cycles_0_0_0_1 2560 # Total active cycles for level _0_0_0_1 + ramulator.busy_cycles_0_0_0_1 2560 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_1 + ramulator.serving_requests_0_0_0_1 2560 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 +ramulator.average_serving_requests_0_0_0_1 0.000167 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 + ramulator.active_cycles_0_0_0_2 4548 # Total active cycles for level _0_0_0_2 + ramulator.busy_cycles_0_0_0_2 4548 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_2 + ramulator.serving_requests_0_0_0_2 4548 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 +ramulator.average_serving_requests_0_0_0_2 0.000297 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 + ramulator.active_cycles_0_0_0_3 2070 # Total active cycles for level _0_0_0_3 + ramulator.busy_cycles_0_0_0_3 2070 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_3 + ramulator.serving_requests_0_0_0_3 2140 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 +ramulator.average_serving_requests_0_0_0_3 0.000140 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 + ramulator.active_cycles_0_0_1 6915 # Total active cycles for level _0_0_1 + ramulator.busy_cycles_0_0_1 6915 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1 + ramulator.serving_requests_0_0_1 7514 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 +ramulator.average_serving_requests_0_0_1 0.000491 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 + ramulator.active_cycles_0_0_1_0 1628 # Total active cycles for level _0_0_1_0 + ramulator.busy_cycles_0_0_1_0 1628 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_0 + ramulator.serving_requests_0_0_1_0 1628 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 +ramulator.average_serving_requests_0_0_1_0 0.000106 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 + ramulator.active_cycles_0_0_1_1 1490 # Total active cycles for level _0_0_1_1 + ramulator.busy_cycles_0_0_1_1 1490 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_1 + ramulator.serving_requests_0_0_1_1 2036 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 +ramulator.average_serving_requests_0_0_1_1 0.000133 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 + ramulator.active_cycles_0_0_1_2 2316 # Total active cycles for level _0_0_1_2 + ramulator.busy_cycles_0_0_1_2 2316 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_2 + ramulator.serving_requests_0_0_1_2 2316 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 +ramulator.average_serving_requests_0_0_1_2 0.000151 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 + ramulator.active_cycles_0_0_1_3 1514 # Total active cycles for level _0_0_1_3 + ramulator.busy_cycles_0_0_1_3 1514 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_3 + ramulator.serving_requests_0_0_1_3 1534 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 +ramulator.average_serving_requests_0_0_1_3 0.000100 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 + ramulator.active_cycles_0_0_2 6886 # Total active cycles for level _0_0_2 + ramulator.busy_cycles_0_0_2 6886 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2 + ramulator.serving_requests_0_0_2 8223 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 +ramulator.average_serving_requests_0_0_2 0.000537 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 + ramulator.active_cycles_0_0_2_0 1442 # Total active cycles for level _0_0_2_0 + ramulator.busy_cycles_0_0_2_0 1442 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_0 + ramulator.serving_requests_0_0_2_0 2079 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 +ramulator.average_serving_requests_0_0_2_0 0.000136 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 + ramulator.active_cycles_0_0_2_1 1390 # Total active cycles for level _0_0_2_1 + ramulator.busy_cycles_0_0_2_1 1390 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_1 + ramulator.serving_requests_0_0_2_1 1390 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 +ramulator.average_serving_requests_0_0_2_1 0.000091 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 + ramulator.active_cycles_0_0_2_2 1264 # Total active cycles for level _0_0_2_2 + ramulator.busy_cycles_0_0_2_2 1264 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_2 + ramulator.serving_requests_0_0_2_2 1264 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 +ramulator.average_serving_requests_0_0_2_2 0.000083 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 + ramulator.active_cycles_0_0_2_3 2818 # Total active cycles for level _0_0_2_3 + ramulator.busy_cycles_0_0_2_3 2818 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_3 + ramulator.serving_requests_0_0_2_3 3490 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 +ramulator.average_serving_requests_0_0_2_3 0.000228 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 + ramulator.active_cycles_0_0_3 14175 # Total active cycles for level _0_0_3 + ramulator.busy_cycles_0_0_3 14175 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3 + ramulator.serving_requests_0_0_3 14668 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 +ramulator.average_serving_requests_0_0_3 0.000958 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 + ramulator.active_cycles_0_0_3_0 5376 # Total active cycles for level _0_0_3_0 + ramulator.busy_cycles_0_0_3_0 5376 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_0 + ramulator.serving_requests_0_0_3_0 5376 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 +ramulator.average_serving_requests_0_0_3_0 0.000351 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 + ramulator.active_cycles_0_0_3_1 3777 # Total active cycles for level _0_0_3_1 + ramulator.busy_cycles_0_0_3_1 3777 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_1 + ramulator.serving_requests_0_0_3_1 4256 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 +ramulator.average_serving_requests_0_0_3_1 0.000278 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 + ramulator.active_cycles_0_0_3_2 4980 # Total active cycles for level _0_0_3_2 + ramulator.busy_cycles_0_0_3_2 4980 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_2 + ramulator.serving_requests_0_0_3_2 4980 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 +ramulator.average_serving_requests_0_0_3_2 0.000325 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 + ramulator.active_cycles_0_0_3_3 42 # Total active cycles for level _0_0_3_3 + ramulator.busy_cycles_0_0_3_3 42 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_3 + ramulator.serving_requests_0_0_3_3 56 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 +ramulator.average_serving_requests_0_0_3_3 0.000004 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 + ramulator.read_transaction_bytes_0 114048 # The total byte of read transaction per channel + ramulator.write_transaction_bytes_0 0 # The total byte of write transaction per channel + ramulator.row_hits_channel_0_core 1577 # Number of row hits per channel per core + ramulator.row_misses_channel_0_core 148 # Number of row misses per channel per core + ramulator.row_conflicts_channel_0_core 57 # Number of row conflicts per channel per core + ramulator.read_row_hits_channel_0_core 1577 # Number of row hits for read requests per channel per core + [0] 1577.0 # +ramulator.read_row_misses_channel_0_core 148 # Number of row misses for read requests per channel per core + [0] 148.0 # +ramulator.read_row_conflicts_channel_0_core 57 # Number of row conflicts for read requests per channel per core + [0] 57.0 # + ramulator.write_row_hits_channel_0_core 0 # Number of row hits for write requests per channel per core + [0] 0.0 # +ramulator.write_row_misses_channel_0_core 0 # Number of row misses for write requests per channel per core + [0] 0.0 # +ramulator.write_row_conflicts_channel_0_core 0 # Number of row conflicts for write requests per channel per core + [0] 0.0 # + ramulator.useless_activates_0_core 0 # Number of useless activations. E.g, ACT -> PRE w/o RD or WR + ramulator.read_latency_avg_0 27.787318 # The average memory latency cycles (in memory time domain) per request for all read requests in this channel + ramulator.read_latency_sum_0 49517 # The memory latency cycles (in memory time domain) sum for all read requests in this channel + ramulator.req_queue_length_avg_0 0.003019 # Average of read and write queue length per memory cycle per channel. + ramulator.req_queue_length_sum_0 46228 # Sum of read and write queue length per memory cycle per channel. + ramulator.read_req_queue_length_avg_0 0.003019 # Read queue length average per memory cycle per channel. + ramulator.read_req_queue_length_sum_0 46228 # Read queue length sum per memory cycle per channel. + ramulator.write_req_queue_length_avg_0 0.000000 # Write queue length average per memory cycle per channel. + ramulator.write_req_queue_length_sum_0 0 # Write queue length sum per memory cycle per channel. + ramulator.record_read_hits 0.0 # record read hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_misses 0.0 # record_read_miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_conflicts 0.0 # record read conflict count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_hits 0.0 # record write hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_misses 0.0 # record write miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_conflicts 0.0 # record write conflict for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.dram_capacity 8589934592 # Number of bytes in simulated DRAM + ramulator.dram_cycles 15310270 # Number of DRAM cycles simulated + ramulator.incoming_requests 1782 # Number of incoming requests to DRAM + ramulator.read_requests 1782 # Number of incoming read requests to DRAM per core + [0] 1782.0 # + ramulator.write_requests 0 # Number of incoming write requests to DRAM per core + [0] 0.0 # + ramulator.ramulator_active_cycles 35872 # The total number of cycles that the DRAM part is active (serving R/W) + ramulator.incoming_requests_per_channel 1782.0 # Number of incoming requests to each DRAM channel + [0] 1782.0 # +ramulator.incoming_read_reqs_per_channel 1782.0 # Number of incoming read requests to each DRAM channel + [0] 1782.0 # + ramulator.physical_page_replacement 0 # The number of times that physical page replacement happens. + ramulator.maximum_bandwidth 19200000000 # The theoretical maximum bandwidth (Bps) + ramulator.in_queue_req_num_sum 46228 # Sum of read/write queue length + ramulator.in_queue_read_req_num_sum 46228 # Sum of read queue length + ramulator.in_queue_write_req_num_sum 0 # Sum of write queue length + ramulator.in_queue_req_num_avg 0.003019 # Average of read/write queue length per memory cycle + ramulator.in_queue_read_req_num_avg 0.003019 # Average of read queue length per memory cycle + ramulator.in_queue_write_req_num_avg 0.000000 # Average of write queue length per memory cycle + ramulator.record_read_requests 0.0 # record read requests for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_requests 0.0 # record write requests for this core when it reaches request limit or to the end + [0] 0.0 # diff --git a/labs/LAB5/runs/exchange2-sms1/run.err b/labs/LAB5/runs/exchange2-sms1/run.err new file mode 100644 index 00000000..e69de29b diff --git a/labs/LAB5/runs/exchange2-sms1/run.out b/labs/LAB5/runs/exchange2-sms1/run.out new file mode 100644 index 00000000..2c691b50 --- /dev/null +++ b/labs/LAB5/runs/exchange2-sms1/run.out @@ -0,0 +1,107 @@ +Scarab gitrev: 7ab9e17 +Scarab started at Sun Jun 11 08:08:38 2023 + +Initialized Ramulator. +** Heartbeat: 1% -- { 1000001 } -- 0.00 KIPS (500.00 KIPS) +** Heartbeat: 2% -- { 2000003 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 3% -- { 3000003 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 4% -- { 4000003 } -- 1000.00 KIPS (571.43 KIPS) +** Heartbeat: 5% -- { 5000006 } -- 500.00 KIPS (555.56 KIPS) +** Heartbeat: 6% -- { 6000008 } -- 500.00 KIPS (545.46 KIPS) +** Heartbeat: 7% -- { 7000009 } -- 1000.00 KIPS (583.33 KIPS) +** Heartbeat: 8% -- { 8000009 } -- 500.00 KIPS (571.43 KIPS) +** Heartbeat: 9% -- { 9000013 } -- 500.00 KIPS (562.50 KIPS) +** Heartbeat: 10% -- { 10000015 } -- 1000.00 KIPS (588.24 KIPS) +** Heartbeat: 11% -- { 11000016 } -- 500.00 KIPS (578.95 KIPS) +** Heartbeat: 12% -- { 12000021 } -- 500.00 KIPS (571.43 KIPS) +** Heartbeat: 13% -- { 13000024 } -- 1000.00 KIPS (590.91 KIPS) +** Heartbeat: 14% -- { 14000029 } -- 500.00 KIPS (583.33 KIPS) +** Heartbeat: 15% -- { 15000034 } -- 500.00 KIPS (576.92 KIPS) +** Heartbeat: 16% -- { 16000037 } -- 1000.00 KIPS (592.59 KIPS) +** Heartbeat: 17% -- { 17000037 } -- 500.00 KIPS (586.21 KIPS) +** Heartbeat: 18% -- { 18000042 } -- 500.00 KIPS (580.65 KIPS) +** Heartbeat: 19% -- { 19000042 } -- 1000.00 KIPS (593.75 KIPS) +** Heartbeat: 20% -- { 20000047 } -- 500.00 KIPS (588.24 KIPS) +** Heartbeat: 21% -- { 21000052 } -- 500.00 KIPS (583.33 KIPS) +** Heartbeat: 22% -- { 22000053 } -- 500.00 KIPS (578.95 KIPS) +** Heartbeat: 23% -- { 23000055 } -- 500.00 KIPS (575.00 KIPS) +** Heartbeat: 24% -- { 24000058 } -- 500.00 KIPS (571.43 KIPS) +** Heartbeat: 25% -- { 25000062 } -- 500.00 KIPS (568.18 KIPS) +** Heartbeat: 26% -- { 26000064 } -- 500.00 KIPS (565.22 KIPS) +** Heartbeat: 27% -- { 27000065 } -- 1000.00 KIPS (574.47 KIPS) +** Heartbeat: 28% -- { 28000065 } -- 500.00 KIPS (571.43 KIPS) +** Heartbeat: 29% -- { 29000067 } -- 500.00 KIPS (568.63 KIPS) +** Heartbeat: 30% -- { 30000068 } -- 500.00 KIPS (566.04 KIPS) +** Heartbeat: 31% -- { 31000073 } -- 500.00 KIPS (563.64 KIPS) +** Heartbeat: 32% -- { 32000074 } -- 500.00 KIPS (561.40 KIPS) +** Heartbeat: 33% -- { 33000079 } -- 500.00 KIPS (559.32 KIPS) +** Heartbeat: 34% -- { 34000079 } -- 500.00 KIPS (557.38 KIPS) +** Heartbeat: 35% -- { 35000081 } -- 500.00 KIPS (555.56 KIPS) +** Heartbeat: 36% -- { 36000082 } -- 500.00 KIPS (553.85 KIPS) +** Heartbeat: 37% -- { 37000087 } -- 500.00 KIPS (552.24 KIPS) +** Heartbeat: 38% -- { 38000089 } -- 500.00 KIPS (550.73 KIPS) +** Heartbeat: 39% -- { 39000090 } -- 1000.00 KIPS (557.14 KIPS) +** Heartbeat: 40% -- { 40000092 } -- 500.00 KIPS (555.56 KIPS) +** Heartbeat: 41% -- { 41000095 } -- 500.00 KIPS (554.06 KIPS) +** Heartbeat: 42% -- { 42000097 } -- 500.00 KIPS (552.63 KIPS) +** Heartbeat: 43% -- { 43000099 } -- 500.00 KIPS (551.28 KIPS) +** Heartbeat: 44% -- { 44000099 } -- 500.00 KIPS (550.00 KIPS) +** Heartbeat: 45% -- { 45000099 } -- 500.00 KIPS (548.78 KIPS) +** Heartbeat: 46% -- { 46000103 } -- 500.00 KIPS (547.62 KIPS) +** Heartbeat: 47% -- { 47000103 } -- 500.00 KIPS (546.51 KIPS) +** Heartbeat: 48% -- { 48000103 } -- 500.00 KIPS (545.46 KIPS) +** Heartbeat: 49% -- { 49000107 } -- 500.00 KIPS (544.45 KIPS) +** Heartbeat: 50% -- { 50000107 } -- 1000.00 KIPS (549.45 KIPS) +** Heartbeat: 51% -- { 51000108 } -- 500.00 KIPS (548.39 KIPS) +** Heartbeat: 52% -- { 52000108 } -- 500.00 KIPS (547.37 KIPS) +** Heartbeat: 53% -- { 53000111 } -- 500.00 KIPS (546.39 KIPS) +** Heartbeat: 54% -- { 54000112 } -- 500.00 KIPS (545.46 KIPS) +** Heartbeat: 55% -- { 55000117 } -- 500.00 KIPS (544.56 KIPS) +** Heartbeat: 56% -- { 56000119 } -- 500.00 KIPS (543.69 KIPS) +** Heartbeat: 57% -- { 57000122 } -- 500.00 KIPS (542.86 KIPS) +** Heartbeat: 58% -- { 58000125 } -- 500.00 KIPS (542.06 KIPS) +** Heartbeat: 59% -- { 59000125 } -- 500.00 KIPS (541.29 KIPS) +** Heartbeat: 60% -- { 60000128 } -- 500.00 KIPS (540.54 KIPS) +** Heartbeat: 61% -- { 61000128 } -- 1000.00 KIPS (544.64 KIPS) +** Heartbeat: 62% -- { 62000130 } -- 500.00 KIPS (543.86 KIPS) +** Heartbeat: 63% -- { 63000135 } -- 500.00 KIPS (543.10 KIPS) +** Heartbeat: 64% -- { 64000139 } -- 500.00 KIPS (542.37 KIPS) +** Heartbeat: 65% -- { 65000144 } -- 500.00 KIPS (541.67 KIPS) +** Heartbeat: 66% -- { 66000148 } -- 500.00 KIPS (540.98 KIPS) +** Heartbeat: 67% -- { 67000153 } -- 500.00 KIPS (540.32 KIPS) +** Heartbeat: 68% -- { 68000156 } -- 500.00 KIPS (539.68 KIPS) +** Heartbeat: 69% -- { 69000157 } -- 500.00 KIPS (539.06 KIPS) +** Heartbeat: 70% -- { 70000161 } -- 500.00 KIPS (538.46 KIPS) +** Heartbeat: 71% -- { 71000163 } -- 1000.00 KIPS (541.99 KIPS) +** Heartbeat: 72% -- { 72000164 } -- 500.00 KIPS (541.35 KIPS) +** Heartbeat: 73% -- { 73000169 } -- 500.00 KIPS (540.74 KIPS) +** Heartbeat: 74% -- { 74000171 } -- 500.00 KIPS (540.15 KIPS) +** Heartbeat: 75% -- { 75000173 } -- 500.00 KIPS (539.57 KIPS) +** Heartbeat: 76% -- { 76000177 } -- 500.00 KIPS (539.01 KIPS) +** Heartbeat: 77% -- { 77000180 } -- 500.00 KIPS (538.46 KIPS) +** Heartbeat: 78% -- { 78000183 } -- 500.00 KIPS (537.93 KIPS) +** Heartbeat: 79% -- { 79000186 } -- 500.00 KIPS (537.42 KIPS) +** Heartbeat: 80% -- { 80000188 } -- 500.00 KIPS (536.91 KIPS) +** Heartbeat: 81% -- { 81000188 } -- 500.00 KIPS (536.43 KIPS) +** Heartbeat: 82% -- { 82000189 } -- 1000.00 KIPS (539.47 KIPS) +** Heartbeat: 83% -- { 83000190 } -- 500.00 KIPS (538.96 KIPS) +** Heartbeat: 84% -- { 84000194 } -- 500.00 KIPS (538.46 KIPS) +** Heartbeat: 85% -- { 85000195 } -- 500.00 KIPS (537.98 KIPS) +** Heartbeat: 86% -- { 86000195 } -- 500.00 KIPS (537.50 KIPS) +** Heartbeat: 87% -- { 87000196 } -- 500.00 KIPS (537.04 KIPS) +** Heartbeat: 88% -- { 88000197 } -- 500.00 KIPS (536.59 KIPS) +** Heartbeat: 89% -- { 89000198 } -- 500.00 KIPS (536.15 KIPS) +** Heartbeat: 90% -- { 90000198 } -- 500.00 KIPS (535.72 KIPS) +** Heartbeat: 91% -- { 91000199 } -- 500.00 KIPS (535.30 KIPS) +** Heartbeat: 92% -- { 92000199 } -- 500.00 KIPS (534.88 KIPS) +** Heartbeat: 93% -- { 93000201 } -- 500.00 KIPS (534.48 KIPS) +** Heartbeat: 94% -- { 94000201 } -- 1000.00 KIPS (537.14 KIPS) +** Heartbeat: 95% -- { 95000204 } -- 500.00 KIPS (536.72 KIPS) +** Heartbeat: 96% -- { 96000207 } -- 500.00 KIPS (536.31 KIPS) +** Heartbeat: 97% -- { 97000207 } -- 500.00 KIPS (535.91 KIPS) +** Heartbeat: 98% -- { 98000207 } -- 500.00 KIPS (535.52 KIPS) +** Heartbeat: 99% -- { 99000207 } -- 500.00 KIPS (535.14 KIPS) +** Core 0 Finished: insts:100000000 cycles:40827371 time:12758553437500 -- 2.45 IPC (2.45 IPC) -- N/A KIPS (534.76 KIPS) +done +Scarab finished at Sun Jun 11 08:11:45 2023 + diff --git a/labs/LAB5/runs/exchange2-sms1/stream.stat.0.out b/labs/LAB5/runs/exchange2-sms1/stream.stat.0.out new file mode 100644 index 00000000..5ee40bab --- /dev/null +++ b/labs/LAB5/runs/exchange2-sms1/stream.stat.0.out @@ -0,0 +1,188 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 40827371 Instructions: 100000000 IPC: 2.44934 + +DCACHE_PREF_HIT 0 0 + +IFETCH_WB_FIRST_SCHEDULE 0 -nan% 0 -nan% +PREFETCH_LAST_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_PREF_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_LOW_OP_SCHEDULE 0 -nan% 0 -nan% +DEMAND_LAST_SCHEDULE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +SEND_MISS_REQ_QUEUE 1782 1782 + +L1_DATA_EVICT 0 0 + +STREAM_BUFFER_REQ 0 0 + +PREF_SEND_TO_MEM_REQ 0 -nan% 0 -nan% +PREF_SEND_TO_MEM_REQ_FAIL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +HIT_TRAIN_STREAM 135 62.500% 135 62.500% +MISS_TRAIN_STREAM 81 37.500% 81 37.500% + 216 100.000% 216 100.000% + 0.38 0.45 0.38 0.45 + +STREAM_TRAIN_CREATE 29 29 + +MEM_REQ_MISS_HWP_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_SW_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_IFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DSTORE_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DPRF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_WB_Q 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_BY_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_WB 0 -nan% 0 -nan% +PREF_HIT_BY_PREF 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_WB 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_L1_FILL 0 -nan% 0 -nan% +DEMAND_L1_FILL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TOUCH_L1_REPLACE 0 -nan% 0 -nan% +NO_TOUCH_L1_REPLACE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_REQ_QUE_FULL 0 0 + +STREAM_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +L2HIT_STREAM_PREF_REQ_QUE_FULL 0 0 + +L2HIT_HIT_TRAIN_STREAM 0 -nan% 0 -nan% +L2HIT_MISS_TRAIN_STREAM 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_TRAIN_CREATE 0 0 + +L2HIT_STREAM_BUFFER_REQ 0 0 + +L2HIT_STREAM_PREF_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_STREAM_PREF_DCACHE_INSERT 0 -nan% 0 -nan% +L2HIT_STREAM_L2_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_DCACHE_PORT_FULL 0 0 + +L2HIT_STREAM_PREF_L1_PORT_FULL 0 0 + +L2HIT_TRAIN_HIT_DEMAND 0 -nan% 0 -nan% +L2HIT_TRAIN_MISS_REQ 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_TRAIN_FILTER_MISS 0 -nan% 0 -nan% +L2HIT_TRAIN_FILTER_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_PREF_REQ_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_PREF_REQ_DCACHE_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_L2SEND_Q_FULL 0 -nan% 0 -nan% +L2HIT_L2SEND_Q_ENTER 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_MEM_REQ 0 0 + +REMOVE_REDUNDANT_STREAM_STAT 0 0 + +REPLACE_OLD_STREAM 13 13 + +REQ_SEND_QUEUE_STALL 0 0 + +STREAM_ENTER_RA 0 0 + +CORE_STREAM_LENGTH_0 5 38.462% 5 38.462% +CORE_STREAM_LENGTH_10 2 15.385% 2 15.385% +CORE_STREAM_LENGTH_20 1 7.692% 1 7.692% +CORE_STREAM_LENGTH_30 3 23.077% 3 23.077% +CORE_STREAM_LENGTH_40 0 0.000% 0 0.000% +CORE_STREAM_LENGTH_50 0 0.000% 0 0.000% +CORE_STREAM_LENGTH_60 0 0.000% 0 0.000% +CORE_STREAM_LENGTH_70 1 7.692% 1 7.692% +CORE_STREAM_LENGTH_80 0 0.000% 0 0.000% +CORE_STREAM_LENGTH_90 0 0.000% 0 0.000% +CORE_STREAM_LENGTH_100_P 1 7.692% 1 7.692% + 13 100.000% 13 100.000% + 2.31 2.76 2.31 2.76 + +CORE_CUM_STREAM_LENGTH_0 38 10.053% 38 10.053% +CORE_CUM_STREAM_LENGTH_10 33 8.730% 33 8.730% +CORE_CUM_STREAM_LENGTH_20 23 6.085% 23 6.085% +CORE_CUM_STREAM_LENGTH_30 104 27.513% 104 27.513% +CORE_CUM_STREAM_LENGTH_40 0 0.000% 0 0.000% +CORE_CUM_STREAM_LENGTH_50 0 0.000% 0 0.000% +CORE_CUM_STREAM_LENGTH_60 0 0.000% 0 0.000% +CORE_CUM_STREAM_LENGTH_70 77 20.370% 77 20.370% +CORE_CUM_STREAM_LENGTH_80 0 0.000% 0 0.000% +CORE_CUM_STREAM_LENGTH_90 0 0.000% 0 0.000% +CORE_CUM_STREAM_LENGTH_100_P 103 27.249% 103 27.249% + 378 100.000% 378 100.000% + 5.19 4.22 5.19 4.22 + +CORE_STREAM_TRAIN_HITS_0 8 61.538% 8 61.538% +CORE_STREAM_TRAIN_HITS_10 3 23.077% 3 23.077% +CORE_STREAM_TRAIN_HITS_20 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_30 1 7.692% 1 7.692% +CORE_STREAM_TRAIN_HITS_40 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_50 1 7.692% 1 7.692% +CORE_STREAM_TRAIN_HITS_60 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_70 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_80 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_90 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_100_P 0 0.000% 0 0.000% + 13 100.000% 13 100.000% + 0.85 1.35 0.85 1.35 + +CORE_CUM_STREAM_TRAIN_HITS_0 49 26.203% 49 26.203% +CORE_CUM_STREAM_TRAIN_HITS_10 48 25.668% 48 25.668% +CORE_CUM_STREAM_TRAIN_HITS_20 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_30 36 19.251% 36 19.251% +CORE_CUM_STREAM_TRAIN_HITS_40 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_50 54 28.877% 54 28.877% +CORE_CUM_STREAM_TRAIN_HITS_60 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_70 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_80 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_90 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_100_P 0 0.000% 0 0.000% + 187 100.000% 187 100.000% + 2.28 1.64 2.28 1.64 + +CORE_STREAM_TRAIN_CREATE 29 29 + + + diff --git a/labs/LAB5/runs/leela_s_base-sms0/PARAMS.in b/labs/LAB5/runs/leela_s_base-sms0/PARAMS.in new file mode 100644 index 00000000..2593c2b8 --- /dev/null +++ b/labs/LAB5/runs/leela_s_base-sms0/PARAMS.in @@ -0,0 +1,226 @@ +# File : PARAMS.kaby_lake +# Date : 03/06/19 +# Description : Kaby Lake Configuration +# +# Based on documentation found here: +# https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake + +## Simulation Parameters +--mode full +--model cmp +--sim_limit none + +## Core Parameters + +# Femptoseconds, 3.2GHz, used for energy estimates. +--chip_cycle_time 312500 + + +### Fetch Stage +--fetch_off_path_ops 1 +--fetch_across_cache_lines 1 + +# Will break the packet upon a taken branch. +--fetch_break_on_taken 1 + +# Number of bubble cycles to wait after taken branch. +--fetch_taken_bubble_cycles 0 + + +#### ICache +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 + +### Branch Predictor +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_mech tagescl + + +#### BTB + +# BTB model to use. +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 + +# Allow the BTB to be updated by off path ops. +--btb_off_path_writes 1 + + +#### CRS + +# Enable return stack +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 + +### iBP +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged + # iBTB Model. tc_tagless, tc_tagged, tc_hybrid. +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 + +### Decode Stage +--decode_cycles 5 + + +### Map Stage +--map_cycles 5 + + +### Issue Stage + +# Max number of instructions to be fetched, decoded, renamed, and issued per cycle. +--issue_width 6 + +--rs_fill_width 0 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 + + +### Exec Stage + +### DCache +--dcache_size 32768 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--dcache_assoc 4 +--dcache_line_size 64 + +### Reorder/Retire Stage + +# Max number of instructions to be retired per cycle. +--node_ret_width 6 +--node_table_size 224 + +# Do not keep stores in RSVs on cache misses; TODO: confirm what this knob does +--stores_do_not_block_window 1 + +# TODO: confirm what this knob does +--prefs_do_not_block_window 1 + + +## Uncore + +### Mid-level cache + +# Enable use of a midlevel cache between i/d and L1 +--mlc_present 0 + +### LLC +--l1_size 1048576 +--l1_banks 1 +--l1_cycles 18 +--l1_assoc 8 +--l1_line_size 64 +--l1_interleave_factor 64 + + +### Prefetcher +--pref_framework_on 1 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--pref_shared_queues 0 +--pref_train_on_pref_misses 0 +--pref_oracle_train 0 +--pref_ul1req_queue_overwrite_on_full 1 + +--stream_length 64 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 + +--pref_throttlefb_on=1 +--pref_acc_thresh_1=0.75 +--pref_acc_thresh_2=0.4 +--pref_acc_thresh_3=0.4 +--pref_timely_thresh=0.01 +--pref_polpf_thresh=0.005 +--pref_update_interval=8192 + +--mem_req_buffer_pref_watermark 4 +--promote_to_higher_priority_mem_req_type 1 + +### Memory +--addr_translation random + +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 + +--mem_req_buffer_entries 32 +--mem_l1_fill_queue_entries 32 +--va_page_size_bytes 4096 +--bus_width_in_bytes 8 + +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 + +## Other + + +### Debug +--debug_inst_start 0 +--debug_inst_stop -1 +--debug_cycle_start 0 +--debug_cycle_stop -1 + + +## Stats and Params +--dump_params 1 +--dump_stats 1 +--dump_trace 0 + +#################################### +--set_off_path_confirmed 1 + +--order_beyond_bus 1 + +--mem_ooo_stores 1 +--mem_obey_store_dep 1 diff --git a/labs/LAB5/runs/leela_s_base-sms0/PARAMS.out b/labs/LAB5/runs/leela_s_base-sms0/PARAMS.out new file mode 100644 index 00000000..71ae9d6d --- /dev/null +++ b/labs/LAB5/runs/leela_s_base-sms0/PARAMS.out @@ -0,0 +1,908 @@ +--mode full +--model cmp +--frontend memtrace +--inst_limit 100000000 +--sim_limit none +--dump_params 1 +--dump_stats 1 +--dump_trace 0 +--mlc_present 0 +--l1_size 1048576 +--l1_assoc 8 +--l1_line_size 64 +--l1_cycles 18 +--l1_banks 1 +--l1_interleave_factor 64 +--va_page_size_bytes 4096 +--addr_translation random +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 +--dcache_size 32768 +--dcache_assoc 4 +--dcache_line_size 64 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--mem_ooo_stores 1 +--mem_obey_store_dep 1 +--mem_req_buffer_entries 32 +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 +--promote_to_higher_priority_mem_req_type 1 +--mem_req_buffer_pref_watermark 4 +--mem_l1_fill_queue_entries 32 +--order_beyond_bus 1 +--set_off_path_confirmed 1 +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--bus_width_in_bytes 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 +--chip_cycle_time 312500 +--issue_width 6 +--rs_fill_width 0 +--node_table_size 224 +--node_ret_width 6 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 +--decode_cycles 5 +--map_cycles 5 +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--fetch_across_cache_lines 1 +--fetch_off_path_ops 0 +--fetch_break_on_taken 1 +--fetch_taken_bubble_cycles 0 +--stores_do_not_block_window 1 +--prefs_do_not_block_window 1 +--cbp_trace_r0 /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir/trace/drmemtrace.leela_s_base.mytest-m64.555086.2935.trace.gz +--memtrace_modules_log /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir/raw +--debug_cycle_start 0 +--debug_cycle_stop -1 +--debug_inst_start 0 +--debug_inst_stop -1 +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--bp_mech tagescl +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 +--btb_off_path_writes 1 +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_length 64 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 +--pref_framework_on 1 +--pref_shared_queues 0 +--pref_ul1req_queue_overwrite_on_full 1 +--pref_train_on_pref_misses 0 +--pref_oracle_train_on 0 +--pref_throttlefb_on 1 +--pref_acc_thresh_1 0.75 +--pref_acc_thresh_2 0.4 +--pref_acc_thresh_3 0.4 +--pref_update_interval 8192 +--pref_timely_thresh 0.01 +--pref_polpf_thresh 0.005 +--pref_sms_on 0 +1 1 1 1 1 1 1 + +--- Cut out everything below to use this file as PARAMS.in --- + +Parameter status at compile time and values supplied on the command line: + +SIM_MODE 0 full +SIM_MODEL 0 cmp +FRONTEND FE_PIN_EXEC_DRIVEN memtrace +INST_LIMIT NULL 100000000 +SIM_LIMIT "none" none +FORWARD_PROGRESS_LIMIT 100000000 +FORWARD_PROGRESS_INTERVAL 10000 +FAST_FORWARD 0 +FAST_FORWARD_UNTIL_ADDR 0 +FAST_FORWARD_TRACE_INS 0 +WARMUP 0 +HEARTBEAT_INTERVAL 1000000 +NUM_HEARTBEATS 0 +FILE_TAG "" +OUTPUT_DIR "." +STATUS_FILE NULL +BINDIR NULL +DUMP_PARAMS TRUE 1 +DUMP_STATS TRUE 1 +DUMP_TRACE FALSE 0 +CLEAR_STATS "never" +STATS_TO_TRACE NULL +STAT_TRACE_FILE "stats.trace" +STAT_TRACE_INTERVAL "i:100000" +PIPEVIEW FALSE +PIPEVIEW_FILE "pipeview" +MEMVIEW FALSE +MEMVIEW_FILE "memview.out" +MEMVIEW_START "never" +INST_HASH_TABLE_SIZE 500021 const +STDOUT_FILE NULL +STDERR_FILE NULL +PIN_EXEC_DRIVEN_FE_SOCKET "./pin_exec_driven_fe_socket.temp" +PRINT_PID FALSE +USE_UNSURE_FREE_LISTS FALSE +OPTIMIZER2_MAX_NUM_SLAVES 64 +OPTIMIZER2_PERFECT_MEMORYLESS FALSE +EXIT_COND 0 +ENABLE_SWPRF FALSE +MLC_PRESENT FALSE 0 +MLC_SIZE (512 * 1024) +MLC_ASSOC 4 +MLC_LINE_SIZE 64 +MLC_CYCLES 12 +PERFECT_MLC FALSE +MLC_READ_PORTS 1 +MLC_WRITE_PORTS 1 +MLC_BANKS 8 +MLC_INTERLEAVE_FACTOR 64 +MLC_CACHE_REPL_POLICY 0 +MLC_WRITE_THROUGH FALSE +PREFETCH_UPDATE_LRU_MLC TRUE +FORCE_L1_MISS FALSE +L1_SIZE (4 * 1024 * 1024) 1048576 +L1_ASSOC 8 8 +L1_LINE_SIZE 64 64 +L1_CYCLES 24 18 +PERFECT_L1 FALSE +PRIVATE_L1 FALSE +L1_READ_PORTS 1 +L1_WRITE_PORTS 1 +L1_BANKS 8 1 +L1_INTERLEAVE_FACTOR 64 64 +L1_CACHE_REPL_POLICY 0 +L1_WRITE_THROUGH FALSE +L1_IGNORE_WB FALSE +L1_USE_CORE_FREQ FALSE +MARK_L1_MISSES TRUE +PREFETCH_UPDATE_LRU_L1 TRUE +MEMORY_RANDOM_ADDR FALSE +VA_PAGE_SIZE_BYTES 4096 4096 +NUM_ADDR_NON_SIGN_EXTEND_BITS 48 +ADDR_TRANSLATION 0 random +CONSTANT_MEMORY_LATENCY FALSE +MEMORY_CYCLES 100 +STALL_MEM_REQS_ONLY FALSE +ICACHE_SIZE (64 * 1024) 32768 +ICACHE_ASSOC 4 4 +ICACHE_LINE_SIZE 64 64 +PERFECT_ICACHE FALSE +ICACHE_READ_PORTS 2 +ICACHE_WRITE_PORTS 1 +ICACHE_BANKS 8 +ICACHE_REPL 0 +DCACHE_SIZE (64 * 1024) 32768 +DCACHE_ASSOC 1 4 +DCACHE_LINE_SIZE 64 64 +DCACHE_CYCLES 2 +PERFECT_DCACHE FALSE +DCACHE_READ_PORTS 8 2 +DCACHE_WRITE_PORTS 1 1 +DCACHE_BANKS 1 1 +DCACHE_REPL 0 +DCACHE_REPL_PREF_THRESH 1 +MEM_OOO_STORES TRUE 1 +MEM_OBEY_STORE_DEP TRUE 1 +PREF_INSERT_LRU FALSE +PREF_INSERT_MIDDLE FALSE +PREF_INSERT_LOWQTR FALSE +PREF_INSERT_DYNACC FALSE +MEM_REQ_BUFFER_ENTRIES 32 32 +PRIVATE_MSHR_ON TRUE +MEM_PRIORITY_IFETCH 0 0 +MEM_PRIORITY_DFETCH 0 1 +MEM_PRIORITY_DSTORE 0 2 +MEM_PRIORITY_IPRF 9 3 +MEM_PRIORITY_DPRF 10 4 +MEM_PRIORITY_WB 0 5 +MEM_PRIORITY_WB_NODIRTY 0 5 +PROMOTE_TO_HIGHER_PRIORITY_MEM_REQ_TYPE FALSE 1 +MEM_REQ_BUFFER_PREF_WATERMARK 0 4 +MEM_REQ_BUFFER_WB_VALVE 2 +MEM_L1_FILL_QUEUE_ENTRIES 32 32 +MEM_BUS_OUT_QUEUE_PARTITION_ENABLE FALSE +MEM_MEM_QUEUE_PARTITION_ENABLE FALSE +MEM_BUS_OUT_QUEUE_AS_FIFO TRUE +OLDEST_FIRST_TO_MEM_QUEUE TRUE +ROUND_ROBIN_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE_TH 0 +L1_CYCLE_TIME 312500 +MLCQ_TO_L1Q_TRANSFER_LATENCY 1 +L1Q_TO_FSB_TRANSFER_LATENCY 1 +PRIORITIZE_PREFETCHES_WITH_UNIQUE FALSE +KICKOUT_PREFETCHES FALSE +KICKOUT_LOOK_FOR_OLDEST_FIRST FALSE +KICKOUT_OLDEST_PREFETCH FALSE +KICKOUT_OLDEST_PREFETCH_WITHIN_BANK FALSE +ORDER_BEYOND_BUS FALSE 1 +ALL_FIFO_QUEUES FALSE +QUEUE_MLC_SIZE 0 +QUEUE_L1_SIZE 0 +QUEUE_BUS_OUT_SIZE 0 +QUEUE_CORE_FILL_SIZE 0 +ALLOW_TYPE_MATCHES FALSE +STREAM_PREFETCH_ON FALSE +DC_PREF_CACHE_ENABLE FALSE +DC_PREF_CACHE_CYCLE 0 +PREF_INSERT_DCACHE_IMM TRUE +DC_PREF_CACHE_SIZE (64 * 1024) +DC_PREF_CACHE_ASSOC 4 +DC_PREF_ONLY_L1HIT FALSE +PREF_CACHE_USE_RDY_CYCLE FALSE +IC_PREF_CACHE_ENABLE FALSE +IC_PREF_CACHE_SIZE (64 * 1024) +IC_PREF_CACHE_ASSOC 4 +L1_PREF_CACHE_ENABLE FALSE +L1_PREF_CACHE_SIZE (1024 * 1024) +L1_PREF_CACHE_ASSOC 8 +SET_OFF_PATH_CONFIRMED FALSE 1 +USE_CONFIRMED_OFF FALSE +PREFCACHE_MOVE_OFFPATH FALSE +CACHE_STAT_ENABLE FALSE +PREF_DCACHE_HIT_FILL_L1 TRUE +PREF_ICACHE_HIT_FILL_L1 TRUE +CRITICAL_ACCESS_PLOT_ENABLE FALSE +CRITICAL_ACCESS_PLOT_FILE "critical_access_plot.dat" +ROUND_ROBIN_TO_L1 FALSE +PREF_I_TOGETHER FALSE +ONE_MORE_CACHE_LINE_ENABLE FALSE +L1_STATIC_PARTITION_ENABLE 0 +L1_STATIC_PARTITION NULL +L1_DYNAMIC_PARTITION_ENABLE FALSE +L1_DYNAMIC_PARTITION_POLICY 0 +PARTITION_UMON_DSS_PREF_ENABLE FALSE +L1_CACHE_HIT_POSITION_COLLECT FALSE +L1_PART_ON FALSE +L1_PART_TRIGGER "c:1000000" +L1_PART_START "t:0" +L1_PART_WARMUP FALSE +L1_PART_SHADOW_WARMUP FALSE +L1_PART_METRIC 0 +L1_PART_SEARCH 0 +L1_PART_USE_STALLING TRUE +L1_PART_FILL_DELAY 0 +L1_SHADOW_TAGS_MODULO 1 +HIER_MSHR_ON FALSE +PERF_PRED_ENABLE FALSE +PERF_PRED_MECH PERF_PRED_CP +PERF_PRED_REQ_LATENCY_MECH PERF_PRED_REQ_LATENCY_MECH_REQ_LATENCY +PERF_PRED_COUNT_ALL FALSE +PERF_PRED_COUNT_INST_MISSES TRUE +PERF_PRED_COUNT_PREFETCHES FALSE +PERF_PRED_COUNT_OFFPATH_REQS FALSE +PERF_PRED_COUNT_BW_REQS TRUE +PERF_PRED_UPDATE_MEM_REQ_TYPE FALSE +PERF_PRED_SLACK_PERIOD_SIZE 32 +PERF_PRED_REQS_FINISH_AT_FILL FALSE +PERF_PRED_MEM_UTIL_VIA_BUS_BW FALSE +PERF_PRED_CHIP_UTIL_VIA_MEM_STALL FALSE +DUMB_MODEL_AVG_REQ_DISTANCE 100 +DUMB_MODEL_RANDOMIZE_DISTANCE FALSE +DUMB_MODEL_AVG_REQ_DISTANCE_PER_CORE NULL +DUMB_MODEL_AVG_ROW_HITS 1 +DUMB_MODEL_AVG_ROW_HITS_PER_CORE NULL +DUMB_MODEL_MLP 1 +DUMB_MODEL_MLP_PER_CORE NULL +RAMULATOR_STANDARD "DDR4" DDR4 +RAMULATOR_SPEED "DDR4_2400R" DDR4_2400R +RAMULATOR_ORG "DDR4_8Gb_x8" DDR4_8Gb_x8 +RAMULATOR_CHANNELS 1 1 +RAMULATOR_RANKS 1 1 +RAMULATOR_BANKGROUPS 4 4 +RAMULATOR_BANKS 4 4 +RAMULATOR_CHIP_WIDTH 8 8 +BUS_WIDTH_IN_BYTES 8 8 +RAMULATOR_ROWS 65536 65536 +RAMULATOR_COLS 1024 1024 +RAMULATOR_SCHEDULING_POLICY "FRFCFS_Cap" FRFCFS_Cap +RAMULATOR_READQ_ENTRIES 32 32 +RAMULATOR_WRITEQ_ENTRIES 32 32 +RAMULATOR_REC_CMD_TRACE "off" FALSE +RAMULATOR_PRINT_CMD_TRACE "off" FALSE +RAMULATOR_USE_REST_OF_ADDR_AS_ROW_ADDR "on" +RAMULATOR_TCK 833333 833333 +RAMULATOR_TCL 16 16 +RAMULATOR_TCCD 6 6 +RAMULATOR_TCCDS 4 4 +RAMULATOR_TCCDL 6 6 +RAMULATOR_TCWL 12 12 +RAMULATOR_TBL 4 4 +RAMULATOR_TWTR 9 9 +RAMULATOR_TWTRS 3 3 +RAMULATOR_TWTRL 9 9 +RAMULATOR_TRP 16 16 +RAMULATOR_TRPpb 16 16 +RAMULATOR_TRPab 16 16 +RAMULATOR_TRCD 16 16 +RAMULATOR_TRCDR 16 16 +RAMULATOR_TRCDW 16 16 +RAMULATOR_TRAS 39 39 +DRAM_TECH_IN_NM 32 32 +DVFS_ON FALSE +DVFS_METRIC DVFS_METRIC_NUM_ELEMS +DVFS_CONFIGS NULL +DVFS_CONFIG_FILE NULL +DVFS_START "t:0" +DVFS_PERIOD "t:312500000000" +DVFS_LOG TRUE +DVFS_INDIVIDUAL_CORES FALSE +DVFS_CHIP_LEVEL FALSE +DVFS_STATIC NULL +DVFS_FORCE_CONFIG NULL +DVFS_REPLAY_CONFIG_TRACE NULL +DVFS_USE_ORACLE FALSE +DVFS_USE_BW_SHARING FALSE +DVFS_USE_DRAM_SHARING FALSE +DVFS_USE_STALL_TIME FALSE +DVFS_DRAM_SHARING_SOLVER_BIN NULL +DVFS_DRAM_SHARING_SOLVER_STRICT TRUE +DVFS_BW_SHARING_BUS_UTIL_THRESH 0.95 +DVFS_BW_SHARING_MAX_REQS 28.0 +DVFS_BW_SHARING_MAX_RW_COST 0.25 +DVFS_BW_SHARING_NO_PREF_STALL TRUE +DVFS_BW_SHARING_CRIT_STATS TRUE +DVFS_COUNT_L1_ACCESS_STALL FALSE +NUM_CORES 1 +CHIP_CYCLE_TIME 312500 312500 +CORE_0_CYCLE_TIME 312500 +CORE_1_CYCLE_TIME 312500 +CORE_2_CYCLE_TIME 312500 +CORE_3_CYCLE_TIME 312500 +CORE_4_CYCLE_TIME 312500 +CORE_5_CYCLE_TIME 312500 +CORE_6_CYCLE_TIME 312500 +CORE_7_CYCLE_TIME 312500 +CORE_8_CYCLE_TIME 312500 +CORE_9_CYCLE_TIME 312500 +CORE_10_CYCLE_TIME 312500 +CORE_11_CYCLE_TIME 312500 +CORE_12_CYCLE_TIME 312500 +CORE_13_CYCLE_TIME 312500 +CORE_14_CYCLE_TIME 312500 +CORE_15_CYCLE_TIME 312500 +CORE_16_CYCLE_TIME 312500 +CORE_17_CYCLE_TIME 312500 +CORE_18_CYCLE_TIME 312500 +CORE_19_CYCLE_TIME 312500 +CORE_20_CYCLE_TIME 312500 +CORE_21_CYCLE_TIME 312500 +CORE_22_CYCLE_TIME 312500 +CORE_23_CYCLE_TIME 312500 +CORE_24_CYCLE_TIME 312500 +CORE_25_CYCLE_TIME 312500 +CORE_26_CYCLE_TIME 312500 +CORE_27_CYCLE_TIME 312500 +CORE_28_CYCLE_TIME 312500 +CORE_29_CYCLE_TIME 312500 +CORE_30_CYCLE_TIME 312500 +CORE_31_CYCLE_TIME 312500 +CORE_32_CYCLE_TIME 312500 +CORE_33_CYCLE_TIME 312500 +CORE_34_CYCLE_TIME 312500 +CORE_35_CYCLE_TIME 312500 +CORE_36_CYCLE_TIME 312500 +CORE_37_CYCLE_TIME 312500 +CORE_38_CYCLE_TIME 312500 +CORE_39_CYCLE_TIME 312500 +CORE_40_CYCLE_TIME 312500 +CORE_41_CYCLE_TIME 312500 +CORE_42_CYCLE_TIME 312500 +CORE_43_CYCLE_TIME 312500 +CORE_44_CYCLE_TIME 312500 +CORE_45_CYCLE_TIME 312500 +CORE_46_CYCLE_TIME 312500 +CORE_47_CYCLE_TIME 312500 +CORE_48_CYCLE_TIME 312500 +CORE_49_CYCLE_TIME 312500 +CORE_50_CYCLE_TIME 312500 +CORE_51_CYCLE_TIME 312500 +CORE_52_CYCLE_TIME 312500 +CORE_53_CYCLE_TIME 312500 +CORE_54_CYCLE_TIME 312500 +CORE_55_CYCLE_TIME 312500 +CORE_56_CYCLE_TIME 312500 +CORE_57_CYCLE_TIME 312500 +CORE_58_CYCLE_TIME 312500 +CORE_59_CYCLE_TIME 312500 +CORE_60_CYCLE_TIME 312500 +CORE_61_CYCLE_TIME 312500 +CORE_62_CYCLE_TIME 312500 +CORE_63_CYCLE_TIME 312500 +ISSUE_WIDTH 4 6 +RS_FILL_WIDTH 8 0 +NODE_TABLE_SIZE 256 224 +NODE_RET_WIDTH 4 6 +NODE_RETIRE_RATE 10 +RS_SIZES "256" 97 +RS_CONNECTIONS "xF" 0 +FU_TYPES "0, 0, 0, 0" 0 0 0 0 0 0 0 0 +DECODE_CYCLES 1 5 +MAP_CYCLES 1 5 +EXTRA_RECOVERY_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after recovery. +EXTRA_REDIRECT_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after redirect. +EXTRA_CALLSYS_CYCLES 20 const +DIE_ON_CALLSYS FALSE +DIE_ON_RET_STALL_THRESH 0 +DIE_ON_RET_STALL_CORE 0 +DIE_ON_MEM_BLOCK_THRESH 0 +DIE_ON_MEM_BLOCK_CORE 0 +FETCH_ACROSS_CACHE_LINES FALSE 1 +FETCH_OFF_PATH_OPS TRUE 0 +FETCH_BREAK_ON_TAKEN FALSE 1 +FETCH_TAKEN_BUBBLE_CYCLES 0 0 +WP_COLLECT_STATS FALSE +SWITCH_IC_FETCH_ON_RECOVERY TRUE +OP_INV_DELAY 1 +OP_NOP_DELAY 1 +OP_CF_DELAY 1 +OP_MOV_DELAY 1 +OP_CMOV_DELAY 1 +OP_LDA_DELAY 1 +OP_IMEM_DELAY 1 +OP_IADD_DELAY 1 +OP_IMUL_DELAY 3 +OP_IDIV_DELAY -20 +OP_ICMP_DELAY 1 +OP_LOGIC_DELAY 1 +OP_SHIFT_DELAY 1 +OP_FMEM_DELAY 1 +OP_FCVT_DELAY 3 +OP_FADD_DELAY 3 +OP_FMUL_DELAY 5 +OP_FMA_DELAY 5 +OP_FDIV_DELAY -20 +OP_FCMP_DELAY 3 +OP_FCMOV_DELAY 1 +OP_GATHER_DELAY 12 +OP_SCATTER_DELAY 18 +OP_PIPELINED_FAST_DELAY 2 +OP_PIPELINED_MEDIUM_DELAY 5 +OP_PIPELINED_SLOW_DELAY 10 +OP_NOTPIPELINED_MEDIUM_DELAY -5 +OP_NOTPIPELINED_SLOW_DELAY -20 +OP_NOTPIPELINED_VERY_SLOW_DELAY -100 +UNIFORM_OP_DELAY 0 +STALL_ON_WAIT_MEM TRUE +STORES_DO_NOT_BLOCK_WINDOW FALSE 1 +PREFS_DO_NOT_BLOCK_WINDOW FALSE 1 +OBEY_REG_DEP TRUE +OLDEST_FIRST_SCHED FALSE +FIND_EMPTIEST_RS FALSE +TRACK_L1_MISS_DEPS FALSE +CBP_TRACE_R0 NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir/trace/drmemtrace.leela_s_base.mytest-m64.555086.2935.trace.gz +CBP_TRACE_R1 NULL +CBP_TRACE_R2 NULL +CBP_TRACE_R3 NULL +CBP_TRACE_R4 NULL +CBP_TRACE_R5 NULL +CBP_TRACE_R6 NULL +CBP_TRACE_R7 NULL +CBP_TRACE_R8 NULL +CBP_TRACE_R9 NULL +CBP_TRACE_R10 NULL +CBP_TRACE_R11 NULL +CBP_TRACE_R12 NULL +CBP_TRACE_R13 NULL +CBP_TRACE_R14 NULL +CBP_TRACE_R15 NULL +CBP_TRACE_R16 NULL +CBP_TRACE_R17 NULL +CBP_TRACE_R18 NULL +CBP_TRACE_R19 NULL +CBP_TRACE_R20 NULL +CBP_TRACE_R21 NULL +CBP_TRACE_R22 NULL +CBP_TRACE_R23 NULL +CBP_TRACE_R24 NULL +CBP_TRACE_R25 NULL +CBP_TRACE_R26 NULL +CBP_TRACE_R27 NULL +CBP_TRACE_R28 NULL +CBP_TRACE_R29 NULL +CBP_TRACE_R30 NULL +CBP_TRACE_R31 NULL +CBP_TRACE_R32 NULL +CBP_TRACE_R33 NULL +CBP_TRACE_R34 NULL +CBP_TRACE_R35 NULL +CBP_TRACE_R36 NULL +CBP_TRACE_R37 NULL +CBP_TRACE_R38 NULL +CBP_TRACE_R39 NULL +CBP_TRACE_R40 NULL +CBP_TRACE_R41 NULL +CBP_TRACE_R42 NULL +CBP_TRACE_R43 NULL +CBP_TRACE_R44 NULL +CBP_TRACE_R45 NULL +CBP_TRACE_R46 NULL +CBP_TRACE_R47 NULL +CBP_TRACE_R48 NULL +CBP_TRACE_R49 NULL +CBP_TRACE_R50 NULL +CBP_TRACE_R51 NULL +CBP_TRACE_R52 NULL +CBP_TRACE_R53 NULL +CBP_TRACE_R54 NULL +CBP_TRACE_R55 NULL +CBP_TRACE_R56 NULL +CBP_TRACE_R57 NULL +CBP_TRACE_R58 NULL +CBP_TRACE_R59 NULL +CBP_TRACE_R60 NULL +CBP_TRACE_R61 NULL +CBP_TRACE_R62 NULL +CBP_TRACE_R63 NULL +MEMTRACE_MODULES_LOG NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir/raw +DUMB_CORE_ON FALSE +DUMB_CORE 1 +DEBUG_CYCLE_START 0 0 +DEBUG_CYCLE_STOP 0 -1 +DEBUG_TIME_START 0 +DEBUG_TIME_STOP 0 +DEBUG_INST_START 0 0 +DEBUG_INST_STOP 0 -1 +DEBUG_OP_START 0 +DEBUG_OP_STOP 0 +DEBUG_CACHE_LIB FALSE +DEBUG_HASH_LIB FALSE +DEBUG_LIST_LIB FALSE +DEBUG_PORT_LIB FALSE +DEBUG_BUS_LIB FALSE +DEBUG_OP_POOL FALSE +DEBUG_ORACLE FALSE +DEBUG_FRONTEND FALSE +DEBUG_ADDR_TRANS FALSE +DEBUG_BP FALSE +DEBUG_BP_DIR FALSE +DEBUG_BTB FALSE +DEBUG_CRS FALSE +DEBUG_MAP FALSE +DEBUG_MEMORY FALSE +DEBUG_REPLAY FALSE +DEBUG_FREQ FALSE +DEBUG_MODEL FALSE +DEBUG_THREAD FALSE +DEBUG_ICACHE_STAGE FALSE +DEBUG_DECODE_STAGE FALSE +DEBUG_MAP_STAGE FALSE +DEBUG_NODE_STAGE FALSE +DEBUG_EXEC_STAGE FALSE +DEBUG_DCACHE_STAGE FALSE +DEBUG_RETIRED_UOPS FALSE +DEBUG_EXC_INSERTS FALSE +DEBUG_BP_CONF FALSE +DEBUG_ONPATH_CONF FALSE +DEBUG_STREAM FALSE +DEBUG_STREAM_MEM FALSE +DEBUG_WAY FALSE +DEBUG_L2MARKV FALSE +DEBUG_L2L1PREF FALSE +DEBUG_PERF_PRED FALSE +DEBUG_POWER_UTILS FALSE +DEBUG_DVFS FALSE +DEBUG_TRACE_READ FALSE +DEBUG_INST_FIELDS FALSE +DEBUG_OP_FIELDS FALSE +DEBUG_PIN_EXEC_DRIVEN FALSE +DEBUG_CACHE_PART FALSE +DEBUG_OPTIMIZER2 FALSE +DEBUG_PREF FALSE +PERFECT_BP FALSE +PERFECT_BTB FALSE +PERFECT_IBP FALSE +PERFECT_CRS FALSE +PERFECT_CBR_BTB FALSE +PERFECT_NT_BTB FALSE +CFS_PER_CYCLE 3 6 # Number of branches that can be predicted in a single cycle +UPDATE_BP_OFF_PATH FALSE 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +BP_UPDATE_AT_RETIRE FALSE 0 # Update the BP at retire. If false, update at the end of exec. +BP_MECH 0 tagescl +LATE_BP_MECH NUM_BP +LATE_BP_LATENCY 5 +HIST_LENGTH 16 +PHT_CTR_BITS 2 const +BHT_ENTRIES (4 * 1024) +BHT_ASSOC 4 +HYBRIDS_INDEX_LENGTH 16 +HYBRIDG_HIST_LENGTH 16 +HYBRIDP_HIST_LENGTH 16 +FILTER_INDEX_LENGTH 16 +USE_FILTER FALSE +INF_HYBRIDGP FALSE +BP_HASH_TOS FALSE +IBTB_HASH_TOS FALSE +BTB_MECH 0 generic +BTB_ENTRIES (4 * 1024) 4096 +BTB_ASSOC 4 4 +BTB_OFF_PATH_WRITES TRUE 1 +ENABLE_CRS TRUE 1 +CRS_ENTRIES 32 32 +CRS_REALISTIC 0 1 +ENABLE_IBP TRUE 1 # Enable the indirect branch predictor +USE_PAT_HIST TRUE +IBTB_MECH 1 tc_tagged +IBTB_HIST_LENGTH 16 +IBTB_OFF_PATH_WRITES TRUE 1 # Allow off path ops to update the ibtb. +TARGETS_IN_HIST 4 +TC_ENTRIES (4 * 1024) 4096 +TC_ASSOC 4 4 +NUM_CORR_BRANCHES 3 +SEL_HIST_BP_ENTRIES 8192 +SEL_HIST_LENGTH 16 +SEL_HIST_DYN_CNT_TH 16 +SEL_HIST_MISPRED_TH 4 +ENABLE_BP_CONF FALSE +CONF_MECH 0 +PERF_BP_CONF_PRED FALSE +BPC_BITS 16 +BPC_MECH 1 +BPC_CTR_RESET TRUE +BPC_CIT_BITS 8 +BPC_CIT_TH 50 +BPC_CTR_BITS 3 +OPC_COUNT_ZEROS FALSE +OPC_COUNT_THRESH 10 +INF_LOOP FALSE +INF_LOOP_BUCKETS 811 +LOOP_ENTRIES (4 * 1024) +LOOP_ASSOC 4 +LOOP_COUNT_MAX 127 +LOOP_REPEAT_MAX 15 +KNOB_PRINT_BRINFO FALSE +BR_MISPRED_FILE NULL +CONF_PERCEPTRON_TH 0 +CONF_PERCEPTRON_CTR_BITS 8 +CONF_PERCEPTRON_ENTRIES 127 +CONF_PERCEPTRON_THRESH_OVRD 0 +CONF_HIST_LENGTH 32 +PERCEPTRON_CONF_USE_CONF FALSE +PERCEPTRON_CONF_TRAIN_HIS FALSE +PERCEPTRON_CONF_TRAIN_CONF FALSE +PERCEPTRON_CONF_TRAIN_OFFSET_CONF FALSE +PERCEPTRON_TRAIN_MISP_FACTOR 1 +PERCEPTRON_TRAIN_CORR_FACTOR 1 +PERCEPTRON_CONF_HIS_BOTH FALSE +PERCEPTRON_CONF_HIS_BOTH_LENGTH 4 +ENABLE_ICACHE_PACKET_BREAKING TRUE +NUM_LOAD_STORE_PER_PACKET 0 +PACKET_BREAK_ON_FUS FALSE +PACKET_BREAK_FU_TYPES "G,G,G,G,G,G,G,G,G,G,G,G" +POWER_INTF_ON FALSE +POWER_INTF_ENABLE_SCALING FALSE +POWER_INTF_EXEC "power/power_intf.py" +POWER_INTF_REF_CHIP_TECH_NM 22 +POWER_INTF_REF_CHIP_FREQ (3.2e9) +POWER_INTF_REF_MEMORY_FREQ (0.8e9) +POWER_OTHER (0.0) +PREF_STREAM_ON FALSE 1 +PREF_STREAM_PER_CORE_ENABLE FALSE 1 +STREAM_BUFFER_N 16 +STREAM_PREFETCH_N 2 4 +STREAM_START_DIS 5 1 +STREAM_LENGTH 16 64 +STREAM_FULL_N 1 +STREAM_TRAIN_LENGTH 16 +STREAM_TRAIN_NUM 1 4 +PREF_ACC_USE_CACHE FALSE +STREAM_STALL_ON_QUEUE_FULL FALSE +PREF_SCHEDULE_NUM 4 +TRAIN_FILTER_SIZE 32 +PREF_REQ_Q_SIZE 64 +STREAM_CREATE_ON_DC_MISS FALSE 0 +STREAM_CREATE_ON_L1_MISS TRUE 1 +STREAM_TRAIN_ON_WRONGPATH TRUE +STREAM_CREATE_ON_WRONGPATH TRUE +STREAM_PREF_INTO_DCACHE FALSE +REMOVE_REDUNDANT_STREAM FALSE +L2HIT_STREAM_SCHEDULE_NUM 4 +PREF_REQ_QUEUE_FILTER_ON FALSE +HW_PREF_HIT_TRAIN_STREAM FALSE +L2HIT_STREAM_BUFFER_N 32 +L2HIT_STREAM_PREFETCH_N 2 +L2HIT_STREAM_START_DIS 2 +L2HIT_STREAM_LENGTH 8 +L2HIT_PREF_REQ_Q_SIZE 128 +L2HIT_L2ACCESS_REQ_Q_SIZE 64 +PREF_STREAM_ACCPERSTREAM FALSE +PREF_ACC_DISTANCE_10 128 +PREF_FRAMEWORK_ON FALSE 1 +PREF_TRACE_ON FALSE +PREF_DL0REQ_QUEUE_SIZE 32 +PREF_UMLC_REQ_QUEUE_SIZE 64 +PREF_UL1REQ_QUEUE_SIZE 128 +PREF_SHARED_QUEUES TRUE 0 +PREF_DL0_MISS_ON TRUE +PREF_DL0_HIT_ON TRUE +PREF_DL0REQ_QUEUE_FILTER_ON TRUE +PREF_UMLC_REQ_QUEUE_FILTER_ON TRUE +PREF_UL1REQ_QUEUE_FILTER_ON TRUE +PREF_DL0REQ_ADD_FILTER_ON TRUE +PREF_UMLC_REQ_ADD_FILTER_ON TRUE +PREF_UL1REQ_ADD_FILTER_ON TRUE +PREF_DL0REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UMLC_REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UL1REQ_QUEUE_OVERWRITE_ON_FULL FALSE 1 +PREF_DL0SCHEDULE_NUM 4 +PREF_UMLC_SCHEDULE_NUM 4 +PREF_UL1SCHEDULE_NUM 4 +PREF_L1Q_DEMAND_RESERVE 0 +PREF_REPORT_PREF_MATCH_AS_MISS FALSE +PREF_REPORT_PREF_MATCH_AS_HIT TRUE +PREF_UPDATE_ON_WRONGPATH TRUE +PREF_TRAIN_ON_PREF_MISSES FALSE 0 +PREF_ORACLE_TRAIN_ON FALSE 0 +PREF_REQ_DROP FALSE +PREF_THROTTLE_ON FALSE +PREF_THROTTLEFB_ON FALSE 1 +PREF_ACC_THRESH_1 0.90 0.75 +PREF_ACC_THRESH_2 0.70 0.4 +PREF_ACC_THRESH_3 0.60 0.4 +PREF_ACC_THRESH_4 0.40 +PREF_UPDATE_INTERVAL 0 8192 +PREF_ANALYZE_LOAD FALSE +PREF_POL_THRESH_1 0.25 +PREF_POL_THRESH_2 0.10 +PREF_POLBV_ON FALSE +PREF_POLBV_SIZE 1024 +PREF_TIMELY_THRESH 0.05 0.01 +PREF_POLPF_THRESH 0.01 0.005 +PREF_DEGFB_USEONLYACC FALSE +PREF_DEGFB_USEONLYPOL FALSE +PREF_DEGFB_USEONLYLATE FALSE +PREF_TIMELY_THRESH_2 0.005 +PREF_DEGFB_STATPHASEFILE FALSE +PREF_MAX_DEGFB 4 +PREF_DHAL FALSE +PREF_DHAL_SENTTHRESH 16 +PREF_DHAL_USETHRESH_MAX 12 +PREF_DHAL_USETHRESH_MIN2 8 +PREF_DHAL_USETHRESH_MIN1 4 +PREF_DHAL_MAXDEG 64 +PREF_HFILTER_ON FALSE +PREF_HFILTER_INDEX_BITS 12 +PREF_HFILTER_USE_PC FALSE +PREF_HFILTER_PRED_USELESS_THRES 2 +PREF_HFILTER_RESET_ENABLE FALSE +PREF_HFILTER_RESET_INTERVAL 100000 +L2L1PREF_ON FALSE +L2WAY_PREF FALSE +L2MARKV_PREF_ON FALSE +L2NEXT_PREF_ON FALSE +L2HIT_STREAM_PREF_ON FALSE +L2L1_DC_HIT_TRAIN FALSE +L1_HIT_DUMP_FILE_ON FALSE +L1_HIT_DUMP_WO_TXT FALSE +L1_HIT_DUMPFILE "l1hit_dump.out" +IDEAL_L2_L1_PREFETCHER FALSE +IDEAL_L2_ICACHE_PREFETCHER FALSE +L1WAY_PREF_SEND_QUEUE 4 +L1PREF_REQ_QUEUE_SIZE 1024 +L1PREF_IMMEDIATE FALSE +L1WAY_PREF_TIMER_DIS 1000 +L1MARKV_PREF_SEND_QUEUE 4 +L1PREF_MARKV_REQ_QUEUE_SIZE 1024 +MARKV_L2ACCESS_REQ_Q_SIZE 64 +L1MARKV_PREF_IMMEDIATE FALSE +L1MARKV_PREF_TIMER_DIS 1 +L2L1_HIT_TRAIN TRUE +L1MARKV_REQ_TH 1 +L2L1_IMMEDIATE_PREF_CACHE FALSE +L2L1_FILL_PREF_CACHE FALSE +L2L1_L2_HIT_STAT FALSE +PREF_GHB_ON FALSE +DEBUG_PREF_GHB FALSE +PREF_GHB_BUFFER_N 1024 +PREF_GHB_INDEX_N 128 +PREF_GHB_CZONE_BITS 12 +PREF_GHB_DEGREE 16 +PREF_GHB_MAX_DEGREE 32 +PREF_STRIDE_ON FALSE +DEBUG_PREF_STRIDE FALSE +PREF_STRIDE_TABLE_N 1024 +PREF_STRIDE_REGION_BITS 16 +PREF_STRIDE_DEGREE 4 +PREF_STRIDE_DISTANCE 16 +PREF_STRIDE_STARTDISTANCE 1 +PREF_STRIDE_SINGLE_THRESH 6 +PREF_STRIDE_MULTI_THRESH 6 +PREF_STRIDE_SINGLE_STRIDE_MODE FALSE +PREF_STRIDEPC_ON FALSE +DEBUG_PREF_STRIDEPC FALSE +PREF_STRIDEPC_TABLE_N 1024 +PREF_STRIDEPC_DEGREE 4 +PREF_STRIDEPC_DISTANCE 16 +PREF_STRIDEPC_USELOADADDR FALSE +PREF_STRIDEPC_TRAINNUM 2 +PREF_STRIDEPC_STARTDIS 4 +PREF_PHASE_ON FALSE +PREF_PHASE_STUDY FALSE +DEBUG_PREF_PHASE FALSE +PREF_PHASE_PRIME_HASH 16381 +PREF_PHASE_INFOSIZE 16384 +PREF_PHASE_LOG2REGIONSIZE 12 +PREF_PHASE_REGIONENTRIES 64 +PREF_PHASE_TRACKEDREGIONS 32 +PREF_PHASE_INTERVAL 100000 +PREF_PHASE_TABLE_SIZE 64 +PREF_PHASE_MAXDIFF_THRESH 64 +PREF_PHASE_MIN_MISSES 64 +PREF_PHASE_MISSPER 0.4 +PREF_2DC_ON FALSE +DEBUG_PREF_2DC FALSE +PREF_2DC_CACHE_SIZE (1 * 1024) +PREF_2DC_CACHE_ASSOC 4 +PREF_2DC_CACHE_LINE_SIZE 1 +PREF_2DC_DEGREE 16 +PREF_2DC_ZONE_SHIFT 10 +PREF_2DC_TAG_SIZE 16 +PREF_2DC_NUM_REGIONS 64 +PREF_2DC_REGION_HASH 61 +PREF_MARKOV_ON FALSE +DEBUG_PREF_MARKOV FALSE +PREF_MARKOV_NUM_ENTRIES 65536 +PREF_MARKOV_NUM_NEXT_STATES 8 +PREF_MARKOV_SEND_ON_PREF_HIT TRUE +PREF_MARKOV_UPDATE_ON_PREF_HIT TRUE +PREF_MARKOV_TABLE_UPDATE_POLICY 0 +PREF_MARKOV_SEND_THRESHOLD 0 +PREF_SMS_ON FALSE 0 +PREF_SMS_AT_SIZE 64 +PREF_SMS_FT_SIZE 64 +PREF_SMS_PHT_SIZE 16384 +PREF_SMS_PRF_SIZE 1024 +PREF_SMS_REGION_SIZE 2048 diff --git a/labs/LAB5/runs/leela_s_base-sms0/bp.stat.0.out b/labs/LAB5/runs/leela_s_base-sms0/bp.stat.0.out new file mode 100644 index 00000000..85f81405 --- /dev/null +++ b/labs/LAB5/runs/leela_s_base-sms0/bp.stat.0.out @@ -0,0 +1,752 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 62388250 Instructions: 100000003 IPC: 1.60287 + +BTB_ON_PATH_MISS 16634 0.104% 16634 0.104% +BTB_ON_PATH_HIT 16037243 99.896% 16037243 99.896% + 16053877 100.000% 16053877 100.000% + 1.00 1.00 1.00 1.00 + +BTB_OFF_PATH_MISS 0 -nan% 0 -nan% +BTB_OFF_PATH_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BTB_ON_PATH_WRITE 16634 100.000% 16634 100.000% +BTB_OFF_PATH_WRITE 0 0.000% 0 0.000% + 16634 100.000% 16634 100.000% + 0.00 0.00 0.00 0.00 + +BP_ON_PATH_CORRECT 14344379 89.351% 14344379 89.351% +BP_ON_PATH_MISPREDICT 786933 4.902% 786933 4.902% +BP_ON_PATH_MISFETCH 922565 5.747% 922565 5.747% + 16053877 100.000% 16053877 100.000% + 0.16 0.48 0.16 0.48 + +BP_OFF_PATH_CORRECT 0 -nan% 0 -nan% +BP_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% +BP_OFF_PATH_MISFETCH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +LATE_BP_ON_PATH_CORRECT 16053877 100.000% 16053877 100.000% +LATE_BP_ON_PATH_MISPREDICT 0 0.000% 0 0.000% +LATE_BP_ON_PATH_MISFETCH 0 0.000% 0 0.000% + 16053877 100.000% 16053877 100.000% + 0.00 0.00 0.00 0.00 + +LATE_BP_OFF_PATH_CORRECT 0 -nan% 0 -nan% +LATE_BP_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% +LATE_BP_OFF_PATH_MISFETCH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_PVN 0 -nan% 0 -nan% +BP_ON_PATH_CONF_PVN_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_PVP 0 -nan% 0 -nan% +BP_ON_PATH_CONF_PVP_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_SPEC 0 -nan% 0 -nan% +BP_ON_PATH_CONF_SPEC_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CRS_MISS_ON_PATH 36711 1.366% 36711 1.366% +CRS_HIT_ON_PATH 2651047 98.634% 2651047 98.634% + 2687758 100.000% 2687758 100.000% + 0.99 0.98 0.99 0.98 + +CRS_MISS_OFF_PATH 0 -nan% 0 -nan% +CRS_HIT_OFF_PATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CRS_CLOBBER 0 0 + +TARG_ON_PATH_MISS 2041 13.016% 2041 13.016% +TARG_ON_PATH_HIT 13640 86.984% 13640 86.984% + 15681 100.000% 15681 100.000% + 0.87 0.82 0.87 0.82 + +TARG_OFF_PATH_MISS 0 -nan% 0 -nan% +TARG_OFF_PATH_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_ON_PATH_WRITE 15681 100.000% 15681 100.000% +TARG_OFF_PATH_WRITE 0 0.000% 0 0.000% + 15681 100.000% 15681 100.000% + 0.00 0.00 0.00 0.00 + +TARG_HYBRID_CORRECT_TAGLESS 0 -nan% 0 -nan% +TARG_HYBRID_CORRECT_TAGGED 0 -nan% 0 -nan% +TARG_HYBRID_MISPRED_TAGLESS 0 -nan% 0 -nan% +TARG_HYBRID_MISPRED_TAGGED 0 -nan% 0 -nan% +TARG_HYBRID_NO_PRED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_VP_INDIRECT_MISPRED 0 -nan% 0 -nan% +TARG_VP_INDIRECT_NOPRED 0 -nan% 0 -nan% +TARG_VP_INDIRECT_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CBR_ON_PATH_CORRECT 9156132 92.086% 9156132 92.086% +CBR_ON_PATH_MISPREDICT 786933 7.914% 786933 7.914% + 9943065 100.000% 9943065 100.000% + 0.08 0.26 0.08 0.26 + +CBR_ON_PATH_CORRECT_PER1000INST 9156132 91.5613 9156132 91.5613 + +CBR_ON_PATH_MISPREDICT_PER1000INST 786933 7.8693 786933 7.8693 + +CBR_OFF_PATH_CORRECT 0 -nan% 0 -nan% +CBR_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PRED_TO_UPDATE_CYCLES_0 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_1 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_2 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_3 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_4 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_5 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_6 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_7 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_8 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_9 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_10 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_11 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_12 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_13 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_14 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_15 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_16 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_17 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_18 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_19 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_20 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_21 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_22 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_23 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_24 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_25 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_26 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_27 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_28 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_29 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_30 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_CORRECTED 0 -nan% 0 -nan% +BP_NOT_CORRECTED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_CORRECTED 0 -nan% 0 -nan% +TARG_NOT_CORRECTED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_MISP_PENALTY 18239341 18239341 + +BP_ON_PATH_CONF_MISPRED 0 -nan% 0 -nan% +BP_ON_PATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_OFF_PATH_CONF_MISPRED 0 -nan% 0 -nan% +BP_OFF_PATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_PRED_MIS_CONF_MISPRED 0 -nan% 0 -nan% +BP_ON_PATH_PRED_MIS_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_PRED_COR_CONF_MISPRED 0 -nan% 0 -nan% +BP_ON_PATH_PRED_COR_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_OFF_PATH_PRED_MIS_CONF_MISPRED 0 -nan% 0 -nan% +BP_OFF_PATH_PRED_MIS_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_OFF_PATH_PRED_COR_CONF_MISPRED 0 -nan% 0 -nan% +BP_OFF_PATH_PRED_COR_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ONPATH_CONF_MISPRED 0 -nan% 0 -nan% +ONPATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ONPATH_ON_PATH_CONF_MISPRED 0 -nan% 0 -nan% +ONPATH_ON_PATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ONPATH_OFF_PATH_CONF_MISPRED 0 -nan% 0 -nan% +ONPATH_OFF_PATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PRED_ONPATH_CONF_MISPRED 0 -nan% 0 -nan% +PRED_ONPATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PRED_OFFPATH_CONF_MISPRED 0 -nan% 0 -nan% +PRED_OFFPATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +LONG_OVWT_MIS 0 -nan% 0 -nan% +LONG_OVWT_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_0_7_MIS 0 -nan% 0 -nan% +OPC_LENGTH_0_7_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_8_15_MIS 0 -nan% 0 -nan% +OPC_LENGTH_8_15_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_16_23_MIS 0 -nan% 0 -nan% +OPC_LENGTH_16_23_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_24_31_MIS 0 -nan% 0 -nan% +OPC_LENGTH_24_31_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_32_39_MIS 0 -nan% 0 -nan% +OPC_LENGTH_32_39_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_40_47_MIS 0 -nan% 0 -nan% +OPC_LENGTH_40_47_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_48_55_MIS 0 -nan% 0 -nan% +OPC_LENGTH_48_55_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_56_63_MIS 0 -nan% 0 -nan% +OPC_LENGTH_56_63_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_64_71_MIS 0 -nan% 0 -nan% +OPC_LENGTH_64_71_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_72_79_MIS 0 -nan% 0 -nan% +OPC_LENGTH_72_79_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_80_MIS 0 -nan% 0 -nan% +OPC_LENGTH_80_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ALL_ONES_MIS 0 -nan% 0 -nan% +ALL_ONES_COR 0 -nan% 0 -nan% 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+CYCLES_UNDER_CRITICAL_MEM_REQ 0 0 + +CYCLES_UNDER_NONCRITICAL_MEM_REQ 0 0 + +CHIP_UTILIZATION_UNDER_MEM_REQ 0 -nan 0 -nan + +CHIP_UTILIZATION_UNDER_NO_MEM_REQ 0 -nan 0 -nan + +CHIP_UTILIZATION_UNDER_CRITICAL_MEM_REQ 0 -nan 0 -nan + +CHIP_UTILIZATION_UNDER_NONCRITICAL_MEM_REQ 0 -nan 0 -nan + +CYCLES_NOT_WAITING_FOR_OFF_CHIP 0 0.0000 0 0.0000 + +FUS_BUSY_NOT_WAITING_FOR_OFF_CHIP 0 -nan 0 -nan + +CYCLES_WAITING_FOR_OFF_CHIP 0 0.0000 0 0.0000 + +FUS_BUSY_WAITING_FOR_OFF_CHIP 0 -nan 0 -nan + +TOTAL_OFF_CHIP_DELAYS_LEFT 0 0 + +WRONG_IO_SCHED 0 0 + +DVFS_CONFIG_SWITCH 0 0 + + + diff --git a/labs/LAB5/runs/leela_s_base-sms0/fetch.stat.0.out b/labs/LAB5/runs/leela_s_base-sms0/fetch.stat.0.out new file mode 100644 index 00000000..ba2a5f96 --- /dev/null +++ b/labs/LAB5/runs/leela_s_base-sms0/fetch.stat.0.out @@ -0,0 +1,248 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 62388250 Instructions: 100000003 IPC: 1.60287 + +ICACHE_CYCLE 62388250 62388250 + +TCACHE_CYCLE 0 0 + +ICACHE_CYCLE_ONPATH 23594347 37.819% 23594347 37.819% +ICACHE_CYCLE_OFFPATH 38793903 62.181% 38793903 62.181% + 62388250 100.000% 62388250 100.000% + 0.62 0.57 0.62 0.57 + +FETCH_ON_PATH 24450437 100.000% 24450437 100.000% +FETCH_OFF_PATH 0 0.000% 0 0.000% + 24450437 100.000% 24450437 100.000% + 0.00 0.00 0.00 0.00 + +FETCHED_OPS_ON_PATH 0 -nan% 0 -nan% +FETCHED_OPS_OFF_PATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +INST_LOST_WAIT_FOR_MISP_RECOVERY 0 0.000% 0 0.000% +INST_LOST_WAIT_FOR_TIMER 0 0.000% 0 0.000% +INST_LOST_WAIT_FOR_EMPTY_ROB 0 0.000% 0 0.000% +INST_LOST_WAIT_FOR_REDIRECT 704178 0.464% 704178 0.464% +INST_LOST_FETCH 122944265 80.951% 122944265 80.951% +INST_LOST_OFF_PATH 0 0.000% 0 0.000% +INST_LOST_FULL_WINDOW 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_OTHER 1664802 1.096% 1664802 1.096% +INST_LOST_ROB_STALL_WAIT_FOR_RECOVERY 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_REDIRECT 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_GAP_FILL 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_L1_MISS 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_MEMORY 1944 0.001% 1944 0.001% +INST_LOST_ROB_STALL_WAIT_FOR_DC_MISS 543960 0.358% 543960 0.358% +INST_LOST_ROB_BLOCK_ISSUE_FULL 0 0.000% 0 0.000% +INST_LOST_ROB_BLOCK_ISSUE_GAP_TOO_LARGE 0 0.000% 0 0.000% +INST_LOST_BREAK_DONT 0 0.000% 0 0.000% +INST_LOST_BREAK_ISSUE_WIDTH 0 0.000% 0 0.000% +INST_LOST_BREAK_CF 0 0.000% 0 0.000% +INST_LOST_BREAK_BTB_MISS 34669 0.023% 34669 0.023% +INST_LOST_BREAK_ICACHE_MISS 2367832 1.559% 2367832 1.559% +INST_LOST_BREAK_LINE_END 0 0.000% 0 0.000% +INST_LOST_BREAK_STALL 0 0.000% 0 0.000% +INST_LOST_BREAK_BARRIER 0 0.000% 0 0.000% +INST_LOST_BREAK_OFFPATH 1238500 0.815% 1238500 0.815% +INST_LOST_BREAK_ALIGNMENT 0 0.000% 0 0.000% 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4161590 3.385% 4161590 3.385% +ST_OP_IMEM 36002236 29.283% 36002236 29.283% +ST_OP_IADD 18229508 14.827% 18229508 14.827% +ST_OP_IMUL 1041032 0.847% 1041032 0.847% +ST_OP_IDIV 227430 0.185% 227430 0.185% +ST_OP_ICMP 7756009 6.309% 7756009 6.309% +ST_OP_LOGIC 11252960 9.153% 11252960 9.153% +ST_OP_SHIFT 5785798 4.706% 5785798 4.706% +ST_OP_FMEM 372607 0.303% 372607 0.303% +ST_OP_FCVT 80299 0.065% 80299 0.065% +ST_OP_FADD 39839 0.032% 39839 0.032% +ST_OP_FMUL 0 0.000% 0 0.000% +ST_OP_FMA 0 0.000% 0 0.000% +ST_OP_FDIV 437 0.000% 437 0.000% +ST_OP_FCMP 0 0.000% 0 0.000% +ST_OP_FCMOV 0 0.000% 0 0.000% +ST_OP_GATHER 0 0.000% 0 0.000% +ST_OP_SCATTER 0 0.000% 0 0.000% +ST_OP_PIPELINED_FAST 0 0.000% 0 0.000% +ST_OP_PIPELINED_MEDIUM 0 0.000% 0 0.000% +ST_OP_PIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_MEDIUM 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_VERY_SLOW 0 0.000% 0 0.000% + 122944265 100.000% 122944265 100.000% + 6.05 3.08 6.05 3.08 + +ST_NOT_CF 106890388 86.942% 106890388 86.942% +ST_CF_BR 719614 0.585% 719614 0.585% +ST_CF_CBR 9943065 8.087% 9943065 8.087% +ST_CF_CALL 2687759 2.186% 2687759 2.186% +ST_CF_IBR 15681 0.013% 15681 0.013% +ST_CF_ICALL 0 0.000% 0 0.000% +ST_CF_ICO 0 0.000% 0 0.000% +ST_CF_RET 2687758 2.186% 2687758 2.186% +ST_CF_SYS 0 0.000% 0 0.000% + 122944265 100.000% 122944265 100.000% + 0.39 1.15 0.39 1.15 + +ST_BAR_NONE 122944265 100.000% 122944265 100.000% +ST_BAR_FETCH 0 0.000% 0 0.000% +ST_BAR_ISSUE 0 0.000% 0 0.000% +ST_BAR_BOTH 0 0.000% 0 0.000% + 122944265 100.000% 122944265 100.000% + 0.00 0.00 0.00 0.00 + +ST_NOT_MEM 86569422 70.414% 86569422 70.414% +ST_MEM_LD 26692415 21.711% 26692415 21.711% +ST_MEM_ST 9682428 7.875% 9682428 7.875% +ST_MEM_PF 0 0.000% 0 0.000% +ST_MEM_WH 0 0.000% 0 0.000% +ST_MEM_EVICT 0 0.000% 0 0.000% + 122944265 100.000% 122944265 100.000% + 0.37 0.54 0.37 0.54 + +ST_NOT_MEM_OFFPATH 0 -nan% 0 -nan% +ST_MEM_LD_OFFPATH 0 -nan% 0 -nan% +ST_MEM_ST_OFFPATH 0 -nan% 0 -nan% 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00000000..8884d4c3 --- /dev/null +++ b/labs/LAB5/runs/leela_s_base-sms0/l2l1pref.stat.0.out @@ -0,0 +1,140 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 62388250 Instructions: 100000003 IPC: 1.60287 + +L2WAY_FILL_L1 0 0 + +L2WAY_WAY_HIT 0 -nan% 0 -nan% +L2WAY_WAY_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_PREF_REQ 0 0 + +L2WAY_PREF_HIT_DATA_IN_CACHE 0 -nan% 0 -nan% +L2WAY_PREF_HIT_DATA_REQ 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_TRAIN_HIT 0 -nan% 0 -nan% +L2WAY_TRAIN_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L1_HIT_REQ_TYPE_IFETCH 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DFETCH 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DSTORE 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_IPRF 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DPRF 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_WB 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2_ACCESS_INTERVAL__0 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__1 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__2 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__3 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__4 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__5 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__6 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__7 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__8 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_L1INSERT_PORT_FULL 0 -nan% 0 -nan% +L2WAY_L1INSERT_PORT_READY 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2MARKV_NEXT_ADDR_HIT 0 -nan% 0 -nan% +L2MARKV_NEXT_ADDR_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2MARKV_LAST_ADDR_HIT 0 -nan% 0 -nan% +L2MARKV_LAST_ADDR_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +MARKV_L2_TIME_DIFF__0 0 -nan% 0 -nan% +MARKV_L2_TIME_DIFF__1 0 -nan% 0 -nan% +MARKV_L2_TIME_DIFF__2 0 -nan% 0 -nan% +MARKV_L2_TIME_DIFF__3 0 -nan% 0 -nan% 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0 -nan% 0 -nan% +DCACHE_PREF_FETCH_1000 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_10000 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_100000 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_1000000 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_10000000 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_100000000 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_MORE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_SAME_IP_DELTA__0 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__1 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__2 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__3 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__4 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__5 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__6 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__7 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__8 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_IP_HIT_COUNT__1 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__2 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__3 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__4 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__5 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__6 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__7 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__8 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__9 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + + + diff --git a/labs/LAB5/runs/leela_s_base-sms0/memory.stat.0.out b/labs/LAB5/runs/leela_s_base-sms0/memory.stat.0.out new file mode 100644 index 00000000..44245c28 --- /dev/null +++ b/labs/LAB5/runs/leela_s_base-sms0/memory.stat.0.out @@ -0,0 +1,3416 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 62388250 Instructions: 100000003 IPC: 1.60287 + +ICACHE_MISS 19476 0.067% 19476 0.067% +ICACHE_HIT 28867837 99.933% 28867837 99.933% + 28887313 100.000% 28887313 100.000% + 1.00 1.00 1.00 1.00 + +ICACHE_MISS_ONPATH 19476 100.000% 19476 100.000% +ICACHE_MISS_OFFPATH 0 0.000% 0 0.000% + 19476 100.000% 19476 100.000% + 0.00 0.00 0.00 0.00 + +ICACHE_HIT_ONPATH 28867837 100.000% 28867837 100.000% +ICACHE_HIT_OFFPATH 0 0.000% 0 0.000% + 28867837 100.000% 28867837 100.000% + 0.00 0.00 0.00 0.00 + +ICACHE_HIT_ONPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +ICACHE_HIT_ONPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ICACHE_HIT_OFFPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +ICACHE_HIT_OFFPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DCACHE_MISS 388096 1.067% 388096 1.067% +DCACHE_ST_BUFFER_HIT 13168 0.036% 13168 0.036% +DCACHE_HIT 35973555 98.897% 35973555 98.897% + 36374819 100.000% 36374819 100.000% + 1.98 1.97 1.98 1.97 + +DCACHE_MISS_COMPULSORY 4077 0.0105 4077 0.0105 + +DCACHE_MISS_CAPACITY 353697 0.9114 353697 0.9114 + +DCACHE_MISS_CONFLICT 30322 0.0781 30322 0.0781 + +DCACHE_MISS_ONPATH 388096 100.000% 388096 100.000% +DCACHE_MISS_OFFPATH 0 0.000% 0 0.000% + 388096 100.000% 388096 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_ST_BUFFER_HIT_ONPATH 13168 100.000% 13168 100.000% +DCACHE_ST_BUFFER_HIT_OFFPATH 0 0.000% 0 0.000% + 13168 100.000% 13168 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_HIT_ONPATH 35973555 100.000% 35973555 100.000% +DCACHE_HIT_OFFPATH 0 0.000% 0 0.000% + 35973555 100.000% 35973555 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_HIT_ONPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +DCACHE_HIT_ONPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DCACHE_HIT_OFFPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +DCACHE_HIT_OFFPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DCACHE_MISS_LD 289816 74.676% 289816 74.676% +DCACHE_MISS_ST 98280 25.324% 98280 25.324% + 388096 100.000% 388096 100.000% + 0.25 0.40 0.25 0.40 + +DCACHE_MISS_LD_ONPATH 289816 100.000% 289816 100.000% +DCACHE_MISS_LD_OFFPATH 0 0.000% 0 0.000% + 289816 100.000% 289816 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_MISS_ST_ONPATH 98280 100.000% 98280 100.000% +DCACHE_MISS_ST_OFFPATH 0 0.000% 0 0.000% + 98280 100.000% 98280 100.000% + 0.00 0.00 0.00 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112.0148 158613 112.0148 + +CORE_L1_MISS_LATENCY 623148 126.9658 623148 126.9658 + +CORE_L1_MISS_LATENCY_DEMAND 464535 133.0284 464535 133.0284 + +CORE_L1_MISS_LATENCY_PREF 158613 112.0148 158613 112.0148 + +CORE_EVICTED_L1_DEMAND 58 87.879% 58 87.879% +CORE_EVICTED_L1_PREF_USED 5 7.576% 5 7.576% +CORE_EVICTED_L1_PREF_NOT_USED 3 4.545% 3 4.545% + 66 100.000% 66 100.000% + 0.17 0.46 0.17 0.46 + +CORE_EVICTED_MLC_DEMAND 0 -nan% 0 -nan% +CORE_EVICTED_MLC_PREF_USED 0 -nan% 0 -nan% +CORE_EVICTED_MLC_PREF_NOT_USED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CORE_MEM_LATENCY_AVE_DEMAND 5660 97.5862 5660 97.5862 + +CORE_MEM_LATENCY_AVE_PREF_USED 292 58.4000 292 58.4000 + +CORE_MEM_LATENCY_AVE_PREF_NOT_USED 594 198.0000 594 198.0000 + +DRAM_LATENCY 0 0 + +TOTAL_DRAM_LATENCY 0 0 + +DRAM_CLOSED_PAGE_POLICY_CMD 0 0 + +DRAM_ACTIVATE_STALLING 0 0 + +DRAM_PRECHARGE_STALLING 0 0 + +DRAM_PRECHARGE_STALLING_WAIT_CYCLES 0 0 + +L1_STAY_DEMAND 1762930605 30395355.2586 1762930605 30395355.2586 + +L1_STAY_PREF_USED 158678860 31735772.0000 158678860 31735772.0000 + +L1_STAY_PREF_NOT_USED 135381328 45127109.3333 135381328 45127109.3333 + +TOTAL_DATA_MISS_LATENCY 454017 454017 + +TOTAL_DATA_MISS_COUNT 3169 3169 + +CORE_PREF_L1_NOT_USED_LATENCY200 1 33.333% 1 33.333% +CORE_PREF_L1_NOT_USED_LATENCY400 2 66.667% 2 66.667% +CORE_PREF_L1_NOT_USED_LATENCY600 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_LATENCY800 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_LATENCY1000 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_LATENCY1200 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_LATENCY1400 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_LATENCY1600 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_LATENCY1600MORE 0 0.000% 0 0.000% + 3 100.000% 3 100.000% + 0.67 0.33 0.67 0.33 + +CORE_PREF_L1_NOT_USED_DISTANCE_1 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_DISTANCE_2 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_DISTANCE_4 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_DISTANCE_8 1 33.333% 1 33.333% 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0 -nan% 0 -nan% +CORE_PREF_MLC_DEMAND_LATENCY1000MORE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TOTAL_BATCH_FORMED 0 0 + +TOTAL_BATCH_MEM_REQ_MARKED 0 -nan 0 -nan + +CORE_BATCH_MEM_REQ_MARKED 0 -nan 0 -nan + +CORE_BATCH_MEM_REQ_MARKED_DEMAND 0 -nan 0 -nan + +CORE_BATCH_MEM_REQ_MARKED_PREF 0 -nan 0 -nan + +DRAM_ROW_BATCHES 0 0 + +REJECTED_QUEUE_MLC 0 0 + +REJECTED_QUEUE_L1 0 0 + +REJECTED_QUEUE_BUS_OUT 0 0 + +LEADING_LOAD_LATENCY 0 0.0000 0 0.0000 + +LEADING_LOADS 0 0.0000 0 0.0000 + +MEM_REQ_CRITICAL_PATH_LENGTH 0 0.0000 0 0.0000 + +TOTAL_MEM_REQ_LATENCY 0 0 + +TOTAL_CRITICAL_MEM_REQ_LATENCY 0 -nan 0 -nan + +TOTAL_CRITICAL_BANK_LATENCY 0 -nan 0 -nan + +TOTAL_MEMORY_SLACK 0 0.0000 0 0.0000 + +TOTAL_CHIP_UTILIZATION 0 0.0000 0 0.0000 + +CHIP_BUSY_UNDER_CRITICAL_REQS 0 0.0000 0 0.0000 + +PERF_PRED_NUM_STAT_RESETS 0 0 + +PERF_PRED_RESET_STATS_CYCLE 0 0 + +PERF_PRED_CYCLE 62388250 62388250 + +ESTIMATED_ALONE_CYCLES 0 0.0000 0 0.0000 + +NUM_WINDOWS_WITH_DCACHE_MISS 108350 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-nan 0 -nan + +DRAM_NUM_REQS_23_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_23_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_23_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_23_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_23_WB_NODIRTY 0 -nan 0 -nan + +DRAM_NUM_REQS_24_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_24_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_24_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_24_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_24_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_24_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_24_WB_NODIRTY 0 -nan 0 -nan + +DRAM_NUM_REQS_25_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_25_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_25_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_25_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_25_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_25_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_25_WB_NODIRTY 0 -nan 0 -nan + +DRAM_NUM_REQS_26_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_26_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_26_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_26_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_26_DPRF 0 -nan 0 -nan + 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-nan 0 -nan + +DRAM_NUM_REQS_30_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_30_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_30_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_30_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_30_WB_NODIRTY 0 -nan 0 -nan + +DRAM_NUM_REQS_31_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_31_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_31_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_31_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_31_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_31_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_31_WB_NODIRTY 0 -nan 0 -nan + +DRAM_NUM_REQS_32_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_32_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_32_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_32_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_32_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_32_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_32_WB_NODIRTY 0 -nan 0 -nan + +DRAM_BOTTLENECK_BUS_0 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_10 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_20 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_30 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_40 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_50 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_60 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_70 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_80 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_90 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_100 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DRAM_BOTTLENECK_BANKS_0 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_10 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_20 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_30 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_40 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_50 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_60 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_70 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_80 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_90 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_100 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DRAM_BOTTLENECK_FAW_0 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_10 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_20 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_30 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_40 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_50 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_60 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_70 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_80 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_90 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_100 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DRAM_ROW_HIT_GEN_AFTER_ROW_OPEN_STALLING 0 0 + +KNOWN_BAD_ADDRESS 0 0.000% 0 0.000% +GOOD_ADDRESS 741935 100.000% 741935 100.000% + 741935 100.000% 741935 100.000% + 1.00 1.00 1.00 1.00 + + + diff --git a/labs/LAB5/runs/leela_s_base-sms0/power.stat.0.out b/labs/LAB5/runs/leela_s_base-sms0/power.stat.0.out new file mode 100644 index 00000000..1a44a52f --- /dev/null +++ b/labs/LAB5/runs/leela_s_base-sms0/power.stat.0.out @@ -0,0 +1,184 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 62388250 Instructions: 100000003 IPC: 1.60287 + +POWER_STATS_BEGIN 0 0 + +POWER_TIME 19496328125000 19496328125000 + +POWER_CYCLE 62388250 62388250 + +POWER_ITLB_ACCESS 28887313 28887313 + +POWER_DTLB_ACCESS 9682423 9682423 + +POWER_ICACHE_ACCESS 28887313 28887313 + +POWER_ICACHE_MISS 19476 19476 + +POWER_BTB_READ 28887313 28887313 + +POWER_BTB_WRITE 1709497 1709497 + +POWER_ROB_READ 122944185 122944185 + +POWER_ROB_WRITE 122944185 122944185 + +POWER_RENAME_READ 245888370 245888370 + +POWER_RENAME_WRITE 122944185 122944185 + +POWER_FP_RENAME_READ 0 0 + +POWER_FP_RENAME_WRITE 0 0 + +POWER_FUNCTION_CALL 2687757 2687757 + +POWER_INST_WINDOW_READ 122944185 122944185 + +POWER_INST_WINDOW_WRITE 122944185 122944185 + +POWER_INT_REGFILE_READ 146903593 146903593 + +POWER_INT_REGFILE_WRITE 116287132 116287132 + +POWER_IALU_ACCESS 121675723 121675723 + +POWER_CDB_IALU_ACCESS 121675723 121675723 + +POWER_MUL_ACCESS 1268462 1268462 + +POWER_CDB_MUL_ACCESS 1268462 1268462 + +POWER_FP_INST_WINDOW_WRITE 0 0 + +POWER_FP_INST_WINDOW_READ 0 0 + +POWER_FP_REGFILE_READ 0 0 + +POWER_FP_REGFILE_WRITE 0 0 + +POWER_FPU_ACCESS 0 0 + +POWER_CDB_FPU_ACCESS 0 0 + +POWER_DCACHE_READ_ACCESS 26693885 26693885 + +POWER_DCACHE_WRITE_ACCESS 9683108 9683108 + +POWER_DCACHE_READ_MISS 304473 304473 + +POWER_DCACHE_WRITE_MISS 98965 98965 + +POWER_MLC_READ_ACCESS 0 0 + +POWER_MLC_WRITE_ACCESS 0 0 + +POWER_MLC_READ_MISS 0 0 + +POWER_MLC_WRITE_MISS 0 0 + +POWER_LLC_READ_ACCESS 261050 261050 + +POWER_LLC_WRITE_ACCESS 65554 65554 + +POWER_LLC_READ_MISS 4908 4908 + +POWER_LLC_WRITE_MISS 0 0 + +POWER_MEMORY_ACCESS 0 0 + +POWER_MEMORY_READ_ACCESS 0 0 + +POWER_MEMORY_WRITE_ACCESS 0 0 + +POWER_INST_WINDOW_WAKEUP_ACCESS 122944185 122944185 + +POWER_FP_INST_WINDOW_WAKEUP_ACCESS 0 0 + +POWER_L1DIREC_READ_ACCESS 0 0 + +POWER_L1DIREC_WRITE_ACCESS 0 0 + +POWER_L1DIREC_READ_MISS 0 0 + +POWER_L1DIREC_WRITE_MISS 0 0 + +POWER_L2DIREC_READ_ACCESS 0 0 + +POWER_L2DIREC_WRITE_ACCESS 0 0 + +POWER_L2DIREC_READ_MISS 0 0 + +POWER_L2DIREC_WRITE_MISS 0 0 + +POWER_MEMORY_CTRL_ACCESS 4917 4917 + +POWER_MEMORY_CTRL_READ 4908 4908 + +POWER_MEMORY_CTRL_WRITE 9 9 + +POWER_OP 122944185 122944185 + +POWER_INT_OP 119457422 119457422 + +POWER_FP_OP 493182 493182 + +POWER_LD_OP 26692398 26692398 + +POWER_ST_OP 9682423 9682423 + +POWER_BRANCH_MISPREDICT 1709497 1709497 + +POWER_COMMITTED_OP 122944185 122944185 + +POWER_COMMITTED_INT_OP 119457422 119457422 + +POWER_COMMITTED_FP_OP 3486763 3486763 + +POWER_BRANCH_OP 16053869 16053869 + +POWER_DRAM_PRECHARGE 1665 1665 + +POWER_DRAM_ACTIVATE 2953 2953 + +POWER_DRAM_READ 4905 4905 + +POWER_DRAM_WRITE 0 0 + +POWER_STATS_END 0 0 + +ENERGY 0.000000 0.000000 + +ENERGY_CORE 0.000000 0.000000 + +ENERGY_UNCORE 0.000000 0.000000 + +ENERGY_MEMORY 0.000000 0.000000 + +ENERGY_OTHER 0.000000 0.000000 + +ENERGY_CORE_STATIC 0.000000 0.000000 + +ENERGY_CORE_DYNAMIC 0.000000 0.000000 + +ENERGY_UNCORE_STATIC 0.000000 0.000000 + +ENERGY_UNCORE_DYNAMIC 0.000000 0.000000 + +ENERGY_MEMORY_STATIC 0.000000 0.000000 + +ENERGY_MEMORY_DYNAMIC 0.000000 0.000000 + +ENERGY_OTHER_STATIC 0.000000 0.000000 + +ENERGY_OTHER_DYNAMIC 0.000000 0.000000 + +TIME 0.000000 0.000000 + +ENERGY_STATS_END 0 0 + + + diff --git a/labs/LAB5/runs/leela_s_base-sms0/pref.stat.0.out b/labs/LAB5/runs/leela_s_base-sms0/pref.stat.0.out new file mode 100644 index 00000000..2661d96a --- /dev/null +++ b/labs/LAB5/runs/leela_s_base-sms0/pref.stat.0.out @@ -0,0 +1,208 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 62388250 Instructions: 100000003 IPC: 1.60287 + +PREF_DL0REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UMLC_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UL1REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_DL0REQ_QUEUE_FULL 0 0 + +PREF_UMLC_REQ_QUEUE_FULL 0 0 + +PREF_UL1REQ_QUEUE_FULL 0 0 + +PREF_DC_HIT_NOSEND 0 0 + +PREF_WBQDC_HIT_NOSEND 0 0 + +PREF_MLCQ_STALL 0 0 + +PREF_L1Q_STALL 0 0 + +PREF_UMLC_REQ_SEND_QUEUE_STALL 0 0 + +PREF_UL1REQ_SEND_QUEUE_STALL 3048 3048 + +PREF_UMLC_REQ_QUEUE_SENTREQ 0 0 + +PREF_UL1REQ_QUEUE_SENTREQ 2528 2528 + +PREF_NEWREQ_MATCHED 51 51 + +PREF_UMLC_REQ_QUEUE_MATCHED_REQ 0 0 + +PREF_UL1REQ_QUEUE_MATCHED_REQ 128 128 + +PREF_DL0REQ_QUEUE_MATCHED_REQ 0 0 + +L1_PREF_HIT 71269 71269 + +L1_PREF_UNIQUE_HIT 931 931 + +L1_PREF_LATE 75 75 + +L1_LATE_PREF_CYCLES 7248 7248 + +L1_LATE_PREF_CYCLES_DIST_0 40 53.333% 40 53.333% +L1_LATE_PREF_CYCLES_DIST_100 31 41.333% 31 41.333% +L1_LATE_PREF_CYCLES_DIST_200 4 5.333% 4 5.333% +L1_LATE_PREF_CYCLES_DIST_300 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_400 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_500 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_600 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_700 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_800 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_900 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1000 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1100 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1200 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1300 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1400 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1500 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1600 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1700 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1800 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1900 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_2000 0 0.000% 0 0.000% + 75 100.000% 75 100.000% + 0.52 0.46 0.52 0.46 + +MLC_PREF_HIT 0 0 + +MLC_PREF_UNIQUE_HIT 0 0 + +MLC_PREF_LATE 0 0 + +PREF_HYBRID_SEL_0 0 -nan% 0 -nan% +PREF_HYBRID_SEL_1 0 -nan% 0 -nan% +PREF_HYBRID_SEL_2 0 -nan% 0 -nan% +PREF_HYBRID_SEL_3 0 -nan% 0 -nan% +PREF_HYBRID_SEL_4 0 -nan% 0 -nan% +PREF_HYBRID_SEL_5 0 -nan% 0 -nan% +PREF_HYBRID_SEL_6 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_DISTANCE_1 0 -nan% 0 -nan% +PREF_DISTANCE_2 0 -nan% 0 -nan% +PREF_DISTANCE_3 0 -nan% 0 -nan% +PREF_DISTANCE_4 0 -nan% 0 -nan% +PREF_DISTANCE_5 0 -nan% 0 -nan% +PREF_DISTANCE_6 0 -nan% 0 -nan% +PREF_DISTANCE_7 0 -nan% 0 -nan% +PREF_DISTANCE_8 0 -nan% 0 -nan% +PREF_DISTANCE_9 0 -nan% 0 -nan% +PREF_DISTANCE_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_REPL_MRU 0 -nan% 0 -nan% +PREF_REPL_MID 0 -nan% 0 -nan% +PREF_REPL_LOWQTR 0 -nan% 0 -nan% +PREF_REPL_LRU 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_REPL_MOVEDOWN 0 -nan% 0 -nan% +PREF_REPL_MOVEUP 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_COV_1 0 -nan% 0 -nan% +PREF_COV_2 0 -nan% 0 -nan% +PREF_COV_3 0 -nan% 0 -nan% +PREF_COV_4 0 -nan% 0 -nan% +PREF_COV_5 0 -nan% 0 -nan% +PREF_COV_6 0 -nan% 0 -nan% +PREF_COV_7 0 -nan% 0 -nan% +PREF_COV_8 0 -nan% 0 -nan% +PREF_COV_9 0 -nan% 0 -nan% +PREF_COV_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_POL_1 0 -nan% 0 -nan% +PREF_POL_2 0 -nan% 0 -nan% +PREF_POL_3 0 -nan% 0 -nan% +PREF_POL_4 0 -nan% 0 -nan% +PREF_POL_5 0 -nan% 0 -nan% +PREF_POL_6 0 -nan% 0 -nan% +PREF_POL_7 0 -nan% 0 -nan% +PREF_POL_8 0 -nan% 0 -nan% +PREF_POL_9 0 -nan% 0 -nan% +PREF_POL_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_ACC_1 0 -nan% 0 -nan% +PREF_ACC_2 0 -nan% 0 -nan% +PREF_ACC_3 0 -nan% 0 -nan% +PREF_ACC_4 0 -nan% 0 -nan% +PREF_ACC_5 0 -nan% 0 -nan% +PREF_ACC_6 0 -nan% 0 -nan% +PREF_ACC_7 0 -nan% 0 -nan% +PREF_ACC_8 0 -nan% 0 -nan% +PREF_ACC_9 0 -nan% 0 -nan% +PREF_ACC_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_TIMELY_1 0 -nan% 0 -nan% +PREF_TIMELY_2 0 -nan% 0 -nan% +PREF_TIMELY_3 0 -nan% 0 -nan% +PREF_TIMELY_4 0 -nan% 0 -nan% +PREF_TIMELY_5 0 -nan% 0 -nan% +PREF_TIMELY_6 0 -nan% 0 -nan% +PREF_TIMELY_7 0 -nan% 0 -nan% +PREF_TIMELY_8 0 -nan% 0 -nan% +PREF_TIMELY_9 0 -nan% 0 -nan% +PREF_TIMELY_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_UNUSED_EVICT 3 3 + +PREF_REGION_SENT 0 0 + +PREF_REGION_USEFUL 0 0 + +PREF_REGION_EVICT 0 0 + +PREF_PFPOL 0 0 + +PREF_PHASE_NEWPHASE_DET 0 0 + +PREF_PHASE_NEWPHASE_NOTVALID 0 0 + +PREF_PHASE_SENTPREF 0 0 + +PREF_PHASE_OVERWRITE_PAGE 0 0 + +PREF_UPDATE_COUNT 0 0 + +PREF_ACC1_HT_HP 0 -nan% 0 -nan% +PREF_ACC1_HT_LP 0 -nan% 0 -nan% +PREF_ACC1_LT_HP 0 -nan% 0 -nan% +PREF_ACC1_LT_LP 0 -nan% 0 -nan% +PREF_ACC2_HT_HP 0 -nan% 0 -nan% +PREF_ACC2_HT_LP 0 -nan% 0 -nan% +PREF_ACC2_LT_HP 0 -nan% 0 -nan% +PREF_ACC2_LT_LP 0 -nan% 0 -nan% +PREF_ACC3_HT_HP 0 -nan% 0 -nan% +PREF_ACC3_HT_LP 0 -nan% 0 -nan% +PREF_ACC3_LT_HP 0 -nan% 0 -nan% +PREF_ACC3_LT_LP 0 -nan% 0 -nan% +PREF_ACC4_HT_HP 0 -nan% 0 -nan% +PREF_ACC4_HT_LP 0 -nan% 0 -nan% +PREF_ACC4_LT_HP 0 -nan% 0 -nan% +PREF_ACC4_LT_LP 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + + + diff --git a/labs/LAB5/runs/leela_s_base-sms0/ramulator.stat.out b/labs/LAB5/runs/leela_s_base-sms0/ramulator.stat.out new file mode 100644 index 00000000..163f39d9 --- /dev/null +++ b/labs/LAB5/runs/leela_s_base-sms0/ramulator.stat.out @@ -0,0 +1,150 @@ + ramulator.active_cycles_0 138921 # Total active cycles for level _0 + ramulator.busy_cycles_0 138921 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0 + ramulator.serving_requests_0 154010 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.average_serving_requests_0 0.006583 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.active_cycles_0_0 138921 # Total active cycles for level _0_0 + ramulator.busy_cycles_0_0 1188501 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0 + ramulator.serving_requests_0_0 154010 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.average_serving_requests_0_0 0.006583 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.active_cycles_0_0_0 37309 # Total active cycles for level _0_0_0 + ramulator.busy_cycles_0_0_0 37309 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0 + ramulator.serving_requests_0_0_0 39541 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 +ramulator.average_serving_requests_0_0_0 0.001690 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 + ramulator.active_cycles_0_0_0_0 8648 # Total active cycles for level _0_0_0_0 + ramulator.busy_cycles_0_0_0_0 8648 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_0 + ramulator.serving_requests_0_0_0_0 9432 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 +ramulator.average_serving_requests_0_0_0_0 0.000403 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 + ramulator.active_cycles_0_0_0_1 10633 # Total active cycles for level _0_0_0_1 + ramulator.busy_cycles_0_0_0_1 10633 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_1 + ramulator.serving_requests_0_0_0_1 11189 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 +ramulator.average_serving_requests_0_0_0_1 0.000478 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 + ramulator.active_cycles_0_0_0_2 11060 # Total active cycles for level _0_0_0_2 + ramulator.busy_cycles_0_0_0_2 11060 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_2 + ramulator.serving_requests_0_0_0_2 11460 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 +ramulator.average_serving_requests_0_0_0_2 0.000490 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 + ramulator.active_cycles_0_0_0_3 7184 # Total active cycles for level _0_0_0_3 + ramulator.busy_cycles_0_0_0_3 7184 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_3 + ramulator.serving_requests_0_0_0_3 7460 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 +ramulator.average_serving_requests_0_0_0_3 0.000319 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 + ramulator.active_cycles_0_0_1 39414 # Total active cycles for level _0_0_1 + ramulator.busy_cycles_0_0_1 39414 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1 + ramulator.serving_requests_0_0_1 43901 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 +ramulator.average_serving_requests_0_0_1 0.001876 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 + ramulator.active_cycles_0_0_1_0 8860 # Total active cycles for level _0_0_1_0 + ramulator.busy_cycles_0_0_1_0 8860 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_0 + ramulator.serving_requests_0_0_1_0 9715 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 +ramulator.average_serving_requests_0_0_1_0 0.000415 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 + ramulator.active_cycles_0_0_1_1 11871 # Total active cycles for level _0_0_1_1 + ramulator.busy_cycles_0_0_1_1 11871 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_1 + ramulator.serving_requests_0_0_1_1 13758 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 +ramulator.average_serving_requests_0_0_1_1 0.000588 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 + ramulator.active_cycles_0_0_1_2 14058 # Total active cycles for level _0_0_1_2 + ramulator.busy_cycles_0_0_1_2 14058 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_2 + ramulator.serving_requests_0_0_1_2 15320 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 +ramulator.average_serving_requests_0_0_1_2 0.000655 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 + ramulator.active_cycles_0_0_1_3 4856 # Total active cycles for level _0_0_1_3 + ramulator.busy_cycles_0_0_1_3 4856 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_3 + ramulator.serving_requests_0_0_1_3 5108 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 +ramulator.average_serving_requests_0_0_1_3 0.000218 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 + ramulator.active_cycles_0_0_2 29111 # Total active cycles for level _0_0_2 + ramulator.busy_cycles_0_0_2 29111 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2 + ramulator.serving_requests_0_0_2 32101 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 +ramulator.average_serving_requests_0_0_2 0.001372 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 + ramulator.active_cycles_0_0_2_0 4820 # Total active cycles for level _0_0_2_0 + ramulator.busy_cycles_0_0_2_0 4820 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_0 + ramulator.serving_requests_0_0_2_0 4848 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 +ramulator.average_serving_requests_0_0_2_0 0.000207 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 + ramulator.active_cycles_0_0_2_1 5304 # Total active cycles for level _0_0_2_1 + ramulator.busy_cycles_0_0_2_1 5304 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_1 + ramulator.serving_requests_0_0_2_1 5388 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 +ramulator.average_serving_requests_0_0_2_1 0.000230 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 + ramulator.active_cycles_0_0_2_2 8029 # Total active cycles for level _0_0_2_2 + ramulator.busy_cycles_0_0_2_2 8029 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_2 + ramulator.serving_requests_0_0_2_2 10729 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 +ramulator.average_serving_requests_0_0_2_2 0.000459 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 + ramulator.active_cycles_0_0_2_3 10958 # Total active cycles for level _0_0_2_3 + ramulator.busy_cycles_0_0_2_3 10958 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_3 + ramulator.serving_requests_0_0_2_3 11136 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 +ramulator.average_serving_requests_0_0_2_3 0.000476 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 + ramulator.active_cycles_0_0_3 36322 # Total active cycles for level _0_0_3 + ramulator.busy_cycles_0_0_3 36322 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3 + ramulator.serving_requests_0_0_3 38467 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 +ramulator.average_serving_requests_0_0_3 0.001644 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 + ramulator.active_cycles_0_0_3_0 8464 # Total active cycles for level _0_0_3_0 + ramulator.busy_cycles_0_0_3_0 8464 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_0 + ramulator.serving_requests_0_0_3_0 9048 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 +ramulator.average_serving_requests_0_0_3_0 0.000387 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 + ramulator.active_cycles_0_0_3_1 6641 # Total active cycles for level _0_0_3_1 + ramulator.busy_cycles_0_0_3_1 6641 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_1 + ramulator.serving_requests_0_0_3_1 6995 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 +ramulator.average_serving_requests_0_0_3_1 0.000299 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 + ramulator.active_cycles_0_0_3_2 6468 # Total active cycles for level _0_0_3_2 + ramulator.busy_cycles_0_0_3_2 6468 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_2 + ramulator.serving_requests_0_0_3_2 6976 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 +ramulator.average_serving_requests_0_0_3_2 0.000298 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 + ramulator.active_cycles_0_0_3_3 14862 # Total active cycles for level _0_0_3_3 + ramulator.busy_cycles_0_0_3_3 14862 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_3 + ramulator.serving_requests_0_0_3_3 15448 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 +ramulator.average_serving_requests_0_0_3_3 0.000660 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 + ramulator.read_transaction_bytes_0 313920 # The total byte of read transaction per channel + ramulator.write_transaction_bytes_0 0 # The total byte of write transaction per channel + ramulator.row_hits_channel_0_core 1952 # Number of row hits per channel per core + ramulator.row_misses_channel_0_core 2421 # Number of row misses per channel per core + ramulator.row_conflicts_channel_0_core 532 # Number of row conflicts per channel per core + ramulator.read_row_hits_channel_0_core 1952 # Number of row hits for read requests per channel per core + [0] 1952.0 # +ramulator.read_row_misses_channel_0_core 2421 # Number of row misses for read requests per channel per core + [0] 2421.0 # +ramulator.read_row_conflicts_channel_0_core 532 # Number of row conflicts for read requests per channel per core + [0] 532.0 # + ramulator.write_row_hits_channel_0_core 0 # Number of row hits for write requests per channel per core + [0] 0.0 # +ramulator.write_row_misses_channel_0_core 0 # Number of row misses for write requests per channel per core + [0] 0.0 # +ramulator.write_row_conflicts_channel_0_core 0 # Number of row conflicts for write requests per channel per core + [0] 0.0 # + ramulator.useless_activates_0_core 0 # Number of useless activations. E.g, ACT -> PRE w/o RD or WR + ramulator.read_latency_avg_0 47.916463 # The average memory latency cycles (in memory time domain) per request for all read requests in this channel + ramulator.read_latency_sum_0 235174 # The memory latency cycles (in memory time domain) sum for all read requests in this channel + ramulator.req_queue_length_avg_0 3.190415 # Average of read and write queue length per memory cycle per channel. + ramulator.req_queue_length_sum_0 74641674 # Sum of read and write queue length per memory cycle per channel. + ramulator.read_req_queue_length_avg_0 0.008032 # Read queue length average per memory cycle per channel. + ramulator.read_req_queue_length_sum_0 187905 # Read queue length sum per memory cycle per channel. + ramulator.write_req_queue_length_avg_0 3.182383 # Write queue length average per memory cycle per channel. + ramulator.write_req_queue_length_sum_0 74453769 # Write queue length sum per memory cycle per channel. + ramulator.record_read_hits 0.0 # record read hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_misses 0.0 # record_read_miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_conflicts 0.0 # record read conflict count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_hits 0.0 # record write hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_misses 0.0 # record write miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_conflicts 0.0 # record write conflict for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.dram_capacity 8589934592 # Number of bytes in simulated DRAM + ramulator.dram_cycles 23395603 # Number of DRAM cycles simulated + ramulator.incoming_requests 4917 # Number of incoming requests to DRAM + ramulator.read_requests 4908 # Number of incoming read requests to DRAM per core + [0] 4908.0 # + ramulator.write_requests 9 # Number of incoming write requests to DRAM per core + [0] 9.0 # + ramulator.ramulator_active_cycles 138921 # The total number of cycles that the DRAM part is active (serving R/W) + ramulator.incoming_requests_per_channel 4917.0 # Number of incoming requests to each DRAM channel + [0] 4917.0 # +ramulator.incoming_read_reqs_per_channel 4908.0 # Number of incoming read requests to each DRAM channel + [0] 4908.0 # + ramulator.physical_page_replacement 0 # The number of times that physical page replacement happens. + ramulator.maximum_bandwidth 19200000000 # The theoretical maximum bandwidth (Bps) + ramulator.in_queue_req_num_sum 74641674 # Sum of read/write queue length + ramulator.in_queue_read_req_num_sum 187905 # Sum of read queue length + ramulator.in_queue_write_req_num_sum 74453769 # Sum of write queue length + ramulator.in_queue_req_num_avg 3.190415 # Average of read/write queue length per memory cycle + ramulator.in_queue_read_req_num_avg 0.008032 # Average of read queue length per memory cycle + ramulator.in_queue_write_req_num_avg 3.182383 # Average of write queue length per memory cycle + ramulator.record_read_requests 0.0 # record read requests for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_requests 0.0 # record write requests for this core when it reaches request limit or to the end + [0] 0.0 # diff --git a/labs/LAB5/runs/leela_s_base-sms0/run.err b/labs/LAB5/runs/leela_s_base-sms0/run.err new file mode 100644 index 00000000..e69de29b diff --git a/labs/LAB5/runs/leela_s_base-sms0/run.out b/labs/LAB5/runs/leela_s_base-sms0/run.out new file mode 100644 index 00000000..f8a6bd9a --- /dev/null +++ b/labs/LAB5/runs/leela_s_base-sms0/run.out @@ -0,0 +1,107 @@ +Scarab gitrev: 7ab9e17 +Scarab started at Sun Jun 11 08:08:38 2023 + +Initialized Ramulator. +** Heartbeat: 1% -- { 1000000 } -- 0.00 KIPS (500.00 KIPS) +** Heartbeat: 2% -- { 2000001 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 3% -- { 3000006 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 4% -- { 4000007 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 5% -- { 5000012 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 6% -- { 6000015 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 7% -- { 7000015 } -- 1000.00 KIPS (538.46 KIPS) +** Heartbeat: 8% -- { 8000018 } -- 500.00 KIPS (533.33 KIPS) +** Heartbeat: 9% -- { 9000021 } -- 500.00 KIPS (529.41 KIPS) +** Heartbeat: 10% -- { 10000025 } -- 500.00 KIPS (526.32 KIPS) +** Heartbeat: 11% -- { 11000030 } -- 500.00 KIPS (523.81 KIPS) +** Heartbeat: 12% -- { 12000034 } -- 500.00 KIPS (521.74 KIPS) +** Heartbeat: 13% -- { 13000035 } -- 1000.00 KIPS (541.67 KIPS) +** Heartbeat: 14% -- { 14000035 } -- 500.00 KIPS (538.46 KIPS) +** Heartbeat: 15% -- { 15000035 } -- 500.00 KIPS (535.72 KIPS) +** Heartbeat: 16% -- { 16000036 } -- 500.00 KIPS (533.33 KIPS) +** Heartbeat: 17% -- { 17000037 } -- 500.00 KIPS (531.25 KIPS) +** Heartbeat: 18% -- { 18000040 } -- 500.00 KIPS (529.41 KIPS) +** Heartbeat: 19% -- { 19000043 } -- 1000.00 KIPS (542.86 KIPS) +** Heartbeat: 20% -- { 20000045 } -- 500.00 KIPS (540.54 KIPS) +** Heartbeat: 21% -- { 21000047 } -- 500.00 KIPS (538.46 KIPS) +** Heartbeat: 22% -- { 22000047 } -- 500.00 KIPS (536.59 KIPS) +** Heartbeat: 23% -- { 23000047 } -- 500.00 KIPS (534.88 KIPS) +** Heartbeat: 24% -- { 24000048 } -- 500.00 KIPS (533.33 KIPS) +** Heartbeat: 25% -- { 25000048 } -- 1000.00 KIPS (543.48 KIPS) +** Heartbeat: 26% -- { 26000048 } -- 500.00 KIPS (541.67 KIPS) +** Heartbeat: 27% -- { 27000050 } -- 500.00 KIPS (540.00 KIPS) +** Heartbeat: 28% -- { 28000050 } -- 500.00 KIPS (538.46 KIPS) +** Heartbeat: 29% -- { 29000052 } -- 500.00 KIPS (537.04 KIPS) +** Heartbeat: 30% -- { 30000054 } -- 500.00 KIPS (535.72 KIPS) +** Heartbeat: 31% -- { 31000057 } -- 1000.00 KIPS (543.86 KIPS) +** Heartbeat: 32% -- { 32000060 } -- 500.00 KIPS (542.37 KIPS) +** Heartbeat: 33% -- { 33000063 } -- 500.00 KIPS (540.98 KIPS) +** Heartbeat: 34% -- { 34000065 } -- 500.00 KIPS (539.68 KIPS) +** Heartbeat: 35% -- { 35000066 } -- 500.00 KIPS (538.46 KIPS) +** Heartbeat: 36% -- { 36000066 } -- 500.00 KIPS (537.31 KIPS) +** Heartbeat: 37% -- { 37000066 } -- 1000.00 KIPS (544.12 KIPS) +** Heartbeat: 38% -- { 38000067 } -- 500.00 KIPS (542.86 KIPS) +** Heartbeat: 39% -- { 39000069 } -- 500.00 KIPS (541.67 KIPS) +** Heartbeat: 40% -- { 40000071 } -- 500.00 KIPS (540.54 KIPS) +** Heartbeat: 41% -- { 41000071 } -- 500.00 KIPS (539.47 KIPS) +** Heartbeat: 42% -- { 42000071 } -- 500.00 KIPS (538.46 KIPS) +** Heartbeat: 43% -- { 43000075 } -- 500.00 KIPS (537.50 KIPS) +** Heartbeat: 44% -- { 44000075 } -- 1000.00 KIPS (543.21 KIPS) +** Heartbeat: 45% -- { 45000075 } -- 500.00 KIPS (542.17 KIPS) +** Heartbeat: 46% -- { 46000079 } -- 500.00 KIPS (541.18 KIPS) +** Heartbeat: 47% -- { 47000080 } -- 500.00 KIPS (540.23 KIPS) +** Heartbeat: 48% -- { 48000080 } -- 500.00 KIPS (539.33 KIPS) +** Heartbeat: 49% -- { 49000080 } -- 500.00 KIPS (538.46 KIPS) +** Heartbeat: 50% -- { 50000080 } -- 500.00 KIPS (537.64 KIPS) +** Heartbeat: 51% -- { 51000083 } -- 1000.00 KIPS (542.55 KIPS) +** Heartbeat: 52% -- { 52000084 } -- 500.00 KIPS (541.67 KIPS) +** Heartbeat: 53% -- { 53000084 } -- 500.00 KIPS (540.82 KIPS) +** Heartbeat: 54% -- { 54000084 } -- 500.00 KIPS (540.00 KIPS) +** Heartbeat: 55% -- { 55000087 } -- 500.00 KIPS (539.22 KIPS) +** Heartbeat: 56% -- { 56000088 } -- 500.00 KIPS (538.46 KIPS) +** Heartbeat: 57% -- { 57000089 } -- 1000.00 KIPS (542.86 KIPS) +** Heartbeat: 58% -- { 58000092 } -- 500.00 KIPS (542.06 KIPS) +** Heartbeat: 59% -- { 59000096 } -- 500.00 KIPS (541.29 KIPS) +** Heartbeat: 60% -- { 60000096 } -- 500.00 KIPS (540.54 KIPS) +** Heartbeat: 61% -- { 61000100 } -- 500.00 KIPS (539.82 KIPS) +** Heartbeat: 62% -- { 62000103 } -- 500.00 KIPS (539.13 KIPS) +** Heartbeat: 63% -- { 63000106 } -- 500.00 KIPS (538.46 KIPS) +** Heartbeat: 64% -- { 64000107 } -- 1000.00 KIPS (542.37 KIPS) +** Heartbeat: 65% -- { 65000107 } -- 500.00 KIPS (541.67 KIPS) +** Heartbeat: 66% -- { 66000110 } -- 500.00 KIPS (540.98 KIPS) +** Heartbeat: 67% -- { 67000111 } -- 500.00 KIPS (540.32 KIPS) +** Heartbeat: 68% -- { 68000114 } -- 500.00 KIPS (539.68 KIPS) +** Heartbeat: 69% -- { 69000115 } -- 500.00 KIPS (539.06 KIPS) +** Heartbeat: 70% -- { 70000119 } -- 500.00 KIPS (538.46 KIPS) +** Heartbeat: 71% -- { 71000122 } -- 1000.00 KIPS (541.99 KIPS) +** Heartbeat: 72% -- { 72000125 } -- 500.00 KIPS (541.35 KIPS) +** Heartbeat: 73% -- { 73000128 } -- 500.00 KIPS (540.74 KIPS) +** Heartbeat: 74% -- { 74000131 } -- 500.00 KIPS (540.15 KIPS) +** Heartbeat: 75% -- { 75000132 } -- 500.00 KIPS (539.57 KIPS) +** Heartbeat: 76% -- { 76000135 } -- 500.00 KIPS (539.01 KIPS) +** Heartbeat: 77% -- { 77000137 } -- 500.00 KIPS (538.46 KIPS) +** Heartbeat: 78% -- { 78000138 } -- 1000.00 KIPS (541.67 KIPS) +** Heartbeat: 79% -- { 79000140 } -- 500.00 KIPS (541.10 KIPS) +** Heartbeat: 80% -- { 80000143 } -- 500.00 KIPS (540.54 KIPS) +** Heartbeat: 81% -- { 81000147 } -- 500.00 KIPS (540.00 KIPS) +** Heartbeat: 82% -- { 82000149 } -- 500.00 KIPS (539.47 KIPS) +** Heartbeat: 83% -- { 83000149 } -- 500.00 KIPS (538.96 KIPS) +** Heartbeat: 84% -- { 84000151 } -- 500.00 KIPS (538.46 KIPS) +** Heartbeat: 85% -- { 85000154 } -- 1000.00 KIPS (541.40 KIPS) +** Heartbeat: 86% -- { 86000158 } -- 500.00 KIPS (540.88 KIPS) +** Heartbeat: 87% -- { 87000158 } -- 500.00 KIPS (540.37 KIPS) +** Heartbeat: 88% -- { 88000158 } -- 500.00 KIPS (539.88 KIPS) +** Heartbeat: 89% -- { 89000160 } -- 500.00 KIPS (539.39 KIPS) +** Heartbeat: 90% -- { 90000165 } -- 500.00 KIPS (538.92 KIPS) +** Heartbeat: 91% -- { 91000165 } -- 1000.00 KIPS (541.67 KIPS) +** Heartbeat: 92% -- { 92000166 } -- 500.00 KIPS (541.18 KIPS) +** Heartbeat: 93% -- { 93000170 } -- 500.00 KIPS (540.70 KIPS) +** Heartbeat: 94% -- { 94000174 } -- 500.00 KIPS (540.23 KIPS) +** Heartbeat: 95% -- { 95000175 } -- 500.00 KIPS (539.77 KIPS) +** Heartbeat: 96% -- { 96000178 } -- 500.00 KIPS (539.33 KIPS) +** Heartbeat: 97% -- { 97000178 } -- 500.00 KIPS (538.89 KIPS) +** Heartbeat: 98% -- { 98000179 } -- 1000.00 KIPS (541.44 KIPS) +** Heartbeat: 99% -- { 99000179 } -- 500.00 KIPS (540.98 KIPS) +** Core 0 Finished: insts:100000003 cycles:62388250 time:19496328125000 -- 1.60 IPC (1.60 IPC) -- N/A KIPS (540.54 KIPS) +done +Scarab finished at Sun Jun 11 08:11:43 2023 + diff --git a/labs/LAB5/runs/leela_s_base-sms0/stream.stat.0.out b/labs/LAB5/runs/leela_s_base-sms0/stream.stat.0.out new file mode 100644 index 00000000..11d37b20 --- /dev/null +++ b/labs/LAB5/runs/leela_s_base-sms0/stream.stat.0.out @@ -0,0 +1,188 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 62388250 Instructions: 100000003 IPC: 1.60287 + +DCACHE_PREF_HIT 0 0 + +IFETCH_WB_FIRST_SCHEDULE 0 -nan% 0 -nan% +PREFETCH_LAST_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_PREF_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_LOW_OP_SCHEDULE 0 -nan% 0 -nan% +DEMAND_LAST_SCHEDULE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +SEND_MISS_REQ_QUEUE 4908 4908 + +L1_DATA_EVICT 66 66 + +STREAM_BUFFER_REQ 0 0 + +PREF_SEND_TO_MEM_REQ 0 -nan% 0 -nan% +PREF_SEND_TO_MEM_REQ_FAIL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +HIT_TRAIN_STREAM 1757 30.830% 1757 30.830% +MISS_TRAIN_STREAM 3942 69.170% 3942 69.170% + 5699 100.000% 5699 100.000% + 0.69 0.63 0.69 0.63 + +STREAM_TRAIN_CREATE 2519 2519 + +MEM_REQ_MISS_HWP_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_SW_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_IFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DSTORE_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DPRF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_WB_Q 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_BY_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_WB 0 -nan% 0 -nan% +PREF_HIT_BY_PREF 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_WB 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_L1_FILL 0 -nan% 0 -nan% +DEMAND_L1_FILL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TOUCH_L1_REPLACE 0 0.000% 0 0.000% +NO_TOUCH_L1_REPLACE 66 100.000% 66 100.000% + 66 100.000% 66 100.000% + 1.00 1.01 1.00 1.01 + +PREF_REQ_QUE_FULL 0 0 + +STREAM_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +L2HIT_STREAM_PREF_REQ_QUE_FULL 0 0 + +L2HIT_HIT_TRAIN_STREAM 0 -nan% 0 -nan% +L2HIT_MISS_TRAIN_STREAM 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_TRAIN_CREATE 0 0 + +L2HIT_STREAM_BUFFER_REQ 0 0 + +L2HIT_STREAM_PREF_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_STREAM_PREF_DCACHE_INSERT 0 -nan% 0 -nan% +L2HIT_STREAM_L2_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_DCACHE_PORT_FULL 0 0 + +L2HIT_STREAM_PREF_L1_PORT_FULL 0 0 + +L2HIT_TRAIN_HIT_DEMAND 0 -nan% 0 -nan% +L2HIT_TRAIN_MISS_REQ 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_TRAIN_FILTER_MISS 0 -nan% 0 -nan% +L2HIT_TRAIN_FILTER_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_PREF_REQ_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_PREF_REQ_DCACHE_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_L2SEND_Q_FULL 0 -nan% 0 -nan% +L2HIT_L2SEND_Q_ENTER 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_MEM_REQ 0 0 + +REMOVE_REDUNDANT_STREAM_STAT 0 0 + +REPLACE_OLD_STREAM 2503 2503 + +REQ_SEND_QUEUE_STALL 0 0 + +STREAM_ENTER_RA 0 0 + +CORE_STREAM_LENGTH_0 24 15.385% 24 15.385% +CORE_STREAM_LENGTH_10 60 38.462% 60 38.462% +CORE_STREAM_LENGTH_20 29 18.590% 29 18.590% +CORE_STREAM_LENGTH_30 15 9.615% 15 9.615% +CORE_STREAM_LENGTH_40 8 5.128% 8 5.128% +CORE_STREAM_LENGTH_50 5 3.205% 5 3.205% +CORE_STREAM_LENGTH_60 1 0.641% 1 0.641% +CORE_STREAM_LENGTH_70 6 3.846% 6 3.846% +CORE_STREAM_LENGTH_80 0 0.000% 0 0.000% +CORE_STREAM_LENGTH_90 6 3.846% 6 3.846% +CORE_STREAM_LENGTH_100_P 2 1.282% 2 1.282% + 156 100.000% 156 100.000% + 2.19 2.16 2.19 2.16 + +CORE_CUM_STREAM_LENGTH_0 170 4.031% 170 4.031% +CORE_CUM_STREAM_LENGTH_10 892 21.152% 892 21.152% +CORE_CUM_STREAM_LENGTH_20 671 15.912% 671 15.912% +CORE_CUM_STREAM_LENGTH_30 540 12.805% 540 12.805% +CORE_CUM_STREAM_LENGTH_40 349 8.276% 349 8.276% +CORE_CUM_STREAM_LENGTH_50 265 6.284% 265 6.284% +CORE_CUM_STREAM_LENGTH_60 60 1.423% 60 1.423% +CORE_CUM_STREAM_LENGTH_70 446 10.576% 446 10.576% +CORE_CUM_STREAM_LENGTH_80 0 0.000% 0 0.000% +CORE_CUM_STREAM_LENGTH_90 547 12.971% 547 12.971% +CORE_CUM_STREAM_LENGTH_100_P 277 6.569% 277 6.569% + 4217 100.000% 4217 100.000% + 4.21 3.23 4.21 3.23 + +CORE_STREAM_TRAIN_HITS_0 99 63.462% 99 63.462% +CORE_STREAM_TRAIN_HITS_10 31 19.872% 31 19.872% +CORE_STREAM_TRAIN_HITS_20 8 5.128% 8 5.128% +CORE_STREAM_TRAIN_HITS_30 4 2.564% 4 2.564% +CORE_STREAM_TRAIN_HITS_40 2 1.282% 2 1.282% +CORE_STREAM_TRAIN_HITS_50 4 2.564% 4 2.564% +CORE_STREAM_TRAIN_HITS_60 1 0.641% 1 0.641% +CORE_STREAM_TRAIN_HITS_70 5 3.205% 5 3.205% +CORE_STREAM_TRAIN_HITS_80 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_90 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_100_P 2 1.282% 2 1.282% + 156 100.000% 156 100.000% + 0.95 1.77 0.95 1.77 + +CORE_CUM_STREAM_TRAIN_HITS_0 598 25.115% 598 25.115% +CORE_CUM_STREAM_TRAIN_HITS_10 462 19.404% 462 19.404% +CORE_CUM_STREAM_TRAIN_HITS_20 181 7.602% 181 7.602% +CORE_CUM_STREAM_TRAIN_HITS_30 135 5.670% 135 5.670% +CORE_CUM_STREAM_TRAIN_HITS_40 89 3.738% 89 3.738% +CORE_CUM_STREAM_TRAIN_HITS_50 234 9.828% 234 9.828% +CORE_CUM_STREAM_TRAIN_HITS_60 60 2.520% 60 2.520% +CORE_CUM_STREAM_TRAIN_HITS_70 376 15.792% 376 15.792% +CORE_CUM_STREAM_TRAIN_HITS_80 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_90 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_100_P 246 10.332% 246 10.332% + 2381 100.000% 2381 100.000% + 3.45 3.07 3.45 3.07 + +CORE_STREAM_TRAIN_CREATE 2519 2519 + + + diff --git a/labs/LAB5/runs/leela_s_base-sms1/PARAMS.in b/labs/LAB5/runs/leela_s_base-sms1/PARAMS.in new file mode 100644 index 00000000..2593c2b8 --- /dev/null +++ b/labs/LAB5/runs/leela_s_base-sms1/PARAMS.in @@ -0,0 +1,226 @@ +# File : PARAMS.kaby_lake +# Date : 03/06/19 +# Description : Kaby Lake Configuration +# +# Based on documentation found here: +# https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake + +## Simulation Parameters +--mode full +--model cmp +--sim_limit none + +## Core Parameters + +# Femptoseconds, 3.2GHz, used for energy estimates. +--chip_cycle_time 312500 + + +### Fetch Stage +--fetch_off_path_ops 1 +--fetch_across_cache_lines 1 + +# Will break the packet upon a taken branch. +--fetch_break_on_taken 1 + +# Number of bubble cycles to wait after taken branch. +--fetch_taken_bubble_cycles 0 + + +#### ICache +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 + +### Branch Predictor +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_mech tagescl + + +#### BTB + +# BTB model to use. +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 + +# Allow the BTB to be updated by off path ops. +--btb_off_path_writes 1 + + +#### CRS + +# Enable return stack +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 + +### iBP +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged + # iBTB Model. tc_tagless, tc_tagged, tc_hybrid. +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 + +### Decode Stage +--decode_cycles 5 + + +### Map Stage +--map_cycles 5 + + +### Issue Stage + +# Max number of instructions to be fetched, decoded, renamed, and issued per cycle. +--issue_width 6 + +--rs_fill_width 0 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 + + +### Exec Stage + +### DCache +--dcache_size 32768 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--dcache_assoc 4 +--dcache_line_size 64 + +### Reorder/Retire Stage + +# Max number of instructions to be retired per cycle. +--node_ret_width 6 +--node_table_size 224 + +# Do not keep stores in RSVs on cache misses; TODO: confirm what this knob does +--stores_do_not_block_window 1 + +# TODO: confirm what this knob does +--prefs_do_not_block_window 1 + + +## Uncore + +### Mid-level cache + +# Enable use of a midlevel cache between i/d and L1 +--mlc_present 0 + +### LLC +--l1_size 1048576 +--l1_banks 1 +--l1_cycles 18 +--l1_assoc 8 +--l1_line_size 64 +--l1_interleave_factor 64 + + +### Prefetcher +--pref_framework_on 1 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--pref_shared_queues 0 +--pref_train_on_pref_misses 0 +--pref_oracle_train 0 +--pref_ul1req_queue_overwrite_on_full 1 + +--stream_length 64 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 + +--pref_throttlefb_on=1 +--pref_acc_thresh_1=0.75 +--pref_acc_thresh_2=0.4 +--pref_acc_thresh_3=0.4 +--pref_timely_thresh=0.01 +--pref_polpf_thresh=0.005 +--pref_update_interval=8192 + +--mem_req_buffer_pref_watermark 4 +--promote_to_higher_priority_mem_req_type 1 + +### Memory +--addr_translation random + +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 + +--mem_req_buffer_entries 32 +--mem_l1_fill_queue_entries 32 +--va_page_size_bytes 4096 +--bus_width_in_bytes 8 + +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 + +## Other + + +### Debug +--debug_inst_start 0 +--debug_inst_stop -1 +--debug_cycle_start 0 +--debug_cycle_stop -1 + + +## Stats and Params +--dump_params 1 +--dump_stats 1 +--dump_trace 0 + +#################################### +--set_off_path_confirmed 1 + +--order_beyond_bus 1 + +--mem_ooo_stores 1 +--mem_obey_store_dep 1 diff --git a/labs/LAB5/runs/leela_s_base-sms1/PARAMS.out b/labs/LAB5/runs/leela_s_base-sms1/PARAMS.out new file mode 100644 index 00000000..6e79dc69 --- /dev/null +++ b/labs/LAB5/runs/leela_s_base-sms1/PARAMS.out @@ -0,0 +1,908 @@ +--mode full +--model cmp +--frontend memtrace +--inst_limit 100000000 +--sim_limit none +--dump_params 1 +--dump_stats 1 +--dump_trace 0 +--mlc_present 0 +--l1_size 1048576 +--l1_assoc 8 +--l1_line_size 64 +--l1_cycles 18 +--l1_banks 1 +--l1_interleave_factor 64 +--va_page_size_bytes 4096 +--addr_translation random +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 +--dcache_size 32768 +--dcache_assoc 4 +--dcache_line_size 64 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--mem_ooo_stores 1 +--mem_obey_store_dep 1 +--mem_req_buffer_entries 32 +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 +--promote_to_higher_priority_mem_req_type 1 +--mem_req_buffer_pref_watermark 4 +--mem_l1_fill_queue_entries 32 +--order_beyond_bus 1 +--set_off_path_confirmed 1 +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--bus_width_in_bytes 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 +--chip_cycle_time 312500 +--issue_width 6 +--rs_fill_width 0 +--node_table_size 224 +--node_ret_width 6 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 +--decode_cycles 5 +--map_cycles 5 +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--fetch_across_cache_lines 1 +--fetch_off_path_ops 0 +--fetch_break_on_taken 1 +--fetch_taken_bubble_cycles 0 +--stores_do_not_block_window 1 +--prefs_do_not_block_window 1 +--cbp_trace_r0 /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir/trace/drmemtrace.leela_s_base.mytest-m64.555086.2935.trace.gz +--memtrace_modules_log /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir/raw +--debug_cycle_start 0 +--debug_cycle_stop -1 +--debug_inst_start 0 +--debug_inst_stop -1 +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--bp_mech tagescl +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 +--btb_off_path_writes 1 +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_length 64 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 +--pref_framework_on 1 +--pref_shared_queues 0 +--pref_ul1req_queue_overwrite_on_full 1 +--pref_train_on_pref_misses 0 +--pref_oracle_train_on 0 +--pref_throttlefb_on 1 +--pref_acc_thresh_1 0.75 +--pref_acc_thresh_2 0.4 +--pref_acc_thresh_3 0.4 +--pref_update_interval 8192 +--pref_timely_thresh 0.01 +--pref_polpf_thresh 0.005 +--pref_sms_on 1 +1 1 1 1 1 1 1 + +--- Cut out everything below to use this file as PARAMS.in --- + +Parameter status at compile time and values supplied on the command line: + +SIM_MODE 0 full +SIM_MODEL 0 cmp +FRONTEND FE_PIN_EXEC_DRIVEN memtrace +INST_LIMIT NULL 100000000 +SIM_LIMIT "none" none +FORWARD_PROGRESS_LIMIT 100000000 +FORWARD_PROGRESS_INTERVAL 10000 +FAST_FORWARD 0 +FAST_FORWARD_UNTIL_ADDR 0 +FAST_FORWARD_TRACE_INS 0 +WARMUP 0 +HEARTBEAT_INTERVAL 1000000 +NUM_HEARTBEATS 0 +FILE_TAG "" +OUTPUT_DIR "." +STATUS_FILE NULL +BINDIR NULL +DUMP_PARAMS TRUE 1 +DUMP_STATS TRUE 1 +DUMP_TRACE FALSE 0 +CLEAR_STATS "never" +STATS_TO_TRACE NULL +STAT_TRACE_FILE "stats.trace" +STAT_TRACE_INTERVAL "i:100000" +PIPEVIEW FALSE +PIPEVIEW_FILE "pipeview" +MEMVIEW FALSE +MEMVIEW_FILE "memview.out" +MEMVIEW_START "never" +INST_HASH_TABLE_SIZE 500021 const +STDOUT_FILE NULL +STDERR_FILE NULL +PIN_EXEC_DRIVEN_FE_SOCKET "./pin_exec_driven_fe_socket.temp" +PRINT_PID FALSE +USE_UNSURE_FREE_LISTS FALSE +OPTIMIZER2_MAX_NUM_SLAVES 64 +OPTIMIZER2_PERFECT_MEMORYLESS FALSE +EXIT_COND 0 +ENABLE_SWPRF FALSE +MLC_PRESENT FALSE 0 +MLC_SIZE (512 * 1024) +MLC_ASSOC 4 +MLC_LINE_SIZE 64 +MLC_CYCLES 12 +PERFECT_MLC FALSE +MLC_READ_PORTS 1 +MLC_WRITE_PORTS 1 +MLC_BANKS 8 +MLC_INTERLEAVE_FACTOR 64 +MLC_CACHE_REPL_POLICY 0 +MLC_WRITE_THROUGH FALSE +PREFETCH_UPDATE_LRU_MLC TRUE +FORCE_L1_MISS FALSE +L1_SIZE (4 * 1024 * 1024) 1048576 +L1_ASSOC 8 8 +L1_LINE_SIZE 64 64 +L1_CYCLES 24 18 +PERFECT_L1 FALSE +PRIVATE_L1 FALSE +L1_READ_PORTS 1 +L1_WRITE_PORTS 1 +L1_BANKS 8 1 +L1_INTERLEAVE_FACTOR 64 64 +L1_CACHE_REPL_POLICY 0 +L1_WRITE_THROUGH FALSE +L1_IGNORE_WB FALSE +L1_USE_CORE_FREQ FALSE +MARK_L1_MISSES TRUE +PREFETCH_UPDATE_LRU_L1 TRUE +MEMORY_RANDOM_ADDR FALSE +VA_PAGE_SIZE_BYTES 4096 4096 +NUM_ADDR_NON_SIGN_EXTEND_BITS 48 +ADDR_TRANSLATION 0 random +CONSTANT_MEMORY_LATENCY FALSE +MEMORY_CYCLES 100 +STALL_MEM_REQS_ONLY FALSE +ICACHE_SIZE (64 * 1024) 32768 +ICACHE_ASSOC 4 4 +ICACHE_LINE_SIZE 64 64 +PERFECT_ICACHE FALSE +ICACHE_READ_PORTS 2 +ICACHE_WRITE_PORTS 1 +ICACHE_BANKS 8 +ICACHE_REPL 0 +DCACHE_SIZE (64 * 1024) 32768 +DCACHE_ASSOC 1 4 +DCACHE_LINE_SIZE 64 64 +DCACHE_CYCLES 2 +PERFECT_DCACHE FALSE +DCACHE_READ_PORTS 8 2 +DCACHE_WRITE_PORTS 1 1 +DCACHE_BANKS 1 1 +DCACHE_REPL 0 +DCACHE_REPL_PREF_THRESH 1 +MEM_OOO_STORES TRUE 1 +MEM_OBEY_STORE_DEP TRUE 1 +PREF_INSERT_LRU FALSE +PREF_INSERT_MIDDLE FALSE +PREF_INSERT_LOWQTR FALSE +PREF_INSERT_DYNACC FALSE +MEM_REQ_BUFFER_ENTRIES 32 32 +PRIVATE_MSHR_ON TRUE +MEM_PRIORITY_IFETCH 0 0 +MEM_PRIORITY_DFETCH 0 1 +MEM_PRIORITY_DSTORE 0 2 +MEM_PRIORITY_IPRF 9 3 +MEM_PRIORITY_DPRF 10 4 +MEM_PRIORITY_WB 0 5 +MEM_PRIORITY_WB_NODIRTY 0 5 +PROMOTE_TO_HIGHER_PRIORITY_MEM_REQ_TYPE FALSE 1 +MEM_REQ_BUFFER_PREF_WATERMARK 0 4 +MEM_REQ_BUFFER_WB_VALVE 2 +MEM_L1_FILL_QUEUE_ENTRIES 32 32 +MEM_BUS_OUT_QUEUE_PARTITION_ENABLE FALSE +MEM_MEM_QUEUE_PARTITION_ENABLE FALSE +MEM_BUS_OUT_QUEUE_AS_FIFO TRUE +OLDEST_FIRST_TO_MEM_QUEUE TRUE +ROUND_ROBIN_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE_TH 0 +L1_CYCLE_TIME 312500 +MLCQ_TO_L1Q_TRANSFER_LATENCY 1 +L1Q_TO_FSB_TRANSFER_LATENCY 1 +PRIORITIZE_PREFETCHES_WITH_UNIQUE FALSE +KICKOUT_PREFETCHES FALSE +KICKOUT_LOOK_FOR_OLDEST_FIRST FALSE +KICKOUT_OLDEST_PREFETCH FALSE +KICKOUT_OLDEST_PREFETCH_WITHIN_BANK FALSE +ORDER_BEYOND_BUS FALSE 1 +ALL_FIFO_QUEUES FALSE +QUEUE_MLC_SIZE 0 +QUEUE_L1_SIZE 0 +QUEUE_BUS_OUT_SIZE 0 +QUEUE_CORE_FILL_SIZE 0 +ALLOW_TYPE_MATCHES FALSE +STREAM_PREFETCH_ON FALSE +DC_PREF_CACHE_ENABLE FALSE +DC_PREF_CACHE_CYCLE 0 +PREF_INSERT_DCACHE_IMM TRUE +DC_PREF_CACHE_SIZE (64 * 1024) +DC_PREF_CACHE_ASSOC 4 +DC_PREF_ONLY_L1HIT FALSE +PREF_CACHE_USE_RDY_CYCLE FALSE +IC_PREF_CACHE_ENABLE FALSE +IC_PREF_CACHE_SIZE (64 * 1024) +IC_PREF_CACHE_ASSOC 4 +L1_PREF_CACHE_ENABLE FALSE +L1_PREF_CACHE_SIZE (1024 * 1024) +L1_PREF_CACHE_ASSOC 8 +SET_OFF_PATH_CONFIRMED FALSE 1 +USE_CONFIRMED_OFF FALSE +PREFCACHE_MOVE_OFFPATH FALSE +CACHE_STAT_ENABLE FALSE +PREF_DCACHE_HIT_FILL_L1 TRUE +PREF_ICACHE_HIT_FILL_L1 TRUE +CRITICAL_ACCESS_PLOT_ENABLE FALSE +CRITICAL_ACCESS_PLOT_FILE "critical_access_plot.dat" +ROUND_ROBIN_TO_L1 FALSE +PREF_I_TOGETHER FALSE +ONE_MORE_CACHE_LINE_ENABLE FALSE +L1_STATIC_PARTITION_ENABLE 0 +L1_STATIC_PARTITION NULL +L1_DYNAMIC_PARTITION_ENABLE FALSE +L1_DYNAMIC_PARTITION_POLICY 0 +PARTITION_UMON_DSS_PREF_ENABLE FALSE +L1_CACHE_HIT_POSITION_COLLECT FALSE +L1_PART_ON FALSE +L1_PART_TRIGGER "c:1000000" +L1_PART_START "t:0" +L1_PART_WARMUP FALSE +L1_PART_SHADOW_WARMUP FALSE +L1_PART_METRIC 0 +L1_PART_SEARCH 0 +L1_PART_USE_STALLING TRUE +L1_PART_FILL_DELAY 0 +L1_SHADOW_TAGS_MODULO 1 +HIER_MSHR_ON FALSE +PERF_PRED_ENABLE FALSE +PERF_PRED_MECH PERF_PRED_CP +PERF_PRED_REQ_LATENCY_MECH PERF_PRED_REQ_LATENCY_MECH_REQ_LATENCY +PERF_PRED_COUNT_ALL FALSE +PERF_PRED_COUNT_INST_MISSES TRUE +PERF_PRED_COUNT_PREFETCHES FALSE +PERF_PRED_COUNT_OFFPATH_REQS FALSE +PERF_PRED_COUNT_BW_REQS TRUE +PERF_PRED_UPDATE_MEM_REQ_TYPE FALSE +PERF_PRED_SLACK_PERIOD_SIZE 32 +PERF_PRED_REQS_FINISH_AT_FILL FALSE +PERF_PRED_MEM_UTIL_VIA_BUS_BW FALSE +PERF_PRED_CHIP_UTIL_VIA_MEM_STALL FALSE +DUMB_MODEL_AVG_REQ_DISTANCE 100 +DUMB_MODEL_RANDOMIZE_DISTANCE FALSE +DUMB_MODEL_AVG_REQ_DISTANCE_PER_CORE NULL +DUMB_MODEL_AVG_ROW_HITS 1 +DUMB_MODEL_AVG_ROW_HITS_PER_CORE NULL +DUMB_MODEL_MLP 1 +DUMB_MODEL_MLP_PER_CORE NULL +RAMULATOR_STANDARD "DDR4" DDR4 +RAMULATOR_SPEED "DDR4_2400R" DDR4_2400R +RAMULATOR_ORG "DDR4_8Gb_x8" DDR4_8Gb_x8 +RAMULATOR_CHANNELS 1 1 +RAMULATOR_RANKS 1 1 +RAMULATOR_BANKGROUPS 4 4 +RAMULATOR_BANKS 4 4 +RAMULATOR_CHIP_WIDTH 8 8 +BUS_WIDTH_IN_BYTES 8 8 +RAMULATOR_ROWS 65536 65536 +RAMULATOR_COLS 1024 1024 +RAMULATOR_SCHEDULING_POLICY "FRFCFS_Cap" FRFCFS_Cap +RAMULATOR_READQ_ENTRIES 32 32 +RAMULATOR_WRITEQ_ENTRIES 32 32 +RAMULATOR_REC_CMD_TRACE "off" FALSE +RAMULATOR_PRINT_CMD_TRACE "off" FALSE +RAMULATOR_USE_REST_OF_ADDR_AS_ROW_ADDR "on" +RAMULATOR_TCK 833333 833333 +RAMULATOR_TCL 16 16 +RAMULATOR_TCCD 6 6 +RAMULATOR_TCCDS 4 4 +RAMULATOR_TCCDL 6 6 +RAMULATOR_TCWL 12 12 +RAMULATOR_TBL 4 4 +RAMULATOR_TWTR 9 9 +RAMULATOR_TWTRS 3 3 +RAMULATOR_TWTRL 9 9 +RAMULATOR_TRP 16 16 +RAMULATOR_TRPpb 16 16 +RAMULATOR_TRPab 16 16 +RAMULATOR_TRCD 16 16 +RAMULATOR_TRCDR 16 16 +RAMULATOR_TRCDW 16 16 +RAMULATOR_TRAS 39 39 +DRAM_TECH_IN_NM 32 32 +DVFS_ON FALSE +DVFS_METRIC DVFS_METRIC_NUM_ELEMS +DVFS_CONFIGS NULL +DVFS_CONFIG_FILE NULL +DVFS_START "t:0" +DVFS_PERIOD "t:312500000000" +DVFS_LOG TRUE +DVFS_INDIVIDUAL_CORES FALSE +DVFS_CHIP_LEVEL FALSE +DVFS_STATIC NULL +DVFS_FORCE_CONFIG NULL +DVFS_REPLAY_CONFIG_TRACE NULL +DVFS_USE_ORACLE FALSE +DVFS_USE_BW_SHARING FALSE +DVFS_USE_DRAM_SHARING FALSE +DVFS_USE_STALL_TIME FALSE +DVFS_DRAM_SHARING_SOLVER_BIN NULL +DVFS_DRAM_SHARING_SOLVER_STRICT TRUE +DVFS_BW_SHARING_BUS_UTIL_THRESH 0.95 +DVFS_BW_SHARING_MAX_REQS 28.0 +DVFS_BW_SHARING_MAX_RW_COST 0.25 +DVFS_BW_SHARING_NO_PREF_STALL TRUE +DVFS_BW_SHARING_CRIT_STATS TRUE +DVFS_COUNT_L1_ACCESS_STALL FALSE +NUM_CORES 1 +CHIP_CYCLE_TIME 312500 312500 +CORE_0_CYCLE_TIME 312500 +CORE_1_CYCLE_TIME 312500 +CORE_2_CYCLE_TIME 312500 +CORE_3_CYCLE_TIME 312500 +CORE_4_CYCLE_TIME 312500 +CORE_5_CYCLE_TIME 312500 +CORE_6_CYCLE_TIME 312500 +CORE_7_CYCLE_TIME 312500 +CORE_8_CYCLE_TIME 312500 +CORE_9_CYCLE_TIME 312500 +CORE_10_CYCLE_TIME 312500 +CORE_11_CYCLE_TIME 312500 +CORE_12_CYCLE_TIME 312500 +CORE_13_CYCLE_TIME 312500 +CORE_14_CYCLE_TIME 312500 +CORE_15_CYCLE_TIME 312500 +CORE_16_CYCLE_TIME 312500 +CORE_17_CYCLE_TIME 312500 +CORE_18_CYCLE_TIME 312500 +CORE_19_CYCLE_TIME 312500 +CORE_20_CYCLE_TIME 312500 +CORE_21_CYCLE_TIME 312500 +CORE_22_CYCLE_TIME 312500 +CORE_23_CYCLE_TIME 312500 +CORE_24_CYCLE_TIME 312500 +CORE_25_CYCLE_TIME 312500 +CORE_26_CYCLE_TIME 312500 +CORE_27_CYCLE_TIME 312500 +CORE_28_CYCLE_TIME 312500 +CORE_29_CYCLE_TIME 312500 +CORE_30_CYCLE_TIME 312500 +CORE_31_CYCLE_TIME 312500 +CORE_32_CYCLE_TIME 312500 +CORE_33_CYCLE_TIME 312500 +CORE_34_CYCLE_TIME 312500 +CORE_35_CYCLE_TIME 312500 +CORE_36_CYCLE_TIME 312500 +CORE_37_CYCLE_TIME 312500 +CORE_38_CYCLE_TIME 312500 +CORE_39_CYCLE_TIME 312500 +CORE_40_CYCLE_TIME 312500 +CORE_41_CYCLE_TIME 312500 +CORE_42_CYCLE_TIME 312500 +CORE_43_CYCLE_TIME 312500 +CORE_44_CYCLE_TIME 312500 +CORE_45_CYCLE_TIME 312500 +CORE_46_CYCLE_TIME 312500 +CORE_47_CYCLE_TIME 312500 +CORE_48_CYCLE_TIME 312500 +CORE_49_CYCLE_TIME 312500 +CORE_50_CYCLE_TIME 312500 +CORE_51_CYCLE_TIME 312500 +CORE_52_CYCLE_TIME 312500 +CORE_53_CYCLE_TIME 312500 +CORE_54_CYCLE_TIME 312500 +CORE_55_CYCLE_TIME 312500 +CORE_56_CYCLE_TIME 312500 +CORE_57_CYCLE_TIME 312500 +CORE_58_CYCLE_TIME 312500 +CORE_59_CYCLE_TIME 312500 +CORE_60_CYCLE_TIME 312500 +CORE_61_CYCLE_TIME 312500 +CORE_62_CYCLE_TIME 312500 +CORE_63_CYCLE_TIME 312500 +ISSUE_WIDTH 4 6 +RS_FILL_WIDTH 8 0 +NODE_TABLE_SIZE 256 224 +NODE_RET_WIDTH 4 6 +NODE_RETIRE_RATE 10 +RS_SIZES "256" 97 +RS_CONNECTIONS "xF" 0 +FU_TYPES "0, 0, 0, 0" 0 0 0 0 0 0 0 0 +DECODE_CYCLES 1 5 +MAP_CYCLES 1 5 +EXTRA_RECOVERY_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after recovery. +EXTRA_REDIRECT_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after redirect. +EXTRA_CALLSYS_CYCLES 20 const +DIE_ON_CALLSYS FALSE +DIE_ON_RET_STALL_THRESH 0 +DIE_ON_RET_STALL_CORE 0 +DIE_ON_MEM_BLOCK_THRESH 0 +DIE_ON_MEM_BLOCK_CORE 0 +FETCH_ACROSS_CACHE_LINES FALSE 1 +FETCH_OFF_PATH_OPS TRUE 0 +FETCH_BREAK_ON_TAKEN FALSE 1 +FETCH_TAKEN_BUBBLE_CYCLES 0 0 +WP_COLLECT_STATS FALSE +SWITCH_IC_FETCH_ON_RECOVERY TRUE +OP_INV_DELAY 1 +OP_NOP_DELAY 1 +OP_CF_DELAY 1 +OP_MOV_DELAY 1 +OP_CMOV_DELAY 1 +OP_LDA_DELAY 1 +OP_IMEM_DELAY 1 +OP_IADD_DELAY 1 +OP_IMUL_DELAY 3 +OP_IDIV_DELAY -20 +OP_ICMP_DELAY 1 +OP_LOGIC_DELAY 1 +OP_SHIFT_DELAY 1 +OP_FMEM_DELAY 1 +OP_FCVT_DELAY 3 +OP_FADD_DELAY 3 +OP_FMUL_DELAY 5 +OP_FMA_DELAY 5 +OP_FDIV_DELAY -20 +OP_FCMP_DELAY 3 +OP_FCMOV_DELAY 1 +OP_GATHER_DELAY 12 +OP_SCATTER_DELAY 18 +OP_PIPELINED_FAST_DELAY 2 +OP_PIPELINED_MEDIUM_DELAY 5 +OP_PIPELINED_SLOW_DELAY 10 +OP_NOTPIPELINED_MEDIUM_DELAY -5 +OP_NOTPIPELINED_SLOW_DELAY -20 +OP_NOTPIPELINED_VERY_SLOW_DELAY -100 +UNIFORM_OP_DELAY 0 +STALL_ON_WAIT_MEM TRUE +STORES_DO_NOT_BLOCK_WINDOW FALSE 1 +PREFS_DO_NOT_BLOCK_WINDOW FALSE 1 +OBEY_REG_DEP TRUE +OLDEST_FIRST_SCHED FALSE +FIND_EMPTIEST_RS FALSE +TRACK_L1_MISS_DEPS FALSE +CBP_TRACE_R0 NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir/trace/drmemtrace.leela_s_base.mytest-m64.555086.2935.trace.gz +CBP_TRACE_R1 NULL +CBP_TRACE_R2 NULL +CBP_TRACE_R3 NULL +CBP_TRACE_R4 NULL +CBP_TRACE_R5 NULL +CBP_TRACE_R6 NULL +CBP_TRACE_R7 NULL +CBP_TRACE_R8 NULL +CBP_TRACE_R9 NULL +CBP_TRACE_R10 NULL +CBP_TRACE_R11 NULL +CBP_TRACE_R12 NULL +CBP_TRACE_R13 NULL +CBP_TRACE_R14 NULL +CBP_TRACE_R15 NULL +CBP_TRACE_R16 NULL +CBP_TRACE_R17 NULL +CBP_TRACE_R18 NULL +CBP_TRACE_R19 NULL +CBP_TRACE_R20 NULL +CBP_TRACE_R21 NULL +CBP_TRACE_R22 NULL +CBP_TRACE_R23 NULL +CBP_TRACE_R24 NULL +CBP_TRACE_R25 NULL +CBP_TRACE_R26 NULL +CBP_TRACE_R27 NULL +CBP_TRACE_R28 NULL +CBP_TRACE_R29 NULL +CBP_TRACE_R30 NULL +CBP_TRACE_R31 NULL +CBP_TRACE_R32 NULL +CBP_TRACE_R33 NULL +CBP_TRACE_R34 NULL +CBP_TRACE_R35 NULL +CBP_TRACE_R36 NULL +CBP_TRACE_R37 NULL +CBP_TRACE_R38 NULL +CBP_TRACE_R39 NULL +CBP_TRACE_R40 NULL +CBP_TRACE_R41 NULL +CBP_TRACE_R42 NULL +CBP_TRACE_R43 NULL +CBP_TRACE_R44 NULL +CBP_TRACE_R45 NULL +CBP_TRACE_R46 NULL +CBP_TRACE_R47 NULL +CBP_TRACE_R48 NULL +CBP_TRACE_R49 NULL +CBP_TRACE_R50 NULL +CBP_TRACE_R51 NULL +CBP_TRACE_R52 NULL +CBP_TRACE_R53 NULL +CBP_TRACE_R54 NULL +CBP_TRACE_R55 NULL +CBP_TRACE_R56 NULL +CBP_TRACE_R57 NULL +CBP_TRACE_R58 NULL +CBP_TRACE_R59 NULL +CBP_TRACE_R60 NULL +CBP_TRACE_R61 NULL +CBP_TRACE_R62 NULL +CBP_TRACE_R63 NULL +MEMTRACE_MODULES_LOG NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.leela_s_base.mytest-m64.555086.8417.dir/raw +DUMB_CORE_ON FALSE +DUMB_CORE 1 +DEBUG_CYCLE_START 0 0 +DEBUG_CYCLE_STOP 0 -1 +DEBUG_TIME_START 0 +DEBUG_TIME_STOP 0 +DEBUG_INST_START 0 0 +DEBUG_INST_STOP 0 -1 +DEBUG_OP_START 0 +DEBUG_OP_STOP 0 +DEBUG_CACHE_LIB FALSE +DEBUG_HASH_LIB FALSE +DEBUG_LIST_LIB FALSE +DEBUG_PORT_LIB FALSE +DEBUG_BUS_LIB FALSE +DEBUG_OP_POOL FALSE +DEBUG_ORACLE FALSE +DEBUG_FRONTEND FALSE +DEBUG_ADDR_TRANS FALSE +DEBUG_BP FALSE +DEBUG_BP_DIR FALSE +DEBUG_BTB FALSE +DEBUG_CRS FALSE +DEBUG_MAP FALSE +DEBUG_MEMORY FALSE +DEBUG_REPLAY FALSE +DEBUG_FREQ FALSE +DEBUG_MODEL FALSE +DEBUG_THREAD FALSE +DEBUG_ICACHE_STAGE FALSE +DEBUG_DECODE_STAGE FALSE +DEBUG_MAP_STAGE FALSE +DEBUG_NODE_STAGE FALSE +DEBUG_EXEC_STAGE FALSE +DEBUG_DCACHE_STAGE FALSE +DEBUG_RETIRED_UOPS FALSE +DEBUG_EXC_INSERTS FALSE +DEBUG_BP_CONF FALSE +DEBUG_ONPATH_CONF FALSE +DEBUG_STREAM FALSE +DEBUG_STREAM_MEM FALSE +DEBUG_WAY FALSE +DEBUG_L2MARKV FALSE +DEBUG_L2L1PREF FALSE +DEBUG_PERF_PRED FALSE +DEBUG_POWER_UTILS FALSE +DEBUG_DVFS FALSE +DEBUG_TRACE_READ FALSE +DEBUG_INST_FIELDS FALSE +DEBUG_OP_FIELDS FALSE +DEBUG_PIN_EXEC_DRIVEN FALSE +DEBUG_CACHE_PART FALSE +DEBUG_OPTIMIZER2 FALSE +DEBUG_PREF FALSE +PERFECT_BP FALSE +PERFECT_BTB FALSE +PERFECT_IBP FALSE +PERFECT_CRS FALSE +PERFECT_CBR_BTB FALSE +PERFECT_NT_BTB FALSE +CFS_PER_CYCLE 3 6 # Number of branches that can be predicted in a single cycle +UPDATE_BP_OFF_PATH FALSE 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +BP_UPDATE_AT_RETIRE FALSE 0 # Update the BP at retire. If false, update at the end of exec. +BP_MECH 0 tagescl +LATE_BP_MECH NUM_BP +LATE_BP_LATENCY 5 +HIST_LENGTH 16 +PHT_CTR_BITS 2 const +BHT_ENTRIES (4 * 1024) +BHT_ASSOC 4 +HYBRIDS_INDEX_LENGTH 16 +HYBRIDG_HIST_LENGTH 16 +HYBRIDP_HIST_LENGTH 16 +FILTER_INDEX_LENGTH 16 +USE_FILTER FALSE +INF_HYBRIDGP FALSE +BP_HASH_TOS FALSE +IBTB_HASH_TOS FALSE +BTB_MECH 0 generic +BTB_ENTRIES (4 * 1024) 4096 +BTB_ASSOC 4 4 +BTB_OFF_PATH_WRITES TRUE 1 +ENABLE_CRS TRUE 1 +CRS_ENTRIES 32 32 +CRS_REALISTIC 0 1 +ENABLE_IBP TRUE 1 # Enable the indirect branch predictor +USE_PAT_HIST TRUE +IBTB_MECH 1 tc_tagged +IBTB_HIST_LENGTH 16 +IBTB_OFF_PATH_WRITES TRUE 1 # Allow off path ops to update the ibtb. +TARGETS_IN_HIST 4 +TC_ENTRIES (4 * 1024) 4096 +TC_ASSOC 4 4 +NUM_CORR_BRANCHES 3 +SEL_HIST_BP_ENTRIES 8192 +SEL_HIST_LENGTH 16 +SEL_HIST_DYN_CNT_TH 16 +SEL_HIST_MISPRED_TH 4 +ENABLE_BP_CONF FALSE +CONF_MECH 0 +PERF_BP_CONF_PRED FALSE +BPC_BITS 16 +BPC_MECH 1 +BPC_CTR_RESET TRUE +BPC_CIT_BITS 8 +BPC_CIT_TH 50 +BPC_CTR_BITS 3 +OPC_COUNT_ZEROS FALSE +OPC_COUNT_THRESH 10 +INF_LOOP FALSE +INF_LOOP_BUCKETS 811 +LOOP_ENTRIES (4 * 1024) +LOOP_ASSOC 4 +LOOP_COUNT_MAX 127 +LOOP_REPEAT_MAX 15 +KNOB_PRINT_BRINFO FALSE +BR_MISPRED_FILE NULL +CONF_PERCEPTRON_TH 0 +CONF_PERCEPTRON_CTR_BITS 8 +CONF_PERCEPTRON_ENTRIES 127 +CONF_PERCEPTRON_THRESH_OVRD 0 +CONF_HIST_LENGTH 32 +PERCEPTRON_CONF_USE_CONF FALSE +PERCEPTRON_CONF_TRAIN_HIS FALSE +PERCEPTRON_CONF_TRAIN_CONF FALSE +PERCEPTRON_CONF_TRAIN_OFFSET_CONF FALSE +PERCEPTRON_TRAIN_MISP_FACTOR 1 +PERCEPTRON_TRAIN_CORR_FACTOR 1 +PERCEPTRON_CONF_HIS_BOTH FALSE +PERCEPTRON_CONF_HIS_BOTH_LENGTH 4 +ENABLE_ICACHE_PACKET_BREAKING TRUE +NUM_LOAD_STORE_PER_PACKET 0 +PACKET_BREAK_ON_FUS FALSE +PACKET_BREAK_FU_TYPES "G,G,G,G,G,G,G,G,G,G,G,G" +POWER_INTF_ON FALSE +POWER_INTF_ENABLE_SCALING FALSE +POWER_INTF_EXEC "power/power_intf.py" +POWER_INTF_REF_CHIP_TECH_NM 22 +POWER_INTF_REF_CHIP_FREQ (3.2e9) +POWER_INTF_REF_MEMORY_FREQ (0.8e9) +POWER_OTHER (0.0) +PREF_STREAM_ON FALSE 1 +PREF_STREAM_PER_CORE_ENABLE FALSE 1 +STREAM_BUFFER_N 16 +STREAM_PREFETCH_N 2 4 +STREAM_START_DIS 5 1 +STREAM_LENGTH 16 64 +STREAM_FULL_N 1 +STREAM_TRAIN_LENGTH 16 +STREAM_TRAIN_NUM 1 4 +PREF_ACC_USE_CACHE FALSE +STREAM_STALL_ON_QUEUE_FULL FALSE +PREF_SCHEDULE_NUM 4 +TRAIN_FILTER_SIZE 32 +PREF_REQ_Q_SIZE 64 +STREAM_CREATE_ON_DC_MISS FALSE 0 +STREAM_CREATE_ON_L1_MISS TRUE 1 +STREAM_TRAIN_ON_WRONGPATH TRUE +STREAM_CREATE_ON_WRONGPATH TRUE +STREAM_PREF_INTO_DCACHE FALSE +REMOVE_REDUNDANT_STREAM FALSE +L2HIT_STREAM_SCHEDULE_NUM 4 +PREF_REQ_QUEUE_FILTER_ON FALSE +HW_PREF_HIT_TRAIN_STREAM FALSE +L2HIT_STREAM_BUFFER_N 32 +L2HIT_STREAM_PREFETCH_N 2 +L2HIT_STREAM_START_DIS 2 +L2HIT_STREAM_LENGTH 8 +L2HIT_PREF_REQ_Q_SIZE 128 +L2HIT_L2ACCESS_REQ_Q_SIZE 64 +PREF_STREAM_ACCPERSTREAM FALSE +PREF_ACC_DISTANCE_10 128 +PREF_FRAMEWORK_ON FALSE 1 +PREF_TRACE_ON FALSE +PREF_DL0REQ_QUEUE_SIZE 32 +PREF_UMLC_REQ_QUEUE_SIZE 64 +PREF_UL1REQ_QUEUE_SIZE 128 +PREF_SHARED_QUEUES TRUE 0 +PREF_DL0_MISS_ON TRUE +PREF_DL0_HIT_ON TRUE +PREF_DL0REQ_QUEUE_FILTER_ON TRUE +PREF_UMLC_REQ_QUEUE_FILTER_ON TRUE +PREF_UL1REQ_QUEUE_FILTER_ON TRUE +PREF_DL0REQ_ADD_FILTER_ON TRUE +PREF_UMLC_REQ_ADD_FILTER_ON TRUE +PREF_UL1REQ_ADD_FILTER_ON TRUE +PREF_DL0REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UMLC_REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UL1REQ_QUEUE_OVERWRITE_ON_FULL FALSE 1 +PREF_DL0SCHEDULE_NUM 4 +PREF_UMLC_SCHEDULE_NUM 4 +PREF_UL1SCHEDULE_NUM 4 +PREF_L1Q_DEMAND_RESERVE 0 +PREF_REPORT_PREF_MATCH_AS_MISS FALSE +PREF_REPORT_PREF_MATCH_AS_HIT TRUE +PREF_UPDATE_ON_WRONGPATH TRUE +PREF_TRAIN_ON_PREF_MISSES FALSE 0 +PREF_ORACLE_TRAIN_ON FALSE 0 +PREF_REQ_DROP FALSE +PREF_THROTTLE_ON FALSE +PREF_THROTTLEFB_ON FALSE 1 +PREF_ACC_THRESH_1 0.90 0.75 +PREF_ACC_THRESH_2 0.70 0.4 +PREF_ACC_THRESH_3 0.60 0.4 +PREF_ACC_THRESH_4 0.40 +PREF_UPDATE_INTERVAL 0 8192 +PREF_ANALYZE_LOAD FALSE +PREF_POL_THRESH_1 0.25 +PREF_POL_THRESH_2 0.10 +PREF_POLBV_ON FALSE +PREF_POLBV_SIZE 1024 +PREF_TIMELY_THRESH 0.05 0.01 +PREF_POLPF_THRESH 0.01 0.005 +PREF_DEGFB_USEONLYACC FALSE +PREF_DEGFB_USEONLYPOL FALSE +PREF_DEGFB_USEONLYLATE FALSE +PREF_TIMELY_THRESH_2 0.005 +PREF_DEGFB_STATPHASEFILE FALSE +PREF_MAX_DEGFB 4 +PREF_DHAL FALSE +PREF_DHAL_SENTTHRESH 16 +PREF_DHAL_USETHRESH_MAX 12 +PREF_DHAL_USETHRESH_MIN2 8 +PREF_DHAL_USETHRESH_MIN1 4 +PREF_DHAL_MAXDEG 64 +PREF_HFILTER_ON FALSE +PREF_HFILTER_INDEX_BITS 12 +PREF_HFILTER_USE_PC FALSE +PREF_HFILTER_PRED_USELESS_THRES 2 +PREF_HFILTER_RESET_ENABLE FALSE +PREF_HFILTER_RESET_INTERVAL 100000 +L2L1PREF_ON FALSE +L2WAY_PREF FALSE +L2MARKV_PREF_ON FALSE +L2NEXT_PREF_ON FALSE +L2HIT_STREAM_PREF_ON FALSE +L2L1_DC_HIT_TRAIN FALSE +L1_HIT_DUMP_FILE_ON FALSE +L1_HIT_DUMP_WO_TXT FALSE +L1_HIT_DUMPFILE "l1hit_dump.out" +IDEAL_L2_L1_PREFETCHER FALSE +IDEAL_L2_ICACHE_PREFETCHER FALSE +L1WAY_PREF_SEND_QUEUE 4 +L1PREF_REQ_QUEUE_SIZE 1024 +L1PREF_IMMEDIATE FALSE +L1WAY_PREF_TIMER_DIS 1000 +L1MARKV_PREF_SEND_QUEUE 4 +L1PREF_MARKV_REQ_QUEUE_SIZE 1024 +MARKV_L2ACCESS_REQ_Q_SIZE 64 +L1MARKV_PREF_IMMEDIATE FALSE +L1MARKV_PREF_TIMER_DIS 1 +L2L1_HIT_TRAIN TRUE +L1MARKV_REQ_TH 1 +L2L1_IMMEDIATE_PREF_CACHE FALSE +L2L1_FILL_PREF_CACHE FALSE +L2L1_L2_HIT_STAT FALSE +PREF_GHB_ON FALSE +DEBUG_PREF_GHB FALSE +PREF_GHB_BUFFER_N 1024 +PREF_GHB_INDEX_N 128 +PREF_GHB_CZONE_BITS 12 +PREF_GHB_DEGREE 16 +PREF_GHB_MAX_DEGREE 32 +PREF_STRIDE_ON FALSE +DEBUG_PREF_STRIDE FALSE +PREF_STRIDE_TABLE_N 1024 +PREF_STRIDE_REGION_BITS 16 +PREF_STRIDE_DEGREE 4 +PREF_STRIDE_DISTANCE 16 +PREF_STRIDE_STARTDISTANCE 1 +PREF_STRIDE_SINGLE_THRESH 6 +PREF_STRIDE_MULTI_THRESH 6 +PREF_STRIDE_SINGLE_STRIDE_MODE FALSE +PREF_STRIDEPC_ON FALSE +DEBUG_PREF_STRIDEPC FALSE +PREF_STRIDEPC_TABLE_N 1024 +PREF_STRIDEPC_DEGREE 4 +PREF_STRIDEPC_DISTANCE 16 +PREF_STRIDEPC_USELOADADDR FALSE +PREF_STRIDEPC_TRAINNUM 2 +PREF_STRIDEPC_STARTDIS 4 +PREF_PHASE_ON FALSE +PREF_PHASE_STUDY FALSE +DEBUG_PREF_PHASE FALSE +PREF_PHASE_PRIME_HASH 16381 +PREF_PHASE_INFOSIZE 16384 +PREF_PHASE_LOG2REGIONSIZE 12 +PREF_PHASE_REGIONENTRIES 64 +PREF_PHASE_TRACKEDREGIONS 32 +PREF_PHASE_INTERVAL 100000 +PREF_PHASE_TABLE_SIZE 64 +PREF_PHASE_MAXDIFF_THRESH 64 +PREF_PHASE_MIN_MISSES 64 +PREF_PHASE_MISSPER 0.4 +PREF_2DC_ON FALSE +DEBUG_PREF_2DC FALSE +PREF_2DC_CACHE_SIZE (1 * 1024) +PREF_2DC_CACHE_ASSOC 4 +PREF_2DC_CACHE_LINE_SIZE 1 +PREF_2DC_DEGREE 16 +PREF_2DC_ZONE_SHIFT 10 +PREF_2DC_TAG_SIZE 16 +PREF_2DC_NUM_REGIONS 64 +PREF_2DC_REGION_HASH 61 +PREF_MARKOV_ON FALSE +DEBUG_PREF_MARKOV FALSE +PREF_MARKOV_NUM_ENTRIES 65536 +PREF_MARKOV_NUM_NEXT_STATES 8 +PREF_MARKOV_SEND_ON_PREF_HIT TRUE +PREF_MARKOV_UPDATE_ON_PREF_HIT TRUE +PREF_MARKOV_TABLE_UPDATE_POLICY 0 +PREF_MARKOV_SEND_THRESHOLD 0 +PREF_SMS_ON FALSE 1 +PREF_SMS_AT_SIZE 64 +PREF_SMS_FT_SIZE 64 +PREF_SMS_PHT_SIZE 16384 +PREF_SMS_PRF_SIZE 1024 +PREF_SMS_REGION_SIZE 2048 diff --git a/labs/LAB5/runs/leela_s_base-sms1/bp.stat.0.out b/labs/LAB5/runs/leela_s_base-sms1/bp.stat.0.out new file mode 100644 index 00000000..85f81405 --- /dev/null +++ b/labs/LAB5/runs/leela_s_base-sms1/bp.stat.0.out @@ -0,0 +1,752 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 62388250 Instructions: 100000003 IPC: 1.60287 + +BTB_ON_PATH_MISS 16634 0.104% 16634 0.104% +BTB_ON_PATH_HIT 16037243 99.896% 16037243 99.896% + 16053877 100.000% 16053877 100.000% + 1.00 1.00 1.00 1.00 + +BTB_OFF_PATH_MISS 0 -nan% 0 -nan% +BTB_OFF_PATH_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BTB_ON_PATH_WRITE 16634 100.000% 16634 100.000% +BTB_OFF_PATH_WRITE 0 0.000% 0 0.000% + 16634 100.000% 16634 100.000% + 0.00 0.00 0.00 0.00 + +BP_ON_PATH_CORRECT 14344379 89.351% 14344379 89.351% +BP_ON_PATH_MISPREDICT 786933 4.902% 786933 4.902% +BP_ON_PATH_MISFETCH 922565 5.747% 922565 5.747% + 16053877 100.000% 16053877 100.000% + 0.16 0.48 0.16 0.48 + +BP_OFF_PATH_CORRECT 0 -nan% 0 -nan% +BP_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% +BP_OFF_PATH_MISFETCH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +LATE_BP_ON_PATH_CORRECT 16053877 100.000% 16053877 100.000% +LATE_BP_ON_PATH_MISPREDICT 0 0.000% 0 0.000% +LATE_BP_ON_PATH_MISFETCH 0 0.000% 0 0.000% + 16053877 100.000% 16053877 100.000% + 0.00 0.00 0.00 0.00 + +LATE_BP_OFF_PATH_CORRECT 0 -nan% 0 -nan% +LATE_BP_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% +LATE_BP_OFF_PATH_MISFETCH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_PVN 0 -nan% 0 -nan% +BP_ON_PATH_CONF_PVN_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_PVP 0 -nan% 0 -nan% +BP_ON_PATH_CONF_PVP_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_SPEC 0 -nan% 0 -nan% +BP_ON_PATH_CONF_SPEC_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CRS_MISS_ON_PATH 36711 1.366% 36711 1.366% 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4161590 3.385% 4161590 3.385% +ST_OP_IMEM 36002236 29.283% 36002236 29.283% +ST_OP_IADD 18229508 14.827% 18229508 14.827% +ST_OP_IMUL 1041032 0.847% 1041032 0.847% +ST_OP_IDIV 227430 0.185% 227430 0.185% +ST_OP_ICMP 7756009 6.309% 7756009 6.309% +ST_OP_LOGIC 11252960 9.153% 11252960 9.153% +ST_OP_SHIFT 5785798 4.706% 5785798 4.706% +ST_OP_FMEM 372607 0.303% 372607 0.303% +ST_OP_FCVT 80299 0.065% 80299 0.065% +ST_OP_FADD 39839 0.032% 39839 0.032% +ST_OP_FMUL 0 0.000% 0 0.000% +ST_OP_FMA 0 0.000% 0 0.000% +ST_OP_FDIV 437 0.000% 437 0.000% +ST_OP_FCMP 0 0.000% 0 0.000% +ST_OP_FCMOV 0 0.000% 0 0.000% +ST_OP_GATHER 0 0.000% 0 0.000% +ST_OP_SCATTER 0 0.000% 0 0.000% +ST_OP_PIPELINED_FAST 0 0.000% 0 0.000% +ST_OP_PIPELINED_MEDIUM 0 0.000% 0 0.000% +ST_OP_PIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_MEDIUM 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_VERY_SLOW 0 0.000% 0 0.000% + 122944265 100.000% 122944265 100.000% + 6.05 3.08 6.05 3.08 + +ST_NOT_CF 106890388 86.942% 106890388 86.942% +ST_CF_BR 719614 0.585% 719614 0.585% +ST_CF_CBR 9943065 8.087% 9943065 8.087% +ST_CF_CALL 2687759 2.186% 2687759 2.186% +ST_CF_IBR 15681 0.013% 15681 0.013% +ST_CF_ICALL 0 0.000% 0 0.000% +ST_CF_ICO 0 0.000% 0 0.000% +ST_CF_RET 2687758 2.186% 2687758 2.186% +ST_CF_SYS 0 0.000% 0 0.000% + 122944265 100.000% 122944265 100.000% + 0.39 1.15 0.39 1.15 + +ST_BAR_NONE 122944265 100.000% 122944265 100.000% +ST_BAR_FETCH 0 0.000% 0 0.000% +ST_BAR_ISSUE 0 0.000% 0 0.000% +ST_BAR_BOTH 0 0.000% 0 0.000% + 122944265 100.000% 122944265 100.000% + 0.00 0.00 0.00 0.00 + +ST_NOT_MEM 86569422 70.414% 86569422 70.414% +ST_MEM_LD 26692415 21.711% 26692415 21.711% +ST_MEM_ST 9682428 7.875% 9682428 7.875% +ST_MEM_PF 0 0.000% 0 0.000% +ST_MEM_WH 0 0.000% 0 0.000% +ST_MEM_EVICT 0 0.000% 0 0.000% + 122944265 100.000% 122944265 100.000% + 0.37 0.54 0.37 0.54 + +ST_NOT_MEM_OFFPATH 0 -nan% 0 -nan% +ST_MEM_LD_OFFPATH 0 -nan% 0 -nan% +ST_MEM_ST_OFFPATH 0 -nan% 0 -nan% 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00000000..8884d4c3 --- /dev/null +++ b/labs/LAB5/runs/leela_s_base-sms1/l2l1pref.stat.0.out @@ -0,0 +1,140 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 62388250 Instructions: 100000003 IPC: 1.60287 + +L2WAY_FILL_L1 0 0 + +L2WAY_WAY_HIT 0 -nan% 0 -nan% +L2WAY_WAY_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_PREF_REQ 0 0 + +L2WAY_PREF_HIT_DATA_IN_CACHE 0 -nan% 0 -nan% +L2WAY_PREF_HIT_DATA_REQ 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_TRAIN_HIT 0 -nan% 0 -nan% +L2WAY_TRAIN_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L1_HIT_REQ_TYPE_IFETCH 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DFETCH 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DSTORE 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_IPRF 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DPRF 0 -nan% 0 -nan% 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0.00 0.00 + +ICACHE_HIT_ONPATH 28867837 100.000% 28867837 100.000% +ICACHE_HIT_OFFPATH 0 0.000% 0 0.000% + 28867837 100.000% 28867837 100.000% + 0.00 0.00 0.00 0.00 + +ICACHE_HIT_ONPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +ICACHE_HIT_ONPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ICACHE_HIT_OFFPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +ICACHE_HIT_OFFPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DCACHE_MISS 388096 1.067% 388096 1.067% +DCACHE_ST_BUFFER_HIT 13168 0.036% 13168 0.036% +DCACHE_HIT 35973555 98.897% 35973555 98.897% + 36374819 100.000% 36374819 100.000% + 1.98 1.97 1.98 1.97 + +DCACHE_MISS_COMPULSORY 4077 0.0105 4077 0.0105 + +DCACHE_MISS_CAPACITY 353697 0.9114 353697 0.9114 + +DCACHE_MISS_CONFLICT 30322 0.0781 30322 0.0781 + +DCACHE_MISS_ONPATH 388096 100.000% 388096 100.000% +DCACHE_MISS_OFFPATH 0 0.000% 0 0.000% + 388096 100.000% 388096 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_ST_BUFFER_HIT_ONPATH 13168 100.000% 13168 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0.00 + +DCACHE_MISS_WAITMEM 2174 2174 + +MEM_REQ_ROW_BUFFER_HITS 0 -nan% 0 -nan% +MEM_REQ_ROW_BUFFER_MISSES 0 -nan% 0 -nan% +MEM_REQ_ROW_BUFFER_CONFLICTS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +SHADOW_ROW_BUFFER_HITS 0 0 + +SHADOW_ROW_HIT_STALL_TIME 0 0 + +CHANNEL0_BUS_BUSY_CYCLES 0 -nan% 0 -nan% +CHANNEL1_BUS_BUSY_CYCLES 0 -nan% 0 -nan% +CHANNEL2_BUS_BUSY_CYCLES 0 -nan% 0 -nan% +CHANNEL3_BUS_BUSY_CYCLES 0 -nan% 0 -nan% +CHANNEL4_BUS_BUSY_CYCLES 0 -nan% 0 -nan% +CHANNEL5_BUS_BUSY_CYCLES 0 -nan% 0 -nan% +CHANNEL6_BUS_BUSY_CYCLES 0 -nan% 0 -nan% +CHANNEL7_BUS_BUSY_CYCLES 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CHANNEL_IDLE_DESPITE_READY_CMD 0 0 + +MEM_NUM_TOTAL_BUS_CYCLES 0 0 + +MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan + +CORE_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan + +CHANNEL0_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan% +CHANNEL1_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan% +CHANNEL2_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan% 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112.0148 158613 112.0148 + +CORE_L1_MISS_LATENCY 623148 126.9658 623148 126.9658 + +CORE_L1_MISS_LATENCY_DEMAND 464535 133.0284 464535 133.0284 + +CORE_L1_MISS_LATENCY_PREF 158613 112.0148 158613 112.0148 + +CORE_EVICTED_L1_DEMAND 58 87.879% 58 87.879% +CORE_EVICTED_L1_PREF_USED 5 7.576% 5 7.576% +CORE_EVICTED_L1_PREF_NOT_USED 3 4.545% 3 4.545% + 66 100.000% 66 100.000% + 0.17 0.46 0.17 0.46 + +CORE_EVICTED_MLC_DEMAND 0 -nan% 0 -nan% +CORE_EVICTED_MLC_PREF_USED 0 -nan% 0 -nan% +CORE_EVICTED_MLC_PREF_NOT_USED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CORE_MEM_LATENCY_AVE_DEMAND 5660 97.5862 5660 97.5862 + +CORE_MEM_LATENCY_AVE_PREF_USED 292 58.4000 292 58.4000 + +CORE_MEM_LATENCY_AVE_PREF_NOT_USED 594 198.0000 594 198.0000 + +DRAM_LATENCY 0 0 + +TOTAL_DRAM_LATENCY 0 0 + +DRAM_CLOSED_PAGE_POLICY_CMD 0 0 + +DRAM_ACTIVATE_STALLING 0 0 + +DRAM_PRECHARGE_STALLING 0 0 + +DRAM_PRECHARGE_STALLING_WAIT_CYCLES 0 0 + +L1_STAY_DEMAND 1762930605 30395355.2586 1762930605 30395355.2586 + +L1_STAY_PREF_USED 158678860 31735772.0000 158678860 31735772.0000 + +L1_STAY_PREF_NOT_USED 135381328 45127109.3333 135381328 45127109.3333 + +TOTAL_DATA_MISS_LATENCY 454017 454017 + +TOTAL_DATA_MISS_COUNT 3169 3169 + +CORE_PREF_L1_NOT_USED_LATENCY200 1 33.333% 1 33.333% +CORE_PREF_L1_NOT_USED_LATENCY400 2 66.667% 2 66.667% +CORE_PREF_L1_NOT_USED_LATENCY600 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_LATENCY800 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_LATENCY1000 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_LATENCY1200 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_LATENCY1400 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_LATENCY1600 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_LATENCY1600MORE 0 0.000% 0 0.000% + 3 100.000% 3 100.000% + 0.67 0.33 0.67 0.33 + +CORE_PREF_L1_NOT_USED_DISTANCE_1 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_DISTANCE_2 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_DISTANCE_4 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_DISTANCE_8 1 33.333% 1 33.333% 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0 -nan% 0 -nan% +CORE_PREF_MLC_DEMAND_LATENCY1000MORE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TOTAL_BATCH_FORMED 0 0 + +TOTAL_BATCH_MEM_REQ_MARKED 0 -nan 0 -nan + +CORE_BATCH_MEM_REQ_MARKED 0 -nan 0 -nan + +CORE_BATCH_MEM_REQ_MARKED_DEMAND 0 -nan 0 -nan + +CORE_BATCH_MEM_REQ_MARKED_PREF 0 -nan 0 -nan + +DRAM_ROW_BATCHES 0 0 + +REJECTED_QUEUE_MLC 0 0 + +REJECTED_QUEUE_L1 0 0 + +REJECTED_QUEUE_BUS_OUT 0 0 + +LEADING_LOAD_LATENCY 0 0.0000 0 0.0000 + +LEADING_LOADS 0 0.0000 0 0.0000 + +MEM_REQ_CRITICAL_PATH_LENGTH 0 0.0000 0 0.0000 + +TOTAL_MEM_REQ_LATENCY 0 0 + +TOTAL_CRITICAL_MEM_REQ_LATENCY 0 -nan 0 -nan + +TOTAL_CRITICAL_BANK_LATENCY 0 -nan 0 -nan + +TOTAL_MEMORY_SLACK 0 0.0000 0 0.0000 + +TOTAL_CHIP_UTILIZATION 0 0.0000 0 0.0000 + +CHIP_BUSY_UNDER_CRITICAL_REQS 0 0.0000 0 0.0000 + +PERF_PRED_NUM_STAT_RESETS 0 0 + +PERF_PRED_RESET_STATS_CYCLE 0 0 + +PERF_PRED_CYCLE 62388250 62388250 + +ESTIMATED_ALONE_CYCLES 0 0.0000 0 0.0000 + +NUM_WINDOWS_WITH_DCACHE_MISS 108350 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-nan 0 -nan + +DRAM_NUM_REQS_23_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_23_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_23_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_23_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_23_WB_NODIRTY 0 -nan 0 -nan + +DRAM_NUM_REQS_24_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_24_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_24_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_24_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_24_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_24_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_24_WB_NODIRTY 0 -nan 0 -nan + +DRAM_NUM_REQS_25_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_25_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_25_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_25_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_25_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_25_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_25_WB_NODIRTY 0 -nan 0 -nan + +DRAM_NUM_REQS_26_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_26_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_26_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_26_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_26_DPRF 0 -nan 0 -nan + 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-nan 0 -nan + +DRAM_NUM_REQS_30_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_30_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_30_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_30_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_30_WB_NODIRTY 0 -nan 0 -nan + +DRAM_NUM_REQS_31_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_31_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_31_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_31_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_31_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_31_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_31_WB_NODIRTY 0 -nan 0 -nan + +DRAM_NUM_REQS_32_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_32_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_32_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_32_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_32_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_32_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_32_WB_NODIRTY 0 -nan 0 -nan + +DRAM_BOTTLENECK_BUS_0 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_10 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_20 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_30 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_40 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_50 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_60 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_70 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_80 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_90 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_100 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DRAM_BOTTLENECK_BANKS_0 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_10 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_20 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_30 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_40 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_50 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_60 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_70 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_80 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_90 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_100 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DRAM_BOTTLENECK_FAW_0 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_10 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_20 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_30 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_40 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_50 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_60 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_70 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_80 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_90 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_100 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DRAM_ROW_HIT_GEN_AFTER_ROW_OPEN_STALLING 0 0 + +KNOWN_BAD_ADDRESS 0 0.000% 0 0.000% +GOOD_ADDRESS 741935 100.000% 741935 100.000% + 741935 100.000% 741935 100.000% + 1.00 1.00 1.00 1.00 + + + diff --git a/labs/LAB5/runs/leela_s_base-sms1/power.stat.0.out b/labs/LAB5/runs/leela_s_base-sms1/power.stat.0.out new file mode 100644 index 00000000..1a44a52f --- /dev/null +++ b/labs/LAB5/runs/leela_s_base-sms1/power.stat.0.out @@ -0,0 +1,184 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 62388250 Instructions: 100000003 IPC: 1.60287 + +POWER_STATS_BEGIN 0 0 + +POWER_TIME 19496328125000 19496328125000 + +POWER_CYCLE 62388250 62388250 + +POWER_ITLB_ACCESS 28887313 28887313 + +POWER_DTLB_ACCESS 9682423 9682423 + +POWER_ICACHE_ACCESS 28887313 28887313 + +POWER_ICACHE_MISS 19476 19476 + +POWER_BTB_READ 28887313 28887313 + +POWER_BTB_WRITE 1709497 1709497 + +POWER_ROB_READ 122944185 122944185 + +POWER_ROB_WRITE 122944185 122944185 + +POWER_RENAME_READ 245888370 245888370 + +POWER_RENAME_WRITE 122944185 122944185 + +POWER_FP_RENAME_READ 0 0 + +POWER_FP_RENAME_WRITE 0 0 + +POWER_FUNCTION_CALL 2687757 2687757 + +POWER_INST_WINDOW_READ 122944185 122944185 + +POWER_INST_WINDOW_WRITE 122944185 122944185 + +POWER_INT_REGFILE_READ 146903593 146903593 + +POWER_INT_REGFILE_WRITE 116287132 116287132 + +POWER_IALU_ACCESS 121675723 121675723 + +POWER_CDB_IALU_ACCESS 121675723 121675723 + +POWER_MUL_ACCESS 1268462 1268462 + +POWER_CDB_MUL_ACCESS 1268462 1268462 + +POWER_FP_INST_WINDOW_WRITE 0 0 + +POWER_FP_INST_WINDOW_READ 0 0 + +POWER_FP_REGFILE_READ 0 0 + +POWER_FP_REGFILE_WRITE 0 0 + +POWER_FPU_ACCESS 0 0 + +POWER_CDB_FPU_ACCESS 0 0 + +POWER_DCACHE_READ_ACCESS 26693885 26693885 + +POWER_DCACHE_WRITE_ACCESS 9683108 9683108 + +POWER_DCACHE_READ_MISS 304473 304473 + +POWER_DCACHE_WRITE_MISS 98965 98965 + +POWER_MLC_READ_ACCESS 0 0 + +POWER_MLC_WRITE_ACCESS 0 0 + +POWER_MLC_READ_MISS 0 0 + +POWER_MLC_WRITE_MISS 0 0 + +POWER_LLC_READ_ACCESS 261050 261050 + +POWER_LLC_WRITE_ACCESS 65554 65554 + +POWER_LLC_READ_MISS 4908 4908 + +POWER_LLC_WRITE_MISS 0 0 + +POWER_MEMORY_ACCESS 0 0 + +POWER_MEMORY_READ_ACCESS 0 0 + +POWER_MEMORY_WRITE_ACCESS 0 0 + +POWER_INST_WINDOW_WAKEUP_ACCESS 122944185 122944185 + +POWER_FP_INST_WINDOW_WAKEUP_ACCESS 0 0 + +POWER_L1DIREC_READ_ACCESS 0 0 + +POWER_L1DIREC_WRITE_ACCESS 0 0 + +POWER_L1DIREC_READ_MISS 0 0 + +POWER_L1DIREC_WRITE_MISS 0 0 + +POWER_L2DIREC_READ_ACCESS 0 0 + +POWER_L2DIREC_WRITE_ACCESS 0 0 + +POWER_L2DIREC_READ_MISS 0 0 + +POWER_L2DIREC_WRITE_MISS 0 0 + +POWER_MEMORY_CTRL_ACCESS 4917 4917 + +POWER_MEMORY_CTRL_READ 4908 4908 + +POWER_MEMORY_CTRL_WRITE 9 9 + +POWER_OP 122944185 122944185 + +POWER_INT_OP 119457422 119457422 + +POWER_FP_OP 493182 493182 + +POWER_LD_OP 26692398 26692398 + +POWER_ST_OP 9682423 9682423 + +POWER_BRANCH_MISPREDICT 1709497 1709497 + +POWER_COMMITTED_OP 122944185 122944185 + +POWER_COMMITTED_INT_OP 119457422 119457422 + +POWER_COMMITTED_FP_OP 3486763 3486763 + +POWER_BRANCH_OP 16053869 16053869 + +POWER_DRAM_PRECHARGE 1665 1665 + +POWER_DRAM_ACTIVATE 2953 2953 + +POWER_DRAM_READ 4905 4905 + +POWER_DRAM_WRITE 0 0 + +POWER_STATS_END 0 0 + +ENERGY 0.000000 0.000000 + +ENERGY_CORE 0.000000 0.000000 + +ENERGY_UNCORE 0.000000 0.000000 + +ENERGY_MEMORY 0.000000 0.000000 + +ENERGY_OTHER 0.000000 0.000000 + +ENERGY_CORE_STATIC 0.000000 0.000000 + +ENERGY_CORE_DYNAMIC 0.000000 0.000000 + +ENERGY_UNCORE_STATIC 0.000000 0.000000 + +ENERGY_UNCORE_DYNAMIC 0.000000 0.000000 + +ENERGY_MEMORY_STATIC 0.000000 0.000000 + +ENERGY_MEMORY_DYNAMIC 0.000000 0.000000 + +ENERGY_OTHER_STATIC 0.000000 0.000000 + +ENERGY_OTHER_DYNAMIC 0.000000 0.000000 + +TIME 0.000000 0.000000 + +ENERGY_STATS_END 0 0 + + + diff --git a/labs/LAB5/runs/leela_s_base-sms1/pref.stat.0.out b/labs/LAB5/runs/leela_s_base-sms1/pref.stat.0.out new file mode 100644 index 00000000..2661d96a --- /dev/null +++ b/labs/LAB5/runs/leela_s_base-sms1/pref.stat.0.out @@ -0,0 +1,208 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 62388250 Instructions: 100000003 IPC: 1.60287 + +PREF_DL0REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UMLC_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UL1REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_DL0REQ_QUEUE_FULL 0 0 + +PREF_UMLC_REQ_QUEUE_FULL 0 0 + +PREF_UL1REQ_QUEUE_FULL 0 0 + +PREF_DC_HIT_NOSEND 0 0 + +PREF_WBQDC_HIT_NOSEND 0 0 + +PREF_MLCQ_STALL 0 0 + +PREF_L1Q_STALL 0 0 + +PREF_UMLC_REQ_SEND_QUEUE_STALL 0 0 + +PREF_UL1REQ_SEND_QUEUE_STALL 3048 3048 + +PREF_UMLC_REQ_QUEUE_SENTREQ 0 0 + +PREF_UL1REQ_QUEUE_SENTREQ 2528 2528 + +PREF_NEWREQ_MATCHED 51 51 + +PREF_UMLC_REQ_QUEUE_MATCHED_REQ 0 0 + +PREF_UL1REQ_QUEUE_MATCHED_REQ 128 128 + +PREF_DL0REQ_QUEUE_MATCHED_REQ 0 0 + +L1_PREF_HIT 71269 71269 + +L1_PREF_UNIQUE_HIT 931 931 + +L1_PREF_LATE 75 75 + +L1_LATE_PREF_CYCLES 7248 7248 + +L1_LATE_PREF_CYCLES_DIST_0 40 53.333% 40 53.333% +L1_LATE_PREF_CYCLES_DIST_100 31 41.333% 31 41.333% +L1_LATE_PREF_CYCLES_DIST_200 4 5.333% 4 5.333% +L1_LATE_PREF_CYCLES_DIST_300 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_400 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_500 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_600 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_700 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_800 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_900 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1000 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1100 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1200 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1300 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1400 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1500 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1600 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1700 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1800 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1900 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_2000 0 0.000% 0 0.000% + 75 100.000% 75 100.000% + 0.52 0.46 0.52 0.46 + +MLC_PREF_HIT 0 0 + +MLC_PREF_UNIQUE_HIT 0 0 + +MLC_PREF_LATE 0 0 + +PREF_HYBRID_SEL_0 0 -nan% 0 -nan% +PREF_HYBRID_SEL_1 0 -nan% 0 -nan% +PREF_HYBRID_SEL_2 0 -nan% 0 -nan% +PREF_HYBRID_SEL_3 0 -nan% 0 -nan% +PREF_HYBRID_SEL_4 0 -nan% 0 -nan% +PREF_HYBRID_SEL_5 0 -nan% 0 -nan% +PREF_HYBRID_SEL_6 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_DISTANCE_1 0 -nan% 0 -nan% +PREF_DISTANCE_2 0 -nan% 0 -nan% +PREF_DISTANCE_3 0 -nan% 0 -nan% +PREF_DISTANCE_4 0 -nan% 0 -nan% +PREF_DISTANCE_5 0 -nan% 0 -nan% +PREF_DISTANCE_6 0 -nan% 0 -nan% +PREF_DISTANCE_7 0 -nan% 0 -nan% +PREF_DISTANCE_8 0 -nan% 0 -nan% +PREF_DISTANCE_9 0 -nan% 0 -nan% +PREF_DISTANCE_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_REPL_MRU 0 -nan% 0 -nan% +PREF_REPL_MID 0 -nan% 0 -nan% +PREF_REPL_LOWQTR 0 -nan% 0 -nan% +PREF_REPL_LRU 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_REPL_MOVEDOWN 0 -nan% 0 -nan% +PREF_REPL_MOVEUP 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_COV_1 0 -nan% 0 -nan% +PREF_COV_2 0 -nan% 0 -nan% +PREF_COV_3 0 -nan% 0 -nan% +PREF_COV_4 0 -nan% 0 -nan% +PREF_COV_5 0 -nan% 0 -nan% +PREF_COV_6 0 -nan% 0 -nan% +PREF_COV_7 0 -nan% 0 -nan% +PREF_COV_8 0 -nan% 0 -nan% +PREF_COV_9 0 -nan% 0 -nan% +PREF_COV_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_POL_1 0 -nan% 0 -nan% +PREF_POL_2 0 -nan% 0 -nan% +PREF_POL_3 0 -nan% 0 -nan% +PREF_POL_4 0 -nan% 0 -nan% +PREF_POL_5 0 -nan% 0 -nan% +PREF_POL_6 0 -nan% 0 -nan% +PREF_POL_7 0 -nan% 0 -nan% +PREF_POL_8 0 -nan% 0 -nan% +PREF_POL_9 0 -nan% 0 -nan% +PREF_POL_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_ACC_1 0 -nan% 0 -nan% +PREF_ACC_2 0 -nan% 0 -nan% +PREF_ACC_3 0 -nan% 0 -nan% +PREF_ACC_4 0 -nan% 0 -nan% +PREF_ACC_5 0 -nan% 0 -nan% +PREF_ACC_6 0 -nan% 0 -nan% +PREF_ACC_7 0 -nan% 0 -nan% +PREF_ACC_8 0 -nan% 0 -nan% +PREF_ACC_9 0 -nan% 0 -nan% +PREF_ACC_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_TIMELY_1 0 -nan% 0 -nan% +PREF_TIMELY_2 0 -nan% 0 -nan% +PREF_TIMELY_3 0 -nan% 0 -nan% +PREF_TIMELY_4 0 -nan% 0 -nan% +PREF_TIMELY_5 0 -nan% 0 -nan% +PREF_TIMELY_6 0 -nan% 0 -nan% +PREF_TIMELY_7 0 -nan% 0 -nan% +PREF_TIMELY_8 0 -nan% 0 -nan% +PREF_TIMELY_9 0 -nan% 0 -nan% +PREF_TIMELY_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_UNUSED_EVICT 3 3 + +PREF_REGION_SENT 0 0 + +PREF_REGION_USEFUL 0 0 + +PREF_REGION_EVICT 0 0 + +PREF_PFPOL 0 0 + +PREF_PHASE_NEWPHASE_DET 0 0 + +PREF_PHASE_NEWPHASE_NOTVALID 0 0 + +PREF_PHASE_SENTPREF 0 0 + +PREF_PHASE_OVERWRITE_PAGE 0 0 + +PREF_UPDATE_COUNT 0 0 + +PREF_ACC1_HT_HP 0 -nan% 0 -nan% +PREF_ACC1_HT_LP 0 -nan% 0 -nan% +PREF_ACC1_LT_HP 0 -nan% 0 -nan% +PREF_ACC1_LT_LP 0 -nan% 0 -nan% +PREF_ACC2_HT_HP 0 -nan% 0 -nan% +PREF_ACC2_HT_LP 0 -nan% 0 -nan% +PREF_ACC2_LT_HP 0 -nan% 0 -nan% +PREF_ACC2_LT_LP 0 -nan% 0 -nan% +PREF_ACC3_HT_HP 0 -nan% 0 -nan% +PREF_ACC3_HT_LP 0 -nan% 0 -nan% +PREF_ACC3_LT_HP 0 -nan% 0 -nan% +PREF_ACC3_LT_LP 0 -nan% 0 -nan% +PREF_ACC4_HT_HP 0 -nan% 0 -nan% +PREF_ACC4_HT_LP 0 -nan% 0 -nan% +PREF_ACC4_LT_HP 0 -nan% 0 -nan% +PREF_ACC4_LT_LP 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + + + diff --git a/labs/LAB5/runs/leela_s_base-sms1/ramulator.stat.out b/labs/LAB5/runs/leela_s_base-sms1/ramulator.stat.out new file mode 100644 index 00000000..163f39d9 --- /dev/null +++ b/labs/LAB5/runs/leela_s_base-sms1/ramulator.stat.out @@ -0,0 +1,150 @@ + ramulator.active_cycles_0 138921 # Total active cycles for level _0 + ramulator.busy_cycles_0 138921 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0 + ramulator.serving_requests_0 154010 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.average_serving_requests_0 0.006583 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.active_cycles_0_0 138921 # Total active cycles for level _0_0 + ramulator.busy_cycles_0_0 1188501 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0 + ramulator.serving_requests_0_0 154010 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.average_serving_requests_0_0 0.006583 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.active_cycles_0_0_0 37309 # Total active cycles for level _0_0_0 + ramulator.busy_cycles_0_0_0 37309 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0 + ramulator.serving_requests_0_0_0 39541 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 +ramulator.average_serving_requests_0_0_0 0.001690 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 + ramulator.active_cycles_0_0_0_0 8648 # Total active cycles for level _0_0_0_0 + ramulator.busy_cycles_0_0_0_0 8648 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_0 + ramulator.serving_requests_0_0_0_0 9432 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 +ramulator.average_serving_requests_0_0_0_0 0.000403 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 + ramulator.active_cycles_0_0_0_1 10633 # Total active cycles for level _0_0_0_1 + ramulator.busy_cycles_0_0_0_1 10633 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_1 + ramulator.serving_requests_0_0_0_1 11189 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 +ramulator.average_serving_requests_0_0_0_1 0.000478 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 + ramulator.active_cycles_0_0_0_2 11060 # Total active cycles for level _0_0_0_2 + ramulator.busy_cycles_0_0_0_2 11060 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_2 + ramulator.serving_requests_0_0_0_2 11460 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 +ramulator.average_serving_requests_0_0_0_2 0.000490 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 + ramulator.active_cycles_0_0_0_3 7184 # Total active cycles for level _0_0_0_3 + ramulator.busy_cycles_0_0_0_3 7184 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_3 + ramulator.serving_requests_0_0_0_3 7460 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 +ramulator.average_serving_requests_0_0_0_3 0.000319 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 + ramulator.active_cycles_0_0_1 39414 # Total active cycles for level _0_0_1 + ramulator.busy_cycles_0_0_1 39414 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1 + ramulator.serving_requests_0_0_1 43901 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 +ramulator.average_serving_requests_0_0_1 0.001876 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 + ramulator.active_cycles_0_0_1_0 8860 # Total active cycles for level _0_0_1_0 + ramulator.busy_cycles_0_0_1_0 8860 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_0 + ramulator.serving_requests_0_0_1_0 9715 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 +ramulator.average_serving_requests_0_0_1_0 0.000415 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 + ramulator.active_cycles_0_0_1_1 11871 # Total active cycles for level _0_0_1_1 + ramulator.busy_cycles_0_0_1_1 11871 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_1 + ramulator.serving_requests_0_0_1_1 13758 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 +ramulator.average_serving_requests_0_0_1_1 0.000588 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 + ramulator.active_cycles_0_0_1_2 14058 # Total active cycles for level _0_0_1_2 + ramulator.busy_cycles_0_0_1_2 14058 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_2 + ramulator.serving_requests_0_0_1_2 15320 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 +ramulator.average_serving_requests_0_0_1_2 0.000655 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 + ramulator.active_cycles_0_0_1_3 4856 # Total active cycles for level _0_0_1_3 + ramulator.busy_cycles_0_0_1_3 4856 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_3 + ramulator.serving_requests_0_0_1_3 5108 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 +ramulator.average_serving_requests_0_0_1_3 0.000218 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 + ramulator.active_cycles_0_0_2 29111 # Total active cycles for level _0_0_2 + ramulator.busy_cycles_0_0_2 29111 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2 + ramulator.serving_requests_0_0_2 32101 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 +ramulator.average_serving_requests_0_0_2 0.001372 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 + ramulator.active_cycles_0_0_2_0 4820 # Total active cycles for level _0_0_2_0 + ramulator.busy_cycles_0_0_2_0 4820 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_0 + ramulator.serving_requests_0_0_2_0 4848 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 +ramulator.average_serving_requests_0_0_2_0 0.000207 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 + ramulator.active_cycles_0_0_2_1 5304 # Total active cycles for level _0_0_2_1 + ramulator.busy_cycles_0_0_2_1 5304 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_1 + ramulator.serving_requests_0_0_2_1 5388 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 +ramulator.average_serving_requests_0_0_2_1 0.000230 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 + ramulator.active_cycles_0_0_2_2 8029 # Total active cycles for level _0_0_2_2 + ramulator.busy_cycles_0_0_2_2 8029 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_2 + ramulator.serving_requests_0_0_2_2 10729 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 +ramulator.average_serving_requests_0_0_2_2 0.000459 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 + ramulator.active_cycles_0_0_2_3 10958 # Total active cycles for level _0_0_2_3 + ramulator.busy_cycles_0_0_2_3 10958 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_3 + ramulator.serving_requests_0_0_2_3 11136 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 +ramulator.average_serving_requests_0_0_2_3 0.000476 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 + ramulator.active_cycles_0_0_3 36322 # Total active cycles for level _0_0_3 + ramulator.busy_cycles_0_0_3 36322 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3 + ramulator.serving_requests_0_0_3 38467 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 +ramulator.average_serving_requests_0_0_3 0.001644 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 + ramulator.active_cycles_0_0_3_0 8464 # Total active cycles for level _0_0_3_0 + ramulator.busy_cycles_0_0_3_0 8464 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_0 + ramulator.serving_requests_0_0_3_0 9048 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 +ramulator.average_serving_requests_0_0_3_0 0.000387 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 + ramulator.active_cycles_0_0_3_1 6641 # Total active cycles for level _0_0_3_1 + ramulator.busy_cycles_0_0_3_1 6641 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_1 + ramulator.serving_requests_0_0_3_1 6995 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 +ramulator.average_serving_requests_0_0_3_1 0.000299 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 + ramulator.active_cycles_0_0_3_2 6468 # Total active cycles for level _0_0_3_2 + ramulator.busy_cycles_0_0_3_2 6468 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_2 + ramulator.serving_requests_0_0_3_2 6976 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 +ramulator.average_serving_requests_0_0_3_2 0.000298 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 + ramulator.active_cycles_0_0_3_3 14862 # Total active cycles for level _0_0_3_3 + ramulator.busy_cycles_0_0_3_3 14862 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_3 + ramulator.serving_requests_0_0_3_3 15448 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 +ramulator.average_serving_requests_0_0_3_3 0.000660 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 + ramulator.read_transaction_bytes_0 313920 # The total byte of read transaction per channel + ramulator.write_transaction_bytes_0 0 # The total byte of write transaction per channel + ramulator.row_hits_channel_0_core 1952 # Number of row hits per channel per core + ramulator.row_misses_channel_0_core 2421 # Number of row misses per channel per core + ramulator.row_conflicts_channel_0_core 532 # Number of row conflicts per channel per core + ramulator.read_row_hits_channel_0_core 1952 # Number of row hits for read requests per channel per core + [0] 1952.0 # +ramulator.read_row_misses_channel_0_core 2421 # Number of row misses for read requests per channel per core + [0] 2421.0 # +ramulator.read_row_conflicts_channel_0_core 532 # Number of row conflicts for read requests per channel per core + [0] 532.0 # + ramulator.write_row_hits_channel_0_core 0 # Number of row hits for write requests per channel per core + [0] 0.0 # +ramulator.write_row_misses_channel_0_core 0 # Number of row misses for write requests per channel per core + [0] 0.0 # +ramulator.write_row_conflicts_channel_0_core 0 # Number of row conflicts for write requests per channel per core + [0] 0.0 # + ramulator.useless_activates_0_core 0 # Number of useless activations. E.g, ACT -> PRE w/o RD or WR + ramulator.read_latency_avg_0 47.916463 # The average memory latency cycles (in memory time domain) per request for all read requests in this channel + ramulator.read_latency_sum_0 235174 # The memory latency cycles (in memory time domain) sum for all read requests in this channel + ramulator.req_queue_length_avg_0 3.190415 # Average of read and write queue length per memory cycle per channel. + ramulator.req_queue_length_sum_0 74641674 # Sum of read and write queue length per memory cycle per channel. + ramulator.read_req_queue_length_avg_0 0.008032 # Read queue length average per memory cycle per channel. + ramulator.read_req_queue_length_sum_0 187905 # Read queue length sum per memory cycle per channel. + ramulator.write_req_queue_length_avg_0 3.182383 # Write queue length average per memory cycle per channel. + ramulator.write_req_queue_length_sum_0 74453769 # Write queue length sum per memory cycle per channel. + ramulator.record_read_hits 0.0 # record read hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_misses 0.0 # record_read_miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_conflicts 0.0 # record read conflict count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_hits 0.0 # record write hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_misses 0.0 # record write miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_conflicts 0.0 # record write conflict for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.dram_capacity 8589934592 # Number of bytes in simulated DRAM + ramulator.dram_cycles 23395603 # Number of DRAM cycles simulated + ramulator.incoming_requests 4917 # Number of incoming requests to DRAM + ramulator.read_requests 4908 # Number of incoming read requests to DRAM per core + [0] 4908.0 # + ramulator.write_requests 9 # Number of incoming write requests to DRAM per core + [0] 9.0 # + ramulator.ramulator_active_cycles 138921 # The total number of cycles that the DRAM part is active (serving R/W) + ramulator.incoming_requests_per_channel 4917.0 # Number of incoming requests to each DRAM channel + [0] 4917.0 # +ramulator.incoming_read_reqs_per_channel 4908.0 # Number of incoming read requests to each DRAM channel + [0] 4908.0 # + ramulator.physical_page_replacement 0 # The number of times that physical page replacement happens. + ramulator.maximum_bandwidth 19200000000 # The theoretical maximum bandwidth (Bps) + ramulator.in_queue_req_num_sum 74641674 # Sum of read/write queue length + ramulator.in_queue_read_req_num_sum 187905 # Sum of read queue length + ramulator.in_queue_write_req_num_sum 74453769 # Sum of write queue length + ramulator.in_queue_req_num_avg 3.190415 # Average of read/write queue length per memory cycle + ramulator.in_queue_read_req_num_avg 0.008032 # Average of read queue length per memory cycle + ramulator.in_queue_write_req_num_avg 3.182383 # Average of write queue length per memory cycle + ramulator.record_read_requests 0.0 # record read requests for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_requests 0.0 # record write requests for this core when it reaches request limit or to the end + [0] 0.0 # diff --git a/labs/LAB5/runs/leela_s_base-sms1/run.err b/labs/LAB5/runs/leela_s_base-sms1/run.err new file mode 100644 index 00000000..e69de29b diff --git a/labs/LAB5/runs/leela_s_base-sms1/run.out b/labs/LAB5/runs/leela_s_base-sms1/run.out new file mode 100644 index 00000000..b15c89ca --- /dev/null +++ b/labs/LAB5/runs/leela_s_base-sms1/run.out @@ -0,0 +1,107 @@ +Scarab gitrev: 7ab9e17 +Scarab started at Sun Jun 11 08:08:38 2023 + +Initialized Ramulator. +** Heartbeat: 1% -- { 1000000 } -- 0.00 KIPS (500.00 KIPS) +** Heartbeat: 2% -- { 2000001 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 3% -- { 3000006 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 4% -- { 4000007 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 5% -- { 5000012 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 6% -- { 6000015 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 7% -- { 7000015 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 8% -- { 8000018 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 9% -- { 9000021 } -- 1000.00 KIPS (529.41 KIPS) +** Heartbeat: 10% -- { 10000025 } -- 500.00 KIPS (526.32 KIPS) +** Heartbeat: 11% -- { 11000030 } -- 500.00 KIPS (523.81 KIPS) +** Heartbeat: 12% -- { 12000034 } -- 500.00 KIPS (521.74 KIPS) +** Heartbeat: 13% -- { 13000035 } -- 500.00 KIPS (520.00 KIPS) +** Heartbeat: 14% -- { 14000035 } -- 500.00 KIPS (518.52 KIPS) +** Heartbeat: 15% -- { 15000035 } -- 500.00 KIPS (517.24 KIPS) +** Heartbeat: 16% -- { 16000036 } -- 500.00 KIPS (516.13 KIPS) +** Heartbeat: 17% -- { 17000037 } -- 500.00 KIPS (515.15 KIPS) +** Heartbeat: 18% -- { 18000040 } -- 1000.00 KIPS (529.41 KIPS) +** Heartbeat: 19% -- { 19000043 } -- 500.00 KIPS (527.78 KIPS) +** Heartbeat: 20% -- { 20000045 } -- 500.00 KIPS (526.32 KIPS) +** Heartbeat: 21% -- { 21000047 } -- 500.00 KIPS (525.00 KIPS) +** Heartbeat: 22% -- { 22000047 } -- 500.00 KIPS (523.81 KIPS) +** Heartbeat: 23% -- { 23000047 } -- 500.00 KIPS (522.73 KIPS) +** Heartbeat: 24% -- { 24000048 } -- 500.00 KIPS (521.74 KIPS) +** Heartbeat: 25% -- { 25000048 } -- 1000.00 KIPS (531.92 KIPS) +** Heartbeat: 26% -- { 26000048 } -- 500.00 KIPS (530.61 KIPS) +** Heartbeat: 27% -- { 27000050 } -- 500.00 KIPS (529.41 KIPS) +** Heartbeat: 28% -- { 28000050 } -- 500.00 KIPS (528.30 KIPS) +** Heartbeat: 29% -- { 29000052 } -- 500.00 KIPS (527.27 KIPS) +** Heartbeat: 30% -- { 30000054 } -- 500.00 KIPS (526.32 KIPS) +** Heartbeat: 31% -- { 31000057 } -- 500.00 KIPS (525.42 KIPS) +** Heartbeat: 32% -- { 32000060 } -- 500.00 KIPS (524.59 KIPS) +** Heartbeat: 33% -- { 33000063 } -- 1000.00 KIPS (532.26 KIPS) +** Heartbeat: 34% -- { 34000065 } -- 500.00 KIPS (531.25 KIPS) +** Heartbeat: 35% -- { 35000066 } -- 500.00 KIPS (530.30 KIPS) +** Heartbeat: 36% -- { 36000066 } -- 500.00 KIPS (529.41 KIPS) +** Heartbeat: 37% -- { 37000066 } -- 500.00 KIPS (528.57 KIPS) +** Heartbeat: 38% -- { 38000067 } -- 500.00 KIPS (527.78 KIPS) +** Heartbeat: 39% -- { 39000069 } -- 500.00 KIPS (527.03 KIPS) +** Heartbeat: 40% -- { 40000071 } -- 500.00 KIPS (526.32 KIPS) +** Heartbeat: 41% -- { 41000071 } -- 500.00 KIPS (525.64 KIPS) +** Heartbeat: 42% -- { 42000071 } -- 1000.00 KIPS (531.65 KIPS) +** Heartbeat: 43% -- { 43000075 } -- 500.00 KIPS (530.87 KIPS) +** Heartbeat: 44% -- { 44000075 } -- 500.00 KIPS (530.12 KIPS) +** Heartbeat: 45% -- { 45000075 } -- 500.00 KIPS (529.41 KIPS) +** Heartbeat: 46% -- { 46000079 } -- 500.00 KIPS (528.74 KIPS) +** Heartbeat: 47% -- { 47000080 } -- 500.00 KIPS (528.09 KIPS) +** Heartbeat: 48% -- { 48000080 } -- 500.00 KIPS (527.47 KIPS) +** Heartbeat: 49% -- { 49000080 } -- 500.00 KIPS (526.88 KIPS) +** Heartbeat: 50% -- { 50000080 } -- 500.00 KIPS (526.32 KIPS) +** Heartbeat: 51% -- { 51000083 } -- 1000.00 KIPS (531.25 KIPS) +** Heartbeat: 52% -- { 52000084 } -- 500.00 KIPS (530.61 KIPS) +** Heartbeat: 53% -- { 53000084 } -- 500.00 KIPS (530.00 KIPS) +** Heartbeat: 54% -- { 54000084 } -- 500.00 KIPS (529.41 KIPS) +** Heartbeat: 55% -- { 55000087 } -- 500.00 KIPS (528.85 KIPS) +** Heartbeat: 56% -- { 56000088 } -- 500.00 KIPS (528.30 KIPS) +** Heartbeat: 57% -- { 57000089 } -- 500.00 KIPS (527.78 KIPS) +** Heartbeat: 58% -- { 58000092 } -- 500.00 KIPS (527.27 KIPS) +** Heartbeat: 59% -- { 59000096 } -- 500.00 KIPS (526.79 KIPS) +** Heartbeat: 60% -- { 60000096 } -- 500.00 KIPS (526.32 KIPS) +** Heartbeat: 61% -- { 61000100 } -- 1000.00 KIPS (530.44 KIPS) +** Heartbeat: 62% -- { 62000103 } -- 500.00 KIPS (529.92 KIPS) +** Heartbeat: 63% -- { 63000106 } -- 500.00 KIPS (529.41 KIPS) +** Heartbeat: 64% -- { 64000107 } -- 500.00 KIPS (528.93 KIPS) +** Heartbeat: 65% -- { 65000107 } -- 500.00 KIPS (528.46 KIPS) +** Heartbeat: 66% -- { 66000110 } -- 500.00 KIPS (528.00 KIPS) +** Heartbeat: 67% -- { 67000111 } -- 500.00 KIPS (527.56 KIPS) +** Heartbeat: 68% -- { 68000114 } -- 500.00 KIPS (527.13 KIPS) +** Heartbeat: 69% -- { 69000115 } -- 500.00 KIPS (526.72 KIPS) +** Heartbeat: 70% -- { 70000119 } -- 1000.00 KIPS (530.30 KIPS) +** Heartbeat: 71% -- { 71000122 } -- 500.00 KIPS (529.85 KIPS) +** Heartbeat: 72% -- { 72000125 } -- 500.00 KIPS (529.41 KIPS) +** Heartbeat: 73% -- { 73000128 } -- 500.00 KIPS (528.99 KIPS) +** Heartbeat: 74% -- { 74000131 } -- 500.00 KIPS (528.57 KIPS) +** Heartbeat: 75% -- { 75000132 } -- 500.00 KIPS (528.17 KIPS) +** Heartbeat: 76% -- { 76000135 } -- 500.00 KIPS (527.78 KIPS) +** Heartbeat: 77% -- { 77000137 } -- 500.00 KIPS (527.40 KIPS) +** Heartbeat: 78% -- { 78000138 } -- 500.00 KIPS (527.03 KIPS) +** Heartbeat: 79% -- { 79000140 } -- 500.00 KIPS (526.67 KIPS) +** Heartbeat: 80% -- { 80000143 } -- 1000.00 KIPS (529.80 KIPS) +** Heartbeat: 81% -- { 81000147 } -- 500.00 KIPS (529.41 KIPS) +** Heartbeat: 82% -- { 82000149 } -- 500.00 KIPS (529.03 KIPS) +** Heartbeat: 83% -- { 83000149 } -- 500.00 KIPS (528.66 KIPS) +** Heartbeat: 84% -- { 84000151 } -- 500.00 KIPS (528.30 KIPS) +** Heartbeat: 85% -- { 85000154 } -- 500.00 KIPS (527.95 KIPS) +** Heartbeat: 86% -- { 86000158 } -- 500.00 KIPS (527.61 KIPS) +** Heartbeat: 87% -- { 87000158 } -- 500.00 KIPS (527.27 KIPS) +** Heartbeat: 88% -- { 88000158 } -- 500.00 KIPS (526.95 KIPS) +** Heartbeat: 89% -- { 89000160 } -- 1000.00 KIPS (529.76 KIPS) +** Heartbeat: 90% -- { 90000165 } -- 500.00 KIPS (529.41 KIPS) +** Heartbeat: 91% -- { 91000165 } -- 500.00 KIPS (529.07 KIPS) +** Heartbeat: 92% -- { 92000166 } -- 500.00 KIPS (528.74 KIPS) +** Heartbeat: 93% -- { 93000170 } -- 500.00 KIPS (528.41 KIPS) +** Heartbeat: 94% -- { 94000174 } -- 500.00 KIPS (528.09 KIPS) +** Heartbeat: 95% -- { 95000175 } -- 500.00 KIPS (527.78 KIPS) +** Heartbeat: 96% -- { 96000178 } -- 500.00 KIPS (527.47 KIPS) +** Heartbeat: 97% -- { 97000178 } -- 1000.00 KIPS (530.06 KIPS) +** Heartbeat: 98% -- { 98000179 } -- 500.00 KIPS (529.73 KIPS) +** Heartbeat: 99% -- { 99000179 } -- 500.00 KIPS (529.41 KIPS) +** Core 0 Finished: insts:100000003 cycles:62388250 time:19496328125000 -- 1.60 IPC (1.60 IPC) -- N/A KIPS (529.10 KIPS) +done +Scarab finished at Sun Jun 11 08:11:47 2023 + diff --git a/labs/LAB5/runs/leela_s_base-sms1/stream.stat.0.out b/labs/LAB5/runs/leela_s_base-sms1/stream.stat.0.out new file mode 100644 index 00000000..11d37b20 --- /dev/null +++ b/labs/LAB5/runs/leela_s_base-sms1/stream.stat.0.out @@ -0,0 +1,188 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 62388250 Instructions: 100000003 IPC: 1.60287 + +DCACHE_PREF_HIT 0 0 + +IFETCH_WB_FIRST_SCHEDULE 0 -nan% 0 -nan% +PREFETCH_LAST_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_PREF_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_LOW_OP_SCHEDULE 0 -nan% 0 -nan% +DEMAND_LAST_SCHEDULE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +SEND_MISS_REQ_QUEUE 4908 4908 + +L1_DATA_EVICT 66 66 + +STREAM_BUFFER_REQ 0 0 + +PREF_SEND_TO_MEM_REQ 0 -nan% 0 -nan% +PREF_SEND_TO_MEM_REQ_FAIL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +HIT_TRAIN_STREAM 1757 30.830% 1757 30.830% +MISS_TRAIN_STREAM 3942 69.170% 3942 69.170% + 5699 100.000% 5699 100.000% + 0.69 0.63 0.69 0.63 + +STREAM_TRAIN_CREATE 2519 2519 + +MEM_REQ_MISS_HWP_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_SW_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_IFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DSTORE_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DPRF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_WB_Q 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_BY_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_WB 0 -nan% 0 -nan% +PREF_HIT_BY_PREF 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_WB 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_L1_FILL 0 -nan% 0 -nan% +DEMAND_L1_FILL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TOUCH_L1_REPLACE 0 0.000% 0 0.000% +NO_TOUCH_L1_REPLACE 66 100.000% 66 100.000% + 66 100.000% 66 100.000% + 1.00 1.01 1.00 1.01 + +PREF_REQ_QUE_FULL 0 0 + +STREAM_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +L2HIT_STREAM_PREF_REQ_QUE_FULL 0 0 + +L2HIT_HIT_TRAIN_STREAM 0 -nan% 0 -nan% +L2HIT_MISS_TRAIN_STREAM 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_TRAIN_CREATE 0 0 + +L2HIT_STREAM_BUFFER_REQ 0 0 + +L2HIT_STREAM_PREF_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_STREAM_PREF_DCACHE_INSERT 0 -nan% 0 -nan% +L2HIT_STREAM_L2_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_DCACHE_PORT_FULL 0 0 + +L2HIT_STREAM_PREF_L1_PORT_FULL 0 0 + +L2HIT_TRAIN_HIT_DEMAND 0 -nan% 0 -nan% +L2HIT_TRAIN_MISS_REQ 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_TRAIN_FILTER_MISS 0 -nan% 0 -nan% +L2HIT_TRAIN_FILTER_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_PREF_REQ_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_PREF_REQ_DCACHE_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_L2SEND_Q_FULL 0 -nan% 0 -nan% +L2HIT_L2SEND_Q_ENTER 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_MEM_REQ 0 0 + +REMOVE_REDUNDANT_STREAM_STAT 0 0 + +REPLACE_OLD_STREAM 2503 2503 + +REQ_SEND_QUEUE_STALL 0 0 + +STREAM_ENTER_RA 0 0 + +CORE_STREAM_LENGTH_0 24 15.385% 24 15.385% +CORE_STREAM_LENGTH_10 60 38.462% 60 38.462% +CORE_STREAM_LENGTH_20 29 18.590% 29 18.590% +CORE_STREAM_LENGTH_30 15 9.615% 15 9.615% +CORE_STREAM_LENGTH_40 8 5.128% 8 5.128% +CORE_STREAM_LENGTH_50 5 3.205% 5 3.205% +CORE_STREAM_LENGTH_60 1 0.641% 1 0.641% +CORE_STREAM_LENGTH_70 6 3.846% 6 3.846% +CORE_STREAM_LENGTH_80 0 0.000% 0 0.000% +CORE_STREAM_LENGTH_90 6 3.846% 6 3.846% +CORE_STREAM_LENGTH_100_P 2 1.282% 2 1.282% + 156 100.000% 156 100.000% + 2.19 2.16 2.19 2.16 + +CORE_CUM_STREAM_LENGTH_0 170 4.031% 170 4.031% +CORE_CUM_STREAM_LENGTH_10 892 21.152% 892 21.152% +CORE_CUM_STREAM_LENGTH_20 671 15.912% 671 15.912% +CORE_CUM_STREAM_LENGTH_30 540 12.805% 540 12.805% +CORE_CUM_STREAM_LENGTH_40 349 8.276% 349 8.276% +CORE_CUM_STREAM_LENGTH_50 265 6.284% 265 6.284% +CORE_CUM_STREAM_LENGTH_60 60 1.423% 60 1.423% +CORE_CUM_STREAM_LENGTH_70 446 10.576% 446 10.576% +CORE_CUM_STREAM_LENGTH_80 0 0.000% 0 0.000% +CORE_CUM_STREAM_LENGTH_90 547 12.971% 547 12.971% +CORE_CUM_STREAM_LENGTH_100_P 277 6.569% 277 6.569% + 4217 100.000% 4217 100.000% + 4.21 3.23 4.21 3.23 + +CORE_STREAM_TRAIN_HITS_0 99 63.462% 99 63.462% +CORE_STREAM_TRAIN_HITS_10 31 19.872% 31 19.872% +CORE_STREAM_TRAIN_HITS_20 8 5.128% 8 5.128% +CORE_STREAM_TRAIN_HITS_30 4 2.564% 4 2.564% +CORE_STREAM_TRAIN_HITS_40 2 1.282% 2 1.282% +CORE_STREAM_TRAIN_HITS_50 4 2.564% 4 2.564% +CORE_STREAM_TRAIN_HITS_60 1 0.641% 1 0.641% +CORE_STREAM_TRAIN_HITS_70 5 3.205% 5 3.205% +CORE_STREAM_TRAIN_HITS_80 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_90 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_100_P 2 1.282% 2 1.282% + 156 100.000% 156 100.000% + 0.95 1.77 0.95 1.77 + +CORE_CUM_STREAM_TRAIN_HITS_0 598 25.115% 598 25.115% +CORE_CUM_STREAM_TRAIN_HITS_10 462 19.404% 462 19.404% +CORE_CUM_STREAM_TRAIN_HITS_20 181 7.602% 181 7.602% +CORE_CUM_STREAM_TRAIN_HITS_30 135 5.670% 135 5.670% +CORE_CUM_STREAM_TRAIN_HITS_40 89 3.738% 89 3.738% +CORE_CUM_STREAM_TRAIN_HITS_50 234 9.828% 234 9.828% +CORE_CUM_STREAM_TRAIN_HITS_60 60 2.520% 60 2.520% +CORE_CUM_STREAM_TRAIN_HITS_70 376 15.792% 376 15.792% +CORE_CUM_STREAM_TRAIN_HITS_80 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_90 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_100_P 246 10.332% 246 10.332% + 2381 100.000% 2381 100.000% + 3.45 3.07 3.45 3.07 + +CORE_STREAM_TRAIN_CREATE 2519 2519 + + + diff --git a/labs/LAB5/runs/mcf_s_base-sms0/PARAMS.in b/labs/LAB5/runs/mcf_s_base-sms0/PARAMS.in new file mode 100644 index 00000000..2593c2b8 --- /dev/null +++ b/labs/LAB5/runs/mcf_s_base-sms0/PARAMS.in @@ -0,0 +1,226 @@ +# File : PARAMS.kaby_lake +# Date : 03/06/19 +# Description : Kaby Lake Configuration +# +# Based on documentation found here: +# https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake + +## Simulation Parameters +--mode full +--model cmp +--sim_limit none + +## Core Parameters + +# Femptoseconds, 3.2GHz, used for energy estimates. +--chip_cycle_time 312500 + + +### Fetch Stage +--fetch_off_path_ops 1 +--fetch_across_cache_lines 1 + +# Will break the packet upon a taken branch. +--fetch_break_on_taken 1 + +# Number of bubble cycles to wait after taken branch. +--fetch_taken_bubble_cycles 0 + + +#### ICache +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 + +### Branch Predictor +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_mech tagescl + + +#### BTB + +# BTB model to use. +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 + +# Allow the BTB to be updated by off path ops. +--btb_off_path_writes 1 + + +#### CRS + +# Enable return stack +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 + +### iBP +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged + # iBTB Model. tc_tagless, tc_tagged, tc_hybrid. +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 + +### Decode Stage +--decode_cycles 5 + + +### Map Stage +--map_cycles 5 + + +### Issue Stage + +# Max number of instructions to be fetched, decoded, renamed, and issued per cycle. +--issue_width 6 + +--rs_fill_width 0 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 + + +### Exec Stage + +### DCache +--dcache_size 32768 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--dcache_assoc 4 +--dcache_line_size 64 + +### Reorder/Retire Stage + +# Max number of instructions to be retired per cycle. +--node_ret_width 6 +--node_table_size 224 + +# Do not keep stores in RSVs on cache misses; TODO: confirm what this knob does +--stores_do_not_block_window 1 + +# TODO: confirm what this knob does +--prefs_do_not_block_window 1 + + +## Uncore + +### Mid-level cache + +# Enable use of a midlevel cache between i/d and L1 +--mlc_present 0 + +### LLC +--l1_size 1048576 +--l1_banks 1 +--l1_cycles 18 +--l1_assoc 8 +--l1_line_size 64 +--l1_interleave_factor 64 + + +### Prefetcher +--pref_framework_on 1 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--pref_shared_queues 0 +--pref_train_on_pref_misses 0 +--pref_oracle_train 0 +--pref_ul1req_queue_overwrite_on_full 1 + +--stream_length 64 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 + +--pref_throttlefb_on=1 +--pref_acc_thresh_1=0.75 +--pref_acc_thresh_2=0.4 +--pref_acc_thresh_3=0.4 +--pref_timely_thresh=0.01 +--pref_polpf_thresh=0.005 +--pref_update_interval=8192 + +--mem_req_buffer_pref_watermark 4 +--promote_to_higher_priority_mem_req_type 1 + +### Memory +--addr_translation random + +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 + +--mem_req_buffer_entries 32 +--mem_l1_fill_queue_entries 32 +--va_page_size_bytes 4096 +--bus_width_in_bytes 8 + +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 + +## Other + + +### Debug +--debug_inst_start 0 +--debug_inst_stop -1 +--debug_cycle_start 0 +--debug_cycle_stop -1 + + +## Stats and Params +--dump_params 1 +--dump_stats 1 +--dump_trace 0 + +#################################### +--set_off_path_confirmed 1 + +--order_beyond_bus 1 + +--mem_ooo_stores 1 +--mem_obey_store_dep 1 diff --git a/labs/LAB5/runs/mcf_s_base-sms0/PARAMS.out b/labs/LAB5/runs/mcf_s_base-sms0/PARAMS.out new file mode 100644 index 00000000..7274c493 --- /dev/null +++ b/labs/LAB5/runs/mcf_s_base-sms0/PARAMS.out @@ -0,0 +1,908 @@ +--mode full +--model cmp +--frontend memtrace +--inst_limit 100000000 +--sim_limit none +--dump_params 1 +--dump_stats 1 +--dump_trace 0 +--mlc_present 0 +--l1_size 1048576 +--l1_assoc 8 +--l1_line_size 64 +--l1_cycles 18 +--l1_banks 1 +--l1_interleave_factor 64 +--va_page_size_bytes 4096 +--addr_translation random +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 +--dcache_size 32768 +--dcache_assoc 4 +--dcache_line_size 64 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--mem_ooo_stores 1 +--mem_obey_store_dep 1 +--mem_req_buffer_entries 32 +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 +--promote_to_higher_priority_mem_req_type 1 +--mem_req_buffer_pref_watermark 4 +--mem_l1_fill_queue_entries 32 +--order_beyond_bus 1 +--set_off_path_confirmed 1 +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--bus_width_in_bytes 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 +--chip_cycle_time 312500 +--issue_width 6 +--rs_fill_width 0 +--node_table_size 224 +--node_ret_width 6 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 +--decode_cycles 5 +--map_cycles 5 +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--fetch_across_cache_lines 1 +--fetch_off_path_ops 0 +--fetch_break_on_taken 1 +--fetch_taken_bubble_cycles 0 +--stores_do_not_block_window 1 +--prefs_do_not_block_window 1 +--cbp_trace_r0 /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir/trace/drmemtrace.mcf_s_base.mytest-m64.554166.7956.trace.gz +--memtrace_modules_log /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir/raw +--debug_cycle_start 0 +--debug_cycle_stop -1 +--debug_inst_start 0 +--debug_inst_stop -1 +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--bp_mech tagescl +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 +--btb_off_path_writes 1 +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_length 64 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 +--pref_framework_on 1 +--pref_shared_queues 0 +--pref_ul1req_queue_overwrite_on_full 1 +--pref_train_on_pref_misses 0 +--pref_oracle_train_on 0 +--pref_throttlefb_on 1 +--pref_acc_thresh_1 0.75 +--pref_acc_thresh_2 0.4 +--pref_acc_thresh_3 0.4 +--pref_update_interval 8192 +--pref_timely_thresh 0.01 +--pref_polpf_thresh 0.005 +--pref_sms_on 0 +1 1 1 1 1 1 1 + +--- Cut out everything below to use this file as PARAMS.in --- + +Parameter status at compile time and values supplied on the command line: + +SIM_MODE 0 full +SIM_MODEL 0 cmp +FRONTEND FE_PIN_EXEC_DRIVEN memtrace +INST_LIMIT NULL 100000000 +SIM_LIMIT "none" none +FORWARD_PROGRESS_LIMIT 100000000 +FORWARD_PROGRESS_INTERVAL 10000 +FAST_FORWARD 0 +FAST_FORWARD_UNTIL_ADDR 0 +FAST_FORWARD_TRACE_INS 0 +WARMUP 0 +HEARTBEAT_INTERVAL 1000000 +NUM_HEARTBEATS 0 +FILE_TAG "" +OUTPUT_DIR "." +STATUS_FILE NULL +BINDIR NULL +DUMP_PARAMS TRUE 1 +DUMP_STATS TRUE 1 +DUMP_TRACE FALSE 0 +CLEAR_STATS "never" +STATS_TO_TRACE NULL +STAT_TRACE_FILE "stats.trace" +STAT_TRACE_INTERVAL "i:100000" +PIPEVIEW FALSE +PIPEVIEW_FILE "pipeview" +MEMVIEW FALSE +MEMVIEW_FILE "memview.out" +MEMVIEW_START "never" +INST_HASH_TABLE_SIZE 500021 const +STDOUT_FILE NULL +STDERR_FILE NULL +PIN_EXEC_DRIVEN_FE_SOCKET "./pin_exec_driven_fe_socket.temp" +PRINT_PID FALSE +USE_UNSURE_FREE_LISTS FALSE +OPTIMIZER2_MAX_NUM_SLAVES 64 +OPTIMIZER2_PERFECT_MEMORYLESS FALSE +EXIT_COND 0 +ENABLE_SWPRF FALSE +MLC_PRESENT FALSE 0 +MLC_SIZE (512 * 1024) +MLC_ASSOC 4 +MLC_LINE_SIZE 64 +MLC_CYCLES 12 +PERFECT_MLC FALSE +MLC_READ_PORTS 1 +MLC_WRITE_PORTS 1 +MLC_BANKS 8 +MLC_INTERLEAVE_FACTOR 64 +MLC_CACHE_REPL_POLICY 0 +MLC_WRITE_THROUGH FALSE +PREFETCH_UPDATE_LRU_MLC TRUE +FORCE_L1_MISS FALSE +L1_SIZE (4 * 1024 * 1024) 1048576 +L1_ASSOC 8 8 +L1_LINE_SIZE 64 64 +L1_CYCLES 24 18 +PERFECT_L1 FALSE +PRIVATE_L1 FALSE +L1_READ_PORTS 1 +L1_WRITE_PORTS 1 +L1_BANKS 8 1 +L1_INTERLEAVE_FACTOR 64 64 +L1_CACHE_REPL_POLICY 0 +L1_WRITE_THROUGH FALSE +L1_IGNORE_WB FALSE +L1_USE_CORE_FREQ FALSE +MARK_L1_MISSES TRUE +PREFETCH_UPDATE_LRU_L1 TRUE +MEMORY_RANDOM_ADDR FALSE +VA_PAGE_SIZE_BYTES 4096 4096 +NUM_ADDR_NON_SIGN_EXTEND_BITS 48 +ADDR_TRANSLATION 0 random +CONSTANT_MEMORY_LATENCY FALSE +MEMORY_CYCLES 100 +STALL_MEM_REQS_ONLY FALSE +ICACHE_SIZE (64 * 1024) 32768 +ICACHE_ASSOC 4 4 +ICACHE_LINE_SIZE 64 64 +PERFECT_ICACHE FALSE +ICACHE_READ_PORTS 2 +ICACHE_WRITE_PORTS 1 +ICACHE_BANKS 8 +ICACHE_REPL 0 +DCACHE_SIZE (64 * 1024) 32768 +DCACHE_ASSOC 1 4 +DCACHE_LINE_SIZE 64 64 +DCACHE_CYCLES 2 +PERFECT_DCACHE FALSE +DCACHE_READ_PORTS 8 2 +DCACHE_WRITE_PORTS 1 1 +DCACHE_BANKS 1 1 +DCACHE_REPL 0 +DCACHE_REPL_PREF_THRESH 1 +MEM_OOO_STORES TRUE 1 +MEM_OBEY_STORE_DEP TRUE 1 +PREF_INSERT_LRU FALSE +PREF_INSERT_MIDDLE FALSE +PREF_INSERT_LOWQTR FALSE +PREF_INSERT_DYNACC FALSE +MEM_REQ_BUFFER_ENTRIES 32 32 +PRIVATE_MSHR_ON TRUE +MEM_PRIORITY_IFETCH 0 0 +MEM_PRIORITY_DFETCH 0 1 +MEM_PRIORITY_DSTORE 0 2 +MEM_PRIORITY_IPRF 9 3 +MEM_PRIORITY_DPRF 10 4 +MEM_PRIORITY_WB 0 5 +MEM_PRIORITY_WB_NODIRTY 0 5 +PROMOTE_TO_HIGHER_PRIORITY_MEM_REQ_TYPE FALSE 1 +MEM_REQ_BUFFER_PREF_WATERMARK 0 4 +MEM_REQ_BUFFER_WB_VALVE 2 +MEM_L1_FILL_QUEUE_ENTRIES 32 32 +MEM_BUS_OUT_QUEUE_PARTITION_ENABLE FALSE +MEM_MEM_QUEUE_PARTITION_ENABLE FALSE +MEM_BUS_OUT_QUEUE_AS_FIFO TRUE +OLDEST_FIRST_TO_MEM_QUEUE TRUE +ROUND_ROBIN_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE_TH 0 +L1_CYCLE_TIME 312500 +MLCQ_TO_L1Q_TRANSFER_LATENCY 1 +L1Q_TO_FSB_TRANSFER_LATENCY 1 +PRIORITIZE_PREFETCHES_WITH_UNIQUE FALSE +KICKOUT_PREFETCHES FALSE +KICKOUT_LOOK_FOR_OLDEST_FIRST FALSE +KICKOUT_OLDEST_PREFETCH FALSE +KICKOUT_OLDEST_PREFETCH_WITHIN_BANK FALSE +ORDER_BEYOND_BUS FALSE 1 +ALL_FIFO_QUEUES FALSE +QUEUE_MLC_SIZE 0 +QUEUE_L1_SIZE 0 +QUEUE_BUS_OUT_SIZE 0 +QUEUE_CORE_FILL_SIZE 0 +ALLOW_TYPE_MATCHES FALSE +STREAM_PREFETCH_ON FALSE +DC_PREF_CACHE_ENABLE FALSE +DC_PREF_CACHE_CYCLE 0 +PREF_INSERT_DCACHE_IMM TRUE +DC_PREF_CACHE_SIZE (64 * 1024) +DC_PREF_CACHE_ASSOC 4 +DC_PREF_ONLY_L1HIT FALSE +PREF_CACHE_USE_RDY_CYCLE FALSE +IC_PREF_CACHE_ENABLE FALSE +IC_PREF_CACHE_SIZE (64 * 1024) +IC_PREF_CACHE_ASSOC 4 +L1_PREF_CACHE_ENABLE FALSE +L1_PREF_CACHE_SIZE (1024 * 1024) +L1_PREF_CACHE_ASSOC 8 +SET_OFF_PATH_CONFIRMED FALSE 1 +USE_CONFIRMED_OFF FALSE +PREFCACHE_MOVE_OFFPATH FALSE +CACHE_STAT_ENABLE FALSE +PREF_DCACHE_HIT_FILL_L1 TRUE +PREF_ICACHE_HIT_FILL_L1 TRUE +CRITICAL_ACCESS_PLOT_ENABLE FALSE +CRITICAL_ACCESS_PLOT_FILE "critical_access_plot.dat" +ROUND_ROBIN_TO_L1 FALSE +PREF_I_TOGETHER FALSE +ONE_MORE_CACHE_LINE_ENABLE FALSE +L1_STATIC_PARTITION_ENABLE 0 +L1_STATIC_PARTITION NULL +L1_DYNAMIC_PARTITION_ENABLE FALSE +L1_DYNAMIC_PARTITION_POLICY 0 +PARTITION_UMON_DSS_PREF_ENABLE FALSE +L1_CACHE_HIT_POSITION_COLLECT FALSE +L1_PART_ON FALSE +L1_PART_TRIGGER "c:1000000" +L1_PART_START "t:0" +L1_PART_WARMUP FALSE +L1_PART_SHADOW_WARMUP FALSE +L1_PART_METRIC 0 +L1_PART_SEARCH 0 +L1_PART_USE_STALLING TRUE +L1_PART_FILL_DELAY 0 +L1_SHADOW_TAGS_MODULO 1 +HIER_MSHR_ON FALSE +PERF_PRED_ENABLE FALSE +PERF_PRED_MECH PERF_PRED_CP +PERF_PRED_REQ_LATENCY_MECH PERF_PRED_REQ_LATENCY_MECH_REQ_LATENCY +PERF_PRED_COUNT_ALL FALSE +PERF_PRED_COUNT_INST_MISSES TRUE +PERF_PRED_COUNT_PREFETCHES FALSE +PERF_PRED_COUNT_OFFPATH_REQS FALSE +PERF_PRED_COUNT_BW_REQS TRUE +PERF_PRED_UPDATE_MEM_REQ_TYPE FALSE +PERF_PRED_SLACK_PERIOD_SIZE 32 +PERF_PRED_REQS_FINISH_AT_FILL FALSE +PERF_PRED_MEM_UTIL_VIA_BUS_BW FALSE +PERF_PRED_CHIP_UTIL_VIA_MEM_STALL FALSE +DUMB_MODEL_AVG_REQ_DISTANCE 100 +DUMB_MODEL_RANDOMIZE_DISTANCE FALSE +DUMB_MODEL_AVG_REQ_DISTANCE_PER_CORE NULL +DUMB_MODEL_AVG_ROW_HITS 1 +DUMB_MODEL_AVG_ROW_HITS_PER_CORE NULL +DUMB_MODEL_MLP 1 +DUMB_MODEL_MLP_PER_CORE NULL +RAMULATOR_STANDARD "DDR4" DDR4 +RAMULATOR_SPEED "DDR4_2400R" DDR4_2400R +RAMULATOR_ORG "DDR4_8Gb_x8" DDR4_8Gb_x8 +RAMULATOR_CHANNELS 1 1 +RAMULATOR_RANKS 1 1 +RAMULATOR_BANKGROUPS 4 4 +RAMULATOR_BANKS 4 4 +RAMULATOR_CHIP_WIDTH 8 8 +BUS_WIDTH_IN_BYTES 8 8 +RAMULATOR_ROWS 65536 65536 +RAMULATOR_COLS 1024 1024 +RAMULATOR_SCHEDULING_POLICY "FRFCFS_Cap" FRFCFS_Cap +RAMULATOR_READQ_ENTRIES 32 32 +RAMULATOR_WRITEQ_ENTRIES 32 32 +RAMULATOR_REC_CMD_TRACE "off" FALSE +RAMULATOR_PRINT_CMD_TRACE "off" FALSE +RAMULATOR_USE_REST_OF_ADDR_AS_ROW_ADDR "on" +RAMULATOR_TCK 833333 833333 +RAMULATOR_TCL 16 16 +RAMULATOR_TCCD 6 6 +RAMULATOR_TCCDS 4 4 +RAMULATOR_TCCDL 6 6 +RAMULATOR_TCWL 12 12 +RAMULATOR_TBL 4 4 +RAMULATOR_TWTR 9 9 +RAMULATOR_TWTRS 3 3 +RAMULATOR_TWTRL 9 9 +RAMULATOR_TRP 16 16 +RAMULATOR_TRPpb 16 16 +RAMULATOR_TRPab 16 16 +RAMULATOR_TRCD 16 16 +RAMULATOR_TRCDR 16 16 +RAMULATOR_TRCDW 16 16 +RAMULATOR_TRAS 39 39 +DRAM_TECH_IN_NM 32 32 +DVFS_ON FALSE +DVFS_METRIC DVFS_METRIC_NUM_ELEMS +DVFS_CONFIGS NULL +DVFS_CONFIG_FILE NULL +DVFS_START "t:0" +DVFS_PERIOD "t:312500000000" +DVFS_LOG TRUE +DVFS_INDIVIDUAL_CORES FALSE +DVFS_CHIP_LEVEL FALSE +DVFS_STATIC NULL +DVFS_FORCE_CONFIG NULL +DVFS_REPLAY_CONFIG_TRACE NULL +DVFS_USE_ORACLE FALSE +DVFS_USE_BW_SHARING FALSE +DVFS_USE_DRAM_SHARING FALSE +DVFS_USE_STALL_TIME FALSE +DVFS_DRAM_SHARING_SOLVER_BIN NULL +DVFS_DRAM_SHARING_SOLVER_STRICT TRUE +DVFS_BW_SHARING_BUS_UTIL_THRESH 0.95 +DVFS_BW_SHARING_MAX_REQS 28.0 +DVFS_BW_SHARING_MAX_RW_COST 0.25 +DVFS_BW_SHARING_NO_PREF_STALL TRUE +DVFS_BW_SHARING_CRIT_STATS TRUE +DVFS_COUNT_L1_ACCESS_STALL FALSE +NUM_CORES 1 +CHIP_CYCLE_TIME 312500 312500 +CORE_0_CYCLE_TIME 312500 +CORE_1_CYCLE_TIME 312500 +CORE_2_CYCLE_TIME 312500 +CORE_3_CYCLE_TIME 312500 +CORE_4_CYCLE_TIME 312500 +CORE_5_CYCLE_TIME 312500 +CORE_6_CYCLE_TIME 312500 +CORE_7_CYCLE_TIME 312500 +CORE_8_CYCLE_TIME 312500 +CORE_9_CYCLE_TIME 312500 +CORE_10_CYCLE_TIME 312500 +CORE_11_CYCLE_TIME 312500 +CORE_12_CYCLE_TIME 312500 +CORE_13_CYCLE_TIME 312500 +CORE_14_CYCLE_TIME 312500 +CORE_15_CYCLE_TIME 312500 +CORE_16_CYCLE_TIME 312500 +CORE_17_CYCLE_TIME 312500 +CORE_18_CYCLE_TIME 312500 +CORE_19_CYCLE_TIME 312500 +CORE_20_CYCLE_TIME 312500 +CORE_21_CYCLE_TIME 312500 +CORE_22_CYCLE_TIME 312500 +CORE_23_CYCLE_TIME 312500 +CORE_24_CYCLE_TIME 312500 +CORE_25_CYCLE_TIME 312500 +CORE_26_CYCLE_TIME 312500 +CORE_27_CYCLE_TIME 312500 +CORE_28_CYCLE_TIME 312500 +CORE_29_CYCLE_TIME 312500 +CORE_30_CYCLE_TIME 312500 +CORE_31_CYCLE_TIME 312500 +CORE_32_CYCLE_TIME 312500 +CORE_33_CYCLE_TIME 312500 +CORE_34_CYCLE_TIME 312500 +CORE_35_CYCLE_TIME 312500 +CORE_36_CYCLE_TIME 312500 +CORE_37_CYCLE_TIME 312500 +CORE_38_CYCLE_TIME 312500 +CORE_39_CYCLE_TIME 312500 +CORE_40_CYCLE_TIME 312500 +CORE_41_CYCLE_TIME 312500 +CORE_42_CYCLE_TIME 312500 +CORE_43_CYCLE_TIME 312500 +CORE_44_CYCLE_TIME 312500 +CORE_45_CYCLE_TIME 312500 +CORE_46_CYCLE_TIME 312500 +CORE_47_CYCLE_TIME 312500 +CORE_48_CYCLE_TIME 312500 +CORE_49_CYCLE_TIME 312500 +CORE_50_CYCLE_TIME 312500 +CORE_51_CYCLE_TIME 312500 +CORE_52_CYCLE_TIME 312500 +CORE_53_CYCLE_TIME 312500 +CORE_54_CYCLE_TIME 312500 +CORE_55_CYCLE_TIME 312500 +CORE_56_CYCLE_TIME 312500 +CORE_57_CYCLE_TIME 312500 +CORE_58_CYCLE_TIME 312500 +CORE_59_CYCLE_TIME 312500 +CORE_60_CYCLE_TIME 312500 +CORE_61_CYCLE_TIME 312500 +CORE_62_CYCLE_TIME 312500 +CORE_63_CYCLE_TIME 312500 +ISSUE_WIDTH 4 6 +RS_FILL_WIDTH 8 0 +NODE_TABLE_SIZE 256 224 +NODE_RET_WIDTH 4 6 +NODE_RETIRE_RATE 10 +RS_SIZES "256" 97 +RS_CONNECTIONS "xF" 0 +FU_TYPES "0, 0, 0, 0" 0 0 0 0 0 0 0 0 +DECODE_CYCLES 1 5 +MAP_CYCLES 1 5 +EXTRA_RECOVERY_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after recovery. +EXTRA_REDIRECT_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after redirect. +EXTRA_CALLSYS_CYCLES 20 const +DIE_ON_CALLSYS FALSE +DIE_ON_RET_STALL_THRESH 0 +DIE_ON_RET_STALL_CORE 0 +DIE_ON_MEM_BLOCK_THRESH 0 +DIE_ON_MEM_BLOCK_CORE 0 +FETCH_ACROSS_CACHE_LINES FALSE 1 +FETCH_OFF_PATH_OPS TRUE 0 +FETCH_BREAK_ON_TAKEN FALSE 1 +FETCH_TAKEN_BUBBLE_CYCLES 0 0 +WP_COLLECT_STATS FALSE +SWITCH_IC_FETCH_ON_RECOVERY TRUE +OP_INV_DELAY 1 +OP_NOP_DELAY 1 +OP_CF_DELAY 1 +OP_MOV_DELAY 1 +OP_CMOV_DELAY 1 +OP_LDA_DELAY 1 +OP_IMEM_DELAY 1 +OP_IADD_DELAY 1 +OP_IMUL_DELAY 3 +OP_IDIV_DELAY -20 +OP_ICMP_DELAY 1 +OP_LOGIC_DELAY 1 +OP_SHIFT_DELAY 1 +OP_FMEM_DELAY 1 +OP_FCVT_DELAY 3 +OP_FADD_DELAY 3 +OP_FMUL_DELAY 5 +OP_FMA_DELAY 5 +OP_FDIV_DELAY -20 +OP_FCMP_DELAY 3 +OP_FCMOV_DELAY 1 +OP_GATHER_DELAY 12 +OP_SCATTER_DELAY 18 +OP_PIPELINED_FAST_DELAY 2 +OP_PIPELINED_MEDIUM_DELAY 5 +OP_PIPELINED_SLOW_DELAY 10 +OP_NOTPIPELINED_MEDIUM_DELAY -5 +OP_NOTPIPELINED_SLOW_DELAY -20 +OP_NOTPIPELINED_VERY_SLOW_DELAY -100 +UNIFORM_OP_DELAY 0 +STALL_ON_WAIT_MEM TRUE +STORES_DO_NOT_BLOCK_WINDOW FALSE 1 +PREFS_DO_NOT_BLOCK_WINDOW FALSE 1 +OBEY_REG_DEP TRUE +OLDEST_FIRST_SCHED FALSE +FIND_EMPTIEST_RS FALSE +TRACK_L1_MISS_DEPS FALSE +CBP_TRACE_R0 NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir/trace/drmemtrace.mcf_s_base.mytest-m64.554166.7956.trace.gz +CBP_TRACE_R1 NULL +CBP_TRACE_R2 NULL +CBP_TRACE_R3 NULL +CBP_TRACE_R4 NULL +CBP_TRACE_R5 NULL +CBP_TRACE_R6 NULL +CBP_TRACE_R7 NULL +CBP_TRACE_R8 NULL +CBP_TRACE_R9 NULL +CBP_TRACE_R10 NULL +CBP_TRACE_R11 NULL +CBP_TRACE_R12 NULL +CBP_TRACE_R13 NULL +CBP_TRACE_R14 NULL +CBP_TRACE_R15 NULL +CBP_TRACE_R16 NULL +CBP_TRACE_R17 NULL +CBP_TRACE_R18 NULL +CBP_TRACE_R19 NULL +CBP_TRACE_R20 NULL +CBP_TRACE_R21 NULL +CBP_TRACE_R22 NULL +CBP_TRACE_R23 NULL +CBP_TRACE_R24 NULL +CBP_TRACE_R25 NULL +CBP_TRACE_R26 NULL +CBP_TRACE_R27 NULL +CBP_TRACE_R28 NULL +CBP_TRACE_R29 NULL +CBP_TRACE_R30 NULL +CBP_TRACE_R31 NULL +CBP_TRACE_R32 NULL +CBP_TRACE_R33 NULL +CBP_TRACE_R34 NULL +CBP_TRACE_R35 NULL +CBP_TRACE_R36 NULL +CBP_TRACE_R37 NULL +CBP_TRACE_R38 NULL +CBP_TRACE_R39 NULL +CBP_TRACE_R40 NULL +CBP_TRACE_R41 NULL +CBP_TRACE_R42 NULL +CBP_TRACE_R43 NULL +CBP_TRACE_R44 NULL +CBP_TRACE_R45 NULL +CBP_TRACE_R46 NULL +CBP_TRACE_R47 NULL +CBP_TRACE_R48 NULL +CBP_TRACE_R49 NULL +CBP_TRACE_R50 NULL +CBP_TRACE_R51 NULL +CBP_TRACE_R52 NULL +CBP_TRACE_R53 NULL +CBP_TRACE_R54 NULL +CBP_TRACE_R55 NULL +CBP_TRACE_R56 NULL +CBP_TRACE_R57 NULL +CBP_TRACE_R58 NULL +CBP_TRACE_R59 NULL +CBP_TRACE_R60 NULL +CBP_TRACE_R61 NULL +CBP_TRACE_R62 NULL +CBP_TRACE_R63 NULL +MEMTRACE_MODULES_LOG NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir/raw +DUMB_CORE_ON FALSE +DUMB_CORE 1 +DEBUG_CYCLE_START 0 0 +DEBUG_CYCLE_STOP 0 -1 +DEBUG_TIME_START 0 +DEBUG_TIME_STOP 0 +DEBUG_INST_START 0 0 +DEBUG_INST_STOP 0 -1 +DEBUG_OP_START 0 +DEBUG_OP_STOP 0 +DEBUG_CACHE_LIB FALSE +DEBUG_HASH_LIB FALSE +DEBUG_LIST_LIB FALSE +DEBUG_PORT_LIB FALSE +DEBUG_BUS_LIB FALSE +DEBUG_OP_POOL FALSE +DEBUG_ORACLE FALSE +DEBUG_FRONTEND FALSE +DEBUG_ADDR_TRANS FALSE +DEBUG_BP FALSE +DEBUG_BP_DIR FALSE +DEBUG_BTB FALSE +DEBUG_CRS FALSE +DEBUG_MAP FALSE +DEBUG_MEMORY FALSE +DEBUG_REPLAY FALSE +DEBUG_FREQ FALSE +DEBUG_MODEL FALSE +DEBUG_THREAD FALSE +DEBUG_ICACHE_STAGE FALSE +DEBUG_DECODE_STAGE FALSE +DEBUG_MAP_STAGE FALSE +DEBUG_NODE_STAGE FALSE +DEBUG_EXEC_STAGE FALSE +DEBUG_DCACHE_STAGE FALSE +DEBUG_RETIRED_UOPS FALSE +DEBUG_EXC_INSERTS FALSE +DEBUG_BP_CONF FALSE +DEBUG_ONPATH_CONF FALSE +DEBUG_STREAM FALSE +DEBUG_STREAM_MEM FALSE +DEBUG_WAY FALSE +DEBUG_L2MARKV FALSE +DEBUG_L2L1PREF FALSE +DEBUG_PERF_PRED FALSE +DEBUG_POWER_UTILS FALSE +DEBUG_DVFS FALSE +DEBUG_TRACE_READ FALSE +DEBUG_INST_FIELDS FALSE +DEBUG_OP_FIELDS FALSE +DEBUG_PIN_EXEC_DRIVEN FALSE +DEBUG_CACHE_PART FALSE +DEBUG_OPTIMIZER2 FALSE +DEBUG_PREF FALSE +PERFECT_BP FALSE +PERFECT_BTB FALSE +PERFECT_IBP FALSE +PERFECT_CRS FALSE +PERFECT_CBR_BTB FALSE +PERFECT_NT_BTB FALSE +CFS_PER_CYCLE 3 6 # Number of branches that can be predicted in a single cycle +UPDATE_BP_OFF_PATH FALSE 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +BP_UPDATE_AT_RETIRE FALSE 0 # Update the BP at retire. If false, update at the end of exec. +BP_MECH 0 tagescl +LATE_BP_MECH NUM_BP +LATE_BP_LATENCY 5 +HIST_LENGTH 16 +PHT_CTR_BITS 2 const +BHT_ENTRIES (4 * 1024) +BHT_ASSOC 4 +HYBRIDS_INDEX_LENGTH 16 +HYBRIDG_HIST_LENGTH 16 +HYBRIDP_HIST_LENGTH 16 +FILTER_INDEX_LENGTH 16 +USE_FILTER FALSE +INF_HYBRIDGP FALSE +BP_HASH_TOS FALSE +IBTB_HASH_TOS FALSE +BTB_MECH 0 generic +BTB_ENTRIES (4 * 1024) 4096 +BTB_ASSOC 4 4 +BTB_OFF_PATH_WRITES TRUE 1 +ENABLE_CRS TRUE 1 +CRS_ENTRIES 32 32 +CRS_REALISTIC 0 1 +ENABLE_IBP TRUE 1 # Enable the indirect branch predictor +USE_PAT_HIST TRUE +IBTB_MECH 1 tc_tagged +IBTB_HIST_LENGTH 16 +IBTB_OFF_PATH_WRITES TRUE 1 # Allow off path ops to update the ibtb. +TARGETS_IN_HIST 4 +TC_ENTRIES (4 * 1024) 4096 +TC_ASSOC 4 4 +NUM_CORR_BRANCHES 3 +SEL_HIST_BP_ENTRIES 8192 +SEL_HIST_LENGTH 16 +SEL_HIST_DYN_CNT_TH 16 +SEL_HIST_MISPRED_TH 4 +ENABLE_BP_CONF FALSE +CONF_MECH 0 +PERF_BP_CONF_PRED FALSE +BPC_BITS 16 +BPC_MECH 1 +BPC_CTR_RESET TRUE +BPC_CIT_BITS 8 +BPC_CIT_TH 50 +BPC_CTR_BITS 3 +OPC_COUNT_ZEROS FALSE +OPC_COUNT_THRESH 10 +INF_LOOP FALSE +INF_LOOP_BUCKETS 811 +LOOP_ENTRIES (4 * 1024) +LOOP_ASSOC 4 +LOOP_COUNT_MAX 127 +LOOP_REPEAT_MAX 15 +KNOB_PRINT_BRINFO FALSE +BR_MISPRED_FILE NULL +CONF_PERCEPTRON_TH 0 +CONF_PERCEPTRON_CTR_BITS 8 +CONF_PERCEPTRON_ENTRIES 127 +CONF_PERCEPTRON_THRESH_OVRD 0 +CONF_HIST_LENGTH 32 +PERCEPTRON_CONF_USE_CONF FALSE +PERCEPTRON_CONF_TRAIN_HIS FALSE +PERCEPTRON_CONF_TRAIN_CONF FALSE +PERCEPTRON_CONF_TRAIN_OFFSET_CONF FALSE +PERCEPTRON_TRAIN_MISP_FACTOR 1 +PERCEPTRON_TRAIN_CORR_FACTOR 1 +PERCEPTRON_CONF_HIS_BOTH FALSE +PERCEPTRON_CONF_HIS_BOTH_LENGTH 4 +ENABLE_ICACHE_PACKET_BREAKING TRUE +NUM_LOAD_STORE_PER_PACKET 0 +PACKET_BREAK_ON_FUS FALSE +PACKET_BREAK_FU_TYPES "G,G,G,G,G,G,G,G,G,G,G,G" +POWER_INTF_ON FALSE +POWER_INTF_ENABLE_SCALING FALSE +POWER_INTF_EXEC "power/power_intf.py" +POWER_INTF_REF_CHIP_TECH_NM 22 +POWER_INTF_REF_CHIP_FREQ (3.2e9) +POWER_INTF_REF_MEMORY_FREQ (0.8e9) +POWER_OTHER (0.0) +PREF_STREAM_ON FALSE 1 +PREF_STREAM_PER_CORE_ENABLE FALSE 1 +STREAM_BUFFER_N 16 +STREAM_PREFETCH_N 2 4 +STREAM_START_DIS 5 1 +STREAM_LENGTH 16 64 +STREAM_FULL_N 1 +STREAM_TRAIN_LENGTH 16 +STREAM_TRAIN_NUM 1 4 +PREF_ACC_USE_CACHE FALSE +STREAM_STALL_ON_QUEUE_FULL FALSE +PREF_SCHEDULE_NUM 4 +TRAIN_FILTER_SIZE 32 +PREF_REQ_Q_SIZE 64 +STREAM_CREATE_ON_DC_MISS FALSE 0 +STREAM_CREATE_ON_L1_MISS TRUE 1 +STREAM_TRAIN_ON_WRONGPATH TRUE +STREAM_CREATE_ON_WRONGPATH TRUE +STREAM_PREF_INTO_DCACHE FALSE +REMOVE_REDUNDANT_STREAM FALSE +L2HIT_STREAM_SCHEDULE_NUM 4 +PREF_REQ_QUEUE_FILTER_ON FALSE +HW_PREF_HIT_TRAIN_STREAM FALSE +L2HIT_STREAM_BUFFER_N 32 +L2HIT_STREAM_PREFETCH_N 2 +L2HIT_STREAM_START_DIS 2 +L2HIT_STREAM_LENGTH 8 +L2HIT_PREF_REQ_Q_SIZE 128 +L2HIT_L2ACCESS_REQ_Q_SIZE 64 +PREF_STREAM_ACCPERSTREAM FALSE +PREF_ACC_DISTANCE_10 128 +PREF_FRAMEWORK_ON FALSE 1 +PREF_TRACE_ON FALSE +PREF_DL0REQ_QUEUE_SIZE 32 +PREF_UMLC_REQ_QUEUE_SIZE 64 +PREF_UL1REQ_QUEUE_SIZE 128 +PREF_SHARED_QUEUES TRUE 0 +PREF_DL0_MISS_ON TRUE +PREF_DL0_HIT_ON TRUE +PREF_DL0REQ_QUEUE_FILTER_ON TRUE +PREF_UMLC_REQ_QUEUE_FILTER_ON TRUE +PREF_UL1REQ_QUEUE_FILTER_ON TRUE +PREF_DL0REQ_ADD_FILTER_ON TRUE +PREF_UMLC_REQ_ADD_FILTER_ON TRUE +PREF_UL1REQ_ADD_FILTER_ON TRUE +PREF_DL0REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UMLC_REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UL1REQ_QUEUE_OVERWRITE_ON_FULL FALSE 1 +PREF_DL0SCHEDULE_NUM 4 +PREF_UMLC_SCHEDULE_NUM 4 +PREF_UL1SCHEDULE_NUM 4 +PREF_L1Q_DEMAND_RESERVE 0 +PREF_REPORT_PREF_MATCH_AS_MISS FALSE +PREF_REPORT_PREF_MATCH_AS_HIT TRUE +PREF_UPDATE_ON_WRONGPATH TRUE +PREF_TRAIN_ON_PREF_MISSES FALSE 0 +PREF_ORACLE_TRAIN_ON FALSE 0 +PREF_REQ_DROP FALSE +PREF_THROTTLE_ON FALSE +PREF_THROTTLEFB_ON FALSE 1 +PREF_ACC_THRESH_1 0.90 0.75 +PREF_ACC_THRESH_2 0.70 0.4 +PREF_ACC_THRESH_3 0.60 0.4 +PREF_ACC_THRESH_4 0.40 +PREF_UPDATE_INTERVAL 0 8192 +PREF_ANALYZE_LOAD FALSE +PREF_POL_THRESH_1 0.25 +PREF_POL_THRESH_2 0.10 +PREF_POLBV_ON FALSE +PREF_POLBV_SIZE 1024 +PREF_TIMELY_THRESH 0.05 0.01 +PREF_POLPF_THRESH 0.01 0.005 +PREF_DEGFB_USEONLYACC FALSE +PREF_DEGFB_USEONLYPOL FALSE +PREF_DEGFB_USEONLYLATE FALSE +PREF_TIMELY_THRESH_2 0.005 +PREF_DEGFB_STATPHASEFILE FALSE +PREF_MAX_DEGFB 4 +PREF_DHAL FALSE +PREF_DHAL_SENTTHRESH 16 +PREF_DHAL_USETHRESH_MAX 12 +PREF_DHAL_USETHRESH_MIN2 8 +PREF_DHAL_USETHRESH_MIN1 4 +PREF_DHAL_MAXDEG 64 +PREF_HFILTER_ON FALSE +PREF_HFILTER_INDEX_BITS 12 +PREF_HFILTER_USE_PC FALSE +PREF_HFILTER_PRED_USELESS_THRES 2 +PREF_HFILTER_RESET_ENABLE FALSE +PREF_HFILTER_RESET_INTERVAL 100000 +L2L1PREF_ON FALSE +L2WAY_PREF FALSE +L2MARKV_PREF_ON FALSE +L2NEXT_PREF_ON FALSE +L2HIT_STREAM_PREF_ON FALSE +L2L1_DC_HIT_TRAIN FALSE +L1_HIT_DUMP_FILE_ON FALSE +L1_HIT_DUMP_WO_TXT FALSE +L1_HIT_DUMPFILE "l1hit_dump.out" +IDEAL_L2_L1_PREFETCHER FALSE +IDEAL_L2_ICACHE_PREFETCHER FALSE +L1WAY_PREF_SEND_QUEUE 4 +L1PREF_REQ_QUEUE_SIZE 1024 +L1PREF_IMMEDIATE FALSE +L1WAY_PREF_TIMER_DIS 1000 +L1MARKV_PREF_SEND_QUEUE 4 +L1PREF_MARKV_REQ_QUEUE_SIZE 1024 +MARKV_L2ACCESS_REQ_Q_SIZE 64 +L1MARKV_PREF_IMMEDIATE FALSE +L1MARKV_PREF_TIMER_DIS 1 +L2L1_HIT_TRAIN TRUE +L1MARKV_REQ_TH 1 +L2L1_IMMEDIATE_PREF_CACHE FALSE +L2L1_FILL_PREF_CACHE FALSE +L2L1_L2_HIT_STAT FALSE +PREF_GHB_ON FALSE +DEBUG_PREF_GHB FALSE +PREF_GHB_BUFFER_N 1024 +PREF_GHB_INDEX_N 128 +PREF_GHB_CZONE_BITS 12 +PREF_GHB_DEGREE 16 +PREF_GHB_MAX_DEGREE 32 +PREF_STRIDE_ON FALSE +DEBUG_PREF_STRIDE FALSE +PREF_STRIDE_TABLE_N 1024 +PREF_STRIDE_REGION_BITS 16 +PREF_STRIDE_DEGREE 4 +PREF_STRIDE_DISTANCE 16 +PREF_STRIDE_STARTDISTANCE 1 +PREF_STRIDE_SINGLE_THRESH 6 +PREF_STRIDE_MULTI_THRESH 6 +PREF_STRIDE_SINGLE_STRIDE_MODE FALSE +PREF_STRIDEPC_ON FALSE +DEBUG_PREF_STRIDEPC FALSE +PREF_STRIDEPC_TABLE_N 1024 +PREF_STRIDEPC_DEGREE 4 +PREF_STRIDEPC_DISTANCE 16 +PREF_STRIDEPC_USELOADADDR FALSE +PREF_STRIDEPC_TRAINNUM 2 +PREF_STRIDEPC_STARTDIS 4 +PREF_PHASE_ON FALSE +PREF_PHASE_STUDY FALSE +DEBUG_PREF_PHASE FALSE +PREF_PHASE_PRIME_HASH 16381 +PREF_PHASE_INFOSIZE 16384 +PREF_PHASE_LOG2REGIONSIZE 12 +PREF_PHASE_REGIONENTRIES 64 +PREF_PHASE_TRACKEDREGIONS 32 +PREF_PHASE_INTERVAL 100000 +PREF_PHASE_TABLE_SIZE 64 +PREF_PHASE_MAXDIFF_THRESH 64 +PREF_PHASE_MIN_MISSES 64 +PREF_PHASE_MISSPER 0.4 +PREF_2DC_ON FALSE +DEBUG_PREF_2DC FALSE +PREF_2DC_CACHE_SIZE (1 * 1024) +PREF_2DC_CACHE_ASSOC 4 +PREF_2DC_CACHE_LINE_SIZE 1 +PREF_2DC_DEGREE 16 +PREF_2DC_ZONE_SHIFT 10 +PREF_2DC_TAG_SIZE 16 +PREF_2DC_NUM_REGIONS 64 +PREF_2DC_REGION_HASH 61 +PREF_MARKOV_ON FALSE +DEBUG_PREF_MARKOV FALSE +PREF_MARKOV_NUM_ENTRIES 65536 +PREF_MARKOV_NUM_NEXT_STATES 8 +PREF_MARKOV_SEND_ON_PREF_HIT TRUE +PREF_MARKOV_UPDATE_ON_PREF_HIT TRUE +PREF_MARKOV_TABLE_UPDATE_POLICY 0 +PREF_MARKOV_SEND_THRESHOLD 0 +PREF_SMS_ON FALSE 0 +PREF_SMS_AT_SIZE 64 +PREF_SMS_FT_SIZE 64 +PREF_SMS_PHT_SIZE 16384 +PREF_SMS_PRF_SIZE 1024 +PREF_SMS_REGION_SIZE 2048 diff --git a/labs/LAB5/runs/mcf_s_base-sms0/bp.stat.0.out b/labs/LAB5/runs/mcf_s_base-sms0/bp.stat.0.out new file mode 100644 index 00000000..4a7eac10 --- /dev/null +++ b/labs/LAB5/runs/mcf_s_base-sms0/bp.stat.0.out @@ -0,0 +1,752 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 121548526 Instructions: 100000002 IPC: 0.82272 + +BTB_ON_PATH_MISS 236 0.001% 236 0.001% +BTB_ON_PATH_HIT 25492868 99.999% 25492868 99.999% + 25493104 100.000% 25493104 100.000% + 1.00 1.00 1.00 1.00 + +BTB_OFF_PATH_MISS 0 -nan% 0 -nan% +BTB_OFF_PATH_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BTB_ON_PATH_WRITE 236 100.000% 236 100.000% +BTB_OFF_PATH_WRITE 0 0.000% 0 0.000% + 236 100.000% 236 100.000% + 0.00 0.00 0.00 0.00 + +BP_ON_PATH_CORRECT 24318367 95.392% 24318367 95.392% +BP_ON_PATH_MISPREDICT 245998 0.965% 245998 0.965% +BP_ON_PATH_MISFETCH 928739 3.643% 928739 3.643% + 25493104 100.000% 25493104 100.000% + 0.08 0.38 0.08 0.38 + +BP_OFF_PATH_CORRECT 0 -nan% 0 -nan% +BP_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% +BP_OFF_PATH_MISFETCH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +LATE_BP_ON_PATH_CORRECT 25493104 100.000% 25493104 100.000% +LATE_BP_ON_PATH_MISPREDICT 0 0.000% 0 0.000% +LATE_BP_ON_PATH_MISFETCH 0 0.000% 0 0.000% + 25493104 100.000% 25493104 100.000% + 0.00 0.00 0.00 0.00 + +LATE_BP_OFF_PATH_CORRECT 0 -nan% 0 -nan% +LATE_BP_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% +LATE_BP_OFF_PATH_MISFETCH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_PVN 0 -nan% 0 -nan% +BP_ON_PATH_CONF_PVN_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_PVP 0 -nan% 0 -nan% +BP_ON_PATH_CONF_PVP_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_SPEC 0 -nan% 0 -nan% +BP_ON_PATH_CONF_SPEC_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CRS_MISS_ON_PATH 22123 0.960% 22123 0.960% +CRS_HIT_ON_PATH 2281157 99.040% 2281157 99.040% + 2303280 100.000% 2303280 100.000% + 0.99 0.99 0.99 0.99 + +CRS_MISS_OFF_PATH 0 -nan% 0 -nan% +CRS_HIT_OFF_PATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CRS_CLOBBER 0 0 + +TARG_ON_PATH_MISS 466812 20.695% 466812 20.695% +TARG_ON_PATH_HIT 1788861 79.305% 1788861 79.305% + 2255673 100.000% 2255673 100.000% + 0.79 0.73 0.79 0.73 + +TARG_OFF_PATH_MISS 0 -nan% 0 -nan% +TARG_OFF_PATH_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_ON_PATH_WRITE 2255673 100.000% 2255673 100.000% +TARG_OFF_PATH_WRITE 0 0.000% 0 0.000% + 2255673 100.000% 2255673 100.000% + 0.00 0.00 0.00 0.00 + +TARG_HYBRID_CORRECT_TAGLESS 0 -nan% 0 -nan% +TARG_HYBRID_CORRECT_TAGGED 0 -nan% 0 -nan% +TARG_HYBRID_MISPRED_TAGLESS 0 -nan% 0 -nan% +TARG_HYBRID_MISPRED_TAGGED 0 -nan% 0 -nan% +TARG_HYBRID_NO_PRED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_VP_INDIRECT_MISPRED 0 -nan% 0 -nan% +TARG_VP_INDIRECT_NOPRED 0 -nan% 0 -nan% +TARG_VP_INDIRECT_CORRECT 0 -nan% 0 -nan% + 0 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12.888% 15442373 12.888% +ST_OP_CMOV 143289 0.120% 143289 0.120% +ST_OP_LDA 2302780 1.922% 2302780 1.922% +ST_OP_IMEM 42522682 35.489% 42522682 35.489% +ST_OP_IADD 12864851 10.737% 12864851 10.737% +ST_OP_IMUL 199955 0.167% 199955 0.167% +ST_OP_IDIV 93130 0.078% 93130 0.078% +ST_OP_ICMP 10060259 8.396% 10060259 8.396% +ST_OP_LOGIC 6535545 5.454% 6535545 5.454% +ST_OP_SHIFT 418811 0.350% 418811 0.350% +ST_OP_FMEM 0 0.000% 0 0.000% +ST_OP_FCVT 0 0.000% 0 0.000% +ST_OP_FADD 0 0.000% 0 0.000% +ST_OP_FMUL 0 0.000% 0 0.000% +ST_OP_FMA 0 0.000% 0 0.000% +ST_OP_FDIV 0 0.000% 0 0.000% +ST_OP_FCMP 0 0.000% 0 0.000% +ST_OP_FCMOV 0 0.000% 0 0.000% +ST_OP_GATHER 0 0.000% 0 0.000% +ST_OP_SCATTER 0 0.000% 0 0.000% +ST_OP_PIPELINED_FAST 0 0.000% 0 0.000% +ST_OP_PIPELINED_MEDIUM 0 0.000% 0 0.000% +ST_OP_PIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_MEDIUM 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_VERY_SLOW 0 0.000% 0 0.000% + 119819899 100.000% 119819899 100.000% + 5.33 2.81 5.33 2.81 + +ST_NOT_CF 94326795 78.724% 94326795 78.724% +ST_CF_BR 2170929 1.812% 2170929 1.812% +ST_CF_CBR 18715628 15.620% 18715628 15.620% +ST_CF_CALL 47594 0.040% 47594 0.040% +ST_CF_IBR 0 0.000% 0 0.000% +ST_CF_ICALL 2255673 1.883% 2255673 1.883% +ST_CF_ICO 0 0.000% 0 0.000% +ST_CF_RET 2303280 1.922% 2303280 1.922% +ST_CF_SYS 0 0.000% 0 0.000% + 119819899 100.000% 119819899 100.000% + 0.56 1.22 0.56 1.22 + +ST_BAR_NONE 119819899 100.000% 119819899 100.000% +ST_BAR_FETCH 0 0.000% 0 0.000% +ST_BAR_ISSUE 0 0.000% 0 0.000% +ST_BAR_BOTH 0 0.000% 0 0.000% + 119819899 100.000% 119819899 100.000% + 0.00 0.00 0.00 0.00 + +ST_NOT_MEM 77297217 64.511% 77297217 64.511% +ST_MEM_LD 34277566 28.608% 34277566 28.608% +ST_MEM_ST 8245116 6.881% 8245116 6.881% +ST_MEM_PF 0 0.000% 0 0.000% +ST_MEM_WH 0 0.000% 0 0.000% +ST_MEM_EVICT 0 0.000% 0 0.000% + 119819899 100.000% 119819899 100.000% + 0.42 0.52 0.42 0.52 + +ST_NOT_MEM_OFFPATH 0 -nan% 0 -nan% +ST_MEM_LD_OFFPATH 0 -nan% 0 -nan% +ST_MEM_ST_OFFPATH 0 -nan% 0 -nan% +ST_MEM_PF_OFFPATH 0 -nan% 0 -nan% +ST_MEM_WH_OFFPATH 0 -nan% 0 -nan% +ST_MEM_EVIC_OFFPATHT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ST_OP_ONPATH 119819899 119819899 + +ST_OP_OFFPATH 0 0 + +ST_FAKE_OP_OFFPATH 0 -nan% 0 -nan% +ST_NOT_FAKE_OP_OFFPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ST_FAKE_REASON_NOT_FAKE 0 -nan% 0 -nan% +ST_FAKE_REASON_REDIRECT_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_RETURN_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_NONRET_CF_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_NOT_TAKEN_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_WRONG_PATH_STORE_TO_NEW_REGION 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ST_INST_ONPATH 100000028 100000028 + +ST_INST_OFFPATH 0 0 + +STATIC_PIN_NOP 0 0 + +DYNAMIC_PIN_REP_GREATER_256 0 0 + + + diff --git a/labs/LAB5/runs/mcf_s_base-sms0/l2l1pref.stat.0.out b/labs/LAB5/runs/mcf_s_base-sms0/l2l1pref.stat.0.out new file mode 100644 index 00000000..4d793c6b --- /dev/null +++ b/labs/LAB5/runs/mcf_s_base-sms0/l2l1pref.stat.0.out @@ -0,0 +1,140 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 121548526 Instructions: 100000002 IPC: 0.82272 + +L2WAY_FILL_L1 0 0 + +L2WAY_WAY_HIT 0 -nan% 0 -nan% +L2WAY_WAY_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_PREF_REQ 0 0 + +L2WAY_PREF_HIT_DATA_IN_CACHE 0 -nan% 0 -nan% +L2WAY_PREF_HIT_DATA_REQ 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_TRAIN_HIT 0 -nan% 0 -nan% +L2WAY_TRAIN_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L1_HIT_REQ_TYPE_IFETCH 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DFETCH 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DSTORE 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_IPRF 0 -nan% 0 -nan% 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0 -nan% 0 -nan% +DCACHE_PREF_FETCH_100 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_1000 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_10000 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_100000 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_1000000 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_10000000 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_100000000 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_MORE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_SAME_IP_DELTA__0 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__1 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__2 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__3 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__4 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__5 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__6 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__7 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__8 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_IP_HIT_COUNT__1 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__2 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__3 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__4 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__5 0 -nan% 0 -nan% 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100.000% + 0.00 0.00 0.00 0.00 + +ICACHE_HIT_ONPATH 39279756 100.000% 39279756 100.000% +ICACHE_HIT_OFFPATH 0 0.000% 0 0.000% + 39279756 100.000% 39279756 100.000% + 0.00 0.00 0.00 0.00 + +ICACHE_HIT_ONPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +ICACHE_HIT_ONPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ICACHE_HIT_OFFPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +ICACHE_HIT_OFFPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DCACHE_MISS 10100419 23.753% 10100419 23.753% +DCACHE_ST_BUFFER_HIT 111003 0.261% 111003 0.261% +DCACHE_HIT 32311246 75.986% 32311246 75.986% + 42522668 100.000% 42522668 100.000% + 1.52 1.39 1.52 1.39 + +DCACHE_MISS_COMPULSORY 345025 0.0342 345025 0.0342 + +DCACHE_MISS_CAPACITY 9754359 0.9657 9754359 0.9657 + +DCACHE_MISS_CONFLICT 1035 0.0001 1035 0.0001 + +DCACHE_MISS_ONPATH 10100419 100.000% 10100419 100.000% +DCACHE_MISS_OFFPATH 0 0.000% 0 0.000% + 10100419 100.000% 10100419 100.000% + 0.00 0.00 0.00 0.00 + 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0.000% 0 0.000% + 647331 100.000% 647331 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_MISS_WAITMEM 4000114 4000114 + +MEM_REQ_ROW_BUFFER_HITS 0 -nan% 0 -nan% +MEM_REQ_ROW_BUFFER_MISSES 0 -nan% 0 -nan% +MEM_REQ_ROW_BUFFER_CONFLICTS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +SHADOW_ROW_BUFFER_HITS 0 0 + +SHADOW_ROW_HIT_STALL_TIME 0 0 + +CHANNEL0_BUS_BUSY_CYCLES 0 -nan% 0 -nan% +CHANNEL1_BUS_BUSY_CYCLES 0 -nan% 0 -nan% +CHANNEL2_BUS_BUSY_CYCLES 0 -nan% 0 -nan% +CHANNEL3_BUS_BUSY_CYCLES 0 -nan% 0 -nan% +CHANNEL4_BUS_BUSY_CYCLES 0 -nan% 0 -nan% +CHANNEL5_BUS_BUSY_CYCLES 0 -nan% 0 -nan% +CHANNEL6_BUS_BUSY_CYCLES 0 -nan% 0 -nan% +CHANNEL7_BUS_BUSY_CYCLES 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CHANNEL_IDLE_DESPITE_READY_CMD 0 0 + +MEM_NUM_TOTAL_BUS_CYCLES 0 0 + +MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan + +CORE_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan + +CHANNEL0_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan% +CHANNEL1_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan% 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1140396314 333.3679 + +CORE_L1_MISS_LATENCY_DEMAND 395664274 239.0168 395664274 239.0168 + +CORE_L1_MISS_LATENCY_PREF 744732040 421.8367 744732040 421.8367 + +CORE_EVICTED_L1_DEMAND 1646979 48.376% 1646979 48.376% +CORE_EVICTED_L1_PREF_USED 1690026 49.640% 1690026 49.640% +CORE_EVICTED_L1_PREF_NOT_USED 67542 1.984% 67542 1.984% + 3404547 100.000% 3404547 100.000% + 0.54 0.39 0.54 0.39 + +CORE_EVICTED_MLC_DEMAND 0 -nan% 0 -nan% +CORE_EVICTED_MLC_PREF_USED 0 -nan% 0 -nan% +CORE_EVICTED_MLC_PREF_NOT_USED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CORE_MEM_LATENCY_AVE_DEMAND 393679901 239.0315 393679901 239.0315 + +CORE_MEM_LATENCY_AVE_PREF_USED 728869714 431.2772 728869714 431.2772 + +CORE_MEM_LATENCY_AVE_PREF_NOT_USED 12808085 189.6314 12808085 189.6314 + +DRAM_LATENCY 0 0 + +TOTAL_DRAM_LATENCY 0 0 + +DRAM_CLOSED_PAGE_POLICY_CMD 0 0 + +DRAM_ACTIVATE_STALLING 0 0 + +DRAM_PRECHARGE_STALLING 0 0 + +DRAM_PRECHARGE_STALLING_WAIT_CYCLES 0 0 + +L1_STAY_DEMAND 1019619365235 619084.6181 1019619365235 619084.6181 + +L1_STAY_PREF_USED 915727820373 541842.4452 915727820373 541842.4452 + +L1_STAY_PREF_NOT_USED 42476104934 628884.3229 42476104934 628884.3229 + +TOTAL_DATA_MISS_LATENCY 400926520 400926520 + +TOTAL_DATA_MISS_COUNT 1666817 1666817 + +CORE_PREF_L1_NOT_USED_LATENCY200 50284 74.448% 50284 74.448% +CORE_PREF_L1_NOT_USED_LATENCY400 10866 16.088% 10866 16.088% +CORE_PREF_L1_NOT_USED_LATENCY600 3417 5.059% 3417 5.059% +CORE_PREF_L1_NOT_USED_LATENCY800 1254 1.857% 1254 1.857% +CORE_PREF_L1_NOT_USED_LATENCY1000 554 0.820% 554 0.820% +CORE_PREF_L1_NOT_USED_LATENCY1200 487 0.721% 487 0.721% +CORE_PREF_L1_NOT_USED_LATENCY1400 369 0.546% 369 0.546% +CORE_PREF_L1_NOT_USED_LATENCY1600 204 0.302% 204 0.302% +CORE_PREF_L1_NOT_USED_LATENCY1600MORE 107 0.158% 107 0.158% + 67542 100.000% 67542 100.000% + 0.45 0.96 0.45 0.96 + +CORE_PREF_L1_NOT_USED_DISTANCE_1 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_DISTANCE_2 273 0.404% 273 0.404% +CORE_PREF_L1_NOT_USED_DISTANCE_4 1555 2.302% 1555 2.302% +CORE_PREF_L1_NOT_USED_DISTANCE_8 3177 4.704% 3177 4.704% +CORE_PREF_L1_NOT_USED_DISTANCE_16 5070 7.506% 5070 7.506% +CORE_PREF_L1_NOT_USED_DISTANCE_32 8855 13.110% 8855 13.110% +CORE_PREF_L1_NOT_USED_DISTANCE_MORE 48612 71.973% 48612 71.973% + 67542 100.000% 67542 100.000% + 5.47 4.75 5.47 4.75 + +CORE_PREF_L1_USED_LATENCY200 347162 20.542% 347162 20.542% +CORE_PREF_L1_USED_LATENCY400 536455 31.742% 536455 31.742% +CORE_PREF_L1_USED_LATENCY600 473174 27.998% 473174 27.998% +CORE_PREF_L1_USED_LATENCY800 208596 12.343% 208596 12.343% +CORE_PREF_L1_USED_LATENCY1000 62373 3.691% 62373 3.691% +CORE_PREF_L1_USED_LATENCY1200 16253 0.962% 16253 0.962% +CORE_PREF_L1_USED_LATENCY1400 9316 0.551% 9316 0.551% +CORE_PREF_L1_USED_LATENCY1600 11310 0.669% 11310 0.669% +CORE_PREF_L1_USED_LATENCY1600MORE 25387 1.502% 25387 1.502% + 1690026 100.000% 1690026 100.000% + 1.64 1.29 1.64 1.29 + +CORE_PREF_L1_USED_DISTANCE_1 0 0.000% 0 0.000% +CORE_PREF_L1_USED_DISTANCE_2 28 0.002% 28 0.002% +CORE_PREF_L1_USED_DISTANCE_4 1184 0.070% 1184 0.070% +CORE_PREF_L1_USED_DISTANCE_8 6071 0.359% 6071 0.359% +CORE_PREF_L1_USED_DISTANCE_16 22216 1.315% 22216 1.315% +CORE_PREF_L1_USED_DISTANCE_32 24072 1.424% 24072 1.424% +CORE_PREF_L1_USED_DISTANCE_MORE 1636455 96.830% 1636455 96.830% + 1690026 100.000% 1690026 100.000% + 5.95 5.86 5.95 5.86 + +CORE_PREF_L1_DEMAND_LATENCY300 1366472 82.968% 1366472 82.968% +CORE_PREF_L1_DEMAND_LATENCY400 125576 7.625% 125576 7.625% +CORE_PREF_L1_DEMAND_LATENCY500 55832 3.390% 55832 3.390% +CORE_PREF_L1_DEMAND_LATENCY600 24650 1.497% 24650 1.497% +CORE_PREF_L1_DEMAND_LATENCY700 15732 0.955% 15732 0.955% +CORE_PREF_L1_DEMAND_LATENCY800 14257 0.866% 14257 0.866% +CORE_PREF_L1_DEMAND_LATENCY900 10053 0.610% 10053 0.610% +CORE_PREF_L1_DEMAND_LATENCY1000 6697 0.407% 6697 0.407% +CORE_PREF_L1_DEMAND_LATENCY1000MORE 27710 1.682% 27710 1.682% + 1646979 100.000% 1646979 100.000% + 0.47 1.35 0.47 1.35 + +CORE_PREF_MLC_NOT_USED_LATENCY200 0 -nan% 0 -nan% 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2.518% +NUM_DCACHE_MISSES_IN_WINDOW_12 6352 2.516% 6352 2.516% +NUM_DCACHE_MISSES_IN_WINDOW_13 6863 2.718% 6863 2.718% +NUM_DCACHE_MISSES_IN_WINDOW_14 7562 2.995% 7562 2.995% +NUM_DCACHE_MISSES_IN_WINDOW_15 8279 3.279% 8279 3.279% +NUM_DCACHE_MISSES_IN_WINDOW_16_OR_MORE 142185 56.318% 142185 56.318% + 252470 100.000% 252470 100.000% + 11.33 9.68 11.33 9.68 + +DCACHE_MLP_IN_WINDOW_1_0 34713 13.749% 34713 13.749% +DCACHE_MLP_IN_WINDOW_1_5 14549 5.763% 14549 5.763% +DCACHE_MLP_IN_WINDOW_2_0 11794 4.671% 11794 4.671% +DCACHE_MLP_IN_WINDOW_2_5 7051 2.793% 7051 2.793% +DCACHE_MLP_IN_WINDOW_3_0 10337 4.094% 10337 4.094% +DCACHE_MLP_IN_WINDOW_3_5 16934 6.707% 16934 6.707% +DCACHE_MLP_IN_WINDOW_4_0 22952 9.091% 22952 9.091% +DCACHE_MLP_IN_WINDOW_4_5 26178 10.369% 26178 10.369% +DCACHE_MLP_IN_WINDOW_5_0 23487 9.303% 23487 9.303% +DCACHE_MLP_IN_WINDOW_5_5 24964 9.888% 24964 9.888% +DCACHE_MLP_IN_WINDOW_6_0 17722 7.019% 17722 7.019% +DCACHE_MLP_IN_WINDOW_6_5 14775 5.852% 14775 5.852% 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100.000% + 1.00 1.00 1.00 1.00 + + + diff --git a/labs/LAB5/runs/mcf_s_base-sms0/power.stat.0.out b/labs/LAB5/runs/mcf_s_base-sms0/power.stat.0.out new file mode 100644 index 00000000..587aca1b --- /dev/null +++ b/labs/LAB5/runs/mcf_s_base-sms0/power.stat.0.out @@ -0,0 +1,184 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 121548526 Instructions: 100000002 IPC: 0.82272 + +POWER_STATS_BEGIN 0 0 + +POWER_TIME 37983914375000 37983914375000 + +POWER_CYCLE 121548526 121548526 + +POWER_ITLB_ACCESS 39279820 39279820 + +POWER_DTLB_ACCESS 8245112 8245112 + +POWER_ICACHE_ACCESS 39279820 39279820 + +POWER_ICACHE_MISS 64 64 + +POWER_BTB_READ 39279820 39279820 + +POWER_BTB_WRITE 1174736 1174736 + +POWER_ROB_READ 119819881 119819881 + +POWER_ROB_WRITE 119819881 119819881 + +POWER_RENAME_READ 239639762 239639762 + +POWER_RENAME_WRITE 119819881 119819881 + +POWER_FP_RENAME_READ 0 0 + +POWER_FP_RENAME_WRITE 0 0 + +POWER_FUNCTION_CALL 2303267 2303267 + +POWER_INST_WINDOW_READ 119819881 119819881 + +POWER_INST_WINDOW_WRITE 119819881 119819881 + +POWER_INT_REGFILE_READ 134827876 134827876 + +POWER_INT_REGFILE_WRITE 91432930 91432930 + +POWER_IALU_ACCESS 119526796 119526796 + +POWER_CDB_IALU_ACCESS 119526796 119526796 + +POWER_MUL_ACCESS 293085 293085 + +POWER_CDB_MUL_ACCESS 293085 293085 + +POWER_FP_INST_WINDOW_WRITE 0 0 + +POWER_FP_INST_WINDOW_READ 0 0 + +POWER_FP_REGFILE_READ 0 0 + +POWER_FP_REGFILE_WRITE 0 0 + +POWER_FPU_ACCESS 0 0 + +POWER_CDB_FPU_ACCESS 0 0 + +POWER_DCACHE_READ_ACCESS 38252946 38252946 + +POWER_DCACHE_WRITE_ACCESS 8269836 8269836 + +POWER_DCACHE_READ_MISS 13539480 13539480 + +POWER_DCACHE_WRITE_MISS 672056 672056 + +POWER_MLC_READ_ACCESS 0 0 + +POWER_MLC_WRITE_ACCESS 0 0 + +POWER_MLC_READ_MISS 0 0 + +POWER_MLC_WRITE_MISS 0 0 + +POWER_LLC_READ_ACCESS 8416061 8416061 + +POWER_LLC_WRITE_ACCESS 341471 341471 + +POWER_LLC_READ_MISS 3420834 3420834 + +POWER_LLC_WRITE_MISS 97 97 + +POWER_MEMORY_ACCESS 0 0 + +POWER_MEMORY_READ_ACCESS 0 0 + +POWER_MEMORY_WRITE_ACCESS 0 0 + +POWER_INST_WINDOW_WAKEUP_ACCESS 119819881 119819881 + +POWER_FP_INST_WINDOW_WAKEUP_ACCESS 0 0 + +POWER_L1DIREC_READ_ACCESS 0 0 + +POWER_L1DIREC_WRITE_ACCESS 0 0 + +POWER_L1DIREC_READ_MISS 0 0 + +POWER_L1DIREC_WRITE_MISS 0 0 + +POWER_L2DIREC_READ_ACCESS 0 0 + +POWER_L2DIREC_WRITE_ACCESS 0 0 + +POWER_L2DIREC_READ_MISS 0 0 + +POWER_L2DIREC_WRITE_MISS 0 0 + +POWER_MEMORY_CTRL_ACCESS 3472281 3472281 + +POWER_MEMORY_CTRL_READ 3420834 3420834 + +POWER_MEMORY_CTRL_WRITE 51447 51447 + +POWER_OP 119819881 119819881 + +POWER_INT_OP 116076761 116076761 + +POWER_FP_OP 0 0 + +POWER_LD_OP 34277560 34277560 + +POWER_ST_OP 8245112 8245112 + +POWER_BRANCH_MISPREDICT 1174736 1174736 + +POWER_COMMITTED_OP 119819881 119819881 + +POWER_COMMITTED_INT_OP 116076761 116076761 + +POWER_COMMITTED_FP_OP 3743120 3743120 + +POWER_BRANCH_OP 25493101 25493101 + +POWER_DRAM_PRECHARGE 1599203 1599203 + +POWER_DRAM_ACTIVATE 1648806 1648806 + +POWER_DRAM_READ 3414039 3414039 + +POWER_DRAM_WRITE 51438 51438 + +POWER_STATS_END 0 0 + +ENERGY 0.000000 0.000000 + +ENERGY_CORE 0.000000 0.000000 + +ENERGY_UNCORE 0.000000 0.000000 + +ENERGY_MEMORY 0.000000 0.000000 + +ENERGY_OTHER 0.000000 0.000000 + +ENERGY_CORE_STATIC 0.000000 0.000000 + +ENERGY_CORE_DYNAMIC 0.000000 0.000000 + +ENERGY_UNCORE_STATIC 0.000000 0.000000 + +ENERGY_UNCORE_DYNAMIC 0.000000 0.000000 + +ENERGY_MEMORY_STATIC 0.000000 0.000000 + +ENERGY_MEMORY_DYNAMIC 0.000000 0.000000 + +ENERGY_OTHER_STATIC 0.000000 0.000000 + +ENERGY_OTHER_DYNAMIC 0.000000 0.000000 + +TIME 0.000000 0.000000 + +ENERGY_STATS_END 0 0 + + + diff --git a/labs/LAB5/runs/mcf_s_base-sms0/pref.stat.0.out b/labs/LAB5/runs/mcf_s_base-sms0/pref.stat.0.out new file mode 100644 index 00000000..9aada6c8 --- /dev/null +++ b/labs/LAB5/runs/mcf_s_base-sms0/pref.stat.0.out @@ -0,0 +1,208 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 121548526 Instructions: 100000002 IPC: 0.82272 + +PREF_DL0REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UMLC_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UL1REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_DL0REQ_QUEUE_FULL 0 0 + +PREF_UMLC_REQ_QUEUE_FULL 0 0 + +PREF_UL1REQ_QUEUE_FULL 50 50 + +PREF_DC_HIT_NOSEND 0 0 + +PREF_WBQDC_HIT_NOSEND 0 0 + +PREF_MLCQ_STALL 0 0 + +PREF_L1Q_STALL 0 0 + +PREF_UMLC_REQ_SEND_QUEUE_STALL 0 0 + +PREF_UL1REQ_SEND_QUEUE_STALL 14465999 14465999 + +PREF_UMLC_REQ_QUEUE_SENTREQ 0 0 + +PREF_UL1REQ_QUEUE_SENTREQ 2717464 2717464 + +PREF_NEWREQ_MATCHED 2917 2917 + +PREF_UMLC_REQ_QUEUE_MATCHED_REQ 0 0 + +PREF_UL1REQ_QUEUE_MATCHED_REQ 42622 42622 + +PREF_DL0REQ_QUEUE_MATCHED_REQ 0 0 + +L1_PREF_HIT 2384115 2384115 + +L1_PREF_UNIQUE_HIT 1686061 1686061 + +L1_PREF_LATE 14073 14073 + +L1_LATE_PREF_CYCLES 3976402 3976402 + +L1_LATE_PREF_CYCLES_DIST_0 4615 32.793% 4615 32.793% +L1_LATE_PREF_CYCLES_DIST_100 2056 14.610% 2056 14.610% +L1_LATE_PREF_CYCLES_DIST_200 1536 10.915% 1536 10.915% +L1_LATE_PREF_CYCLES_DIST_300 1925 13.679% 1925 13.679% +L1_LATE_PREF_CYCLES_DIST_400 1776 12.620% 1776 12.620% +L1_LATE_PREF_CYCLES_DIST_500 853 6.061% 853 6.061% +L1_LATE_PREF_CYCLES_DIST_600 407 2.892% 407 2.892% +L1_LATE_PREF_CYCLES_DIST_700 261 1.855% 261 1.855% +L1_LATE_PREF_CYCLES_DIST_800 172 1.222% 172 1.222% +L1_LATE_PREF_CYCLES_DIST_900 115 0.817% 115 0.817% +L1_LATE_PREF_CYCLES_DIST_1000 76 0.540% 76 0.540% +L1_LATE_PREF_CYCLES_DIST_1100 33 0.234% 33 0.234% +L1_LATE_PREF_CYCLES_DIST_1200 23 0.163% 23 0.163% +L1_LATE_PREF_CYCLES_DIST_1300 16 0.114% 16 0.114% +L1_LATE_PREF_CYCLES_DIST_1400 27 0.192% 27 0.192% +L1_LATE_PREF_CYCLES_DIST_1500 52 0.370% 52 0.370% +L1_LATE_PREF_CYCLES_DIST_1600 61 0.433% 61 0.433% +L1_LATE_PREF_CYCLES_DIST_1700 42 0.298% 42 0.298% +L1_LATE_PREF_CYCLES_DIST_1800 22 0.156% 22 0.156% +L1_LATE_PREF_CYCLES_DIST_1900 2 0.014% 2 0.014% +L1_LATE_PREF_CYCLES_DIST_2000 3 0.021% 3 0.021% + 14073 100.000% 14073 100.000% + 2.41 2.47 2.41 2.47 + +MLC_PREF_HIT 0 0 + +MLC_PREF_UNIQUE_HIT 0 0 + +MLC_PREF_LATE 0 0 + +PREF_HYBRID_SEL_0 0 -nan% 0 -nan% +PREF_HYBRID_SEL_1 0 -nan% 0 -nan% +PREF_HYBRID_SEL_2 0 -nan% 0 -nan% +PREF_HYBRID_SEL_3 0 -nan% 0 -nan% +PREF_HYBRID_SEL_4 0 -nan% 0 -nan% +PREF_HYBRID_SEL_5 0 -nan% 0 -nan% +PREF_HYBRID_SEL_6 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_DISTANCE_1 0 0.000% 0 0.000% +PREF_DISTANCE_2 0 0.000% 0 0.000% +PREF_DISTANCE_3 0 0.000% 0 0.000% +PREF_DISTANCE_4 1 0.241% 1 0.241% +PREF_DISTANCE_5 414 99.759% 414 99.759% +PREF_DISTANCE_6 0 0.000% 0 0.000% +PREF_DISTANCE_7 0 0.000% 0 0.000% +PREF_DISTANCE_8 0 0.000% 0 0.000% +PREF_DISTANCE_9 0 0.000% 0 0.000% +PREF_DISTANCE_10 0 0.000% 0 0.000% + 415 100.000% 415 100.000% + 4.00 0.05 4.00 0.05 + +PREF_REPL_MRU 0 -nan% 0 -nan% +PREF_REPL_MID 0 -nan% 0 -nan% +PREF_REPL_LOWQTR 0 -nan% 0 -nan% +PREF_REPL_LRU 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_REPL_MOVEDOWN 0 -nan% 0 -nan% +PREF_REPL_MOVEUP 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_COV_1 0 -nan% 0 -nan% +PREF_COV_2 0 -nan% 0 -nan% +PREF_COV_3 0 -nan% 0 -nan% +PREF_COV_4 0 -nan% 0 -nan% +PREF_COV_5 0 -nan% 0 -nan% +PREF_COV_6 0 -nan% 0 -nan% +PREF_COV_7 0 -nan% 0 -nan% +PREF_COV_8 0 -nan% 0 -nan% +PREF_COV_9 0 -nan% 0 -nan% +PREF_COV_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_POL_1 0 0.000% 0 0.000% +PREF_POL_2 0 0.000% 0 0.000% +PREF_POL_3 0 0.000% 0 0.000% +PREF_POL_4 0 0.000% 0 0.000% +PREF_POL_5 0 0.000% 0 0.000% +PREF_POL_6 0 0.000% 0 0.000% +PREF_POL_7 0 0.000% 0 0.000% +PREF_POL_8 0 0.000% 0 0.000% +PREF_POL_9 0 0.000% 0 0.000% +PREF_POL_10 415 100.000% 415 100.000% + 415 100.000% 415 100.000% + 9.00 9.01 9.00 9.01 + +PREF_ACC_1 415 100.000% 415 100.000% +PREF_ACC_2 0 0.000% 0 0.000% +PREF_ACC_3 0 0.000% 0 0.000% +PREF_ACC_4 0 0.000% 0 0.000% +PREF_ACC_5 0 0.000% 0 0.000% +PREF_ACC_6 0 0.000% 0 0.000% +PREF_ACC_7 0 0.000% 0 0.000% +PREF_ACC_8 0 0.000% 0 0.000% +PREF_ACC_9 0 0.000% 0 0.000% +PREF_ACC_10 0 0.000% 0 0.000% + 415 100.000% 415 100.000% + 0.00 0.00 0.00 0.00 + +PREF_TIMELY_1 0 0.000% 0 0.000% +PREF_TIMELY_2 0 0.000% 0 0.000% +PREF_TIMELY_3 0 0.000% 0 0.000% +PREF_TIMELY_4 0 0.000% 0 0.000% +PREF_TIMELY_5 0 0.000% 0 0.000% +PREF_TIMELY_6 0 0.000% 0 0.000% +PREF_TIMELY_7 1 0.241% 1 0.241% +PREF_TIMELY_8 0 0.000% 0 0.000% +PREF_TIMELY_9 2 0.482% 2 0.482% +PREF_TIMELY_10 412 99.277% 412 99.277% + 415 100.000% 415 100.000% + 8.99 8.97 8.99 8.97 + +PREF_UNUSED_EVICT 67542 67542 + +PREF_REGION_SENT 0 0 + +PREF_REGION_USEFUL 0 0 + +PREF_REGION_EVICT 0 0 + +PREF_PFPOL 0 0 + +PREF_PHASE_NEWPHASE_DET 0 0 + +PREF_PHASE_NEWPHASE_NOTVALID 0 0 + +PREF_PHASE_SENTPREF 0 0 + +PREF_PHASE_OVERWRITE_PAGE 0 0 + +PREF_UPDATE_COUNT 415 415 + +PREF_ACC1_HT_HP 0 0.000% 0 0.000% +PREF_ACC1_HT_LP 386 93.012% 386 93.012% +PREF_ACC1_LT_HP 0 0.000% 0 0.000% +PREF_ACC1_LT_LP 29 6.988% 29 6.988% +PREF_ACC2_HT_HP 0 0.000% 0 0.000% +PREF_ACC2_HT_LP 0 0.000% 0 0.000% +PREF_ACC2_LT_HP 0 0.000% 0 0.000% +PREF_ACC2_LT_LP 0 0.000% 0 0.000% +PREF_ACC3_HT_HP 0 0.000% 0 0.000% +PREF_ACC3_HT_LP 0 0.000% 0 0.000% +PREF_ACC3_LT_HP 0 0.000% 0 0.000% +PREF_ACC3_LT_LP 0 0.000% 0 0.000% +PREF_ACC4_HT_HP 0 0.000% 0 0.000% +PREF_ACC4_HT_LP 0 0.000% 0 0.000% +PREF_ACC4_LT_HP 0 0.000% 0 0.000% +PREF_ACC4_LT_LP 0 0.000% 0 0.000% + 415 100.000% 415 100.000% + 1.14 0.51 1.14 0.51 + + + diff --git a/labs/LAB5/runs/mcf_s_base-sms0/ramulator.stat.out b/labs/LAB5/runs/mcf_s_base-sms0/ramulator.stat.out new file mode 100644 index 00000000..d2b163b9 --- /dev/null +++ b/labs/LAB5/runs/mcf_s_base-sms0/ramulator.stat.out @@ -0,0 +1,150 @@ + ramulator.active_cycles_0 27626317 # Total active cycles for level _0 + ramulator.busy_cycles_0 27626317 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0 + ramulator.serving_requests_0 139172482 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.average_serving_requests_0 3.053319 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.active_cycles_0_0 27626317 # Total active cycles for level _0_0 + ramulator.busy_cycles_0_0 28806517 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0 + ramulator.serving_requests_0_0 139172482 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.average_serving_requests_0_0 3.053319 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.active_cycles_0_0_0 17432583 # Total active cycles for level _0_0_0 + ramulator.busy_cycles_0_0_0 17432583 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0 + ramulator.serving_requests_0_0_0 34413933 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 +ramulator.average_serving_requests_0_0_0 0.755011 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 + ramulator.active_cycles_0_0_0_0 6323105 # Total active cycles for level _0_0_0_0 + ramulator.busy_cycles_0_0_0_0 6323105 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_0 + ramulator.serving_requests_0_0_0_0 7943624 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 +ramulator.average_serving_requests_0_0_0_0 0.174276 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 + ramulator.active_cycles_0_0_0_1 6554340 # Total active cycles for level _0_0_0_1 + ramulator.busy_cycles_0_0_0_1 6554340 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_1 + ramulator.serving_requests_0_0_0_1 8057398 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 +ramulator.average_serving_requests_0_0_0_1 0.176772 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 + ramulator.active_cycles_0_0_0_2 6792577 # Total active cycles for level _0_0_0_2 + ramulator.busy_cycles_0_0_0_2 6792577 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_2 + ramulator.serving_requests_0_0_0_2 8481635 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 +ramulator.average_serving_requests_0_0_0_2 0.186079 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 + ramulator.active_cycles_0_0_0_3 8165919 # Total active cycles for level _0_0_0_3 + ramulator.busy_cycles_0_0_0_3 8165919 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_3 + ramulator.serving_requests_0_0_0_3 9931276 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 +ramulator.average_serving_requests_0_0_0_3 0.217883 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 + ramulator.active_cycles_0_0_1 17776100 # Total active cycles for level _0_0_1 + ramulator.busy_cycles_0_0_1 17776100 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1 + ramulator.serving_requests_0_0_1 34567844 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 +ramulator.average_serving_requests_0_0_1 0.758387 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 + ramulator.active_cycles_0_0_1_0 5538143 # Total active cycles for level _0_0_1_0 + ramulator.busy_cycles_0_0_1_0 5538143 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_0 + ramulator.serving_requests_0_0_1_0 7051891 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 +ramulator.average_serving_requests_0_0_1_0 0.154712 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 + ramulator.active_cycles_0_0_1_1 5639646 # Total active cycles for level _0_0_1_1 + ramulator.busy_cycles_0_0_1_1 5639646 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_1 + ramulator.serving_requests_0_0_1_1 7173187 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 +ramulator.average_serving_requests_0_0_1_1 0.157373 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 + ramulator.active_cycles_0_0_1_2 9160823 # Total active cycles for level _0_0_1_2 + ramulator.busy_cycles_0_0_1_2 9160823 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_2 + ramulator.serving_requests_0_0_1_2 11002576 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 +ramulator.average_serving_requests_0_0_1_2 0.241387 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 + ramulator.active_cycles_0_0_1_3 7561416 # Total active cycles for level _0_0_1_3 + ramulator.busy_cycles_0_0_1_3 7561416 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_3 + ramulator.serving_requests_0_0_1_3 9340190 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 +ramulator.average_serving_requests_0_0_1_3 0.204915 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 + ramulator.active_cycles_0_0_2 17293990 # Total active cycles for level _0_0_2 + ramulator.busy_cycles_0_0_2 17293990 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2 + ramulator.serving_requests_0_0_2 34334760 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 +ramulator.average_serving_requests_0_0_2 0.753274 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 + ramulator.active_cycles_0_0_2_0 7206363 # Total active cycles for level _0_0_2_0 + ramulator.busy_cycles_0_0_2_0 7206363 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_0 + ramulator.serving_requests_0_0_2_0 8962446 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 +ramulator.average_serving_requests_0_0_2_0 0.196628 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 + ramulator.active_cycles_0_0_2_1 7262459 # Total active cycles for level _0_0_2_1 + ramulator.busy_cycles_0_0_2_1 7262459 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_1 + ramulator.serving_requests_0_0_2_1 8868277 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 +ramulator.average_serving_requests_0_0_2_1 0.194562 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 + ramulator.active_cycles_0_0_2_2 6426184 # Total active cycles for level _0_0_2_2 + ramulator.busy_cycles_0_0_2_2 6426184 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_2 + ramulator.serving_requests_0_0_2_2 8011149 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 +ramulator.average_serving_requests_0_0_2_2 0.175757 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 + ramulator.active_cycles_0_0_2_3 6869315 # Total active cycles for level _0_0_2_3 + ramulator.busy_cycles_0_0_2_3 6869315 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_3 + ramulator.serving_requests_0_0_2_3 8492888 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 +ramulator.average_serving_requests_0_0_2_3 0.186326 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 + ramulator.active_cycles_0_0_3 17609202 # Total active cycles for level _0_0_3 + ramulator.busy_cycles_0_0_3 17609202 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3 + ramulator.serving_requests_0_0_3 35855945 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 +ramulator.average_serving_requests_0_0_3 0.786647 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 + ramulator.active_cycles_0_0_3_0 6699419 # Total active cycles for level _0_0_3_0 + ramulator.busy_cycles_0_0_3_0 6699419 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_0 + ramulator.serving_requests_0_0_3_0 8231766 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 +ramulator.average_serving_requests_0_0_3_0 0.180598 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 + ramulator.active_cycles_0_0_3_1 8116353 # Total active cycles for level _0_0_3_1 + ramulator.busy_cycles_0_0_3_1 8116353 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_1 + ramulator.serving_requests_0_0_3_1 9841922 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 +ramulator.average_serving_requests_0_0_3_1 0.215923 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 + ramulator.active_cycles_0_0_3_2 7558016 # Total active cycles for level _0_0_3_2 + ramulator.busy_cycles_0_0_3_2 7558016 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_2 + ramulator.serving_requests_0_0_3_2 9177831 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 +ramulator.average_serving_requests_0_0_3_2 0.201353 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 + ramulator.active_cycles_0_0_3_3 6997065 # Total active cycles for level _0_0_3_3 + ramulator.busy_cycles_0_0_3_3 6997065 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_3 + ramulator.serving_requests_0_0_3_3 8604426 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 +ramulator.average_serving_requests_0_0_3_3 0.188773 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 + ramulator.read_transaction_bytes_0 218498496 # The total byte of read transaction per channel + ramulator.write_transaction_bytes_0 3292032 # The total byte of write transaction per channel + ramulator.row_hits_channel_0_core 1816811 # Number of row hits per channel per core + ramulator.row_misses_channel_0_core 126297 # Number of row misses per channel per core + ramulator.row_conflicts_channel_0_core 1522369 # Number of row conflicts per channel per core + ramulator.read_row_hits_channel_0_core 1784357 # Number of row hits for read requests per channel per core + [0] 1784357.0 # +ramulator.read_row_misses_channel_0_core 124616 # Number of row misses for read requests per channel per core + [0] 124616.0 # +ramulator.read_row_conflicts_channel_0_core 1505066 # Number of row conflicts for read requests per channel per core + [0] 1505066.0 # + ramulator.write_row_hits_channel_0_core 32454 # Number of row hits for write requests per channel per core + [0] 32454.0 # +ramulator.write_row_misses_channel_0_core 1681 # Number of row misses for write requests per channel per core + [0] 1681.0 # +ramulator.write_row_conflicts_channel_0_core 17303 # Number of row conflicts for write requests per channel per core + [0] 17303.0 # + ramulator.useless_activates_0_core 147 # Number of useless activations. E.g, ACT -> PRE w/o RD or WR + ramulator.read_latency_avg_0 125.298980 # The average memory latency cycles (in memory time domain) per request for all read requests in this channel + ramulator.read_latency_sum_0 428627012 # The memory latency cycles (in memory time domain) sum for all read requests in this channel + ramulator.req_queue_length_avg_0 23.681642 # Average of read and write queue length per memory cycle per channel. + ramulator.req_queue_length_sum_0 1079426196 # Sum of read and write queue length per memory cycle per channel. + ramulator.read_req_queue_length_avg_0 8.801184 # Read queue length average per memory cycle per channel. + ramulator.read_req_queue_length_sum_0 401164260 # Read queue length sum per memory cycle per channel. + ramulator.write_req_queue_length_avg_0 14.880458 # Write queue length average per memory cycle per channel. + ramulator.write_req_queue_length_sum_0 678261936 # Write queue length sum per memory cycle per channel. + ramulator.record_read_hits 0.0 # record read hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_misses 0.0 # record_read_miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_conflicts 0.0 # record read conflict count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_hits 0.0 # record write hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_misses 0.0 # record write miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_conflicts 0.0 # record write conflict for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.dram_capacity 8589934592 # Number of bytes in simulated DRAM + ramulator.dram_cycles 45580715 # Number of DRAM cycles simulated + ramulator.incoming_requests 3472281 # Number of incoming requests to DRAM + ramulator.read_requests 3420834 # Number of incoming read requests to DRAM per core + [0] 3420834.0 # + ramulator.write_requests 51447 # Number of incoming write requests to DRAM per core + [0] 51447.0 # + ramulator.ramulator_active_cycles 27626317 # The total number of cycles that the DRAM part is active (serving R/W) + ramulator.incoming_requests_per_channel 3472281.0 # Number of incoming requests to each DRAM channel + [0] 3472281.0 # +ramulator.incoming_read_reqs_per_channel 3420834.0 # Number of incoming read requests to each DRAM channel + [0] 3420834.0 # + ramulator.physical_page_replacement 0 # The number of times that physical page replacement happens. + ramulator.maximum_bandwidth 19200000000 # The theoretical maximum bandwidth (Bps) + ramulator.in_queue_req_num_sum 1079426196 # Sum of read/write queue length + ramulator.in_queue_read_req_num_sum 401164260 # Sum of read queue length + ramulator.in_queue_write_req_num_sum 678261936 # Sum of write queue length + ramulator.in_queue_req_num_avg 23.681642 # Average of read/write queue length per memory cycle + ramulator.in_queue_read_req_num_avg 8.801184 # Average of read queue length per memory cycle + ramulator.in_queue_write_req_num_avg 14.880458 # Average of write queue length per memory cycle + ramulator.record_read_requests 0.0 # record read requests for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_requests 0.0 # record write requests for this core when it reaches request limit or to the end + [0] 0.0 # diff --git a/labs/LAB5/runs/mcf_s_base-sms0/run.err b/labs/LAB5/runs/mcf_s_base-sms0/run.err new file mode 100644 index 00000000..e69de29b diff --git a/labs/LAB5/runs/mcf_s_base-sms0/run.out b/labs/LAB5/runs/mcf_s_base-sms0/run.out new file mode 100644 index 00000000..12712c6b --- /dev/null +++ b/labs/LAB5/runs/mcf_s_base-sms0/run.out @@ -0,0 +1,107 @@ +Scarab gitrev: 7ab9e17 +Scarab started at Sun Jun 11 08:08:38 2023 + +Initialized Ramulator. +** Heartbeat: 1% -- { 1000003 } -- 0.00 KIPS (333.33 KIPS) +** Heartbeat: 2% -- { 2000007 } -- 333.33 KIPS (333.33 KIPS) +** Heartbeat: 3% -- { 3000007 } -- 333.33 KIPS (333.33 KIPS) +** Heartbeat: 4% -- { 4000009 } -- 500.00 KIPS (363.64 KIPS) +** Heartbeat: 5% -- { 5000012 } -- 333.33 KIPS (357.14 KIPS) +** Heartbeat: 6% -- { 6000014 } -- 333.33 KIPS (352.94 KIPS) +** Heartbeat: 7% -- { 7000015 } -- 500.00 KIPS (368.42 KIPS) +** Heartbeat: 8% -- { 8000018 } -- 333.33 KIPS (363.64 KIPS) +** Heartbeat: 9% -- { 9000018 } -- 333.33 KIPS (360.00 KIPS) +** Heartbeat: 10% -- { 10000022 } -- 500.00 KIPS (370.37 KIPS) +** Heartbeat: 11% -- { 11000023 } -- 333.33 KIPS (366.67 KIPS) +** Heartbeat: 12% -- { 12000023 } -- 333.33 KIPS (363.64 KIPS) +** Heartbeat: 13% -- { 13000023 } -- 333.33 KIPS (361.11 KIPS) +** Heartbeat: 14% -- { 14000025 } -- 500.00 KIPS (368.42 KIPS) +** Heartbeat: 15% -- { 15000025 } -- 333.33 KIPS (365.85 KIPS) +** Heartbeat: 16% -- { 16000027 } -- 333.33 KIPS (363.64 KIPS) +** Heartbeat: 17% -- { 17000027 } -- 500.00 KIPS (369.57 KIPS) +** Heartbeat: 18% -- { 18000028 } -- 333.33 KIPS (367.35 KIPS) +** Heartbeat: 19% -- { 19000031 } -- 500.00 KIPS (372.55 KIPS) +** Heartbeat: 20% -- { 20000032 } -- 333.33 KIPS (370.37 KIPS) +** Heartbeat: 21% -- { 21000037 } -- 333.33 KIPS (368.42 KIPS) +** Heartbeat: 22% -- { 22000040 } -- 333.33 KIPS (366.67 KIPS) +** Heartbeat: 23% -- { 23000041 } -- 500.00 KIPS (370.97 KIPS) +** Heartbeat: 24% -- { 24000041 } -- 333.33 KIPS (369.23 KIPS) +** Heartbeat: 25% -- { 25000042 } -- 333.33 KIPS (367.65 KIPS) +** Heartbeat: 26% -- { 26000042 } -- 500.00 KIPS (371.43 KIPS) +** Heartbeat: 27% -- { 27000047 } -- 333.33 KIPS (369.86 KIPS) +** Heartbeat: 28% -- { 28000047 } -- 333.33 KIPS (368.42 KIPS) +** Heartbeat: 29% -- { 29000049 } -- 333.33 KIPS (367.09 KIPS) +** Heartbeat: 30% -- { 30000049 } -- 500.00 KIPS (370.37 KIPS) +** Heartbeat: 31% -- { 31000053 } -- 333.33 KIPS (369.05 KIPS) +** Heartbeat: 32% -- { 32000055 } -- 333.33 KIPS (367.82 KIPS) +** Heartbeat: 33% -- { 33000055 } -- 333.33 KIPS (366.67 KIPS) +** Heartbeat: 34% -- { 34000057 } -- 500.00 KIPS (369.57 KIPS) +** Heartbeat: 35% -- { 35000061 } -- 333.33 KIPS (368.42 KIPS) +** Heartbeat: 36% -- { 36000063 } -- 500.00 KIPS (371.13 KIPS) +** Heartbeat: 37% -- { 37000066 } -- 333.33 KIPS (370.00 KIPS) +** Heartbeat: 38% -- { 38000069 } -- 333.33 KIPS (368.93 KIPS) +** Heartbeat: 39% -- { 39000074 } -- 500.00 KIPS (371.43 KIPS) +** Heartbeat: 40% -- { 40000076 } -- 333.33 KIPS (370.37 KIPS) +** Heartbeat: 41% -- { 41000079 } -- 333.33 KIPS (369.37 KIPS) +** Heartbeat: 42% -- { 42000081 } -- 333.33 KIPS (368.42 KIPS) +** Heartbeat: 43% -- { 43000084 } -- 500.00 KIPS (370.69 KIPS) +** Heartbeat: 44% -- { 44000086 } -- 333.33 KIPS (369.75 KIPS) +** Heartbeat: 45% -- { 45000087 } -- 333.33 KIPS (368.85 KIPS) +** Heartbeat: 46% -- { 46000087 } -- 500.00 KIPS (370.97 KIPS) +** Heartbeat: 47% -- { 47000088 } -- 333.33 KIPS (370.08 KIPS) +** Heartbeat: 48% -- { 48000090 } -- 333.33 KIPS (369.23 KIPS) +** Heartbeat: 49% -- { 49000090 } -- 333.33 KIPS (368.42 KIPS) +** Heartbeat: 50% -- { 50000091 } -- 500.00 KIPS (370.37 KIPS) +** Heartbeat: 51% -- { 51000094 } -- 333.33 KIPS (369.57 KIPS) +** Heartbeat: 52% -- { 52000099 } -- 333.33 KIPS (368.80 KIPS) +** Heartbeat: 53% -- { 53000099 } -- 500.00 KIPS (370.63 KIPS) +** Heartbeat: 54% -- { 54000102 } -- 333.33 KIPS (369.86 KIPS) +** Heartbeat: 55% -- { 55000102 } -- 500.00 KIPS (371.62 KIPS) +** Heartbeat: 56% -- { 56000105 } -- 333.33 KIPS (370.86 KIPS) +** Heartbeat: 57% -- { 57000107 } -- 333.33 KIPS (370.13 KIPS) +** Heartbeat: 58% -- { 58000109 } -- 333.33 KIPS (369.43 KIPS) +** Heartbeat: 59% -- { 59000111 } -- 500.00 KIPS (371.07 KIPS) +** Heartbeat: 60% -- { 60000111 } -- 333.33 KIPS (370.37 KIPS) +** Heartbeat: 61% -- { 61000112 } -- 333.33 KIPS (369.70 KIPS) +** Heartbeat: 62% -- { 62000112 } -- 500.00 KIPS (371.26 KIPS) +** Heartbeat: 63% -- { 63000112 } -- 333.33 KIPS (370.59 KIPS) +** Heartbeat: 64% -- { 64000113 } -- 333.33 KIPS (369.94 KIPS) +** Heartbeat: 65% -- { 65000113 } -- 333.33 KIPS (369.32 KIPS) +** Heartbeat: 66% -- { 66000114 } -- 500.00 KIPS (370.79 KIPS) +** Heartbeat: 67% -- { 67000114 } -- 333.33 KIPS (370.17 KIPS) +** Heartbeat: 68% -- { 68000117 } -- 333.33 KIPS (369.57 KIPS) +** Heartbeat: 69% -- { 69000117 } -- 500.00 KIPS (370.97 KIPS) +** Heartbeat: 70% -- { 70000120 } -- 333.33 KIPS (370.37 KIPS) +** Heartbeat: 71% -- { 71000120 } -- 333.33 KIPS (369.79 KIPS) +** Heartbeat: 72% -- { 72000124 } -- 500.00 KIPS (371.13 KIPS) +** Heartbeat: 73% -- { 73000127 } -- 333.33 KIPS (370.56 KIPS) +** Heartbeat: 74% -- { 74000131 } -- 333.33 KIPS (370.00 KIPS) +** Heartbeat: 75% -- { 75000135 } -- 500.00 KIPS (371.29 KIPS) +** Heartbeat: 76% -- { 76000139 } -- 333.33 KIPS (370.73 KIPS) +** Heartbeat: 77% -- { 77000142 } -- 500.00 KIPS (371.98 KIPS) +** Heartbeat: 78% -- { 78000142 } -- 333.33 KIPS (371.43 KIPS) +** Heartbeat: 79% -- { 79000142 } -- 333.33 KIPS (370.89 KIPS) +** Heartbeat: 80% -- { 80000143 } -- 500.00 KIPS (372.09 KIPS) +** Heartbeat: 81% -- { 81000143 } -- 333.33 KIPS (371.56 KIPS) +** Heartbeat: 82% -- { 82000145 } -- 333.33 KIPS (371.04 KIPS) +** Heartbeat: 83% -- { 83000148 } -- 333.33 KIPS (370.54 KIPS) +** Heartbeat: 84% -- { 84000148 } -- 500.00 KIPS (371.68 KIPS) +** Heartbeat: 85% -- { 85000148 } -- 333.33 KIPS (371.18 KIPS) +** Heartbeat: 86% -- { 86000148 } -- 333.33 KIPS (370.69 KIPS) +** Heartbeat: 87% -- { 87000148 } -- 500.00 KIPS (371.80 KIPS) +** Heartbeat: 88% -- { 88000153 } -- 333.33 KIPS (371.31 KIPS) +** Heartbeat: 89% -- { 89000153 } -- 500.00 KIPS (372.39 KIPS) +** Heartbeat: 90% -- { 90000157 } -- 333.33 KIPS (371.90 KIPS) +** Heartbeat: 91% -- { 91000160 } -- 333.33 KIPS (371.43 KIPS) +** Heartbeat: 92% -- { 92000163 } -- 500.00 KIPS (372.47 KIPS) +** Heartbeat: 93% -- { 93000163 } -- 333.33 KIPS (372.00 KIPS) +** Heartbeat: 94% -- { 94000164 } -- 333.33 KIPS (371.54 KIPS) +** Heartbeat: 95% -- { 95000169 } -- 500.00 KIPS (372.55 KIPS) +** Heartbeat: 96% -- { 96000170 } -- 333.33 KIPS (372.09 KIPS) +** Heartbeat: 97% -- { 97000172 } -- 500.00 KIPS (373.08 KIPS) +** Heartbeat: 98% -- { 98000172 } -- 333.33 KIPS (372.62 KIPS) +** Heartbeat: 99% -- { 99000172 } -- 333.33 KIPS (372.18 KIPS) +** Core 0 Finished: insts:100000002 cycles:121548526 time:37983914375000 -- 0.82 IPC (0.82 IPC) -- N/A KIPS (373.13 KIPS) +done +Scarab finished at Sun Jun 11 08:13:06 2023 + diff --git a/labs/LAB5/runs/mcf_s_base-sms0/stream.stat.0.out b/labs/LAB5/runs/mcf_s_base-sms0/stream.stat.0.out new file mode 100644 index 00000000..3d155486 --- /dev/null +++ b/labs/LAB5/runs/mcf_s_base-sms0/stream.stat.0.out @@ -0,0 +1,188 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 121548526 Instructions: 100000002 IPC: 0.82272 + +DCACHE_PREF_HIT 0 0 + +IFETCH_WB_FIRST_SCHEDULE 0 -nan% 0 -nan% +PREFETCH_LAST_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_PREF_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_LOW_OP_SCHEDULE 0 -nan% 0 -nan% +DEMAND_LAST_SCHEDULE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +SEND_MISS_REQ_QUEUE 3420834 3420834 + +L1_DATA_EVICT 3404547 3404547 + +STREAM_BUFFER_REQ 0 0 + +PREF_SEND_TO_MEM_REQ 0 -nan% 0 -nan% +PREF_SEND_TO_MEM_REQ_FAIL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +HIT_TRAIN_STREAM 1830382 52.025% 1830382 52.025% +MISS_TRAIN_STREAM 1687900 47.975% 1687900 47.975% + 3518282 100.000% 3518282 100.000% + 0.48 0.49 0.48 0.49 + +STREAM_TRAIN_CREATE 1632003 1632003 + +MEM_REQ_MISS_HWP_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_SW_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_IFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DSTORE_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DPRF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_WB_Q 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_BY_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_WB 0 -nan% 0 -nan% +PREF_HIT_BY_PREF 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_WB 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_L1_FILL 0 -nan% 0 -nan% +DEMAND_L1_FILL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TOUCH_L1_REPLACE 0 0.000% 0 0.000% +NO_TOUCH_L1_REPLACE 3404547 100.000% 3404547 100.000% + 3404547 100.000% 3404547 100.000% + 1.00 1.00 1.00 1.00 + +PREF_REQ_QUE_FULL 0 0 + +STREAM_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +L2HIT_STREAM_PREF_REQ_QUE_FULL 0 0 + +L2HIT_HIT_TRAIN_STREAM 0 -nan% 0 -nan% +L2HIT_MISS_TRAIN_STREAM 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_TRAIN_CREATE 0 0 + +L2HIT_STREAM_BUFFER_REQ 0 0 + +L2HIT_STREAM_PREF_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_STREAM_PREF_DCACHE_INSERT 0 -nan% 0 -nan% +L2HIT_STREAM_L2_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_DCACHE_PORT_FULL 0 0 + +L2HIT_STREAM_PREF_L1_PORT_FULL 0 0 + +L2HIT_TRAIN_HIT_DEMAND 0 -nan% 0 -nan% +L2HIT_TRAIN_MISS_REQ 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_TRAIN_FILTER_MISS 0 -nan% 0 -nan% +L2HIT_TRAIN_FILTER_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_PREF_REQ_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_PREF_REQ_DCACHE_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_L2SEND_Q_FULL 0 -nan% 0 -nan% +L2HIT_L2SEND_Q_ENTER 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_MEM_REQ 0 0 + +REMOVE_REDUNDANT_STREAM_STAT 0 0 + +REPLACE_OLD_STREAM 1631987 1631987 + +REQ_SEND_QUEUE_STALL 0 0 + +STREAM_ENTER_RA 0 0 + +CORE_STREAM_LENGTH_0 285 4.227% 285 4.227% +CORE_STREAM_LENGTH_10 1060 15.722% 1060 15.722% +CORE_STREAM_LENGTH_20 589 8.736% 589 8.736% +CORE_STREAM_LENGTH_30 334 4.954% 334 4.954% +CORE_STREAM_LENGTH_40 162 2.403% 162 2.403% +CORE_STREAM_LENGTH_50 138 2.047% 138 2.047% +CORE_STREAM_LENGTH_60 152 2.255% 152 2.255% +CORE_STREAM_LENGTH_70 143 2.121% 143 2.121% +CORE_STREAM_LENGTH_80 203 3.011% 203 3.011% +CORE_STREAM_LENGTH_90 210 3.115% 210 3.115% +CORE_STREAM_LENGTH_100_P 3466 51.409% 3466 51.409% + 6742 100.000% 6742 100.000% + 6.62 6.03 6.62 6.03 + +CORE_CUM_STREAM_LENGTH_0 2169 0.077% 2169 0.077% +CORE_CUM_STREAM_LENGTH_10 14452 0.512% 14452 0.512% +CORE_CUM_STREAM_LENGTH_20 14194 0.503% 14194 0.503% +CORE_CUM_STREAM_LENGTH_30 11273 0.400% 11273 0.400% +CORE_CUM_STREAM_LENGTH_40 7110 0.252% 7110 0.252% +CORE_CUM_STREAM_LENGTH_50 7487 0.265% 7487 0.265% +CORE_CUM_STREAM_LENGTH_60 9822 0.348% 9822 0.348% +CORE_CUM_STREAM_LENGTH_70 10651 0.378% 10651 0.378% +CORE_CUM_STREAM_LENGTH_80 17223 0.611% 17223 0.611% +CORE_CUM_STREAM_LENGTH_90 19886 0.705% 19886 0.705% +CORE_CUM_STREAM_LENGTH_100_P 2706311 95.949% 2706311 95.949% + 2820578 100.000% 2820578 100.000% + 9.81 9.67 9.81 9.67 + +CORE_STREAM_TRAIN_HITS_0 1995 29.591% 1995 29.591% +CORE_STREAM_TRAIN_HITS_10 753 11.169% 753 11.169% +CORE_STREAM_TRAIN_HITS_20 586 8.692% 586 8.692% +CORE_STREAM_TRAIN_HITS_30 420 6.230% 420 6.230% +CORE_STREAM_TRAIN_HITS_40 489 7.253% 489 7.253% +CORE_STREAM_TRAIN_HITS_50 624 9.255% 624 9.255% +CORE_STREAM_TRAIN_HITS_60 105 1.557% 105 1.557% +CORE_STREAM_TRAIN_HITS_70 110 1.632% 110 1.632% +CORE_STREAM_TRAIN_HITS_80 113 1.676% 113 1.676% +CORE_STREAM_TRAIN_HITS_90 131 1.943% 131 1.943% +CORE_STREAM_TRAIN_HITS_100_P 1416 21.003% 1416 21.003% + 6742 100.000% 6742 100.000% + 3.84 3.67 3.84 3.67 + +CORE_CUM_STREAM_TRAIN_HITS_0 12163 0.655% 12163 0.655% +CORE_CUM_STREAM_TRAIN_HITS_10 10186 0.548% 10186 0.548% +CORE_CUM_STREAM_TRAIN_HITS_20 14389 0.775% 14389 0.775% +CORE_CUM_STREAM_TRAIN_HITS_30 14330 0.772% 14330 0.772% +CORE_CUM_STREAM_TRAIN_HITS_40 22359 1.204% 22359 1.204% +CORE_CUM_STREAM_TRAIN_HITS_50 32546 1.752% 32546 1.752% +CORE_CUM_STREAM_TRAIN_HITS_60 6733 0.363% 6733 0.363% +CORE_CUM_STREAM_TRAIN_HITS_70 8175 0.440% 8175 0.440% +CORE_CUM_STREAM_TRAIN_HITS_80 9545 0.514% 9545 0.514% +CORE_CUM_STREAM_TRAIN_HITS_90 12216 0.658% 12216 0.658% +CORE_CUM_STREAM_TRAIN_HITS_100_P 1714708 92.320% 1714708 92.320% + 1857350 100.000% 1857350 100.000% + 9.56 9.31 9.56 9.31 + +CORE_STREAM_TRAIN_CREATE 1632003 1632003 + + + diff --git a/labs/LAB5/runs/mcf_s_base-sms1/PARAMS.in b/labs/LAB5/runs/mcf_s_base-sms1/PARAMS.in new file mode 100644 index 00000000..2593c2b8 --- /dev/null +++ b/labs/LAB5/runs/mcf_s_base-sms1/PARAMS.in @@ -0,0 +1,226 @@ +# File : PARAMS.kaby_lake +# Date : 03/06/19 +# Description : Kaby Lake Configuration +# +# Based on documentation found here: +# https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake + +## Simulation Parameters +--mode full +--model cmp +--sim_limit none + +## Core Parameters + +# Femptoseconds, 3.2GHz, used for energy estimates. +--chip_cycle_time 312500 + + +### Fetch Stage +--fetch_off_path_ops 1 +--fetch_across_cache_lines 1 + +# Will break the packet upon a taken branch. +--fetch_break_on_taken 1 + +# Number of bubble cycles to wait after taken branch. +--fetch_taken_bubble_cycles 0 + + +#### ICache +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 + +### Branch Predictor +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_mech tagescl + + +#### BTB + +# BTB model to use. +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 + +# Allow the BTB to be updated by off path ops. +--btb_off_path_writes 1 + + +#### CRS + +# Enable return stack +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 + +### iBP +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged + # iBTB Model. tc_tagless, tc_tagged, tc_hybrid. +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 + +### Decode Stage +--decode_cycles 5 + + +### Map Stage +--map_cycles 5 + + +### Issue Stage + +# Max number of instructions to be fetched, decoded, renamed, and issued per cycle. +--issue_width 6 + +--rs_fill_width 0 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 + + +### Exec Stage + +### DCache +--dcache_size 32768 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--dcache_assoc 4 +--dcache_line_size 64 + +### Reorder/Retire Stage + +# Max number of instructions to be retired per cycle. +--node_ret_width 6 +--node_table_size 224 + +# Do not keep stores in RSVs on cache misses; TODO: confirm what this knob does +--stores_do_not_block_window 1 + +# TODO: confirm what this knob does +--prefs_do_not_block_window 1 + + +## Uncore + +### Mid-level cache + +# Enable use of a midlevel cache between i/d and L1 +--mlc_present 0 + +### LLC +--l1_size 1048576 +--l1_banks 1 +--l1_cycles 18 +--l1_assoc 8 +--l1_line_size 64 +--l1_interleave_factor 64 + + +### Prefetcher +--pref_framework_on 1 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--pref_shared_queues 0 +--pref_train_on_pref_misses 0 +--pref_oracle_train 0 +--pref_ul1req_queue_overwrite_on_full 1 + +--stream_length 64 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 + +--pref_throttlefb_on=1 +--pref_acc_thresh_1=0.75 +--pref_acc_thresh_2=0.4 +--pref_acc_thresh_3=0.4 +--pref_timely_thresh=0.01 +--pref_polpf_thresh=0.005 +--pref_update_interval=8192 + +--mem_req_buffer_pref_watermark 4 +--promote_to_higher_priority_mem_req_type 1 + +### Memory +--addr_translation random + +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 + +--mem_req_buffer_entries 32 +--mem_l1_fill_queue_entries 32 +--va_page_size_bytes 4096 +--bus_width_in_bytes 8 + +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 + +## Other + + +### Debug +--debug_inst_start 0 +--debug_inst_stop -1 +--debug_cycle_start 0 +--debug_cycle_stop -1 + + +## Stats and Params +--dump_params 1 +--dump_stats 1 +--dump_trace 0 + +#################################### +--set_off_path_confirmed 1 + +--order_beyond_bus 1 + +--mem_ooo_stores 1 +--mem_obey_store_dep 1 diff --git a/labs/LAB5/runs/mcf_s_base-sms1/PARAMS.out b/labs/LAB5/runs/mcf_s_base-sms1/PARAMS.out new file mode 100644 index 00000000..805125c9 --- /dev/null +++ b/labs/LAB5/runs/mcf_s_base-sms1/PARAMS.out @@ -0,0 +1,908 @@ +--mode full +--model cmp +--frontend memtrace +--inst_limit 100000000 +--sim_limit none +--dump_params 1 +--dump_stats 1 +--dump_trace 0 +--mlc_present 0 +--l1_size 1048576 +--l1_assoc 8 +--l1_line_size 64 +--l1_cycles 18 +--l1_banks 1 +--l1_interleave_factor 64 +--va_page_size_bytes 4096 +--addr_translation random +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 +--dcache_size 32768 +--dcache_assoc 4 +--dcache_line_size 64 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--mem_ooo_stores 1 +--mem_obey_store_dep 1 +--mem_req_buffer_entries 32 +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 +--promote_to_higher_priority_mem_req_type 1 +--mem_req_buffer_pref_watermark 4 +--mem_l1_fill_queue_entries 32 +--order_beyond_bus 1 +--set_off_path_confirmed 1 +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--bus_width_in_bytes 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 +--chip_cycle_time 312500 +--issue_width 6 +--rs_fill_width 0 +--node_table_size 224 +--node_ret_width 6 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 +--decode_cycles 5 +--map_cycles 5 +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--fetch_across_cache_lines 1 +--fetch_off_path_ops 0 +--fetch_break_on_taken 1 +--fetch_taken_bubble_cycles 0 +--stores_do_not_block_window 1 +--prefs_do_not_block_window 1 +--cbp_trace_r0 /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir/trace/drmemtrace.mcf_s_base.mytest-m64.554166.7956.trace.gz +--memtrace_modules_log /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir/raw +--debug_cycle_start 0 +--debug_cycle_stop -1 +--debug_inst_start 0 +--debug_inst_stop -1 +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--bp_mech tagescl +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 +--btb_off_path_writes 1 +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_length 64 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 +--pref_framework_on 1 +--pref_shared_queues 0 +--pref_ul1req_queue_overwrite_on_full 1 +--pref_train_on_pref_misses 0 +--pref_oracle_train_on 0 +--pref_throttlefb_on 1 +--pref_acc_thresh_1 0.75 +--pref_acc_thresh_2 0.4 +--pref_acc_thresh_3 0.4 +--pref_update_interval 8192 +--pref_timely_thresh 0.01 +--pref_polpf_thresh 0.005 +--pref_sms_on 1 +1 1 1 1 1 1 1 + +--- Cut out everything below to use this file as PARAMS.in --- + +Parameter status at compile time and values supplied on the command line: + +SIM_MODE 0 full +SIM_MODEL 0 cmp +FRONTEND FE_PIN_EXEC_DRIVEN memtrace +INST_LIMIT NULL 100000000 +SIM_LIMIT "none" none +FORWARD_PROGRESS_LIMIT 100000000 +FORWARD_PROGRESS_INTERVAL 10000 +FAST_FORWARD 0 +FAST_FORWARD_UNTIL_ADDR 0 +FAST_FORWARD_TRACE_INS 0 +WARMUP 0 +HEARTBEAT_INTERVAL 1000000 +NUM_HEARTBEATS 0 +FILE_TAG "" +OUTPUT_DIR "." +STATUS_FILE NULL +BINDIR NULL +DUMP_PARAMS TRUE 1 +DUMP_STATS TRUE 1 +DUMP_TRACE FALSE 0 +CLEAR_STATS "never" +STATS_TO_TRACE NULL +STAT_TRACE_FILE "stats.trace" +STAT_TRACE_INTERVAL "i:100000" +PIPEVIEW FALSE +PIPEVIEW_FILE "pipeview" +MEMVIEW FALSE +MEMVIEW_FILE "memview.out" +MEMVIEW_START "never" +INST_HASH_TABLE_SIZE 500021 const +STDOUT_FILE NULL +STDERR_FILE NULL +PIN_EXEC_DRIVEN_FE_SOCKET "./pin_exec_driven_fe_socket.temp" +PRINT_PID FALSE +USE_UNSURE_FREE_LISTS FALSE +OPTIMIZER2_MAX_NUM_SLAVES 64 +OPTIMIZER2_PERFECT_MEMORYLESS FALSE +EXIT_COND 0 +ENABLE_SWPRF FALSE +MLC_PRESENT FALSE 0 +MLC_SIZE (512 * 1024) +MLC_ASSOC 4 +MLC_LINE_SIZE 64 +MLC_CYCLES 12 +PERFECT_MLC FALSE +MLC_READ_PORTS 1 +MLC_WRITE_PORTS 1 +MLC_BANKS 8 +MLC_INTERLEAVE_FACTOR 64 +MLC_CACHE_REPL_POLICY 0 +MLC_WRITE_THROUGH FALSE +PREFETCH_UPDATE_LRU_MLC TRUE +FORCE_L1_MISS FALSE +L1_SIZE (4 * 1024 * 1024) 1048576 +L1_ASSOC 8 8 +L1_LINE_SIZE 64 64 +L1_CYCLES 24 18 +PERFECT_L1 FALSE +PRIVATE_L1 FALSE +L1_READ_PORTS 1 +L1_WRITE_PORTS 1 +L1_BANKS 8 1 +L1_INTERLEAVE_FACTOR 64 64 +L1_CACHE_REPL_POLICY 0 +L1_WRITE_THROUGH FALSE +L1_IGNORE_WB FALSE +L1_USE_CORE_FREQ FALSE +MARK_L1_MISSES TRUE +PREFETCH_UPDATE_LRU_L1 TRUE +MEMORY_RANDOM_ADDR FALSE +VA_PAGE_SIZE_BYTES 4096 4096 +NUM_ADDR_NON_SIGN_EXTEND_BITS 48 +ADDR_TRANSLATION 0 random +CONSTANT_MEMORY_LATENCY FALSE +MEMORY_CYCLES 100 +STALL_MEM_REQS_ONLY FALSE +ICACHE_SIZE (64 * 1024) 32768 +ICACHE_ASSOC 4 4 +ICACHE_LINE_SIZE 64 64 +PERFECT_ICACHE FALSE +ICACHE_READ_PORTS 2 +ICACHE_WRITE_PORTS 1 +ICACHE_BANKS 8 +ICACHE_REPL 0 +DCACHE_SIZE (64 * 1024) 32768 +DCACHE_ASSOC 1 4 +DCACHE_LINE_SIZE 64 64 +DCACHE_CYCLES 2 +PERFECT_DCACHE FALSE +DCACHE_READ_PORTS 8 2 +DCACHE_WRITE_PORTS 1 1 +DCACHE_BANKS 1 1 +DCACHE_REPL 0 +DCACHE_REPL_PREF_THRESH 1 +MEM_OOO_STORES TRUE 1 +MEM_OBEY_STORE_DEP TRUE 1 +PREF_INSERT_LRU FALSE +PREF_INSERT_MIDDLE FALSE +PREF_INSERT_LOWQTR FALSE +PREF_INSERT_DYNACC FALSE +MEM_REQ_BUFFER_ENTRIES 32 32 +PRIVATE_MSHR_ON TRUE +MEM_PRIORITY_IFETCH 0 0 +MEM_PRIORITY_DFETCH 0 1 +MEM_PRIORITY_DSTORE 0 2 +MEM_PRIORITY_IPRF 9 3 +MEM_PRIORITY_DPRF 10 4 +MEM_PRIORITY_WB 0 5 +MEM_PRIORITY_WB_NODIRTY 0 5 +PROMOTE_TO_HIGHER_PRIORITY_MEM_REQ_TYPE FALSE 1 +MEM_REQ_BUFFER_PREF_WATERMARK 0 4 +MEM_REQ_BUFFER_WB_VALVE 2 +MEM_L1_FILL_QUEUE_ENTRIES 32 32 +MEM_BUS_OUT_QUEUE_PARTITION_ENABLE FALSE +MEM_MEM_QUEUE_PARTITION_ENABLE FALSE +MEM_BUS_OUT_QUEUE_AS_FIFO TRUE +OLDEST_FIRST_TO_MEM_QUEUE TRUE +ROUND_ROBIN_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE_TH 0 +L1_CYCLE_TIME 312500 +MLCQ_TO_L1Q_TRANSFER_LATENCY 1 +L1Q_TO_FSB_TRANSFER_LATENCY 1 +PRIORITIZE_PREFETCHES_WITH_UNIQUE FALSE +KICKOUT_PREFETCHES FALSE +KICKOUT_LOOK_FOR_OLDEST_FIRST FALSE +KICKOUT_OLDEST_PREFETCH FALSE +KICKOUT_OLDEST_PREFETCH_WITHIN_BANK FALSE +ORDER_BEYOND_BUS FALSE 1 +ALL_FIFO_QUEUES FALSE +QUEUE_MLC_SIZE 0 +QUEUE_L1_SIZE 0 +QUEUE_BUS_OUT_SIZE 0 +QUEUE_CORE_FILL_SIZE 0 +ALLOW_TYPE_MATCHES FALSE +STREAM_PREFETCH_ON FALSE +DC_PREF_CACHE_ENABLE FALSE +DC_PREF_CACHE_CYCLE 0 +PREF_INSERT_DCACHE_IMM TRUE +DC_PREF_CACHE_SIZE (64 * 1024) +DC_PREF_CACHE_ASSOC 4 +DC_PREF_ONLY_L1HIT FALSE +PREF_CACHE_USE_RDY_CYCLE FALSE +IC_PREF_CACHE_ENABLE FALSE +IC_PREF_CACHE_SIZE (64 * 1024) +IC_PREF_CACHE_ASSOC 4 +L1_PREF_CACHE_ENABLE FALSE +L1_PREF_CACHE_SIZE (1024 * 1024) +L1_PREF_CACHE_ASSOC 8 +SET_OFF_PATH_CONFIRMED FALSE 1 +USE_CONFIRMED_OFF FALSE +PREFCACHE_MOVE_OFFPATH FALSE +CACHE_STAT_ENABLE FALSE +PREF_DCACHE_HIT_FILL_L1 TRUE +PREF_ICACHE_HIT_FILL_L1 TRUE +CRITICAL_ACCESS_PLOT_ENABLE FALSE +CRITICAL_ACCESS_PLOT_FILE "critical_access_plot.dat" +ROUND_ROBIN_TO_L1 FALSE +PREF_I_TOGETHER FALSE +ONE_MORE_CACHE_LINE_ENABLE FALSE +L1_STATIC_PARTITION_ENABLE 0 +L1_STATIC_PARTITION NULL +L1_DYNAMIC_PARTITION_ENABLE FALSE +L1_DYNAMIC_PARTITION_POLICY 0 +PARTITION_UMON_DSS_PREF_ENABLE FALSE +L1_CACHE_HIT_POSITION_COLLECT FALSE +L1_PART_ON FALSE +L1_PART_TRIGGER "c:1000000" +L1_PART_START "t:0" +L1_PART_WARMUP FALSE +L1_PART_SHADOW_WARMUP FALSE +L1_PART_METRIC 0 +L1_PART_SEARCH 0 +L1_PART_USE_STALLING TRUE +L1_PART_FILL_DELAY 0 +L1_SHADOW_TAGS_MODULO 1 +HIER_MSHR_ON FALSE +PERF_PRED_ENABLE FALSE +PERF_PRED_MECH PERF_PRED_CP +PERF_PRED_REQ_LATENCY_MECH PERF_PRED_REQ_LATENCY_MECH_REQ_LATENCY +PERF_PRED_COUNT_ALL FALSE +PERF_PRED_COUNT_INST_MISSES TRUE +PERF_PRED_COUNT_PREFETCHES FALSE +PERF_PRED_COUNT_OFFPATH_REQS FALSE +PERF_PRED_COUNT_BW_REQS TRUE +PERF_PRED_UPDATE_MEM_REQ_TYPE FALSE +PERF_PRED_SLACK_PERIOD_SIZE 32 +PERF_PRED_REQS_FINISH_AT_FILL FALSE +PERF_PRED_MEM_UTIL_VIA_BUS_BW FALSE +PERF_PRED_CHIP_UTIL_VIA_MEM_STALL FALSE +DUMB_MODEL_AVG_REQ_DISTANCE 100 +DUMB_MODEL_RANDOMIZE_DISTANCE FALSE +DUMB_MODEL_AVG_REQ_DISTANCE_PER_CORE NULL +DUMB_MODEL_AVG_ROW_HITS 1 +DUMB_MODEL_AVG_ROW_HITS_PER_CORE NULL +DUMB_MODEL_MLP 1 +DUMB_MODEL_MLP_PER_CORE NULL +RAMULATOR_STANDARD "DDR4" DDR4 +RAMULATOR_SPEED "DDR4_2400R" DDR4_2400R +RAMULATOR_ORG "DDR4_8Gb_x8" DDR4_8Gb_x8 +RAMULATOR_CHANNELS 1 1 +RAMULATOR_RANKS 1 1 +RAMULATOR_BANKGROUPS 4 4 +RAMULATOR_BANKS 4 4 +RAMULATOR_CHIP_WIDTH 8 8 +BUS_WIDTH_IN_BYTES 8 8 +RAMULATOR_ROWS 65536 65536 +RAMULATOR_COLS 1024 1024 +RAMULATOR_SCHEDULING_POLICY "FRFCFS_Cap" FRFCFS_Cap +RAMULATOR_READQ_ENTRIES 32 32 +RAMULATOR_WRITEQ_ENTRIES 32 32 +RAMULATOR_REC_CMD_TRACE "off" FALSE +RAMULATOR_PRINT_CMD_TRACE "off" FALSE +RAMULATOR_USE_REST_OF_ADDR_AS_ROW_ADDR "on" +RAMULATOR_TCK 833333 833333 +RAMULATOR_TCL 16 16 +RAMULATOR_TCCD 6 6 +RAMULATOR_TCCDS 4 4 +RAMULATOR_TCCDL 6 6 +RAMULATOR_TCWL 12 12 +RAMULATOR_TBL 4 4 +RAMULATOR_TWTR 9 9 +RAMULATOR_TWTRS 3 3 +RAMULATOR_TWTRL 9 9 +RAMULATOR_TRP 16 16 +RAMULATOR_TRPpb 16 16 +RAMULATOR_TRPab 16 16 +RAMULATOR_TRCD 16 16 +RAMULATOR_TRCDR 16 16 +RAMULATOR_TRCDW 16 16 +RAMULATOR_TRAS 39 39 +DRAM_TECH_IN_NM 32 32 +DVFS_ON FALSE +DVFS_METRIC DVFS_METRIC_NUM_ELEMS +DVFS_CONFIGS NULL +DVFS_CONFIG_FILE NULL +DVFS_START "t:0" +DVFS_PERIOD "t:312500000000" +DVFS_LOG TRUE +DVFS_INDIVIDUAL_CORES FALSE +DVFS_CHIP_LEVEL FALSE +DVFS_STATIC NULL +DVFS_FORCE_CONFIG NULL +DVFS_REPLAY_CONFIG_TRACE NULL +DVFS_USE_ORACLE FALSE +DVFS_USE_BW_SHARING FALSE +DVFS_USE_DRAM_SHARING FALSE +DVFS_USE_STALL_TIME FALSE +DVFS_DRAM_SHARING_SOLVER_BIN NULL +DVFS_DRAM_SHARING_SOLVER_STRICT TRUE +DVFS_BW_SHARING_BUS_UTIL_THRESH 0.95 +DVFS_BW_SHARING_MAX_REQS 28.0 +DVFS_BW_SHARING_MAX_RW_COST 0.25 +DVFS_BW_SHARING_NO_PREF_STALL TRUE +DVFS_BW_SHARING_CRIT_STATS TRUE +DVFS_COUNT_L1_ACCESS_STALL FALSE +NUM_CORES 1 +CHIP_CYCLE_TIME 312500 312500 +CORE_0_CYCLE_TIME 312500 +CORE_1_CYCLE_TIME 312500 +CORE_2_CYCLE_TIME 312500 +CORE_3_CYCLE_TIME 312500 +CORE_4_CYCLE_TIME 312500 +CORE_5_CYCLE_TIME 312500 +CORE_6_CYCLE_TIME 312500 +CORE_7_CYCLE_TIME 312500 +CORE_8_CYCLE_TIME 312500 +CORE_9_CYCLE_TIME 312500 +CORE_10_CYCLE_TIME 312500 +CORE_11_CYCLE_TIME 312500 +CORE_12_CYCLE_TIME 312500 +CORE_13_CYCLE_TIME 312500 +CORE_14_CYCLE_TIME 312500 +CORE_15_CYCLE_TIME 312500 +CORE_16_CYCLE_TIME 312500 +CORE_17_CYCLE_TIME 312500 +CORE_18_CYCLE_TIME 312500 +CORE_19_CYCLE_TIME 312500 +CORE_20_CYCLE_TIME 312500 +CORE_21_CYCLE_TIME 312500 +CORE_22_CYCLE_TIME 312500 +CORE_23_CYCLE_TIME 312500 +CORE_24_CYCLE_TIME 312500 +CORE_25_CYCLE_TIME 312500 +CORE_26_CYCLE_TIME 312500 +CORE_27_CYCLE_TIME 312500 +CORE_28_CYCLE_TIME 312500 +CORE_29_CYCLE_TIME 312500 +CORE_30_CYCLE_TIME 312500 +CORE_31_CYCLE_TIME 312500 +CORE_32_CYCLE_TIME 312500 +CORE_33_CYCLE_TIME 312500 +CORE_34_CYCLE_TIME 312500 +CORE_35_CYCLE_TIME 312500 +CORE_36_CYCLE_TIME 312500 +CORE_37_CYCLE_TIME 312500 +CORE_38_CYCLE_TIME 312500 +CORE_39_CYCLE_TIME 312500 +CORE_40_CYCLE_TIME 312500 +CORE_41_CYCLE_TIME 312500 +CORE_42_CYCLE_TIME 312500 +CORE_43_CYCLE_TIME 312500 +CORE_44_CYCLE_TIME 312500 +CORE_45_CYCLE_TIME 312500 +CORE_46_CYCLE_TIME 312500 +CORE_47_CYCLE_TIME 312500 +CORE_48_CYCLE_TIME 312500 +CORE_49_CYCLE_TIME 312500 +CORE_50_CYCLE_TIME 312500 +CORE_51_CYCLE_TIME 312500 +CORE_52_CYCLE_TIME 312500 +CORE_53_CYCLE_TIME 312500 +CORE_54_CYCLE_TIME 312500 +CORE_55_CYCLE_TIME 312500 +CORE_56_CYCLE_TIME 312500 +CORE_57_CYCLE_TIME 312500 +CORE_58_CYCLE_TIME 312500 +CORE_59_CYCLE_TIME 312500 +CORE_60_CYCLE_TIME 312500 +CORE_61_CYCLE_TIME 312500 +CORE_62_CYCLE_TIME 312500 +CORE_63_CYCLE_TIME 312500 +ISSUE_WIDTH 4 6 +RS_FILL_WIDTH 8 0 +NODE_TABLE_SIZE 256 224 +NODE_RET_WIDTH 4 6 +NODE_RETIRE_RATE 10 +RS_SIZES "256" 97 +RS_CONNECTIONS "xF" 0 +FU_TYPES "0, 0, 0, 0" 0 0 0 0 0 0 0 0 +DECODE_CYCLES 1 5 +MAP_CYCLES 1 5 +EXTRA_RECOVERY_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after recovery. +EXTRA_REDIRECT_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after redirect. +EXTRA_CALLSYS_CYCLES 20 const +DIE_ON_CALLSYS FALSE +DIE_ON_RET_STALL_THRESH 0 +DIE_ON_RET_STALL_CORE 0 +DIE_ON_MEM_BLOCK_THRESH 0 +DIE_ON_MEM_BLOCK_CORE 0 +FETCH_ACROSS_CACHE_LINES FALSE 1 +FETCH_OFF_PATH_OPS TRUE 0 +FETCH_BREAK_ON_TAKEN FALSE 1 +FETCH_TAKEN_BUBBLE_CYCLES 0 0 +WP_COLLECT_STATS FALSE +SWITCH_IC_FETCH_ON_RECOVERY TRUE +OP_INV_DELAY 1 +OP_NOP_DELAY 1 +OP_CF_DELAY 1 +OP_MOV_DELAY 1 +OP_CMOV_DELAY 1 +OP_LDA_DELAY 1 +OP_IMEM_DELAY 1 +OP_IADD_DELAY 1 +OP_IMUL_DELAY 3 +OP_IDIV_DELAY -20 +OP_ICMP_DELAY 1 +OP_LOGIC_DELAY 1 +OP_SHIFT_DELAY 1 +OP_FMEM_DELAY 1 +OP_FCVT_DELAY 3 +OP_FADD_DELAY 3 +OP_FMUL_DELAY 5 +OP_FMA_DELAY 5 +OP_FDIV_DELAY -20 +OP_FCMP_DELAY 3 +OP_FCMOV_DELAY 1 +OP_GATHER_DELAY 12 +OP_SCATTER_DELAY 18 +OP_PIPELINED_FAST_DELAY 2 +OP_PIPELINED_MEDIUM_DELAY 5 +OP_PIPELINED_SLOW_DELAY 10 +OP_NOTPIPELINED_MEDIUM_DELAY -5 +OP_NOTPIPELINED_SLOW_DELAY -20 +OP_NOTPIPELINED_VERY_SLOW_DELAY -100 +UNIFORM_OP_DELAY 0 +STALL_ON_WAIT_MEM TRUE +STORES_DO_NOT_BLOCK_WINDOW FALSE 1 +PREFS_DO_NOT_BLOCK_WINDOW FALSE 1 +OBEY_REG_DEP TRUE +OLDEST_FIRST_SCHED FALSE +FIND_EMPTIEST_RS FALSE +TRACK_L1_MISS_DEPS FALSE +CBP_TRACE_R0 NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir/trace/drmemtrace.mcf_s_base.mytest-m64.554166.7956.trace.gz +CBP_TRACE_R1 NULL +CBP_TRACE_R2 NULL +CBP_TRACE_R3 NULL +CBP_TRACE_R4 NULL +CBP_TRACE_R5 NULL +CBP_TRACE_R6 NULL +CBP_TRACE_R7 NULL +CBP_TRACE_R8 NULL +CBP_TRACE_R9 NULL +CBP_TRACE_R10 NULL +CBP_TRACE_R11 NULL +CBP_TRACE_R12 NULL +CBP_TRACE_R13 NULL +CBP_TRACE_R14 NULL +CBP_TRACE_R15 NULL +CBP_TRACE_R16 NULL +CBP_TRACE_R17 NULL +CBP_TRACE_R18 NULL +CBP_TRACE_R19 NULL +CBP_TRACE_R20 NULL +CBP_TRACE_R21 NULL +CBP_TRACE_R22 NULL +CBP_TRACE_R23 NULL +CBP_TRACE_R24 NULL +CBP_TRACE_R25 NULL +CBP_TRACE_R26 NULL +CBP_TRACE_R27 NULL +CBP_TRACE_R28 NULL +CBP_TRACE_R29 NULL +CBP_TRACE_R30 NULL +CBP_TRACE_R31 NULL +CBP_TRACE_R32 NULL +CBP_TRACE_R33 NULL +CBP_TRACE_R34 NULL +CBP_TRACE_R35 NULL +CBP_TRACE_R36 NULL +CBP_TRACE_R37 NULL +CBP_TRACE_R38 NULL +CBP_TRACE_R39 NULL +CBP_TRACE_R40 NULL +CBP_TRACE_R41 NULL +CBP_TRACE_R42 NULL +CBP_TRACE_R43 NULL +CBP_TRACE_R44 NULL +CBP_TRACE_R45 NULL +CBP_TRACE_R46 NULL +CBP_TRACE_R47 NULL +CBP_TRACE_R48 NULL +CBP_TRACE_R49 NULL +CBP_TRACE_R50 NULL +CBP_TRACE_R51 NULL +CBP_TRACE_R52 NULL +CBP_TRACE_R53 NULL +CBP_TRACE_R54 NULL +CBP_TRACE_R55 NULL +CBP_TRACE_R56 NULL +CBP_TRACE_R57 NULL +CBP_TRACE_R58 NULL +CBP_TRACE_R59 NULL +CBP_TRACE_R60 NULL +CBP_TRACE_R61 NULL +CBP_TRACE_R62 NULL +CBP_TRACE_R63 NULL +MEMTRACE_MODULES_LOG NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.mcf_s_base.mytest-m64.554166.9011.dir/raw +DUMB_CORE_ON FALSE +DUMB_CORE 1 +DEBUG_CYCLE_START 0 0 +DEBUG_CYCLE_STOP 0 -1 +DEBUG_TIME_START 0 +DEBUG_TIME_STOP 0 +DEBUG_INST_START 0 0 +DEBUG_INST_STOP 0 -1 +DEBUG_OP_START 0 +DEBUG_OP_STOP 0 +DEBUG_CACHE_LIB FALSE +DEBUG_HASH_LIB FALSE +DEBUG_LIST_LIB FALSE +DEBUG_PORT_LIB FALSE +DEBUG_BUS_LIB FALSE +DEBUG_OP_POOL FALSE +DEBUG_ORACLE FALSE +DEBUG_FRONTEND FALSE +DEBUG_ADDR_TRANS FALSE +DEBUG_BP FALSE +DEBUG_BP_DIR FALSE +DEBUG_BTB FALSE +DEBUG_CRS FALSE +DEBUG_MAP FALSE +DEBUG_MEMORY FALSE +DEBUG_REPLAY FALSE +DEBUG_FREQ FALSE +DEBUG_MODEL FALSE +DEBUG_THREAD FALSE +DEBUG_ICACHE_STAGE FALSE +DEBUG_DECODE_STAGE FALSE +DEBUG_MAP_STAGE FALSE +DEBUG_NODE_STAGE FALSE +DEBUG_EXEC_STAGE FALSE +DEBUG_DCACHE_STAGE FALSE +DEBUG_RETIRED_UOPS FALSE +DEBUG_EXC_INSERTS FALSE +DEBUG_BP_CONF FALSE +DEBUG_ONPATH_CONF FALSE +DEBUG_STREAM FALSE +DEBUG_STREAM_MEM FALSE +DEBUG_WAY FALSE +DEBUG_L2MARKV FALSE +DEBUG_L2L1PREF FALSE +DEBUG_PERF_PRED FALSE +DEBUG_POWER_UTILS FALSE +DEBUG_DVFS FALSE +DEBUG_TRACE_READ FALSE +DEBUG_INST_FIELDS FALSE +DEBUG_OP_FIELDS FALSE +DEBUG_PIN_EXEC_DRIVEN FALSE +DEBUG_CACHE_PART FALSE +DEBUG_OPTIMIZER2 FALSE +DEBUG_PREF FALSE +PERFECT_BP FALSE +PERFECT_BTB FALSE +PERFECT_IBP FALSE +PERFECT_CRS FALSE +PERFECT_CBR_BTB FALSE +PERFECT_NT_BTB FALSE +CFS_PER_CYCLE 3 6 # Number of branches that can be predicted in a single cycle +UPDATE_BP_OFF_PATH FALSE 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +BP_UPDATE_AT_RETIRE FALSE 0 # Update the BP at retire. If false, update at the end of exec. +BP_MECH 0 tagescl +LATE_BP_MECH NUM_BP +LATE_BP_LATENCY 5 +HIST_LENGTH 16 +PHT_CTR_BITS 2 const +BHT_ENTRIES (4 * 1024) +BHT_ASSOC 4 +HYBRIDS_INDEX_LENGTH 16 +HYBRIDG_HIST_LENGTH 16 +HYBRIDP_HIST_LENGTH 16 +FILTER_INDEX_LENGTH 16 +USE_FILTER FALSE +INF_HYBRIDGP FALSE +BP_HASH_TOS FALSE +IBTB_HASH_TOS FALSE +BTB_MECH 0 generic +BTB_ENTRIES (4 * 1024) 4096 +BTB_ASSOC 4 4 +BTB_OFF_PATH_WRITES TRUE 1 +ENABLE_CRS TRUE 1 +CRS_ENTRIES 32 32 +CRS_REALISTIC 0 1 +ENABLE_IBP TRUE 1 # Enable the indirect branch predictor +USE_PAT_HIST TRUE +IBTB_MECH 1 tc_tagged +IBTB_HIST_LENGTH 16 +IBTB_OFF_PATH_WRITES TRUE 1 # Allow off path ops to update the ibtb. +TARGETS_IN_HIST 4 +TC_ENTRIES (4 * 1024) 4096 +TC_ASSOC 4 4 +NUM_CORR_BRANCHES 3 +SEL_HIST_BP_ENTRIES 8192 +SEL_HIST_LENGTH 16 +SEL_HIST_DYN_CNT_TH 16 +SEL_HIST_MISPRED_TH 4 +ENABLE_BP_CONF FALSE +CONF_MECH 0 +PERF_BP_CONF_PRED FALSE +BPC_BITS 16 +BPC_MECH 1 +BPC_CTR_RESET TRUE +BPC_CIT_BITS 8 +BPC_CIT_TH 50 +BPC_CTR_BITS 3 +OPC_COUNT_ZEROS FALSE +OPC_COUNT_THRESH 10 +INF_LOOP FALSE +INF_LOOP_BUCKETS 811 +LOOP_ENTRIES (4 * 1024) +LOOP_ASSOC 4 +LOOP_COUNT_MAX 127 +LOOP_REPEAT_MAX 15 +KNOB_PRINT_BRINFO FALSE +BR_MISPRED_FILE NULL +CONF_PERCEPTRON_TH 0 +CONF_PERCEPTRON_CTR_BITS 8 +CONF_PERCEPTRON_ENTRIES 127 +CONF_PERCEPTRON_THRESH_OVRD 0 +CONF_HIST_LENGTH 32 +PERCEPTRON_CONF_USE_CONF FALSE +PERCEPTRON_CONF_TRAIN_HIS FALSE +PERCEPTRON_CONF_TRAIN_CONF FALSE +PERCEPTRON_CONF_TRAIN_OFFSET_CONF FALSE +PERCEPTRON_TRAIN_MISP_FACTOR 1 +PERCEPTRON_TRAIN_CORR_FACTOR 1 +PERCEPTRON_CONF_HIS_BOTH FALSE +PERCEPTRON_CONF_HIS_BOTH_LENGTH 4 +ENABLE_ICACHE_PACKET_BREAKING TRUE +NUM_LOAD_STORE_PER_PACKET 0 +PACKET_BREAK_ON_FUS FALSE +PACKET_BREAK_FU_TYPES "G,G,G,G,G,G,G,G,G,G,G,G" +POWER_INTF_ON FALSE +POWER_INTF_ENABLE_SCALING FALSE +POWER_INTF_EXEC "power/power_intf.py" +POWER_INTF_REF_CHIP_TECH_NM 22 +POWER_INTF_REF_CHIP_FREQ (3.2e9) +POWER_INTF_REF_MEMORY_FREQ (0.8e9) +POWER_OTHER (0.0) +PREF_STREAM_ON FALSE 1 +PREF_STREAM_PER_CORE_ENABLE FALSE 1 +STREAM_BUFFER_N 16 +STREAM_PREFETCH_N 2 4 +STREAM_START_DIS 5 1 +STREAM_LENGTH 16 64 +STREAM_FULL_N 1 +STREAM_TRAIN_LENGTH 16 +STREAM_TRAIN_NUM 1 4 +PREF_ACC_USE_CACHE FALSE +STREAM_STALL_ON_QUEUE_FULL FALSE +PREF_SCHEDULE_NUM 4 +TRAIN_FILTER_SIZE 32 +PREF_REQ_Q_SIZE 64 +STREAM_CREATE_ON_DC_MISS FALSE 0 +STREAM_CREATE_ON_L1_MISS TRUE 1 +STREAM_TRAIN_ON_WRONGPATH TRUE +STREAM_CREATE_ON_WRONGPATH TRUE +STREAM_PREF_INTO_DCACHE FALSE +REMOVE_REDUNDANT_STREAM FALSE +L2HIT_STREAM_SCHEDULE_NUM 4 +PREF_REQ_QUEUE_FILTER_ON FALSE +HW_PREF_HIT_TRAIN_STREAM FALSE +L2HIT_STREAM_BUFFER_N 32 +L2HIT_STREAM_PREFETCH_N 2 +L2HIT_STREAM_START_DIS 2 +L2HIT_STREAM_LENGTH 8 +L2HIT_PREF_REQ_Q_SIZE 128 +L2HIT_L2ACCESS_REQ_Q_SIZE 64 +PREF_STREAM_ACCPERSTREAM FALSE +PREF_ACC_DISTANCE_10 128 +PREF_FRAMEWORK_ON FALSE 1 +PREF_TRACE_ON FALSE +PREF_DL0REQ_QUEUE_SIZE 32 +PREF_UMLC_REQ_QUEUE_SIZE 64 +PREF_UL1REQ_QUEUE_SIZE 128 +PREF_SHARED_QUEUES TRUE 0 +PREF_DL0_MISS_ON TRUE +PREF_DL0_HIT_ON TRUE +PREF_DL0REQ_QUEUE_FILTER_ON TRUE +PREF_UMLC_REQ_QUEUE_FILTER_ON TRUE +PREF_UL1REQ_QUEUE_FILTER_ON TRUE +PREF_DL0REQ_ADD_FILTER_ON TRUE +PREF_UMLC_REQ_ADD_FILTER_ON TRUE +PREF_UL1REQ_ADD_FILTER_ON TRUE +PREF_DL0REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UMLC_REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UL1REQ_QUEUE_OVERWRITE_ON_FULL FALSE 1 +PREF_DL0SCHEDULE_NUM 4 +PREF_UMLC_SCHEDULE_NUM 4 +PREF_UL1SCHEDULE_NUM 4 +PREF_L1Q_DEMAND_RESERVE 0 +PREF_REPORT_PREF_MATCH_AS_MISS FALSE +PREF_REPORT_PREF_MATCH_AS_HIT TRUE +PREF_UPDATE_ON_WRONGPATH TRUE +PREF_TRAIN_ON_PREF_MISSES FALSE 0 +PREF_ORACLE_TRAIN_ON FALSE 0 +PREF_REQ_DROP FALSE +PREF_THROTTLE_ON FALSE +PREF_THROTTLEFB_ON FALSE 1 +PREF_ACC_THRESH_1 0.90 0.75 +PREF_ACC_THRESH_2 0.70 0.4 +PREF_ACC_THRESH_3 0.60 0.4 +PREF_ACC_THRESH_4 0.40 +PREF_UPDATE_INTERVAL 0 8192 +PREF_ANALYZE_LOAD FALSE +PREF_POL_THRESH_1 0.25 +PREF_POL_THRESH_2 0.10 +PREF_POLBV_ON FALSE +PREF_POLBV_SIZE 1024 +PREF_TIMELY_THRESH 0.05 0.01 +PREF_POLPF_THRESH 0.01 0.005 +PREF_DEGFB_USEONLYACC FALSE +PREF_DEGFB_USEONLYPOL FALSE +PREF_DEGFB_USEONLYLATE FALSE +PREF_TIMELY_THRESH_2 0.005 +PREF_DEGFB_STATPHASEFILE FALSE +PREF_MAX_DEGFB 4 +PREF_DHAL FALSE +PREF_DHAL_SENTTHRESH 16 +PREF_DHAL_USETHRESH_MAX 12 +PREF_DHAL_USETHRESH_MIN2 8 +PREF_DHAL_USETHRESH_MIN1 4 +PREF_DHAL_MAXDEG 64 +PREF_HFILTER_ON FALSE +PREF_HFILTER_INDEX_BITS 12 +PREF_HFILTER_USE_PC FALSE +PREF_HFILTER_PRED_USELESS_THRES 2 +PREF_HFILTER_RESET_ENABLE FALSE +PREF_HFILTER_RESET_INTERVAL 100000 +L2L1PREF_ON FALSE +L2WAY_PREF FALSE +L2MARKV_PREF_ON FALSE +L2NEXT_PREF_ON FALSE +L2HIT_STREAM_PREF_ON FALSE +L2L1_DC_HIT_TRAIN FALSE +L1_HIT_DUMP_FILE_ON FALSE +L1_HIT_DUMP_WO_TXT FALSE +L1_HIT_DUMPFILE "l1hit_dump.out" +IDEAL_L2_L1_PREFETCHER FALSE +IDEAL_L2_ICACHE_PREFETCHER FALSE +L1WAY_PREF_SEND_QUEUE 4 +L1PREF_REQ_QUEUE_SIZE 1024 +L1PREF_IMMEDIATE FALSE +L1WAY_PREF_TIMER_DIS 1000 +L1MARKV_PREF_SEND_QUEUE 4 +L1PREF_MARKV_REQ_QUEUE_SIZE 1024 +MARKV_L2ACCESS_REQ_Q_SIZE 64 +L1MARKV_PREF_IMMEDIATE FALSE +L1MARKV_PREF_TIMER_DIS 1 +L2L1_HIT_TRAIN TRUE +L1MARKV_REQ_TH 1 +L2L1_IMMEDIATE_PREF_CACHE FALSE +L2L1_FILL_PREF_CACHE FALSE +L2L1_L2_HIT_STAT FALSE +PREF_GHB_ON FALSE +DEBUG_PREF_GHB FALSE +PREF_GHB_BUFFER_N 1024 +PREF_GHB_INDEX_N 128 +PREF_GHB_CZONE_BITS 12 +PREF_GHB_DEGREE 16 +PREF_GHB_MAX_DEGREE 32 +PREF_STRIDE_ON FALSE +DEBUG_PREF_STRIDE FALSE +PREF_STRIDE_TABLE_N 1024 +PREF_STRIDE_REGION_BITS 16 +PREF_STRIDE_DEGREE 4 +PREF_STRIDE_DISTANCE 16 +PREF_STRIDE_STARTDISTANCE 1 +PREF_STRIDE_SINGLE_THRESH 6 +PREF_STRIDE_MULTI_THRESH 6 +PREF_STRIDE_SINGLE_STRIDE_MODE FALSE +PREF_STRIDEPC_ON FALSE +DEBUG_PREF_STRIDEPC FALSE +PREF_STRIDEPC_TABLE_N 1024 +PREF_STRIDEPC_DEGREE 4 +PREF_STRIDEPC_DISTANCE 16 +PREF_STRIDEPC_USELOADADDR FALSE +PREF_STRIDEPC_TRAINNUM 2 +PREF_STRIDEPC_STARTDIS 4 +PREF_PHASE_ON FALSE +PREF_PHASE_STUDY FALSE +DEBUG_PREF_PHASE FALSE +PREF_PHASE_PRIME_HASH 16381 +PREF_PHASE_INFOSIZE 16384 +PREF_PHASE_LOG2REGIONSIZE 12 +PREF_PHASE_REGIONENTRIES 64 +PREF_PHASE_TRACKEDREGIONS 32 +PREF_PHASE_INTERVAL 100000 +PREF_PHASE_TABLE_SIZE 64 +PREF_PHASE_MAXDIFF_THRESH 64 +PREF_PHASE_MIN_MISSES 64 +PREF_PHASE_MISSPER 0.4 +PREF_2DC_ON FALSE +DEBUG_PREF_2DC FALSE +PREF_2DC_CACHE_SIZE (1 * 1024) +PREF_2DC_CACHE_ASSOC 4 +PREF_2DC_CACHE_LINE_SIZE 1 +PREF_2DC_DEGREE 16 +PREF_2DC_ZONE_SHIFT 10 +PREF_2DC_TAG_SIZE 16 +PREF_2DC_NUM_REGIONS 64 +PREF_2DC_REGION_HASH 61 +PREF_MARKOV_ON FALSE +DEBUG_PREF_MARKOV FALSE +PREF_MARKOV_NUM_ENTRIES 65536 +PREF_MARKOV_NUM_NEXT_STATES 8 +PREF_MARKOV_SEND_ON_PREF_HIT TRUE +PREF_MARKOV_UPDATE_ON_PREF_HIT TRUE +PREF_MARKOV_TABLE_UPDATE_POLICY 0 +PREF_MARKOV_SEND_THRESHOLD 0 +PREF_SMS_ON FALSE 1 +PREF_SMS_AT_SIZE 64 +PREF_SMS_FT_SIZE 64 +PREF_SMS_PHT_SIZE 16384 +PREF_SMS_PRF_SIZE 1024 +PREF_SMS_REGION_SIZE 2048 diff --git a/labs/LAB5/runs/mcf_s_base-sms1/bp.stat.0.out b/labs/LAB5/runs/mcf_s_base-sms1/bp.stat.0.out new file mode 100644 index 00000000..4a7eac10 --- /dev/null +++ b/labs/LAB5/runs/mcf_s_base-sms1/bp.stat.0.out @@ -0,0 +1,752 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 121548526 Instructions: 100000002 IPC: 0.82272 + +BTB_ON_PATH_MISS 236 0.001% 236 0.001% +BTB_ON_PATH_HIT 25492868 99.999% 25492868 99.999% + 25493104 100.000% 25493104 100.000% + 1.00 1.00 1.00 1.00 + +BTB_OFF_PATH_MISS 0 -nan% 0 -nan% +BTB_OFF_PATH_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BTB_ON_PATH_WRITE 236 100.000% 236 100.000% +BTB_OFF_PATH_WRITE 0 0.000% 0 0.000% + 236 100.000% 236 100.000% + 0.00 0.00 0.00 0.00 + +BP_ON_PATH_CORRECT 24318367 95.392% 24318367 95.392% +BP_ON_PATH_MISPREDICT 245998 0.965% 245998 0.965% +BP_ON_PATH_MISFETCH 928739 3.643% 928739 3.643% + 25493104 100.000% 25493104 100.000% + 0.08 0.38 0.08 0.38 + +BP_OFF_PATH_CORRECT 0 -nan% 0 -nan% +BP_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% +BP_OFF_PATH_MISFETCH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +LATE_BP_ON_PATH_CORRECT 25493104 100.000% 25493104 100.000% +LATE_BP_ON_PATH_MISPREDICT 0 0.000% 0 0.000% +LATE_BP_ON_PATH_MISFETCH 0 0.000% 0 0.000% + 25493104 100.000% 25493104 100.000% + 0.00 0.00 0.00 0.00 + +LATE_BP_OFF_PATH_CORRECT 0 -nan% 0 -nan% +LATE_BP_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% +LATE_BP_OFF_PATH_MISFETCH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_PVN 0 -nan% 0 -nan% +BP_ON_PATH_CONF_PVN_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_PVP 0 -nan% 0 -nan% +BP_ON_PATH_CONF_PVP_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_SPEC 0 -nan% 0 -nan% +BP_ON_PATH_CONF_SPEC_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CRS_MISS_ON_PATH 22123 0.960% 22123 0.960% +CRS_HIT_ON_PATH 2281157 99.040% 2281157 99.040% + 2303280 100.000% 2303280 100.000% + 0.99 0.99 0.99 0.99 + +CRS_MISS_OFF_PATH 0 -nan% 0 -nan% +CRS_HIT_OFF_PATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CRS_CLOBBER 0 0 + +TARG_ON_PATH_MISS 466812 20.695% 466812 20.695% +TARG_ON_PATH_HIT 1788861 79.305% 1788861 79.305% + 2255673 100.000% 2255673 100.000% + 0.79 0.73 0.79 0.73 + +TARG_OFF_PATH_MISS 0 -nan% 0 -nan% +TARG_OFF_PATH_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_ON_PATH_WRITE 2255673 100.000% 2255673 100.000% +TARG_OFF_PATH_WRITE 0 0.000% 0 0.000% + 2255673 100.000% 2255673 100.000% + 0.00 0.00 0.00 0.00 + +TARG_HYBRID_CORRECT_TAGLESS 0 -nan% 0 -nan% +TARG_HYBRID_CORRECT_TAGGED 0 -nan% 0 -nan% +TARG_HYBRID_MISPRED_TAGLESS 0 -nan% 0 -nan% +TARG_HYBRID_MISPRED_TAGGED 0 -nan% 0 -nan% +TARG_HYBRID_NO_PRED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_VP_INDIRECT_MISPRED 0 -nan% 0 -nan% +TARG_VP_INDIRECT_NOPRED 0 -nan% 0 -nan% +TARG_VP_INDIRECT_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CBR_ON_PATH_CORRECT 18469630 98.686% 18469630 98.686% +CBR_ON_PATH_MISPREDICT 245998 1.314% 245998 1.314% + 18715628 100.000% 18715628 100.000% + 0.01 0.11 0.01 0.11 + +CBR_ON_PATH_CORRECT_PER1000INST 18469630 184.6963 18469630 184.6963 + +CBR_ON_PATH_MISPREDICT_PER1000INST 245998 2.4600 245998 2.4600 + +CBR_OFF_PATH_CORRECT 0 -nan% 0 -nan% +CBR_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PRED_TO_UPDATE_CYCLES_0 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_1 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_2 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_3 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_4 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_5 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_6 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_7 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_8 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_9 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_10 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_11 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_12 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_13 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_14 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_15 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_16 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_17 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_18 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_19 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_20 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_21 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_22 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_23 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_24 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_25 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_26 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_27 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_28 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_29 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_30 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_CORRECTED 0 -nan% 0 -nan% +BP_NOT_CORRECTED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_CORRECTED 0 -nan% 0 -nan% +TARG_NOT_CORRECTED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_MISP_PENALTY 43002992 43002992 + +BP_ON_PATH_CONF_MISPRED 0 -nan% 0 -nan% +BP_ON_PATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_OFF_PATH_CONF_MISPRED 0 -nan% 0 -nan% +BP_OFF_PATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_PRED_MIS_CONF_MISPRED 0 -nan% 0 -nan% +BP_ON_PATH_PRED_MIS_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_PRED_COR_CONF_MISPRED 0 -nan% 0 -nan% +BP_ON_PATH_PRED_COR_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_OFF_PATH_PRED_MIS_CONF_MISPRED 0 -nan% 0 -nan% +BP_OFF_PATH_PRED_MIS_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_OFF_PATH_PRED_COR_CONF_MISPRED 0 -nan% 0 -nan% +BP_OFF_PATH_PRED_COR_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ONPATH_CONF_MISPRED 0 -nan% 0 -nan% +ONPATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ONPATH_ON_PATH_CONF_MISPRED 0 -nan% 0 -nan% +ONPATH_ON_PATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ONPATH_OFF_PATH_CONF_MISPRED 0 -nan% 0 -nan% +ONPATH_OFF_PATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PRED_ONPATH_CONF_MISPRED 0 -nan% 0 -nan% +PRED_ONPATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PRED_OFFPATH_CONF_MISPRED 0 -nan% 0 -nan% +PRED_OFFPATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +LONG_OVWT_MIS 0 -nan% 0 -nan% +LONG_OVWT_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_0_7_MIS 0 -nan% 0 -nan% +OPC_LENGTH_0_7_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_8_15_MIS 0 -nan% 0 -nan% +OPC_LENGTH_8_15_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_16_23_MIS 0 -nan% 0 -nan% +OPC_LENGTH_16_23_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_24_31_MIS 0 -nan% 0 -nan% +OPC_LENGTH_24_31_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_32_39_MIS 0 -nan% 0 -nan% +OPC_LENGTH_32_39_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_40_47_MIS 0 -nan% 0 -nan% +OPC_LENGTH_40_47_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_48_55_MIS 0 -nan% 0 -nan% +OPC_LENGTH_48_55_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_56_63_MIS 0 -nan% 0 -nan% +OPC_LENGTH_56_63_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_64_71_MIS 0 -nan% 0 -nan% +OPC_LENGTH_64_71_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_72_79_MIS 0 -nan% 0 -nan% +OPC_LENGTH_72_79_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_80_MIS 0 -nan% 0 -nan% +OPC_LENGTH_80_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ALL_ONES_MIS 0 -nan% 0 -nan% +ALL_ONES_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan 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+CHIP_UTILIZATION 0 0.0000 0 0.0000 + +CYCLES_UNDER_MEM_REQ 0 0 + +CYCLES_UNDER_NO_MEM_REQ 0 0 + +CYCLES_UNDER_CRITICAL_MEM_REQ 0 0 + +CYCLES_UNDER_NONCRITICAL_MEM_REQ 0 0 + +CHIP_UTILIZATION_UNDER_MEM_REQ 0 -nan 0 -nan + +CHIP_UTILIZATION_UNDER_NO_MEM_REQ 0 -nan 0 -nan + +CHIP_UTILIZATION_UNDER_CRITICAL_MEM_REQ 0 -nan 0 -nan + +CHIP_UTILIZATION_UNDER_NONCRITICAL_MEM_REQ 0 -nan 0 -nan + +CYCLES_NOT_WAITING_FOR_OFF_CHIP 0 0.0000 0 0.0000 + +FUS_BUSY_NOT_WAITING_FOR_OFF_CHIP 0 -nan 0 -nan + +CYCLES_WAITING_FOR_OFF_CHIP 0 0.0000 0 0.0000 + +FUS_BUSY_WAITING_FOR_OFF_CHIP 0 -nan 0 -nan + +TOTAL_OFF_CHIP_DELAYS_LEFT 0 0 + +WRONG_IO_SCHED 0 0 + +DVFS_CONFIG_SWITCH 0 0 + + + diff --git a/labs/LAB5/runs/mcf_s_base-sms1/fetch.stat.0.out b/labs/LAB5/runs/mcf_s_base-sms1/fetch.stat.0.out new file mode 100644 index 00000000..e2a9e050 --- /dev/null +++ b/labs/LAB5/runs/mcf_s_base-sms1/fetch.stat.0.out @@ -0,0 +1,248 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 121548526 Instructions: 100000002 IPC: 0.82272 + +ICACHE_CYCLE 121548526 121548526 + +TCACHE_CYCLE 0 0 + +ICACHE_CYCLE_ONPATH 60241540 49.562% 60241540 49.562% +ICACHE_CYCLE_OFFPATH 61306986 50.438% 61306986 50.438% + 121548526 100.000% 121548526 100.000% + 0.50 0.50 0.50 0.50 + +FETCH_ON_PATH 26679047 100.000% 26679047 100.000% +FETCH_OFF_PATH 0 0.000% 0 0.000% + 26679047 100.000% 26679047 100.000% + 0.00 0.00 0.00 0.00 + +FETCHED_OPS_ON_PATH 0 -nan% 0 -nan% +FETCHED_OPS_OFF_PATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +INST_LOST_WAIT_FOR_MISP_RECOVERY 0 0.000% 0 0.000% +INST_LOST_WAIT_FOR_TIMER 0 0.000% 0 0.000% +INST_LOST_WAIT_FOR_EMPTY_ROB 0 0.000% 0 0.000% +INST_LOST_WAIT_FOR_REDIRECT 10446 0.003% 10446 0.003% +INST_LOST_FETCH 119819899 31.979% 119819899 31.979% +INST_LOST_OFF_PATH 0 0.000% 0 0.000% +INST_LOST_FULL_WINDOW 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_OTHER 9883644 2.638% 9883644 2.638% +INST_LOST_ROB_STALL_WAIT_FOR_RECOVERY 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_REDIRECT 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_GAP_FILL 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_L1_MISS 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_MEMORY 35538 0.009% 35538 0.009% +INST_LOST_ROB_STALL_WAIT_FOR_DC_MISS 204633060 54.616% 204633060 54.616% +INST_LOST_ROB_BLOCK_ISSUE_FULL 0 0.000% 0 0.000% +INST_LOST_ROB_BLOCK_ISSUE_GAP_TOO_LARGE 0 0.000% 0 0.000% +INST_LOST_BREAK_DONT 0 0.000% 0 0.000% +INST_LOST_BREAK_ISSUE_WIDTH 0 0.000% 0 0.000% +INST_LOST_BREAK_CF 0 0.000% 0 0.000% +INST_LOST_BREAK_BTB_MISS 662 0.000% 662 0.000% +INST_LOST_BREAK_ICACHE_MISS 41238 0.011% 41238 0.011% +INST_LOST_BREAK_LINE_END 0 0.000% 0 0.000% +INST_LOST_BREAK_STALL 0 0.000% 0 0.000% +INST_LOST_BREAK_BARRIER 0 0.000% 0 0.000% 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12.888% 15442373 12.888% +ST_OP_CMOV 143289 0.120% 143289 0.120% +ST_OP_LDA 2302780 1.922% 2302780 1.922% +ST_OP_IMEM 42522682 35.489% 42522682 35.489% +ST_OP_IADD 12864851 10.737% 12864851 10.737% +ST_OP_IMUL 199955 0.167% 199955 0.167% +ST_OP_IDIV 93130 0.078% 93130 0.078% +ST_OP_ICMP 10060259 8.396% 10060259 8.396% +ST_OP_LOGIC 6535545 5.454% 6535545 5.454% +ST_OP_SHIFT 418811 0.350% 418811 0.350% +ST_OP_FMEM 0 0.000% 0 0.000% +ST_OP_FCVT 0 0.000% 0 0.000% +ST_OP_FADD 0 0.000% 0 0.000% +ST_OP_FMUL 0 0.000% 0 0.000% +ST_OP_FMA 0 0.000% 0 0.000% +ST_OP_FDIV 0 0.000% 0 0.000% +ST_OP_FCMP 0 0.000% 0 0.000% +ST_OP_FCMOV 0 0.000% 0 0.000% +ST_OP_GATHER 0 0.000% 0 0.000% +ST_OP_SCATTER 0 0.000% 0 0.000% +ST_OP_PIPELINED_FAST 0 0.000% 0 0.000% +ST_OP_PIPELINED_MEDIUM 0 0.000% 0 0.000% +ST_OP_PIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_MEDIUM 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_VERY_SLOW 0 0.000% 0 0.000% + 119819899 100.000% 119819899 100.000% + 5.33 2.81 5.33 2.81 + +ST_NOT_CF 94326795 78.724% 94326795 78.724% +ST_CF_BR 2170929 1.812% 2170929 1.812% +ST_CF_CBR 18715628 15.620% 18715628 15.620% +ST_CF_CALL 47594 0.040% 47594 0.040% +ST_CF_IBR 0 0.000% 0 0.000% +ST_CF_ICALL 2255673 1.883% 2255673 1.883% +ST_CF_ICO 0 0.000% 0 0.000% +ST_CF_RET 2303280 1.922% 2303280 1.922% +ST_CF_SYS 0 0.000% 0 0.000% + 119819899 100.000% 119819899 100.000% + 0.56 1.22 0.56 1.22 + +ST_BAR_NONE 119819899 100.000% 119819899 100.000% +ST_BAR_FETCH 0 0.000% 0 0.000% +ST_BAR_ISSUE 0 0.000% 0 0.000% +ST_BAR_BOTH 0 0.000% 0 0.000% + 119819899 100.000% 119819899 100.000% + 0.00 0.00 0.00 0.00 + +ST_NOT_MEM 77297217 64.511% 77297217 64.511% +ST_MEM_LD 34277566 28.608% 34277566 28.608% +ST_MEM_ST 8245116 6.881% 8245116 6.881% +ST_MEM_PF 0 0.000% 0 0.000% +ST_MEM_WH 0 0.000% 0 0.000% +ST_MEM_EVICT 0 0.000% 0 0.000% + 119819899 100.000% 119819899 100.000% + 0.42 0.52 0.42 0.52 + +ST_NOT_MEM_OFFPATH 0 -nan% 0 -nan% +ST_MEM_LD_OFFPATH 0 -nan% 0 -nan% +ST_MEM_ST_OFFPATH 0 -nan% 0 -nan% +ST_MEM_PF_OFFPATH 0 -nan% 0 -nan% +ST_MEM_WH_OFFPATH 0 -nan% 0 -nan% +ST_MEM_EVIC_OFFPATHT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ST_OP_ONPATH 119819899 119819899 + +ST_OP_OFFPATH 0 0 + +ST_FAKE_OP_OFFPATH 0 -nan% 0 -nan% +ST_NOT_FAKE_OP_OFFPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ST_FAKE_REASON_NOT_FAKE 0 -nan% 0 -nan% +ST_FAKE_REASON_REDIRECT_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_RETURN_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_NONRET_CF_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_NOT_TAKEN_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_WRONG_PATH_STORE_TO_NEW_REGION 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ST_INST_ONPATH 100000028 100000028 + +ST_INST_OFFPATH 0 0 + +STATIC_PIN_NOP 0 0 + +DYNAMIC_PIN_REP_GREATER_256 0 0 + + + diff --git a/labs/LAB5/runs/mcf_s_base-sms1/l2l1pref.stat.0.out b/labs/LAB5/runs/mcf_s_base-sms1/l2l1pref.stat.0.out new file mode 100644 index 00000000..4d793c6b --- /dev/null +++ b/labs/LAB5/runs/mcf_s_base-sms1/l2l1pref.stat.0.out @@ -0,0 +1,140 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 121548526 Instructions: 100000002 IPC: 0.82272 + +L2WAY_FILL_L1 0 0 + +L2WAY_WAY_HIT 0 -nan% 0 -nan% +L2WAY_WAY_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_PREF_REQ 0 0 + +L2WAY_PREF_HIT_DATA_IN_CACHE 0 -nan% 0 -nan% +L2WAY_PREF_HIT_DATA_REQ 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_TRAIN_HIT 0 -nan% 0 -nan% +L2WAY_TRAIN_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L1_HIT_REQ_TYPE_IFETCH 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DFETCH 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DSTORE 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_IPRF 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DPRF 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_WB 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2_ACCESS_INTERVAL__0 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__1 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__2 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__3 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__4 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__5 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__6 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__7 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__8 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_L1INSERT_PORT_FULL 0 -nan% 0 -nan% +L2WAY_L1INSERT_PORT_READY 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2MARKV_NEXT_ADDR_HIT 0 -nan% 0 -nan% +L2MARKV_NEXT_ADDR_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2MARKV_LAST_ADDR_HIT 0 -nan% 0 -nan% +L2MARKV_LAST_ADDR_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +MARKV_L2_TIME_DIFF__0 0 -nan% 0 -nan% +MARKV_L2_TIME_DIFF__1 0 -nan% 0 -nan% +MARKV_L2_TIME_DIFF__2 0 -nan% 0 -nan% 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0 -nan% 0 -nan% +DCACHE_PREF_FETCH_100 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_1000 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_10000 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_100000 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_1000000 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_10000000 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_100000000 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_MORE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_SAME_IP_DELTA__0 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__1 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__2 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__3 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__4 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__5 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__6 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__7 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__8 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_IP_HIT_COUNT__1 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__2 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__3 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__4 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__5 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__6 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__7 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__8 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__9 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + + + diff --git a/labs/LAB5/runs/mcf_s_base-sms1/memory.stat.0.out b/labs/LAB5/runs/mcf_s_base-sms1/memory.stat.0.out new file mode 100644 index 00000000..10c51649 --- /dev/null +++ b/labs/LAB5/runs/mcf_s_base-sms1/memory.stat.0.out @@ -0,0 +1,3416 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 121548526 Instructions: 100000002 IPC: 0.82272 + +ICACHE_MISS 64 0.000% 64 0.000% +ICACHE_HIT 39279756 100.000% 39279756 100.000% + 39279820 100.000% 39279820 100.000% + 1.00 1.00 1.00 1.00 + +ICACHE_MISS_ONPATH 64 100.000% 64 100.000% +ICACHE_MISS_OFFPATH 0 0.000% 0 0.000% + 64 100.000% 64 100.000% + 0.00 0.00 0.00 0.00 + +ICACHE_HIT_ONPATH 39279756 100.000% 39279756 100.000% +ICACHE_HIT_OFFPATH 0 0.000% 0 0.000% + 39279756 100.000% 39279756 100.000% + 0.00 0.00 0.00 0.00 + +ICACHE_HIT_ONPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +ICACHE_HIT_ONPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ICACHE_HIT_OFFPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +ICACHE_HIT_OFFPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DCACHE_MISS 10100419 23.753% 10100419 23.753% +DCACHE_ST_BUFFER_HIT 111003 0.261% 111003 0.261% +DCACHE_HIT 32311246 75.986% 32311246 75.986% + 42522668 100.000% 42522668 100.000% + 1.52 1.39 1.52 1.39 + +DCACHE_MISS_COMPULSORY 345025 0.0342 345025 0.0342 + +DCACHE_MISS_CAPACITY 9754359 0.9657 9754359 0.9657 + +DCACHE_MISS_CONFLICT 1035 0.0001 1035 0.0001 + +DCACHE_MISS_ONPATH 10100419 100.000% 10100419 100.000% +DCACHE_MISS_OFFPATH 0 0.000% 0 0.000% + 10100419 100.000% 10100419 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_ST_BUFFER_HIT_ONPATH 111003 100.000% 111003 100.000% +DCACHE_ST_BUFFER_HIT_OFFPATH 0 0.000% 0 0.000% + 111003 100.000% 111003 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_HIT_ONPATH 32311246 100.000% 32311246 100.000% +DCACHE_HIT_OFFPATH 0 0.000% 0 0.000% + 32311246 100.000% 32311246 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_HIT_ONPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +DCACHE_HIT_ONPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DCACHE_HIT_OFFPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +DCACHE_HIT_OFFPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DCACHE_MISS_LD 9453088 93.591% 9453088 93.591% +DCACHE_MISS_ST 647331 6.409% 647331 6.409% + 10100419 100.000% 10100419 100.000% + 0.06 0.24 0.06 0.24 + +DCACHE_MISS_LD_ONPATH 9453088 100.000% 9453088 100.000% +DCACHE_MISS_LD_OFFPATH 0 0.000% 0 0.000% + 9453088 100.000% 9453088 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_MISS_ST_ONPATH 647331 100.000% 647331 100.000% +DCACHE_MISS_ST_OFFPATH 0 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1555 2.302% 1555 2.302% +CORE_PREF_L1_NOT_USED_DISTANCE_8 3177 4.704% 3177 4.704% +CORE_PREF_L1_NOT_USED_DISTANCE_16 5070 7.506% 5070 7.506% +CORE_PREF_L1_NOT_USED_DISTANCE_32 8855 13.110% 8855 13.110% +CORE_PREF_L1_NOT_USED_DISTANCE_MORE 48612 71.973% 48612 71.973% + 67542 100.000% 67542 100.000% + 5.47 4.75 5.47 4.75 + +CORE_PREF_L1_USED_LATENCY200 347162 20.542% 347162 20.542% +CORE_PREF_L1_USED_LATENCY400 536455 31.742% 536455 31.742% +CORE_PREF_L1_USED_LATENCY600 473174 27.998% 473174 27.998% +CORE_PREF_L1_USED_LATENCY800 208596 12.343% 208596 12.343% +CORE_PREF_L1_USED_LATENCY1000 62373 3.691% 62373 3.691% +CORE_PREF_L1_USED_LATENCY1200 16253 0.962% 16253 0.962% +CORE_PREF_L1_USED_LATENCY1400 9316 0.551% 9316 0.551% +CORE_PREF_L1_USED_LATENCY1600 11310 0.669% 11310 0.669% +CORE_PREF_L1_USED_LATENCY1600MORE 25387 1.502% 25387 1.502% + 1690026 100.000% 1690026 100.000% + 1.64 1.29 1.64 1.29 + +CORE_PREF_L1_USED_DISTANCE_1 0 0.000% 0 0.000% +CORE_PREF_L1_USED_DISTANCE_2 28 0.002% 28 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100.000% + 1.00 1.00 1.00 1.00 + + + diff --git a/labs/LAB5/runs/mcf_s_base-sms1/power.stat.0.out b/labs/LAB5/runs/mcf_s_base-sms1/power.stat.0.out new file mode 100644 index 00000000..587aca1b --- /dev/null +++ b/labs/LAB5/runs/mcf_s_base-sms1/power.stat.0.out @@ -0,0 +1,184 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 121548526 Instructions: 100000002 IPC: 0.82272 + +POWER_STATS_BEGIN 0 0 + +POWER_TIME 37983914375000 37983914375000 + +POWER_CYCLE 121548526 121548526 + +POWER_ITLB_ACCESS 39279820 39279820 + +POWER_DTLB_ACCESS 8245112 8245112 + +POWER_ICACHE_ACCESS 39279820 39279820 + +POWER_ICACHE_MISS 64 64 + +POWER_BTB_READ 39279820 39279820 + +POWER_BTB_WRITE 1174736 1174736 + +POWER_ROB_READ 119819881 119819881 + +POWER_ROB_WRITE 119819881 119819881 + +POWER_RENAME_READ 239639762 239639762 + +POWER_RENAME_WRITE 119819881 119819881 + +POWER_FP_RENAME_READ 0 0 + +POWER_FP_RENAME_WRITE 0 0 + +POWER_FUNCTION_CALL 2303267 2303267 + +POWER_INST_WINDOW_READ 119819881 119819881 + +POWER_INST_WINDOW_WRITE 119819881 119819881 + +POWER_INT_REGFILE_READ 134827876 134827876 + +POWER_INT_REGFILE_WRITE 91432930 91432930 + +POWER_IALU_ACCESS 119526796 119526796 + +POWER_CDB_IALU_ACCESS 119526796 119526796 + +POWER_MUL_ACCESS 293085 293085 + +POWER_CDB_MUL_ACCESS 293085 293085 + +POWER_FP_INST_WINDOW_WRITE 0 0 + +POWER_FP_INST_WINDOW_READ 0 0 + +POWER_FP_REGFILE_READ 0 0 + +POWER_FP_REGFILE_WRITE 0 0 + +POWER_FPU_ACCESS 0 0 + +POWER_CDB_FPU_ACCESS 0 0 + +POWER_DCACHE_READ_ACCESS 38252946 38252946 + +POWER_DCACHE_WRITE_ACCESS 8269836 8269836 + +POWER_DCACHE_READ_MISS 13539480 13539480 + +POWER_DCACHE_WRITE_MISS 672056 672056 + +POWER_MLC_READ_ACCESS 0 0 + +POWER_MLC_WRITE_ACCESS 0 0 + +POWER_MLC_READ_MISS 0 0 + +POWER_MLC_WRITE_MISS 0 0 + +POWER_LLC_READ_ACCESS 8416061 8416061 + +POWER_LLC_WRITE_ACCESS 341471 341471 + +POWER_LLC_READ_MISS 3420834 3420834 + +POWER_LLC_WRITE_MISS 97 97 + +POWER_MEMORY_ACCESS 0 0 + +POWER_MEMORY_READ_ACCESS 0 0 + +POWER_MEMORY_WRITE_ACCESS 0 0 + +POWER_INST_WINDOW_WAKEUP_ACCESS 119819881 119819881 + +POWER_FP_INST_WINDOW_WAKEUP_ACCESS 0 0 + +POWER_L1DIREC_READ_ACCESS 0 0 + +POWER_L1DIREC_WRITE_ACCESS 0 0 + +POWER_L1DIREC_READ_MISS 0 0 + +POWER_L1DIREC_WRITE_MISS 0 0 + +POWER_L2DIREC_READ_ACCESS 0 0 + +POWER_L2DIREC_WRITE_ACCESS 0 0 + +POWER_L2DIREC_READ_MISS 0 0 + +POWER_L2DIREC_WRITE_MISS 0 0 + +POWER_MEMORY_CTRL_ACCESS 3472281 3472281 + +POWER_MEMORY_CTRL_READ 3420834 3420834 + +POWER_MEMORY_CTRL_WRITE 51447 51447 + +POWER_OP 119819881 119819881 + +POWER_INT_OP 116076761 116076761 + +POWER_FP_OP 0 0 + +POWER_LD_OP 34277560 34277560 + +POWER_ST_OP 8245112 8245112 + +POWER_BRANCH_MISPREDICT 1174736 1174736 + +POWER_COMMITTED_OP 119819881 119819881 + +POWER_COMMITTED_INT_OP 116076761 116076761 + +POWER_COMMITTED_FP_OP 3743120 3743120 + +POWER_BRANCH_OP 25493101 25493101 + +POWER_DRAM_PRECHARGE 1599203 1599203 + +POWER_DRAM_ACTIVATE 1648806 1648806 + +POWER_DRAM_READ 3414039 3414039 + +POWER_DRAM_WRITE 51438 51438 + +POWER_STATS_END 0 0 + +ENERGY 0.000000 0.000000 + +ENERGY_CORE 0.000000 0.000000 + +ENERGY_UNCORE 0.000000 0.000000 + +ENERGY_MEMORY 0.000000 0.000000 + +ENERGY_OTHER 0.000000 0.000000 + +ENERGY_CORE_STATIC 0.000000 0.000000 + +ENERGY_CORE_DYNAMIC 0.000000 0.000000 + +ENERGY_UNCORE_STATIC 0.000000 0.000000 + +ENERGY_UNCORE_DYNAMIC 0.000000 0.000000 + +ENERGY_MEMORY_STATIC 0.000000 0.000000 + +ENERGY_MEMORY_DYNAMIC 0.000000 0.000000 + +ENERGY_OTHER_STATIC 0.000000 0.000000 + +ENERGY_OTHER_DYNAMIC 0.000000 0.000000 + +TIME 0.000000 0.000000 + +ENERGY_STATS_END 0 0 + + + diff --git a/labs/LAB5/runs/mcf_s_base-sms1/pref.stat.0.out b/labs/LAB5/runs/mcf_s_base-sms1/pref.stat.0.out new file mode 100644 index 00000000..9aada6c8 --- /dev/null +++ b/labs/LAB5/runs/mcf_s_base-sms1/pref.stat.0.out @@ -0,0 +1,208 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 121548526 Instructions: 100000002 IPC: 0.82272 + +PREF_DL0REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UMLC_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UL1REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_DL0REQ_QUEUE_FULL 0 0 + +PREF_UMLC_REQ_QUEUE_FULL 0 0 + +PREF_UL1REQ_QUEUE_FULL 50 50 + +PREF_DC_HIT_NOSEND 0 0 + +PREF_WBQDC_HIT_NOSEND 0 0 + +PREF_MLCQ_STALL 0 0 + +PREF_L1Q_STALL 0 0 + +PREF_UMLC_REQ_SEND_QUEUE_STALL 0 0 + +PREF_UL1REQ_SEND_QUEUE_STALL 14465999 14465999 + +PREF_UMLC_REQ_QUEUE_SENTREQ 0 0 + +PREF_UL1REQ_QUEUE_SENTREQ 2717464 2717464 + +PREF_NEWREQ_MATCHED 2917 2917 + +PREF_UMLC_REQ_QUEUE_MATCHED_REQ 0 0 + +PREF_UL1REQ_QUEUE_MATCHED_REQ 42622 42622 + +PREF_DL0REQ_QUEUE_MATCHED_REQ 0 0 + +L1_PREF_HIT 2384115 2384115 + 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+L1_LATE_PREF_CYCLES_DIST_1700 42 0.298% 42 0.298% +L1_LATE_PREF_CYCLES_DIST_1800 22 0.156% 22 0.156% +L1_LATE_PREF_CYCLES_DIST_1900 2 0.014% 2 0.014% +L1_LATE_PREF_CYCLES_DIST_2000 3 0.021% 3 0.021% + 14073 100.000% 14073 100.000% + 2.41 2.47 2.41 2.47 + +MLC_PREF_HIT 0 0 + +MLC_PREF_UNIQUE_HIT 0 0 + +MLC_PREF_LATE 0 0 + +PREF_HYBRID_SEL_0 0 -nan% 0 -nan% +PREF_HYBRID_SEL_1 0 -nan% 0 -nan% +PREF_HYBRID_SEL_2 0 -nan% 0 -nan% +PREF_HYBRID_SEL_3 0 -nan% 0 -nan% +PREF_HYBRID_SEL_4 0 -nan% 0 -nan% +PREF_HYBRID_SEL_5 0 -nan% 0 -nan% +PREF_HYBRID_SEL_6 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_DISTANCE_1 0 0.000% 0 0.000% +PREF_DISTANCE_2 0 0.000% 0 0.000% +PREF_DISTANCE_3 0 0.000% 0 0.000% +PREF_DISTANCE_4 1 0.241% 1 0.241% +PREF_DISTANCE_5 414 99.759% 414 99.759% +PREF_DISTANCE_6 0 0.000% 0 0.000% +PREF_DISTANCE_7 0 0.000% 0 0.000% +PREF_DISTANCE_8 0 0.000% 0 0.000% +PREF_DISTANCE_9 0 0.000% 0 0.000% +PREF_DISTANCE_10 0 0.000% 0 0.000% + 415 100.000% 415 100.000% + 4.00 0.05 4.00 0.05 + +PREF_REPL_MRU 0 -nan% 0 -nan% +PREF_REPL_MID 0 -nan% 0 -nan% +PREF_REPL_LOWQTR 0 -nan% 0 -nan% +PREF_REPL_LRU 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_REPL_MOVEDOWN 0 -nan% 0 -nan% +PREF_REPL_MOVEUP 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_COV_1 0 -nan% 0 -nan% +PREF_COV_2 0 -nan% 0 -nan% +PREF_COV_3 0 -nan% 0 -nan% +PREF_COV_4 0 -nan% 0 -nan% +PREF_COV_5 0 -nan% 0 -nan% +PREF_COV_6 0 -nan% 0 -nan% +PREF_COV_7 0 -nan% 0 -nan% +PREF_COV_8 0 -nan% 0 -nan% +PREF_COV_9 0 -nan% 0 -nan% +PREF_COV_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_POL_1 0 0.000% 0 0.000% +PREF_POL_2 0 0.000% 0 0.000% +PREF_POL_3 0 0.000% 0 0.000% +PREF_POL_4 0 0.000% 0 0.000% +PREF_POL_5 0 0.000% 0 0.000% +PREF_POL_6 0 0.000% 0 0.000% +PREF_POL_7 0 0.000% 0 0.000% +PREF_POL_8 0 0.000% 0 0.000% +PREF_POL_9 0 0.000% 0 0.000% +PREF_POL_10 415 100.000% 415 100.000% + 415 100.000% 415 100.000% + 9.00 9.01 9.00 9.01 + +PREF_ACC_1 415 100.000% 415 100.000% +PREF_ACC_2 0 0.000% 0 0.000% +PREF_ACC_3 0 0.000% 0 0.000% +PREF_ACC_4 0 0.000% 0 0.000% +PREF_ACC_5 0 0.000% 0 0.000% +PREF_ACC_6 0 0.000% 0 0.000% +PREF_ACC_7 0 0.000% 0 0.000% +PREF_ACC_8 0 0.000% 0 0.000% +PREF_ACC_9 0 0.000% 0 0.000% +PREF_ACC_10 0 0.000% 0 0.000% + 415 100.000% 415 100.000% + 0.00 0.00 0.00 0.00 + +PREF_TIMELY_1 0 0.000% 0 0.000% +PREF_TIMELY_2 0 0.000% 0 0.000% +PREF_TIMELY_3 0 0.000% 0 0.000% +PREF_TIMELY_4 0 0.000% 0 0.000% +PREF_TIMELY_5 0 0.000% 0 0.000% +PREF_TIMELY_6 0 0.000% 0 0.000% +PREF_TIMELY_7 1 0.241% 1 0.241% +PREF_TIMELY_8 0 0.000% 0 0.000% +PREF_TIMELY_9 2 0.482% 2 0.482% +PREF_TIMELY_10 412 99.277% 412 99.277% + 415 100.000% 415 100.000% + 8.99 8.97 8.99 8.97 + +PREF_UNUSED_EVICT 67542 67542 + +PREF_REGION_SENT 0 0 + +PREF_REGION_USEFUL 0 0 + +PREF_REGION_EVICT 0 0 + +PREF_PFPOL 0 0 + +PREF_PHASE_NEWPHASE_DET 0 0 + +PREF_PHASE_NEWPHASE_NOTVALID 0 0 + +PREF_PHASE_SENTPREF 0 0 + +PREF_PHASE_OVERWRITE_PAGE 0 0 + +PREF_UPDATE_COUNT 415 415 + +PREF_ACC1_HT_HP 0 0.000% 0 0.000% +PREF_ACC1_HT_LP 386 93.012% 386 93.012% +PREF_ACC1_LT_HP 0 0.000% 0 0.000% +PREF_ACC1_LT_LP 29 6.988% 29 6.988% +PREF_ACC2_HT_HP 0 0.000% 0 0.000% +PREF_ACC2_HT_LP 0 0.000% 0 0.000% +PREF_ACC2_LT_HP 0 0.000% 0 0.000% +PREF_ACC2_LT_LP 0 0.000% 0 0.000% +PREF_ACC3_HT_HP 0 0.000% 0 0.000% +PREF_ACC3_HT_LP 0 0.000% 0 0.000% +PREF_ACC3_LT_HP 0 0.000% 0 0.000% +PREF_ACC3_LT_LP 0 0.000% 0 0.000% +PREF_ACC4_HT_HP 0 0.000% 0 0.000% +PREF_ACC4_HT_LP 0 0.000% 0 0.000% +PREF_ACC4_LT_HP 0 0.000% 0 0.000% +PREF_ACC4_LT_LP 0 0.000% 0 0.000% + 415 100.000% 415 100.000% + 1.14 0.51 1.14 0.51 + + + diff --git a/labs/LAB5/runs/mcf_s_base-sms1/ramulator.stat.out b/labs/LAB5/runs/mcf_s_base-sms1/ramulator.stat.out new file mode 100644 index 00000000..d2b163b9 --- /dev/null +++ b/labs/LAB5/runs/mcf_s_base-sms1/ramulator.stat.out @@ -0,0 +1,150 @@ + ramulator.active_cycles_0 27626317 # Total active cycles for level _0 + ramulator.busy_cycles_0 27626317 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0 + ramulator.serving_requests_0 139172482 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.average_serving_requests_0 3.053319 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.active_cycles_0_0 27626317 # Total active cycles for level _0_0 + ramulator.busy_cycles_0_0 28806517 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0 + ramulator.serving_requests_0_0 139172482 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.average_serving_requests_0_0 3.053319 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.active_cycles_0_0_0 17432583 # Total active cycles for level _0_0_0 + ramulator.busy_cycles_0_0_0 17432583 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0 + ramulator.serving_requests_0_0_0 34413933 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 +ramulator.average_serving_requests_0_0_0 0.755011 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 + ramulator.active_cycles_0_0_0_0 6323105 # Total active cycles for level _0_0_0_0 + ramulator.busy_cycles_0_0_0_0 6323105 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_0 + ramulator.serving_requests_0_0_0_0 7943624 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 +ramulator.average_serving_requests_0_0_0_0 0.174276 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 + ramulator.active_cycles_0_0_0_1 6554340 # Total active cycles for level _0_0_0_1 + ramulator.busy_cycles_0_0_0_1 6554340 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_1 + ramulator.serving_requests_0_0_0_1 8057398 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 +ramulator.average_serving_requests_0_0_0_1 0.176772 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 + ramulator.active_cycles_0_0_0_2 6792577 # Total active cycles for level _0_0_0_2 + ramulator.busy_cycles_0_0_0_2 6792577 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_2 + ramulator.serving_requests_0_0_0_2 8481635 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 +ramulator.average_serving_requests_0_0_0_2 0.186079 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 + ramulator.active_cycles_0_0_0_3 8165919 # Total active cycles for level _0_0_0_3 + ramulator.busy_cycles_0_0_0_3 8165919 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_3 + ramulator.serving_requests_0_0_0_3 9931276 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 +ramulator.average_serving_requests_0_0_0_3 0.217883 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 + ramulator.active_cycles_0_0_1 17776100 # Total active cycles for level _0_0_1 + ramulator.busy_cycles_0_0_1 17776100 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1 + ramulator.serving_requests_0_0_1 34567844 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 +ramulator.average_serving_requests_0_0_1 0.758387 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 + ramulator.active_cycles_0_0_1_0 5538143 # Total active cycles for level _0_0_1_0 + ramulator.busy_cycles_0_0_1_0 5538143 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_0 + ramulator.serving_requests_0_0_1_0 7051891 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 +ramulator.average_serving_requests_0_0_1_0 0.154712 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 + ramulator.active_cycles_0_0_1_1 5639646 # Total active cycles for level _0_0_1_1 + ramulator.busy_cycles_0_0_1_1 5639646 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_1 + ramulator.serving_requests_0_0_1_1 7173187 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 +ramulator.average_serving_requests_0_0_1_1 0.157373 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 + ramulator.active_cycles_0_0_1_2 9160823 # Total active cycles for level _0_0_1_2 + ramulator.busy_cycles_0_0_1_2 9160823 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_2 + ramulator.serving_requests_0_0_1_2 11002576 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 +ramulator.average_serving_requests_0_0_1_2 0.241387 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 + ramulator.active_cycles_0_0_1_3 7561416 # Total active cycles for level _0_0_1_3 + ramulator.busy_cycles_0_0_1_3 7561416 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_3 + ramulator.serving_requests_0_0_1_3 9340190 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 +ramulator.average_serving_requests_0_0_1_3 0.204915 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 + ramulator.active_cycles_0_0_2 17293990 # Total active cycles for level _0_0_2 + ramulator.busy_cycles_0_0_2 17293990 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2 + ramulator.serving_requests_0_0_2 34334760 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 +ramulator.average_serving_requests_0_0_2 0.753274 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 + ramulator.active_cycles_0_0_2_0 7206363 # Total active cycles for level _0_0_2_0 + ramulator.busy_cycles_0_0_2_0 7206363 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_0 + ramulator.serving_requests_0_0_2_0 8962446 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 +ramulator.average_serving_requests_0_0_2_0 0.196628 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 + ramulator.active_cycles_0_0_2_1 7262459 # Total active cycles for level _0_0_2_1 + ramulator.busy_cycles_0_0_2_1 7262459 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_1 + ramulator.serving_requests_0_0_2_1 8868277 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 +ramulator.average_serving_requests_0_0_2_1 0.194562 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 + ramulator.active_cycles_0_0_2_2 6426184 # Total active cycles for level _0_0_2_2 + ramulator.busy_cycles_0_0_2_2 6426184 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_2 + ramulator.serving_requests_0_0_2_2 8011149 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 +ramulator.average_serving_requests_0_0_2_2 0.175757 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 + ramulator.active_cycles_0_0_2_3 6869315 # Total active cycles for level _0_0_2_3 + ramulator.busy_cycles_0_0_2_3 6869315 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_3 + ramulator.serving_requests_0_0_2_3 8492888 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 +ramulator.average_serving_requests_0_0_2_3 0.186326 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 + ramulator.active_cycles_0_0_3 17609202 # Total active cycles for level _0_0_3 + ramulator.busy_cycles_0_0_3 17609202 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3 + ramulator.serving_requests_0_0_3 35855945 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 +ramulator.average_serving_requests_0_0_3 0.786647 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 + ramulator.active_cycles_0_0_3_0 6699419 # Total active cycles for level _0_0_3_0 + ramulator.busy_cycles_0_0_3_0 6699419 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_0 + ramulator.serving_requests_0_0_3_0 8231766 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 +ramulator.average_serving_requests_0_0_3_0 0.180598 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 + ramulator.active_cycles_0_0_3_1 8116353 # Total active cycles for level _0_0_3_1 + ramulator.busy_cycles_0_0_3_1 8116353 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_1 + ramulator.serving_requests_0_0_3_1 9841922 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 +ramulator.average_serving_requests_0_0_3_1 0.215923 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 + ramulator.active_cycles_0_0_3_2 7558016 # Total active cycles for level _0_0_3_2 + ramulator.busy_cycles_0_0_3_2 7558016 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_2 + ramulator.serving_requests_0_0_3_2 9177831 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 +ramulator.average_serving_requests_0_0_3_2 0.201353 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 + ramulator.active_cycles_0_0_3_3 6997065 # Total active cycles for level _0_0_3_3 + ramulator.busy_cycles_0_0_3_3 6997065 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_3 + ramulator.serving_requests_0_0_3_3 8604426 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 +ramulator.average_serving_requests_0_0_3_3 0.188773 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 + ramulator.read_transaction_bytes_0 218498496 # The total byte of read transaction per channel + ramulator.write_transaction_bytes_0 3292032 # The total byte of write transaction per channel + ramulator.row_hits_channel_0_core 1816811 # Number of row hits per channel per core + ramulator.row_misses_channel_0_core 126297 # Number of row misses per channel per core + ramulator.row_conflicts_channel_0_core 1522369 # Number of row conflicts per channel per core + ramulator.read_row_hits_channel_0_core 1784357 # Number of row hits for read requests per channel per core + [0] 1784357.0 # +ramulator.read_row_misses_channel_0_core 124616 # Number of row misses for read requests per channel per core + [0] 124616.0 # +ramulator.read_row_conflicts_channel_0_core 1505066 # Number of row conflicts for read requests per channel per core + [0] 1505066.0 # + ramulator.write_row_hits_channel_0_core 32454 # Number of row hits for write requests per channel per core + [0] 32454.0 # +ramulator.write_row_misses_channel_0_core 1681 # Number of row misses for write requests per channel per core + [0] 1681.0 # +ramulator.write_row_conflicts_channel_0_core 17303 # Number of row conflicts for write requests per channel per core + [0] 17303.0 # + ramulator.useless_activates_0_core 147 # Number of useless activations. E.g, ACT -> PRE w/o RD or WR + ramulator.read_latency_avg_0 125.298980 # The average memory latency cycles (in memory time domain) per request for all read requests in this channel + ramulator.read_latency_sum_0 428627012 # The memory latency cycles (in memory time domain) sum for all read requests in this channel + ramulator.req_queue_length_avg_0 23.681642 # Average of read and write queue length per memory cycle per channel. + ramulator.req_queue_length_sum_0 1079426196 # Sum of read and write queue length per memory cycle per channel. + ramulator.read_req_queue_length_avg_0 8.801184 # Read queue length average per memory cycle per channel. + ramulator.read_req_queue_length_sum_0 401164260 # Read queue length sum per memory cycle per channel. + ramulator.write_req_queue_length_avg_0 14.880458 # Write queue length average per memory cycle per channel. + ramulator.write_req_queue_length_sum_0 678261936 # Write queue length sum per memory cycle per channel. + ramulator.record_read_hits 0.0 # record read hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_misses 0.0 # record_read_miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_conflicts 0.0 # record read conflict count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_hits 0.0 # record write hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_misses 0.0 # record write miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_conflicts 0.0 # record write conflict for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.dram_capacity 8589934592 # Number of bytes in simulated DRAM + ramulator.dram_cycles 45580715 # Number of DRAM cycles simulated + ramulator.incoming_requests 3472281 # Number of incoming requests to DRAM + ramulator.read_requests 3420834 # Number of incoming read requests to DRAM per core + [0] 3420834.0 # + ramulator.write_requests 51447 # Number of incoming write requests to DRAM per core + [0] 51447.0 # + ramulator.ramulator_active_cycles 27626317 # The total number of cycles that the DRAM part is active (serving R/W) + ramulator.incoming_requests_per_channel 3472281.0 # Number of incoming requests to each DRAM channel + [0] 3472281.0 # +ramulator.incoming_read_reqs_per_channel 3420834.0 # Number of incoming read requests to each DRAM channel + [0] 3420834.0 # + ramulator.physical_page_replacement 0 # The number of times that physical page replacement happens. + ramulator.maximum_bandwidth 19200000000 # The theoretical maximum bandwidth (Bps) + ramulator.in_queue_req_num_sum 1079426196 # Sum of read/write queue length + ramulator.in_queue_read_req_num_sum 401164260 # Sum of read queue length + ramulator.in_queue_write_req_num_sum 678261936 # Sum of write queue length + ramulator.in_queue_req_num_avg 23.681642 # Average of read/write queue length per memory cycle + ramulator.in_queue_read_req_num_avg 8.801184 # Average of read queue length per memory cycle + ramulator.in_queue_write_req_num_avg 14.880458 # Average of write queue length per memory cycle + ramulator.record_read_requests 0.0 # record read requests for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_requests 0.0 # record write requests for this core when it reaches request limit or to the end + [0] 0.0 # diff --git a/labs/LAB5/runs/mcf_s_base-sms1/run.err b/labs/LAB5/runs/mcf_s_base-sms1/run.err new file mode 100644 index 00000000..e69de29b diff --git a/labs/LAB5/runs/mcf_s_base-sms1/run.out b/labs/LAB5/runs/mcf_s_base-sms1/run.out new file mode 100644 index 00000000..198ce7e5 --- /dev/null +++ b/labs/LAB5/runs/mcf_s_base-sms1/run.out @@ -0,0 +1,107 @@ +Scarab gitrev: 7ab9e17 +Scarab started at Sun Jun 11 08:08:38 2023 + +Initialized Ramulator. +** Heartbeat: 1% -- { 1000003 } -- 0.00 KIPS (333.33 KIPS) +** Heartbeat: 2% -- { 2000007 } -- 250.00 KIPS (285.72 KIPS) +** Heartbeat: 3% -- { 3000007 } -- 500.00 KIPS (333.33 KIPS) +** Heartbeat: 4% -- { 4000009 } -- 333.33 KIPS (333.33 KIPS) +** Heartbeat: 5% -- { 5000012 } -- 333.33 KIPS (333.33 KIPS) +** Heartbeat: 6% -- { 6000014 } -- 333.33 KIPS (333.33 KIPS) +** Heartbeat: 7% -- { 7000015 } -- 333.33 KIPS (333.33 KIPS) +** Heartbeat: 8% -- { 8000018 } -- 333.33 KIPS (333.33 KIPS) +** Heartbeat: 9% -- { 9000018 } -- 333.33 KIPS (333.33 KIPS) +** Heartbeat: 10% -- { 10000022 } -- 333.33 KIPS (333.33 KIPS) +** Heartbeat: 11% -- { 11000023 } -- 333.33 KIPS (333.33 KIPS) +** Heartbeat: 12% -- { 12000023 } -- 333.33 KIPS (333.33 KIPS) +** Heartbeat: 13% -- { 13000023 } -- 333.33 KIPS (333.33 KIPS) +** Heartbeat: 14% -- { 14000025 } -- 333.33 KIPS (333.33 KIPS) +** Heartbeat: 15% -- { 15000025 } -- 500.00 KIPS (340.91 KIPS) +** Heartbeat: 16% -- { 16000027 } -- 250.00 KIPS (333.33 KIPS) +** Heartbeat: 17% -- { 17000027 } -- 333.33 KIPS (333.33 KIPS) +** Heartbeat: 18% -- { 18000028 } -- 500.00 KIPS (339.62 KIPS) +** Heartbeat: 19% -- { 19000031 } -- 333.33 KIPS (339.29 KIPS) +** Heartbeat: 20% -- { 20000032 } -- 333.33 KIPS (338.98 KIPS) +** Heartbeat: 21% -- { 21000037 } -- 333.33 KIPS (338.71 KIPS) +** Heartbeat: 22% -- { 22000040 } -- 333.33 KIPS (338.46 KIPS) +** Heartbeat: 23% -- { 23000041 } -- 333.33 KIPS (338.24 KIPS) +** Heartbeat: 24% -- { 24000041 } -- 333.33 KIPS (338.03 KIPS) +** Heartbeat: 25% -- { 25000042 } -- 333.33 KIPS (337.84 KIPS) +** Heartbeat: 26% -- { 26000042 } -- 500.00 KIPS (342.11 KIPS) +** Heartbeat: 27% -- { 27000047 } -- 333.33 KIPS (341.77 KIPS) +** Heartbeat: 28% -- { 28000047 } -- 333.33 KIPS (341.46 KIPS) +** Heartbeat: 29% -- { 29000049 } -- 333.33 KIPS (341.18 KIPS) +** Heartbeat: 30% -- { 30000049 } -- 333.33 KIPS (340.91 KIPS) +** Heartbeat: 31% -- { 31000053 } -- 333.33 KIPS (340.66 KIPS) +** Heartbeat: 32% -- { 32000055 } -- 333.33 KIPS (340.43 KIPS) +** Heartbeat: 33% -- { 33000055 } -- 333.33 KIPS (340.21 KIPS) +** Heartbeat: 34% -- { 34000057 } -- 333.33 KIPS (340.00 KIPS) +** Heartbeat: 35% -- { 35000061 } -- 500.00 KIPS (343.14 KIPS) +** Heartbeat: 36% -- { 36000063 } -- 250.00 KIPS (339.62 KIPS) +** Heartbeat: 37% -- { 37000066 } -- 333.33 KIPS (339.45 KIPS) +** Heartbeat: 38% -- { 38000069 } -- 500.00 KIPS (342.34 KIPS) +** Heartbeat: 39% -- { 39000074 } -- 333.33 KIPS (342.11 KIPS) +** Heartbeat: 40% -- { 40000076 } -- 333.33 KIPS (341.88 KIPS) +** Heartbeat: 41% -- { 41000079 } -- 333.33 KIPS (341.67 KIPS) +** Heartbeat: 42% -- { 42000081 } -- 333.33 KIPS (341.46 KIPS) +** Heartbeat: 43% -- { 43000084 } -- 333.33 KIPS (341.27 KIPS) +** Heartbeat: 44% -- { 44000086 } -- 333.33 KIPS (341.09 KIPS) +** Heartbeat: 45% -- { 45000087 } -- 333.33 KIPS (340.91 KIPS) +** Heartbeat: 46% -- { 46000087 } -- 333.33 KIPS (340.74 KIPS) +** Heartbeat: 47% -- { 47000088 } -- 500.00 KIPS (343.07 KIPS) +** Heartbeat: 48% -- { 48000090 } -- 250.00 KIPS (340.43 KIPS) +** Heartbeat: 49% -- { 49000090 } -- 333.33 KIPS (340.28 KIPS) +** Heartbeat: 50% -- { 50000091 } -- 500.00 KIPS (342.47 KIPS) +** Heartbeat: 51% -- { 51000094 } -- 333.33 KIPS (342.28 KIPS) +** Heartbeat: 52% -- { 52000099 } -- 333.33 KIPS (342.11 KIPS) +** Heartbeat: 53% -- { 53000099 } -- 333.33 KIPS (341.94 KIPS) +** Heartbeat: 54% -- { 54000102 } -- 333.33 KIPS (341.77 KIPS) +** Heartbeat: 55% -- { 55000102 } -- 333.33 KIPS (341.62 KIPS) +** Heartbeat: 56% -- { 56000105 } -- 333.33 KIPS (341.46 KIPS) +** Heartbeat: 57% -- { 57000107 } -- 333.33 KIPS (341.32 KIPS) +** Heartbeat: 58% -- { 58000109 } -- 333.33 KIPS (341.18 KIPS) +** Heartbeat: 59% -- { 59000111 } -- 500.00 KIPS (343.02 KIPS) +** Heartbeat: 60% -- { 60000111 } -- 333.33 KIPS (342.86 KIPS) +** Heartbeat: 61% -- { 61000112 } -- 333.33 KIPS (342.70 KIPS) +** Heartbeat: 62% -- { 62000112 } -- 333.33 KIPS (342.54 KIPS) +** Heartbeat: 63% -- { 63000112 } -- 333.33 KIPS (342.39 KIPS) +** Heartbeat: 64% -- { 64000113 } -- 333.33 KIPS (342.25 KIPS) +** Heartbeat: 65% -- { 65000113 } -- 333.33 KIPS (342.11 KIPS) +** Heartbeat: 66% -- { 66000114 } -- 333.33 KIPS (341.97 KIPS) +** Heartbeat: 67% -- { 67000114 } -- 333.33 KIPS (341.84 KIPS) +** Heartbeat: 68% -- { 68000117 } -- 333.33 KIPS (341.71 KIPS) +** Heartbeat: 69% -- { 69000117 } -- 333.33 KIPS (341.58 KIPS) +** Heartbeat: 70% -- { 70000120 } -- 333.33 KIPS (341.46 KIPS) +** Heartbeat: 71% -- { 71000120 } -- 500.00 KIPS (343.00 KIPS) +** Heartbeat: 72% -- { 72000124 } -- 333.33 KIPS (342.86 KIPS) +** Heartbeat: 73% -- { 73000127 } -- 333.33 KIPS (342.72 KIPS) +** Heartbeat: 74% -- { 74000131 } -- 333.33 KIPS (342.59 KIPS) +** Heartbeat: 75% -- { 75000135 } -- 333.33 KIPS (342.47 KIPS) +** Heartbeat: 76% -- { 76000139 } -- 500.00 KIPS (343.89 KIPS) +** Heartbeat: 77% -- { 77000142 } -- 333.33 KIPS (343.75 KIPS) +** Heartbeat: 78% -- { 78000142 } -- 333.33 KIPS (343.61 KIPS) +** Heartbeat: 79% -- { 79000142 } -- 333.33 KIPS (343.48 KIPS) +** Heartbeat: 80% -- { 80000143 } -- 333.33 KIPS (343.35 KIPS) +** Heartbeat: 81% -- { 81000143 } -- 500.00 KIPS (344.68 KIPS) +** Heartbeat: 82% -- { 82000145 } -- 250.00 KIPS (343.10 KIPS) +** Heartbeat: 83% -- { 83000148 } -- 333.33 KIPS (342.98 KIPS) +** Heartbeat: 84% -- { 84000148 } -- 500.00 KIPS (344.26 KIPS) +** Heartbeat: 85% -- { 85000148 } -- 333.33 KIPS (344.13 KIPS) +** Heartbeat: 86% -- { 86000148 } -- 333.33 KIPS (344.00 KIPS) +** Heartbeat: 87% -- { 87000148 } -- 333.33 KIPS (343.87 KIPS) +** Heartbeat: 88% -- { 88000153 } -- 333.33 KIPS (343.75 KIPS) +** Heartbeat: 89% -- { 89000153 } -- 333.33 KIPS (343.63 KIPS) +** Heartbeat: 90% -- { 90000157 } -- 333.33 KIPS (343.51 KIPS) +** Heartbeat: 91% -- { 91000160 } -- 333.33 KIPS (343.40 KIPS) +** Heartbeat: 92% -- { 92000163 } -- 500.00 KIPS (344.57 KIPS) +** Heartbeat: 93% -- { 93000163 } -- 333.33 KIPS (344.45 KIPS) +** Heartbeat: 94% -- { 94000164 } -- 333.33 KIPS (344.32 KIPS) +** Heartbeat: 95% -- { 95000169 } -- 333.33 KIPS (344.20 KIPS) +** Heartbeat: 96% -- { 96000170 } -- 333.33 KIPS (344.09 KIPS) +** Heartbeat: 97% -- { 97000172 } -- 333.33 KIPS (343.97 KIPS) +** Heartbeat: 98% -- { 98000172 } -- 500.00 KIPS (345.07 KIPS) +** Heartbeat: 99% -- { 99000172 } -- 333.33 KIPS (344.95 KIPS) +** Core 0 Finished: insts:100000002 cycles:121548526 time:37983914375000 -- 0.82 IPC (0.82 IPC) -- N/A KIPS (344.83 KIPS) +done +Scarab finished at Sun Jun 11 08:13:28 2023 + diff --git a/labs/LAB5/runs/mcf_s_base-sms1/stream.stat.0.out b/labs/LAB5/runs/mcf_s_base-sms1/stream.stat.0.out new file mode 100644 index 00000000..3d155486 --- /dev/null +++ b/labs/LAB5/runs/mcf_s_base-sms1/stream.stat.0.out @@ -0,0 +1,188 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 121548526 Instructions: 100000002 IPC: 0.82272 + +DCACHE_PREF_HIT 0 0 + +IFETCH_WB_FIRST_SCHEDULE 0 -nan% 0 -nan% +PREFETCH_LAST_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_PREF_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_LOW_OP_SCHEDULE 0 -nan% 0 -nan% +DEMAND_LAST_SCHEDULE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +SEND_MISS_REQ_QUEUE 3420834 3420834 + +L1_DATA_EVICT 3404547 3404547 + +STREAM_BUFFER_REQ 0 0 + +PREF_SEND_TO_MEM_REQ 0 -nan% 0 -nan% +PREF_SEND_TO_MEM_REQ_FAIL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +HIT_TRAIN_STREAM 1830382 52.025% 1830382 52.025% +MISS_TRAIN_STREAM 1687900 47.975% 1687900 47.975% + 3518282 100.000% 3518282 100.000% + 0.48 0.49 0.48 0.49 + +STREAM_TRAIN_CREATE 1632003 1632003 + +MEM_REQ_MISS_HWP_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_SW_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_IFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DSTORE_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DPRF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_WB_Q 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_BY_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_WB 0 -nan% 0 -nan% +PREF_HIT_BY_PREF 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_WB 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_L1_FILL 0 -nan% 0 -nan% +DEMAND_L1_FILL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TOUCH_L1_REPLACE 0 0.000% 0 0.000% +NO_TOUCH_L1_REPLACE 3404547 100.000% 3404547 100.000% + 3404547 100.000% 3404547 100.000% + 1.00 1.00 1.00 1.00 + +PREF_REQ_QUE_FULL 0 0 + +STREAM_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +L2HIT_STREAM_PREF_REQ_QUE_FULL 0 0 + +L2HIT_HIT_TRAIN_STREAM 0 -nan% 0 -nan% +L2HIT_MISS_TRAIN_STREAM 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_TRAIN_CREATE 0 0 + +L2HIT_STREAM_BUFFER_REQ 0 0 + +L2HIT_STREAM_PREF_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_STREAM_PREF_DCACHE_INSERT 0 -nan% 0 -nan% +L2HIT_STREAM_L2_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_DCACHE_PORT_FULL 0 0 + +L2HIT_STREAM_PREF_L1_PORT_FULL 0 0 + +L2HIT_TRAIN_HIT_DEMAND 0 -nan% 0 -nan% +L2HIT_TRAIN_MISS_REQ 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_TRAIN_FILTER_MISS 0 -nan% 0 -nan% +L2HIT_TRAIN_FILTER_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_PREF_REQ_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_PREF_REQ_DCACHE_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_L2SEND_Q_FULL 0 -nan% 0 -nan% +L2HIT_L2SEND_Q_ENTER 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_MEM_REQ 0 0 + +REMOVE_REDUNDANT_STREAM_STAT 0 0 + +REPLACE_OLD_STREAM 1631987 1631987 + +REQ_SEND_QUEUE_STALL 0 0 + +STREAM_ENTER_RA 0 0 + +CORE_STREAM_LENGTH_0 285 4.227% 285 4.227% +CORE_STREAM_LENGTH_10 1060 15.722% 1060 15.722% +CORE_STREAM_LENGTH_20 589 8.736% 589 8.736% +CORE_STREAM_LENGTH_30 334 4.954% 334 4.954% +CORE_STREAM_LENGTH_40 162 2.403% 162 2.403% +CORE_STREAM_LENGTH_50 138 2.047% 138 2.047% +CORE_STREAM_LENGTH_60 152 2.255% 152 2.255% +CORE_STREAM_LENGTH_70 143 2.121% 143 2.121% +CORE_STREAM_LENGTH_80 203 3.011% 203 3.011% +CORE_STREAM_LENGTH_90 210 3.115% 210 3.115% +CORE_STREAM_LENGTH_100_P 3466 51.409% 3466 51.409% + 6742 100.000% 6742 100.000% + 6.62 6.03 6.62 6.03 + +CORE_CUM_STREAM_LENGTH_0 2169 0.077% 2169 0.077% +CORE_CUM_STREAM_LENGTH_10 14452 0.512% 14452 0.512% +CORE_CUM_STREAM_LENGTH_20 14194 0.503% 14194 0.503% +CORE_CUM_STREAM_LENGTH_30 11273 0.400% 11273 0.400% +CORE_CUM_STREAM_LENGTH_40 7110 0.252% 7110 0.252% +CORE_CUM_STREAM_LENGTH_50 7487 0.265% 7487 0.265% +CORE_CUM_STREAM_LENGTH_60 9822 0.348% 9822 0.348% +CORE_CUM_STREAM_LENGTH_70 10651 0.378% 10651 0.378% +CORE_CUM_STREAM_LENGTH_80 17223 0.611% 17223 0.611% +CORE_CUM_STREAM_LENGTH_90 19886 0.705% 19886 0.705% +CORE_CUM_STREAM_LENGTH_100_P 2706311 95.949% 2706311 95.949% + 2820578 100.000% 2820578 100.000% + 9.81 9.67 9.81 9.67 + +CORE_STREAM_TRAIN_HITS_0 1995 29.591% 1995 29.591% +CORE_STREAM_TRAIN_HITS_10 753 11.169% 753 11.169% +CORE_STREAM_TRAIN_HITS_20 586 8.692% 586 8.692% +CORE_STREAM_TRAIN_HITS_30 420 6.230% 420 6.230% +CORE_STREAM_TRAIN_HITS_40 489 7.253% 489 7.253% +CORE_STREAM_TRAIN_HITS_50 624 9.255% 624 9.255% +CORE_STREAM_TRAIN_HITS_60 105 1.557% 105 1.557% +CORE_STREAM_TRAIN_HITS_70 110 1.632% 110 1.632% +CORE_STREAM_TRAIN_HITS_80 113 1.676% 113 1.676% +CORE_STREAM_TRAIN_HITS_90 131 1.943% 131 1.943% +CORE_STREAM_TRAIN_HITS_100_P 1416 21.003% 1416 21.003% + 6742 100.000% 6742 100.000% + 3.84 3.67 3.84 3.67 + +CORE_CUM_STREAM_TRAIN_HITS_0 12163 0.655% 12163 0.655% +CORE_CUM_STREAM_TRAIN_HITS_10 10186 0.548% 10186 0.548% +CORE_CUM_STREAM_TRAIN_HITS_20 14389 0.775% 14389 0.775% +CORE_CUM_STREAM_TRAIN_HITS_30 14330 0.772% 14330 0.772% +CORE_CUM_STREAM_TRAIN_HITS_40 22359 1.204% 22359 1.204% +CORE_CUM_STREAM_TRAIN_HITS_50 32546 1.752% 32546 1.752% +CORE_CUM_STREAM_TRAIN_HITS_60 6733 0.363% 6733 0.363% +CORE_CUM_STREAM_TRAIN_HITS_70 8175 0.440% 8175 0.440% +CORE_CUM_STREAM_TRAIN_HITS_80 9545 0.514% 9545 0.514% +CORE_CUM_STREAM_TRAIN_HITS_90 12216 0.658% 12216 0.658% +CORE_CUM_STREAM_TRAIN_HITS_100_P 1714708 92.320% 1714708 92.320% + 1857350 100.000% 1857350 100.000% + 9.56 9.31 9.56 9.31 + +CORE_STREAM_TRAIN_CREATE 1632003 1632003 + + + diff --git a/labs/LAB5/runs/omnetpp-sms0/PARAMS.in b/labs/LAB5/runs/omnetpp-sms0/PARAMS.in new file mode 100644 index 00000000..2593c2b8 --- /dev/null +++ b/labs/LAB5/runs/omnetpp-sms0/PARAMS.in @@ -0,0 +1,226 @@ +# File : PARAMS.kaby_lake +# Date : 03/06/19 +# Description : Kaby Lake Configuration +# +# Based on documentation found here: +# https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake + +## Simulation Parameters +--mode full +--model cmp +--sim_limit none + +## Core Parameters + +# Femptoseconds, 3.2GHz, used for energy estimates. +--chip_cycle_time 312500 + + +### Fetch Stage +--fetch_off_path_ops 1 +--fetch_across_cache_lines 1 + +# Will break the packet upon a taken branch. +--fetch_break_on_taken 1 + +# Number of bubble cycles to wait after taken branch. +--fetch_taken_bubble_cycles 0 + + +#### ICache +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 + +### Branch Predictor +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_mech tagescl + + +#### BTB + +# BTB model to use. +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 + +# Allow the BTB to be updated by off path ops. +--btb_off_path_writes 1 + + +#### CRS + +# Enable return stack +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 + +### iBP +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged + # iBTB Model. tc_tagless, tc_tagged, tc_hybrid. +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 + +### Decode Stage +--decode_cycles 5 + + +### Map Stage +--map_cycles 5 + + +### Issue Stage + +# Max number of instructions to be fetched, decoded, renamed, and issued per cycle. +--issue_width 6 + +--rs_fill_width 0 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 + + +### Exec Stage + +### DCache +--dcache_size 32768 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--dcache_assoc 4 +--dcache_line_size 64 + +### Reorder/Retire Stage + +# Max number of instructions to be retired per cycle. +--node_ret_width 6 +--node_table_size 224 + +# Do not keep stores in RSVs on cache misses; TODO: confirm what this knob does +--stores_do_not_block_window 1 + +# TODO: confirm what this knob does +--prefs_do_not_block_window 1 + + +## Uncore + +### Mid-level cache + +# Enable use of a midlevel cache between i/d and L1 +--mlc_present 0 + +### LLC +--l1_size 1048576 +--l1_banks 1 +--l1_cycles 18 +--l1_assoc 8 +--l1_line_size 64 +--l1_interleave_factor 64 + + +### Prefetcher +--pref_framework_on 1 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--pref_shared_queues 0 +--pref_train_on_pref_misses 0 +--pref_oracle_train 0 +--pref_ul1req_queue_overwrite_on_full 1 + +--stream_length 64 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 + +--pref_throttlefb_on=1 +--pref_acc_thresh_1=0.75 +--pref_acc_thresh_2=0.4 +--pref_acc_thresh_3=0.4 +--pref_timely_thresh=0.01 +--pref_polpf_thresh=0.005 +--pref_update_interval=8192 + +--mem_req_buffer_pref_watermark 4 +--promote_to_higher_priority_mem_req_type 1 + +### Memory +--addr_translation random + +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 + +--mem_req_buffer_entries 32 +--mem_l1_fill_queue_entries 32 +--va_page_size_bytes 4096 +--bus_width_in_bytes 8 + +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 + +## Other + + +### Debug +--debug_inst_start 0 +--debug_inst_stop -1 +--debug_cycle_start 0 +--debug_cycle_stop -1 + + +## Stats and Params +--dump_params 1 +--dump_stats 1 +--dump_trace 0 + +#################################### +--set_off_path_confirmed 1 + +--order_beyond_bus 1 + +--mem_ooo_stores 1 +--mem_obey_store_dep 1 diff --git a/labs/LAB5/runs/omnetpp-sms0/PARAMS.out b/labs/LAB5/runs/omnetpp-sms0/PARAMS.out new file mode 100644 index 00000000..7ded6def --- /dev/null +++ b/labs/LAB5/runs/omnetpp-sms0/PARAMS.out @@ -0,0 +1,908 @@ +--mode full +--model cmp +--frontend memtrace +--inst_limit 100000000 +--sim_limit none +--dump_params 1 +--dump_stats 1 +--dump_trace 0 +--mlc_present 0 +--l1_size 1048576 +--l1_assoc 8 +--l1_line_size 64 +--l1_cycles 18 +--l1_banks 1 +--l1_interleave_factor 64 +--va_page_size_bytes 4096 +--addr_translation random +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 +--dcache_size 32768 +--dcache_assoc 4 +--dcache_line_size 64 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--mem_ooo_stores 1 +--mem_obey_store_dep 1 +--mem_req_buffer_entries 32 +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 +--promote_to_higher_priority_mem_req_type 1 +--mem_req_buffer_pref_watermark 4 +--mem_l1_fill_queue_entries 32 +--order_beyond_bus 1 +--set_off_path_confirmed 1 +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--bus_width_in_bytes 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 +--chip_cycle_time 312500 +--issue_width 6 +--rs_fill_width 0 +--node_table_size 224 +--node_ret_width 6 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 +--decode_cycles 5 +--map_cycles 5 +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--fetch_across_cache_lines 1 +--fetch_off_path_ops 0 +--fetch_break_on_taken 1 +--fetch_taken_bubble_cycles 0 +--stores_do_not_block_window 1 +--prefs_do_not_block_window 1 +--cbp_trace_r0 /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir/trace/drmemtrace.omnetpp.552936.3514.trace.gz +--memtrace_modules_log /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir/raw +--debug_cycle_start 0 +--debug_cycle_stop -1 +--debug_inst_start 0 +--debug_inst_stop -1 +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--bp_mech tagescl +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 +--btb_off_path_writes 1 +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_length 64 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 +--pref_framework_on 1 +--pref_shared_queues 0 +--pref_ul1req_queue_overwrite_on_full 1 +--pref_train_on_pref_misses 0 +--pref_oracle_train_on 0 +--pref_throttlefb_on 1 +--pref_acc_thresh_1 0.75 +--pref_acc_thresh_2 0.4 +--pref_acc_thresh_3 0.4 +--pref_update_interval 8192 +--pref_timely_thresh 0.01 +--pref_polpf_thresh 0.005 +--pref_sms_on 0 +1 1 1 1 1 1 1 + +--- Cut out everything below to use this file as PARAMS.in --- + +Parameter status at compile time and values supplied on the command line: + +SIM_MODE 0 full +SIM_MODEL 0 cmp +FRONTEND FE_PIN_EXEC_DRIVEN memtrace +INST_LIMIT NULL 100000000 +SIM_LIMIT "none" none +FORWARD_PROGRESS_LIMIT 100000000 +FORWARD_PROGRESS_INTERVAL 10000 +FAST_FORWARD 0 +FAST_FORWARD_UNTIL_ADDR 0 +FAST_FORWARD_TRACE_INS 0 +WARMUP 0 +HEARTBEAT_INTERVAL 1000000 +NUM_HEARTBEATS 0 +FILE_TAG "" +OUTPUT_DIR "." +STATUS_FILE NULL +BINDIR NULL +DUMP_PARAMS TRUE 1 +DUMP_STATS TRUE 1 +DUMP_TRACE FALSE 0 +CLEAR_STATS "never" +STATS_TO_TRACE NULL +STAT_TRACE_FILE "stats.trace" +STAT_TRACE_INTERVAL "i:100000" +PIPEVIEW FALSE +PIPEVIEW_FILE "pipeview" +MEMVIEW FALSE +MEMVIEW_FILE "memview.out" +MEMVIEW_START "never" +INST_HASH_TABLE_SIZE 500021 const +STDOUT_FILE NULL +STDERR_FILE NULL +PIN_EXEC_DRIVEN_FE_SOCKET "./pin_exec_driven_fe_socket.temp" +PRINT_PID FALSE +USE_UNSURE_FREE_LISTS FALSE +OPTIMIZER2_MAX_NUM_SLAVES 64 +OPTIMIZER2_PERFECT_MEMORYLESS FALSE +EXIT_COND 0 +ENABLE_SWPRF FALSE +MLC_PRESENT FALSE 0 +MLC_SIZE (512 * 1024) +MLC_ASSOC 4 +MLC_LINE_SIZE 64 +MLC_CYCLES 12 +PERFECT_MLC FALSE +MLC_READ_PORTS 1 +MLC_WRITE_PORTS 1 +MLC_BANKS 8 +MLC_INTERLEAVE_FACTOR 64 +MLC_CACHE_REPL_POLICY 0 +MLC_WRITE_THROUGH FALSE +PREFETCH_UPDATE_LRU_MLC TRUE +FORCE_L1_MISS FALSE +L1_SIZE (4 * 1024 * 1024) 1048576 +L1_ASSOC 8 8 +L1_LINE_SIZE 64 64 +L1_CYCLES 24 18 +PERFECT_L1 FALSE +PRIVATE_L1 FALSE +L1_READ_PORTS 1 +L1_WRITE_PORTS 1 +L1_BANKS 8 1 +L1_INTERLEAVE_FACTOR 64 64 +L1_CACHE_REPL_POLICY 0 +L1_WRITE_THROUGH FALSE +L1_IGNORE_WB FALSE +L1_USE_CORE_FREQ FALSE +MARK_L1_MISSES TRUE +PREFETCH_UPDATE_LRU_L1 TRUE +MEMORY_RANDOM_ADDR FALSE +VA_PAGE_SIZE_BYTES 4096 4096 +NUM_ADDR_NON_SIGN_EXTEND_BITS 48 +ADDR_TRANSLATION 0 random +CONSTANT_MEMORY_LATENCY FALSE +MEMORY_CYCLES 100 +STALL_MEM_REQS_ONLY FALSE +ICACHE_SIZE (64 * 1024) 32768 +ICACHE_ASSOC 4 4 +ICACHE_LINE_SIZE 64 64 +PERFECT_ICACHE FALSE +ICACHE_READ_PORTS 2 +ICACHE_WRITE_PORTS 1 +ICACHE_BANKS 8 +ICACHE_REPL 0 +DCACHE_SIZE (64 * 1024) 32768 +DCACHE_ASSOC 1 4 +DCACHE_LINE_SIZE 64 64 +DCACHE_CYCLES 2 +PERFECT_DCACHE FALSE +DCACHE_READ_PORTS 8 2 +DCACHE_WRITE_PORTS 1 1 +DCACHE_BANKS 1 1 +DCACHE_REPL 0 +DCACHE_REPL_PREF_THRESH 1 +MEM_OOO_STORES TRUE 1 +MEM_OBEY_STORE_DEP TRUE 1 +PREF_INSERT_LRU FALSE +PREF_INSERT_MIDDLE FALSE +PREF_INSERT_LOWQTR FALSE +PREF_INSERT_DYNACC FALSE +MEM_REQ_BUFFER_ENTRIES 32 32 +PRIVATE_MSHR_ON TRUE +MEM_PRIORITY_IFETCH 0 0 +MEM_PRIORITY_DFETCH 0 1 +MEM_PRIORITY_DSTORE 0 2 +MEM_PRIORITY_IPRF 9 3 +MEM_PRIORITY_DPRF 10 4 +MEM_PRIORITY_WB 0 5 +MEM_PRIORITY_WB_NODIRTY 0 5 +PROMOTE_TO_HIGHER_PRIORITY_MEM_REQ_TYPE FALSE 1 +MEM_REQ_BUFFER_PREF_WATERMARK 0 4 +MEM_REQ_BUFFER_WB_VALVE 2 +MEM_L1_FILL_QUEUE_ENTRIES 32 32 +MEM_BUS_OUT_QUEUE_PARTITION_ENABLE FALSE +MEM_MEM_QUEUE_PARTITION_ENABLE FALSE +MEM_BUS_OUT_QUEUE_AS_FIFO TRUE +OLDEST_FIRST_TO_MEM_QUEUE TRUE +ROUND_ROBIN_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE_TH 0 +L1_CYCLE_TIME 312500 +MLCQ_TO_L1Q_TRANSFER_LATENCY 1 +L1Q_TO_FSB_TRANSFER_LATENCY 1 +PRIORITIZE_PREFETCHES_WITH_UNIQUE FALSE +KICKOUT_PREFETCHES FALSE +KICKOUT_LOOK_FOR_OLDEST_FIRST FALSE +KICKOUT_OLDEST_PREFETCH FALSE +KICKOUT_OLDEST_PREFETCH_WITHIN_BANK FALSE +ORDER_BEYOND_BUS FALSE 1 +ALL_FIFO_QUEUES FALSE +QUEUE_MLC_SIZE 0 +QUEUE_L1_SIZE 0 +QUEUE_BUS_OUT_SIZE 0 +QUEUE_CORE_FILL_SIZE 0 +ALLOW_TYPE_MATCHES FALSE +STREAM_PREFETCH_ON FALSE +DC_PREF_CACHE_ENABLE FALSE +DC_PREF_CACHE_CYCLE 0 +PREF_INSERT_DCACHE_IMM TRUE +DC_PREF_CACHE_SIZE (64 * 1024) +DC_PREF_CACHE_ASSOC 4 +DC_PREF_ONLY_L1HIT FALSE +PREF_CACHE_USE_RDY_CYCLE FALSE +IC_PREF_CACHE_ENABLE FALSE +IC_PREF_CACHE_SIZE (64 * 1024) +IC_PREF_CACHE_ASSOC 4 +L1_PREF_CACHE_ENABLE FALSE +L1_PREF_CACHE_SIZE (1024 * 1024) +L1_PREF_CACHE_ASSOC 8 +SET_OFF_PATH_CONFIRMED FALSE 1 +USE_CONFIRMED_OFF FALSE +PREFCACHE_MOVE_OFFPATH FALSE +CACHE_STAT_ENABLE FALSE +PREF_DCACHE_HIT_FILL_L1 TRUE +PREF_ICACHE_HIT_FILL_L1 TRUE +CRITICAL_ACCESS_PLOT_ENABLE FALSE +CRITICAL_ACCESS_PLOT_FILE "critical_access_plot.dat" +ROUND_ROBIN_TO_L1 FALSE +PREF_I_TOGETHER FALSE +ONE_MORE_CACHE_LINE_ENABLE FALSE +L1_STATIC_PARTITION_ENABLE 0 +L1_STATIC_PARTITION NULL +L1_DYNAMIC_PARTITION_ENABLE FALSE +L1_DYNAMIC_PARTITION_POLICY 0 +PARTITION_UMON_DSS_PREF_ENABLE FALSE +L1_CACHE_HIT_POSITION_COLLECT FALSE +L1_PART_ON FALSE +L1_PART_TRIGGER "c:1000000" +L1_PART_START "t:0" +L1_PART_WARMUP FALSE +L1_PART_SHADOW_WARMUP FALSE +L1_PART_METRIC 0 +L1_PART_SEARCH 0 +L1_PART_USE_STALLING TRUE +L1_PART_FILL_DELAY 0 +L1_SHADOW_TAGS_MODULO 1 +HIER_MSHR_ON FALSE +PERF_PRED_ENABLE FALSE +PERF_PRED_MECH PERF_PRED_CP +PERF_PRED_REQ_LATENCY_MECH PERF_PRED_REQ_LATENCY_MECH_REQ_LATENCY +PERF_PRED_COUNT_ALL FALSE +PERF_PRED_COUNT_INST_MISSES TRUE +PERF_PRED_COUNT_PREFETCHES FALSE +PERF_PRED_COUNT_OFFPATH_REQS FALSE +PERF_PRED_COUNT_BW_REQS TRUE +PERF_PRED_UPDATE_MEM_REQ_TYPE FALSE +PERF_PRED_SLACK_PERIOD_SIZE 32 +PERF_PRED_REQS_FINISH_AT_FILL FALSE +PERF_PRED_MEM_UTIL_VIA_BUS_BW FALSE +PERF_PRED_CHIP_UTIL_VIA_MEM_STALL FALSE +DUMB_MODEL_AVG_REQ_DISTANCE 100 +DUMB_MODEL_RANDOMIZE_DISTANCE FALSE +DUMB_MODEL_AVG_REQ_DISTANCE_PER_CORE NULL +DUMB_MODEL_AVG_ROW_HITS 1 +DUMB_MODEL_AVG_ROW_HITS_PER_CORE NULL +DUMB_MODEL_MLP 1 +DUMB_MODEL_MLP_PER_CORE NULL +RAMULATOR_STANDARD "DDR4" DDR4 +RAMULATOR_SPEED "DDR4_2400R" DDR4_2400R +RAMULATOR_ORG "DDR4_8Gb_x8" DDR4_8Gb_x8 +RAMULATOR_CHANNELS 1 1 +RAMULATOR_RANKS 1 1 +RAMULATOR_BANKGROUPS 4 4 +RAMULATOR_BANKS 4 4 +RAMULATOR_CHIP_WIDTH 8 8 +BUS_WIDTH_IN_BYTES 8 8 +RAMULATOR_ROWS 65536 65536 +RAMULATOR_COLS 1024 1024 +RAMULATOR_SCHEDULING_POLICY "FRFCFS_Cap" FRFCFS_Cap +RAMULATOR_READQ_ENTRIES 32 32 +RAMULATOR_WRITEQ_ENTRIES 32 32 +RAMULATOR_REC_CMD_TRACE "off" FALSE +RAMULATOR_PRINT_CMD_TRACE "off" FALSE +RAMULATOR_USE_REST_OF_ADDR_AS_ROW_ADDR "on" +RAMULATOR_TCK 833333 833333 +RAMULATOR_TCL 16 16 +RAMULATOR_TCCD 6 6 +RAMULATOR_TCCDS 4 4 +RAMULATOR_TCCDL 6 6 +RAMULATOR_TCWL 12 12 +RAMULATOR_TBL 4 4 +RAMULATOR_TWTR 9 9 +RAMULATOR_TWTRS 3 3 +RAMULATOR_TWTRL 9 9 +RAMULATOR_TRP 16 16 +RAMULATOR_TRPpb 16 16 +RAMULATOR_TRPab 16 16 +RAMULATOR_TRCD 16 16 +RAMULATOR_TRCDR 16 16 +RAMULATOR_TRCDW 16 16 +RAMULATOR_TRAS 39 39 +DRAM_TECH_IN_NM 32 32 +DVFS_ON FALSE +DVFS_METRIC DVFS_METRIC_NUM_ELEMS +DVFS_CONFIGS NULL +DVFS_CONFIG_FILE NULL +DVFS_START "t:0" +DVFS_PERIOD "t:312500000000" +DVFS_LOG TRUE +DVFS_INDIVIDUAL_CORES FALSE +DVFS_CHIP_LEVEL FALSE +DVFS_STATIC NULL +DVFS_FORCE_CONFIG NULL +DVFS_REPLAY_CONFIG_TRACE NULL +DVFS_USE_ORACLE FALSE +DVFS_USE_BW_SHARING FALSE +DVFS_USE_DRAM_SHARING FALSE +DVFS_USE_STALL_TIME FALSE +DVFS_DRAM_SHARING_SOLVER_BIN NULL +DVFS_DRAM_SHARING_SOLVER_STRICT TRUE +DVFS_BW_SHARING_BUS_UTIL_THRESH 0.95 +DVFS_BW_SHARING_MAX_REQS 28.0 +DVFS_BW_SHARING_MAX_RW_COST 0.25 +DVFS_BW_SHARING_NO_PREF_STALL TRUE +DVFS_BW_SHARING_CRIT_STATS TRUE +DVFS_COUNT_L1_ACCESS_STALL FALSE +NUM_CORES 1 +CHIP_CYCLE_TIME 312500 312500 +CORE_0_CYCLE_TIME 312500 +CORE_1_CYCLE_TIME 312500 +CORE_2_CYCLE_TIME 312500 +CORE_3_CYCLE_TIME 312500 +CORE_4_CYCLE_TIME 312500 +CORE_5_CYCLE_TIME 312500 +CORE_6_CYCLE_TIME 312500 +CORE_7_CYCLE_TIME 312500 +CORE_8_CYCLE_TIME 312500 +CORE_9_CYCLE_TIME 312500 +CORE_10_CYCLE_TIME 312500 +CORE_11_CYCLE_TIME 312500 +CORE_12_CYCLE_TIME 312500 +CORE_13_CYCLE_TIME 312500 +CORE_14_CYCLE_TIME 312500 +CORE_15_CYCLE_TIME 312500 +CORE_16_CYCLE_TIME 312500 +CORE_17_CYCLE_TIME 312500 +CORE_18_CYCLE_TIME 312500 +CORE_19_CYCLE_TIME 312500 +CORE_20_CYCLE_TIME 312500 +CORE_21_CYCLE_TIME 312500 +CORE_22_CYCLE_TIME 312500 +CORE_23_CYCLE_TIME 312500 +CORE_24_CYCLE_TIME 312500 +CORE_25_CYCLE_TIME 312500 +CORE_26_CYCLE_TIME 312500 +CORE_27_CYCLE_TIME 312500 +CORE_28_CYCLE_TIME 312500 +CORE_29_CYCLE_TIME 312500 +CORE_30_CYCLE_TIME 312500 +CORE_31_CYCLE_TIME 312500 +CORE_32_CYCLE_TIME 312500 +CORE_33_CYCLE_TIME 312500 +CORE_34_CYCLE_TIME 312500 +CORE_35_CYCLE_TIME 312500 +CORE_36_CYCLE_TIME 312500 +CORE_37_CYCLE_TIME 312500 +CORE_38_CYCLE_TIME 312500 +CORE_39_CYCLE_TIME 312500 +CORE_40_CYCLE_TIME 312500 +CORE_41_CYCLE_TIME 312500 +CORE_42_CYCLE_TIME 312500 +CORE_43_CYCLE_TIME 312500 +CORE_44_CYCLE_TIME 312500 +CORE_45_CYCLE_TIME 312500 +CORE_46_CYCLE_TIME 312500 +CORE_47_CYCLE_TIME 312500 +CORE_48_CYCLE_TIME 312500 +CORE_49_CYCLE_TIME 312500 +CORE_50_CYCLE_TIME 312500 +CORE_51_CYCLE_TIME 312500 +CORE_52_CYCLE_TIME 312500 +CORE_53_CYCLE_TIME 312500 +CORE_54_CYCLE_TIME 312500 +CORE_55_CYCLE_TIME 312500 +CORE_56_CYCLE_TIME 312500 +CORE_57_CYCLE_TIME 312500 +CORE_58_CYCLE_TIME 312500 +CORE_59_CYCLE_TIME 312500 +CORE_60_CYCLE_TIME 312500 +CORE_61_CYCLE_TIME 312500 +CORE_62_CYCLE_TIME 312500 +CORE_63_CYCLE_TIME 312500 +ISSUE_WIDTH 4 6 +RS_FILL_WIDTH 8 0 +NODE_TABLE_SIZE 256 224 +NODE_RET_WIDTH 4 6 +NODE_RETIRE_RATE 10 +RS_SIZES "256" 97 +RS_CONNECTIONS "xF" 0 +FU_TYPES "0, 0, 0, 0" 0 0 0 0 0 0 0 0 +DECODE_CYCLES 1 5 +MAP_CYCLES 1 5 +EXTRA_RECOVERY_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after recovery. +EXTRA_REDIRECT_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after redirect. +EXTRA_CALLSYS_CYCLES 20 const +DIE_ON_CALLSYS FALSE +DIE_ON_RET_STALL_THRESH 0 +DIE_ON_RET_STALL_CORE 0 +DIE_ON_MEM_BLOCK_THRESH 0 +DIE_ON_MEM_BLOCK_CORE 0 +FETCH_ACROSS_CACHE_LINES FALSE 1 +FETCH_OFF_PATH_OPS TRUE 0 +FETCH_BREAK_ON_TAKEN FALSE 1 +FETCH_TAKEN_BUBBLE_CYCLES 0 0 +WP_COLLECT_STATS FALSE +SWITCH_IC_FETCH_ON_RECOVERY TRUE +OP_INV_DELAY 1 +OP_NOP_DELAY 1 +OP_CF_DELAY 1 +OP_MOV_DELAY 1 +OP_CMOV_DELAY 1 +OP_LDA_DELAY 1 +OP_IMEM_DELAY 1 +OP_IADD_DELAY 1 +OP_IMUL_DELAY 3 +OP_IDIV_DELAY -20 +OP_ICMP_DELAY 1 +OP_LOGIC_DELAY 1 +OP_SHIFT_DELAY 1 +OP_FMEM_DELAY 1 +OP_FCVT_DELAY 3 +OP_FADD_DELAY 3 +OP_FMUL_DELAY 5 +OP_FMA_DELAY 5 +OP_FDIV_DELAY -20 +OP_FCMP_DELAY 3 +OP_FCMOV_DELAY 1 +OP_GATHER_DELAY 12 +OP_SCATTER_DELAY 18 +OP_PIPELINED_FAST_DELAY 2 +OP_PIPELINED_MEDIUM_DELAY 5 +OP_PIPELINED_SLOW_DELAY 10 +OP_NOTPIPELINED_MEDIUM_DELAY -5 +OP_NOTPIPELINED_SLOW_DELAY -20 +OP_NOTPIPELINED_VERY_SLOW_DELAY -100 +UNIFORM_OP_DELAY 0 +STALL_ON_WAIT_MEM TRUE +STORES_DO_NOT_BLOCK_WINDOW FALSE 1 +PREFS_DO_NOT_BLOCK_WINDOW FALSE 1 +OBEY_REG_DEP TRUE +OLDEST_FIRST_SCHED FALSE +FIND_EMPTIEST_RS FALSE +TRACK_L1_MISS_DEPS FALSE +CBP_TRACE_R0 NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir/trace/drmemtrace.omnetpp.552936.3514.trace.gz +CBP_TRACE_R1 NULL +CBP_TRACE_R2 NULL +CBP_TRACE_R3 NULL +CBP_TRACE_R4 NULL +CBP_TRACE_R5 NULL +CBP_TRACE_R6 NULL +CBP_TRACE_R7 NULL +CBP_TRACE_R8 NULL +CBP_TRACE_R9 NULL +CBP_TRACE_R10 NULL +CBP_TRACE_R11 NULL +CBP_TRACE_R12 NULL +CBP_TRACE_R13 NULL +CBP_TRACE_R14 NULL +CBP_TRACE_R15 NULL +CBP_TRACE_R16 NULL +CBP_TRACE_R17 NULL +CBP_TRACE_R18 NULL +CBP_TRACE_R19 NULL +CBP_TRACE_R20 NULL +CBP_TRACE_R21 NULL +CBP_TRACE_R22 NULL +CBP_TRACE_R23 NULL +CBP_TRACE_R24 NULL +CBP_TRACE_R25 NULL +CBP_TRACE_R26 NULL +CBP_TRACE_R27 NULL +CBP_TRACE_R28 NULL +CBP_TRACE_R29 NULL +CBP_TRACE_R30 NULL +CBP_TRACE_R31 NULL +CBP_TRACE_R32 NULL +CBP_TRACE_R33 NULL +CBP_TRACE_R34 NULL +CBP_TRACE_R35 NULL +CBP_TRACE_R36 NULL +CBP_TRACE_R37 NULL +CBP_TRACE_R38 NULL +CBP_TRACE_R39 NULL +CBP_TRACE_R40 NULL +CBP_TRACE_R41 NULL +CBP_TRACE_R42 NULL +CBP_TRACE_R43 NULL +CBP_TRACE_R44 NULL +CBP_TRACE_R45 NULL +CBP_TRACE_R46 NULL +CBP_TRACE_R47 NULL +CBP_TRACE_R48 NULL +CBP_TRACE_R49 NULL +CBP_TRACE_R50 NULL +CBP_TRACE_R51 NULL +CBP_TRACE_R52 NULL +CBP_TRACE_R53 NULL +CBP_TRACE_R54 NULL +CBP_TRACE_R55 NULL +CBP_TRACE_R56 NULL +CBP_TRACE_R57 NULL +CBP_TRACE_R58 NULL +CBP_TRACE_R59 NULL +CBP_TRACE_R60 NULL +CBP_TRACE_R61 NULL +CBP_TRACE_R62 NULL +CBP_TRACE_R63 NULL +MEMTRACE_MODULES_LOG NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir/raw +DUMB_CORE_ON FALSE +DUMB_CORE 1 +DEBUG_CYCLE_START 0 0 +DEBUG_CYCLE_STOP 0 -1 +DEBUG_TIME_START 0 +DEBUG_TIME_STOP 0 +DEBUG_INST_START 0 0 +DEBUG_INST_STOP 0 -1 +DEBUG_OP_START 0 +DEBUG_OP_STOP 0 +DEBUG_CACHE_LIB FALSE +DEBUG_HASH_LIB FALSE +DEBUG_LIST_LIB FALSE +DEBUG_PORT_LIB FALSE +DEBUG_BUS_LIB FALSE +DEBUG_OP_POOL FALSE +DEBUG_ORACLE FALSE +DEBUG_FRONTEND FALSE +DEBUG_ADDR_TRANS FALSE +DEBUG_BP FALSE +DEBUG_BP_DIR FALSE +DEBUG_BTB FALSE +DEBUG_CRS FALSE +DEBUG_MAP FALSE +DEBUG_MEMORY FALSE +DEBUG_REPLAY FALSE +DEBUG_FREQ FALSE +DEBUG_MODEL FALSE +DEBUG_THREAD FALSE +DEBUG_ICACHE_STAGE FALSE +DEBUG_DECODE_STAGE FALSE +DEBUG_MAP_STAGE FALSE +DEBUG_NODE_STAGE FALSE +DEBUG_EXEC_STAGE FALSE +DEBUG_DCACHE_STAGE FALSE +DEBUG_RETIRED_UOPS FALSE +DEBUG_EXC_INSERTS FALSE +DEBUG_BP_CONF FALSE +DEBUG_ONPATH_CONF FALSE +DEBUG_STREAM FALSE +DEBUG_STREAM_MEM FALSE +DEBUG_WAY FALSE +DEBUG_L2MARKV FALSE +DEBUG_L2L1PREF FALSE +DEBUG_PERF_PRED FALSE +DEBUG_POWER_UTILS FALSE +DEBUG_DVFS FALSE +DEBUG_TRACE_READ FALSE +DEBUG_INST_FIELDS FALSE +DEBUG_OP_FIELDS FALSE +DEBUG_PIN_EXEC_DRIVEN FALSE +DEBUG_CACHE_PART FALSE +DEBUG_OPTIMIZER2 FALSE +DEBUG_PREF FALSE +PERFECT_BP FALSE +PERFECT_BTB FALSE +PERFECT_IBP FALSE +PERFECT_CRS FALSE +PERFECT_CBR_BTB FALSE +PERFECT_NT_BTB FALSE +CFS_PER_CYCLE 3 6 # Number of branches that can be predicted in a single cycle +UPDATE_BP_OFF_PATH FALSE 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +BP_UPDATE_AT_RETIRE FALSE 0 # Update the BP at retire. If false, update at the end of exec. +BP_MECH 0 tagescl +LATE_BP_MECH NUM_BP +LATE_BP_LATENCY 5 +HIST_LENGTH 16 +PHT_CTR_BITS 2 const +BHT_ENTRIES (4 * 1024) +BHT_ASSOC 4 +HYBRIDS_INDEX_LENGTH 16 +HYBRIDG_HIST_LENGTH 16 +HYBRIDP_HIST_LENGTH 16 +FILTER_INDEX_LENGTH 16 +USE_FILTER FALSE +INF_HYBRIDGP FALSE +BP_HASH_TOS FALSE +IBTB_HASH_TOS FALSE +BTB_MECH 0 generic +BTB_ENTRIES (4 * 1024) 4096 +BTB_ASSOC 4 4 +BTB_OFF_PATH_WRITES TRUE 1 +ENABLE_CRS TRUE 1 +CRS_ENTRIES 32 32 +CRS_REALISTIC 0 1 +ENABLE_IBP TRUE 1 # Enable the indirect branch predictor +USE_PAT_HIST TRUE +IBTB_MECH 1 tc_tagged +IBTB_HIST_LENGTH 16 +IBTB_OFF_PATH_WRITES TRUE 1 # Allow off path ops to update the ibtb. +TARGETS_IN_HIST 4 +TC_ENTRIES (4 * 1024) 4096 +TC_ASSOC 4 4 +NUM_CORR_BRANCHES 3 +SEL_HIST_BP_ENTRIES 8192 +SEL_HIST_LENGTH 16 +SEL_HIST_DYN_CNT_TH 16 +SEL_HIST_MISPRED_TH 4 +ENABLE_BP_CONF FALSE +CONF_MECH 0 +PERF_BP_CONF_PRED FALSE +BPC_BITS 16 +BPC_MECH 1 +BPC_CTR_RESET TRUE +BPC_CIT_BITS 8 +BPC_CIT_TH 50 +BPC_CTR_BITS 3 +OPC_COUNT_ZEROS FALSE +OPC_COUNT_THRESH 10 +INF_LOOP FALSE +INF_LOOP_BUCKETS 811 +LOOP_ENTRIES (4 * 1024) +LOOP_ASSOC 4 +LOOP_COUNT_MAX 127 +LOOP_REPEAT_MAX 15 +KNOB_PRINT_BRINFO FALSE +BR_MISPRED_FILE NULL +CONF_PERCEPTRON_TH 0 +CONF_PERCEPTRON_CTR_BITS 8 +CONF_PERCEPTRON_ENTRIES 127 +CONF_PERCEPTRON_THRESH_OVRD 0 +CONF_HIST_LENGTH 32 +PERCEPTRON_CONF_USE_CONF FALSE +PERCEPTRON_CONF_TRAIN_HIS FALSE +PERCEPTRON_CONF_TRAIN_CONF FALSE +PERCEPTRON_CONF_TRAIN_OFFSET_CONF FALSE +PERCEPTRON_TRAIN_MISP_FACTOR 1 +PERCEPTRON_TRAIN_CORR_FACTOR 1 +PERCEPTRON_CONF_HIS_BOTH FALSE +PERCEPTRON_CONF_HIS_BOTH_LENGTH 4 +ENABLE_ICACHE_PACKET_BREAKING TRUE +NUM_LOAD_STORE_PER_PACKET 0 +PACKET_BREAK_ON_FUS FALSE +PACKET_BREAK_FU_TYPES "G,G,G,G,G,G,G,G,G,G,G,G" +POWER_INTF_ON FALSE +POWER_INTF_ENABLE_SCALING FALSE +POWER_INTF_EXEC "power/power_intf.py" +POWER_INTF_REF_CHIP_TECH_NM 22 +POWER_INTF_REF_CHIP_FREQ (3.2e9) +POWER_INTF_REF_MEMORY_FREQ (0.8e9) +POWER_OTHER (0.0) +PREF_STREAM_ON FALSE 1 +PREF_STREAM_PER_CORE_ENABLE FALSE 1 +STREAM_BUFFER_N 16 +STREAM_PREFETCH_N 2 4 +STREAM_START_DIS 5 1 +STREAM_LENGTH 16 64 +STREAM_FULL_N 1 +STREAM_TRAIN_LENGTH 16 +STREAM_TRAIN_NUM 1 4 +PREF_ACC_USE_CACHE FALSE +STREAM_STALL_ON_QUEUE_FULL FALSE +PREF_SCHEDULE_NUM 4 +TRAIN_FILTER_SIZE 32 +PREF_REQ_Q_SIZE 64 +STREAM_CREATE_ON_DC_MISS FALSE 0 +STREAM_CREATE_ON_L1_MISS TRUE 1 +STREAM_TRAIN_ON_WRONGPATH TRUE +STREAM_CREATE_ON_WRONGPATH TRUE +STREAM_PREF_INTO_DCACHE FALSE +REMOVE_REDUNDANT_STREAM FALSE +L2HIT_STREAM_SCHEDULE_NUM 4 +PREF_REQ_QUEUE_FILTER_ON FALSE +HW_PREF_HIT_TRAIN_STREAM FALSE +L2HIT_STREAM_BUFFER_N 32 +L2HIT_STREAM_PREFETCH_N 2 +L2HIT_STREAM_START_DIS 2 +L2HIT_STREAM_LENGTH 8 +L2HIT_PREF_REQ_Q_SIZE 128 +L2HIT_L2ACCESS_REQ_Q_SIZE 64 +PREF_STREAM_ACCPERSTREAM FALSE +PREF_ACC_DISTANCE_10 128 +PREF_FRAMEWORK_ON FALSE 1 +PREF_TRACE_ON FALSE +PREF_DL0REQ_QUEUE_SIZE 32 +PREF_UMLC_REQ_QUEUE_SIZE 64 +PREF_UL1REQ_QUEUE_SIZE 128 +PREF_SHARED_QUEUES TRUE 0 +PREF_DL0_MISS_ON TRUE +PREF_DL0_HIT_ON TRUE +PREF_DL0REQ_QUEUE_FILTER_ON TRUE +PREF_UMLC_REQ_QUEUE_FILTER_ON TRUE +PREF_UL1REQ_QUEUE_FILTER_ON TRUE +PREF_DL0REQ_ADD_FILTER_ON TRUE +PREF_UMLC_REQ_ADD_FILTER_ON TRUE +PREF_UL1REQ_ADD_FILTER_ON TRUE +PREF_DL0REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UMLC_REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UL1REQ_QUEUE_OVERWRITE_ON_FULL FALSE 1 +PREF_DL0SCHEDULE_NUM 4 +PREF_UMLC_SCHEDULE_NUM 4 +PREF_UL1SCHEDULE_NUM 4 +PREF_L1Q_DEMAND_RESERVE 0 +PREF_REPORT_PREF_MATCH_AS_MISS FALSE +PREF_REPORT_PREF_MATCH_AS_HIT TRUE +PREF_UPDATE_ON_WRONGPATH TRUE +PREF_TRAIN_ON_PREF_MISSES FALSE 0 +PREF_ORACLE_TRAIN_ON FALSE 0 +PREF_REQ_DROP FALSE +PREF_THROTTLE_ON FALSE +PREF_THROTTLEFB_ON FALSE 1 +PREF_ACC_THRESH_1 0.90 0.75 +PREF_ACC_THRESH_2 0.70 0.4 +PREF_ACC_THRESH_3 0.60 0.4 +PREF_ACC_THRESH_4 0.40 +PREF_UPDATE_INTERVAL 0 8192 +PREF_ANALYZE_LOAD FALSE +PREF_POL_THRESH_1 0.25 +PREF_POL_THRESH_2 0.10 +PREF_POLBV_ON FALSE +PREF_POLBV_SIZE 1024 +PREF_TIMELY_THRESH 0.05 0.01 +PREF_POLPF_THRESH 0.01 0.005 +PREF_DEGFB_USEONLYACC FALSE +PREF_DEGFB_USEONLYPOL FALSE +PREF_DEGFB_USEONLYLATE FALSE +PREF_TIMELY_THRESH_2 0.005 +PREF_DEGFB_STATPHASEFILE FALSE +PREF_MAX_DEGFB 4 +PREF_DHAL FALSE +PREF_DHAL_SENTTHRESH 16 +PREF_DHAL_USETHRESH_MAX 12 +PREF_DHAL_USETHRESH_MIN2 8 +PREF_DHAL_USETHRESH_MIN1 4 +PREF_DHAL_MAXDEG 64 +PREF_HFILTER_ON FALSE +PREF_HFILTER_INDEX_BITS 12 +PREF_HFILTER_USE_PC FALSE +PREF_HFILTER_PRED_USELESS_THRES 2 +PREF_HFILTER_RESET_ENABLE FALSE +PREF_HFILTER_RESET_INTERVAL 100000 +L2L1PREF_ON FALSE +L2WAY_PREF FALSE +L2MARKV_PREF_ON FALSE +L2NEXT_PREF_ON FALSE +L2HIT_STREAM_PREF_ON FALSE +L2L1_DC_HIT_TRAIN FALSE +L1_HIT_DUMP_FILE_ON FALSE +L1_HIT_DUMP_WO_TXT FALSE +L1_HIT_DUMPFILE "l1hit_dump.out" +IDEAL_L2_L1_PREFETCHER FALSE +IDEAL_L2_ICACHE_PREFETCHER FALSE +L1WAY_PREF_SEND_QUEUE 4 +L1PREF_REQ_QUEUE_SIZE 1024 +L1PREF_IMMEDIATE FALSE +L1WAY_PREF_TIMER_DIS 1000 +L1MARKV_PREF_SEND_QUEUE 4 +L1PREF_MARKV_REQ_QUEUE_SIZE 1024 +MARKV_L2ACCESS_REQ_Q_SIZE 64 +L1MARKV_PREF_IMMEDIATE FALSE +L1MARKV_PREF_TIMER_DIS 1 +L2L1_HIT_TRAIN TRUE +L1MARKV_REQ_TH 1 +L2L1_IMMEDIATE_PREF_CACHE FALSE +L2L1_FILL_PREF_CACHE FALSE +L2L1_L2_HIT_STAT FALSE +PREF_GHB_ON FALSE +DEBUG_PREF_GHB FALSE +PREF_GHB_BUFFER_N 1024 +PREF_GHB_INDEX_N 128 +PREF_GHB_CZONE_BITS 12 +PREF_GHB_DEGREE 16 +PREF_GHB_MAX_DEGREE 32 +PREF_STRIDE_ON FALSE +DEBUG_PREF_STRIDE FALSE +PREF_STRIDE_TABLE_N 1024 +PREF_STRIDE_REGION_BITS 16 +PREF_STRIDE_DEGREE 4 +PREF_STRIDE_DISTANCE 16 +PREF_STRIDE_STARTDISTANCE 1 +PREF_STRIDE_SINGLE_THRESH 6 +PREF_STRIDE_MULTI_THRESH 6 +PREF_STRIDE_SINGLE_STRIDE_MODE FALSE +PREF_STRIDEPC_ON FALSE +DEBUG_PREF_STRIDEPC FALSE +PREF_STRIDEPC_TABLE_N 1024 +PREF_STRIDEPC_DEGREE 4 +PREF_STRIDEPC_DISTANCE 16 +PREF_STRIDEPC_USELOADADDR FALSE +PREF_STRIDEPC_TRAINNUM 2 +PREF_STRIDEPC_STARTDIS 4 +PREF_PHASE_ON FALSE +PREF_PHASE_STUDY FALSE +DEBUG_PREF_PHASE FALSE +PREF_PHASE_PRIME_HASH 16381 +PREF_PHASE_INFOSIZE 16384 +PREF_PHASE_LOG2REGIONSIZE 12 +PREF_PHASE_REGIONENTRIES 64 +PREF_PHASE_TRACKEDREGIONS 32 +PREF_PHASE_INTERVAL 100000 +PREF_PHASE_TABLE_SIZE 64 +PREF_PHASE_MAXDIFF_THRESH 64 +PREF_PHASE_MIN_MISSES 64 +PREF_PHASE_MISSPER 0.4 +PREF_2DC_ON FALSE +DEBUG_PREF_2DC FALSE +PREF_2DC_CACHE_SIZE (1 * 1024) +PREF_2DC_CACHE_ASSOC 4 +PREF_2DC_CACHE_LINE_SIZE 1 +PREF_2DC_DEGREE 16 +PREF_2DC_ZONE_SHIFT 10 +PREF_2DC_TAG_SIZE 16 +PREF_2DC_NUM_REGIONS 64 +PREF_2DC_REGION_HASH 61 +PREF_MARKOV_ON FALSE +DEBUG_PREF_MARKOV FALSE +PREF_MARKOV_NUM_ENTRIES 65536 +PREF_MARKOV_NUM_NEXT_STATES 8 +PREF_MARKOV_SEND_ON_PREF_HIT TRUE +PREF_MARKOV_UPDATE_ON_PREF_HIT TRUE +PREF_MARKOV_TABLE_UPDATE_POLICY 0 +PREF_MARKOV_SEND_THRESHOLD 0 +PREF_SMS_ON FALSE 0 +PREF_SMS_AT_SIZE 64 +PREF_SMS_FT_SIZE 64 +PREF_SMS_PHT_SIZE 16384 +PREF_SMS_PRF_SIZE 1024 +PREF_SMS_REGION_SIZE 2048 diff --git a/labs/LAB5/runs/omnetpp-sms0/bp.stat.0.out b/labs/LAB5/runs/omnetpp-sms0/bp.stat.0.out new file mode 100644 index 00000000..8330cd7a --- /dev/null +++ b/labs/LAB5/runs/omnetpp-sms0/bp.stat.0.out @@ -0,0 +1,752 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 80804991 Instructions: 100000000 IPC: 1.23755 + +BTB_ON_PATH_MISS 10364 0.050% 10364 0.050% +BTB_ON_PATH_HIT 20637713 99.950% 20637713 99.950% + 20648077 100.000% 20648077 100.000% + 1.00 1.00 1.00 1.00 + +BTB_OFF_PATH_MISS 0 -nan% 0 -nan% +BTB_OFF_PATH_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BTB_ON_PATH_WRITE 10364 100.000% 10364 100.000% +BTB_OFF_PATH_WRITE 0 0.000% 0 0.000% + 10364 100.000% 10364 100.000% + 0.00 0.00 0.00 0.00 + +BP_ON_PATH_CORRECT 19959332 96.664% 19959332 96.664% +BP_ON_PATH_MISPREDICT 241183 1.168% 241183 1.168% +BP_ON_PATH_MISFETCH 447562 2.168% 447562 2.168% + 20648077 100.000% 20648077 100.000% + 0.06 0.30 0.06 0.30 + +BP_OFF_PATH_CORRECT 0 -nan% 0 -nan% +BP_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% +BP_OFF_PATH_MISFETCH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +LATE_BP_ON_PATH_CORRECT 20648077 100.000% 20648077 100.000% +LATE_BP_ON_PATH_MISPREDICT 0 0.000% 0 0.000% +LATE_BP_ON_PATH_MISFETCH 0 0.000% 0 0.000% + 20648077 100.000% 20648077 100.000% + 0.00 0.00 0.00 0.00 + +LATE_BP_OFF_PATH_CORRECT 0 -nan% 0 -nan% +LATE_BP_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% +LATE_BP_OFF_PATH_MISFETCH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_PVN 0 -nan% 0 -nan% +BP_ON_PATH_CONF_PVN_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_PVP 0 -nan% 0 -nan% +BP_ON_PATH_CONF_PVP_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_SPEC 0 -nan% 0 -nan% +BP_ON_PATH_CONF_SPEC_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CRS_MISS_ON_PATH 63615 2.542% 63615 2.542% +CRS_HIT_ON_PATH 2439104 97.458% 2439104 97.458% + 2502719 100.000% 2502719 100.000% + 0.97 0.96 0.97 0.96 + +CRS_MISS_OFF_PATH 0 -nan% 0 -nan% +CRS_HIT_OFF_PATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CRS_CLOBBER 0 0 + +TARG_ON_PATH_MISS 285060 16.021% 285060 16.021% +TARG_ON_PATH_HIT 1494285 83.979% 1494285 83.979% + 1779345 100.000% 1779345 100.000% + 0.84 0.78 0.84 0.78 + +TARG_OFF_PATH_MISS 0 -nan% 0 -nan% +TARG_OFF_PATH_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_ON_PATH_WRITE 1779345 100.000% 1779345 100.000% +TARG_OFF_PATH_WRITE 0 0.000% 0 0.000% + 1779345 100.000% 1779345 100.000% + 0.00 0.00 0.00 0.00 + +TARG_HYBRID_CORRECT_TAGLESS 0 -nan% 0 -nan% +TARG_HYBRID_CORRECT_TAGGED 0 -nan% 0 -nan% +TARG_HYBRID_MISPRED_TAGLESS 0 -nan% 0 -nan% +TARG_HYBRID_MISPRED_TAGGED 0 -nan% 0 -nan% +TARG_HYBRID_NO_PRED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_VP_INDIRECT_MISPRED 0 -nan% 0 -nan% +TARG_VP_INDIRECT_NOPRED 0 -nan% 0 -nan% +TARG_VP_INDIRECT_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CBR_ON_PATH_CORRECT 13113453 98.194% 13113453 98.194% +CBR_ON_PATH_MISPREDICT 241183 1.806% 241183 1.806% + 13354636 100.000% 13354636 100.000% + 0.02 0.13 0.02 0.13 + +CBR_ON_PATH_CORRECT_PER1000INST 13113453 131.1345 13113453 131.1345 + +CBR_ON_PATH_MISPREDICT_PER1000INST 241183 2.4118 241183 2.4118 + +CBR_OFF_PATH_CORRECT 0 -nan% 0 -nan% +CBR_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PRED_TO_UPDATE_CYCLES_0 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_1 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_2 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_3 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_4 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_5 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_6 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_7 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_8 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_9 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_10 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_11 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_12 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_13 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_14 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_15 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_16 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_17 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_18 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_19 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_20 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_21 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_22 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_23 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_24 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_25 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_26 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_27 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_28 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_29 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_30 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_CORRECTED 0 -nan% 0 -nan% +BP_NOT_CORRECTED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_CORRECTED 0 -nan% 0 -nan% +TARG_NOT_CORRECTED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_MISP_PENALTY 24283698 24283698 + +BP_ON_PATH_CONF_MISPRED 0 -nan% 0 -nan% +BP_ON_PATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_OFF_PATH_CONF_MISPRED 0 -nan% 0 -nan% +BP_OFF_PATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_PRED_MIS_CONF_MISPRED 0 -nan% 0 -nan% +BP_ON_PATH_PRED_MIS_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_PRED_COR_CONF_MISPRED 0 -nan% 0 -nan% +BP_ON_PATH_PRED_COR_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_OFF_PATH_PRED_MIS_CONF_MISPRED 0 -nan% 0 -nan% +BP_OFF_PATH_PRED_MIS_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_OFF_PATH_PRED_COR_CONF_MISPRED 0 -nan% 0 -nan% +BP_OFF_PATH_PRED_COR_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ONPATH_CONF_MISPRED 0 -nan% 0 -nan% +ONPATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ONPATH_ON_PATH_CONF_MISPRED 0 -nan% 0 -nan% +ONPATH_ON_PATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ONPATH_OFF_PATH_CONF_MISPRED 0 -nan% 0 -nan% +ONPATH_OFF_PATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PRED_ONPATH_CONF_MISPRED 0 -nan% 0 -nan% +PRED_ONPATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PRED_OFFPATH_CONF_MISPRED 0 -nan% 0 -nan% +PRED_OFFPATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +LONG_OVWT_MIS 0 -nan% 0 -nan% +LONG_OVWT_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_0_7_MIS 0 -nan% 0 -nan% +OPC_LENGTH_0_7_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_8_15_MIS 0 -nan% 0 -nan% +OPC_LENGTH_8_15_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_16_23_MIS 0 -nan% 0 -nan% +OPC_LENGTH_16_23_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_24_31_MIS 0 -nan% 0 -nan% +OPC_LENGTH_24_31_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_32_39_MIS 0 -nan% 0 -nan% +OPC_LENGTH_32_39_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_40_47_MIS 0 -nan% 0 -nan% +OPC_LENGTH_40_47_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_48_55_MIS 0 -nan% 0 -nan% +OPC_LENGTH_48_55_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_56_63_MIS 0 -nan% 0 -nan% +OPC_LENGTH_56_63_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_64_71_MIS 0 -nan% 0 -nan% +OPC_LENGTH_64_71_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_72_79_MIS 0 -nan% 0 -nan% +OPC_LENGTH_72_79_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_80_MIS 0 -nan% 0 -nan% +OPC_LENGTH_80_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ALL_ONES_MIS 0 -nan% 0 -nan% +ALL_ONES_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan 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0 0 + +CHIP_UTILIZATION_UNDER_MEM_REQ 0 -nan 0 -nan + +CHIP_UTILIZATION_UNDER_NO_MEM_REQ 0 -nan 0 -nan + +CHIP_UTILIZATION_UNDER_CRITICAL_MEM_REQ 0 -nan 0 -nan + +CHIP_UTILIZATION_UNDER_NONCRITICAL_MEM_REQ 0 -nan 0 -nan + +CYCLES_NOT_WAITING_FOR_OFF_CHIP 0 0.0000 0 0.0000 + +FUS_BUSY_NOT_WAITING_FOR_OFF_CHIP 0 -nan 0 -nan + +CYCLES_WAITING_FOR_OFF_CHIP 0 0.0000 0 0.0000 + +FUS_BUSY_WAITING_FOR_OFF_CHIP 0 -nan 0 -nan + +TOTAL_OFF_CHIP_DELAYS_LEFT 0 0 + +WRONG_IO_SCHED 0 0 + +DVFS_CONFIG_SWITCH 0 0 + + + diff --git a/labs/LAB5/runs/omnetpp-sms0/fetch.stat.0.out b/labs/LAB5/runs/omnetpp-sms0/fetch.stat.0.out new file mode 100644 index 00000000..fe330050 --- /dev/null +++ b/labs/LAB5/runs/omnetpp-sms0/fetch.stat.0.out @@ -0,0 +1,248 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 80804991 Instructions: 100000000 IPC: 1.23755 + +ICACHE_CYCLE 80804991 80804991 + +TCACHE_CYCLE 0 0 + +ICACHE_CYCLE_ONPATH 44047698 54.511% 44047698 54.511% +ICACHE_CYCLE_OFFPATH 36757293 45.489% 36757293 45.489% + 80804991 100.000% 80804991 100.000% + 0.45 0.48 0.45 0.48 + +FETCH_ON_PATH 26446473 100.000% 26446473 100.000% +FETCH_OFF_PATH 0 0.000% 0 0.000% + 26446473 100.000% 26446473 100.000% + 0.00 0.00 0.00 0.00 + +FETCHED_OPS_ON_PATH 0 -nan% 0 -nan% +FETCHED_OPS_OFF_PATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +INST_LOST_WAIT_FOR_MISP_RECOVERY 0 0.000% 0 0.000% +INST_LOST_WAIT_FOR_TIMER 0 0.000% 0 0.000% +INST_LOST_WAIT_FOR_EMPTY_ROB 0 0.000% 0 0.000% +INST_LOST_WAIT_FOR_REDIRECT 701274 0.260% 701274 0.260% +INST_LOST_FETCH 128794978 47.787% 128794978 47.787% +INST_LOST_OFF_PATH 0 0.000% 0 0.000% +INST_LOST_FULL_WINDOW 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_OTHER 2873268 1.066% 2873268 1.066% +INST_LOST_ROB_STALL_WAIT_FOR_RECOVERY 0 0.000% 0 0.000% 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+LOW_CONF_COUNT_RET_19 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_20 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + + + diff --git a/labs/LAB5/runs/omnetpp-sms0/inst.stat.0.out b/labs/LAB5/runs/omnetpp-sms0/inst.stat.0.out new file mode 100644 index 00000000..b33ed648 --- /dev/null +++ b/labs/LAB5/runs/omnetpp-sms0/inst.stat.0.out @@ -0,0 +1,103 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 80804991 Instructions: 100000000 IPC: 1.23755 + +ST_OP_INV 0 0.000% 0 0.000% +ST_OP_NOP 3767097 2.925% 3767097 2.925% +ST_OP_CF 20648077 16.032% 20648077 16.032% +ST_OP_MOV 11427755 8.873% 11427755 8.873% +ST_OP_CMOV 131149 0.102% 131149 0.102% +ST_OP_LDA 4577584 3.554% 4577584 3.554% +ST_OP_IMEM 46557190 36.148% 46557190 36.148% +ST_OP_IADD 21401620 16.617% 21401620 16.617% +ST_OP_IMUL 49026 0.038% 49026 0.038% +ST_OP_IDIV 0 0.000% 0 0.000% +ST_OP_ICMP 8294421 6.440% 8294421 6.440% +ST_OP_LOGIC 8896172 6.907% 8896172 6.907% +ST_OP_SHIFT 1027803 0.798% 1027803 0.798% +ST_OP_FMEM 1072759 0.833% 1072759 0.833% +ST_OP_FCVT 185482 0.144% 185482 0.144% +ST_OP_FADD 2 0.000% 2 0.000% +ST_OP_FMUL 121551 0.094% 121551 0.094% +ST_OP_FMA 2 0.000% 2 0.000% +ST_OP_FDIV 0 0.000% 0 0.000% +ST_OP_FCMP 0 0.000% 0 0.000% +ST_OP_FCMOV 0 0.000% 0 0.000% +ST_OP_GATHER 0 0.000% 0 0.000% +ST_OP_SCATTER 0 0.000% 0 0.000% +ST_OP_PIPELINED_FAST 319006 0.248% 319006 0.248% +ST_OP_PIPELINED_MEDIUM 0 0.000% 0 0.000% +ST_OP_PIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_MEDIUM 318282 0.247% 318282 0.247% +ST_OP_NOTPIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_VERY_SLOW 0 0.000% 0 0.000% + 128794978 100.000% 128794978 100.000% + 5.90 3.10 5.90 3.10 + +ST_NOT_CF 108146901 83.968% 108146901 83.968% +ST_CF_BR 1425785 1.107% 1425785 1.107% +ST_CF_CBR 13354636 10.369% 13354636 10.369% +ST_CF_CALL 1585592 1.231% 1585592 1.231% +ST_CF_IBR 862220 0.669% 862220 0.669% +ST_CF_ICALL 917125 0.712% 917125 0.712% +ST_CF_ICO 0 0.000% 0 0.000% +ST_CF_RET 2502719 1.943% 2502719 1.943% +ST_CF_SYS 0 0.000% 0 0.000% + 128794978 100.000% 128794978 100.000% + 0.45 1.18 0.45 1.18 + +ST_BAR_NONE 128794978 100.000% 128794978 100.000% +ST_BAR_FETCH 0 0.000% 0 0.000% +ST_BAR_ISSUE 0 0.000% 0 0.000% +ST_BAR_BOTH 0 0.000% 0 0.000% + 128794978 100.000% 128794978 100.000% + 0.00 0.00 0.00 0.00 + +ST_NOT_MEM 81165029 63.019% 81165029 63.019% +ST_MEM_LD 30704585 23.840% 30704585 23.840% +ST_MEM_ST 16925364 13.141% 16925364 13.141% +ST_MEM_PF 0 0.000% 0 0.000% +ST_MEM_WH 0 0.000% 0 0.000% +ST_MEM_EVICT 0 0.000% 0 0.000% + 128794978 100.000% 128794978 100.000% + 0.50 0.60 0.50 0.60 + +ST_NOT_MEM_OFFPATH 0 -nan% 0 -nan% +ST_MEM_LD_OFFPATH 0 -nan% 0 -nan% +ST_MEM_ST_OFFPATH 0 -nan% 0 -nan% +ST_MEM_PF_OFFPATH 0 -nan% 0 -nan% +ST_MEM_WH_OFFPATH 0 -nan% 0 -nan% +ST_MEM_EVIC_OFFPATHT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ST_OP_ONPATH 128794978 128794978 + +ST_OP_OFFPATH 0 0 + +ST_FAKE_OP_OFFPATH 0 -nan% 0 -nan% +ST_NOT_FAKE_OP_OFFPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ST_FAKE_REASON_NOT_FAKE 0 -nan% 0 -nan% +ST_FAKE_REASON_REDIRECT_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_RETURN_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_NONRET_CF_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_NOT_TAKEN_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_WRONG_PATH_STORE_TO_NEW_REGION 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ST_INST_ONPATH 100000072 100000072 + +ST_INST_OFFPATH 0 0 + +STATIC_PIN_NOP 0 0 + +DYNAMIC_PIN_REP_GREATER_256 0 0 + + + diff --git a/labs/LAB5/runs/omnetpp-sms0/l2l1pref.stat.0.out b/labs/LAB5/runs/omnetpp-sms0/l2l1pref.stat.0.out new file mode 100644 index 00000000..02950f42 --- /dev/null +++ b/labs/LAB5/runs/omnetpp-sms0/l2l1pref.stat.0.out @@ -0,0 +1,140 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 80804991 Instructions: 100000000 IPC: 1.23755 + +L2WAY_FILL_L1 0 0 + +L2WAY_WAY_HIT 0 -nan% 0 -nan% +L2WAY_WAY_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_PREF_REQ 0 0 + +L2WAY_PREF_HIT_DATA_IN_CACHE 0 -nan% 0 -nan% +L2WAY_PREF_HIT_DATA_REQ 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_TRAIN_HIT 0 -nan% 0 -nan% +L2WAY_TRAIN_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L1_HIT_REQ_TYPE_IFETCH 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DFETCH 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DSTORE 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_IPRF 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DPRF 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_WB 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2_ACCESS_INTERVAL__0 0 -nan% 0 -nan% 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0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + + + diff --git a/labs/LAB5/runs/omnetpp-sms0/memory.stat.0.out b/labs/LAB5/runs/omnetpp-sms0/memory.stat.0.out new file mode 100644 index 00000000..ddb99076 --- /dev/null +++ b/labs/LAB5/runs/omnetpp-sms0/memory.stat.0.out @@ -0,0 +1,3416 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 80804991 Instructions: 100000000 IPC: 1.23755 + +ICACHE_MISS 391787 1.155% 391787 1.155% +ICACHE_HIT 33515548 98.845% 33515548 98.845% + 33907335 100.000% 33907335 100.000% + 0.99 0.98 0.99 0.98 + +ICACHE_MISS_ONPATH 391787 100.000% 391787 100.000% +ICACHE_MISS_OFFPATH 0 0.000% 0 0.000% + 391787 100.000% 391787 100.000% + 0.00 0.00 0.00 0.00 + +ICACHE_HIT_ONPATH 33515548 100.000% 33515548 100.000% +ICACHE_HIT_OFFPATH 0 0.000% 0 0.000% + 33515548 100.000% 33515548 100.000% + 0.00 0.00 0.00 0.00 + +ICACHE_HIT_ONPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +ICACHE_HIT_ONPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ICACHE_HIT_OFFPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +ICACHE_HIT_OFFPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DCACHE_MISS 3089015 6.485% 3089015 6.485% +DCACHE_ST_BUFFER_HIT 72589 0.152% 72589 0.152% +DCACHE_HIT 44468310 93.362% 44468310 93.362% + 47629914 100.000% 47629914 100.000% + 1.87 1.81 1.87 1.81 + +DCACHE_MISS_COMPULSORY 293163 0.0949 293163 0.0949 + +DCACHE_MISS_CAPACITY 2793769 0.9044 2793769 0.9044 + +DCACHE_MISS_CONFLICT 2083 0.0007 2083 0.0007 + +DCACHE_MISS_ONPATH 3089015 100.000% 3089015 100.000% +DCACHE_MISS_OFFPATH 0 0.000% 0 0.000% + 3089015 100.000% 3089015 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_ST_BUFFER_HIT_ONPATH 72589 100.000% 72589 100.000% +DCACHE_ST_BUFFER_HIT_OFFPATH 0 0.000% 0 0.000% + 72589 100.000% 72589 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_HIT_ONPATH 44468310 100.000% 44468310 100.000% +DCACHE_HIT_OFFPATH 0 0.000% 0 0.000% + 44468310 100.000% 44468310 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_HIT_ONPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +DCACHE_HIT_ONPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DCACHE_HIT_OFFPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +DCACHE_HIT_OFFPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DCACHE_MISS_LD 2184167 70.708% 2184167 70.708% +DCACHE_MISS_ST 904848 29.292% 904848 29.292% + 3089015 100.000% 3089015 100.000% + 0.29 0.41 0.29 0.41 + +DCACHE_MISS_LD_ONPATH 2184167 100.000% 2184167 100.000% +DCACHE_MISS_LD_OFFPATH 0 0.000% 0 0.000% + 2184167 100.000% 2184167 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_MISS_ST_ONPATH 904848 100.000% 904848 100.000% +DCACHE_MISS_ST_OFFPATH 0 0.000% 0 0.000% + 904848 100.000% 904848 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_MISS_WAITMEM 0 0 + +MEM_REQ_ROW_BUFFER_HITS 0 -nan% 0 -nan% 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5.239% +CORE_PREF_L1_NOT_USED_LATENCY800 1351 2.889% 1351 2.889% +CORE_PREF_L1_NOT_USED_LATENCY1000 175 0.374% 175 0.374% +CORE_PREF_L1_NOT_USED_LATENCY1200 190 0.406% 190 0.406% +CORE_PREF_L1_NOT_USED_LATENCY1400 280 0.599% 280 0.599% +CORE_PREF_L1_NOT_USED_LATENCY1600 29 0.062% 29 0.062% +CORE_PREF_L1_NOT_USED_LATENCY1600MORE 140 0.299% 140 0.299% + 46765 100.000% 46765 100.000% + 0.34 0.95 0.34 0.95 + +CORE_PREF_L1_NOT_USED_DISTANCE_1 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_DISTANCE_2 2103 4.497% 2103 4.497% +CORE_PREF_L1_NOT_USED_DISTANCE_4 11404 24.386% 11404 24.386% +CORE_PREF_L1_NOT_USED_DISTANCE_8 18141 38.792% 18141 38.792% +CORE_PREF_L1_NOT_USED_DISTANCE_16 13236 28.303% 13236 28.303% +CORE_PREF_L1_NOT_USED_DISTANCE_32 1881 4.022% 1881 4.022% +CORE_PREF_L1_NOT_USED_DISTANCE_MORE 0 0.000% 0 0.000% + 46765 100.000% 46765 100.000% + 3.03 0.93 3.03 0.93 + +CORE_PREF_L1_USED_LATENCY200 24461 89.821% 24461 89.821% +CORE_PREF_L1_USED_LATENCY400 910 3.342% 910 3.342% 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-nan% +DRAM_BOTTLENECK_FAW_90 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_100 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DRAM_ROW_HIT_GEN_AFTER_ROW_OPEN_STALLING 0 0 + +KNOWN_BAD_ADDRESS 0 0.000% 0 0.000% +GOOD_ADDRESS 6588691 100.000% 6588691 100.000% + 6588691 100.000% 6588691 100.000% + 1.00 1.00 1.00 1.00 + + + diff --git a/labs/LAB5/runs/omnetpp-sms0/power.stat.0.out b/labs/LAB5/runs/omnetpp-sms0/power.stat.0.out new file mode 100644 index 00000000..1e998cac --- /dev/null +++ b/labs/LAB5/runs/omnetpp-sms0/power.stat.0.out @@ -0,0 +1,184 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 80804991 Instructions: 100000000 IPC: 1.23755 + +POWER_STATS_BEGIN 0 0 + +POWER_TIME 25251559687500 25251559687500 + +POWER_CYCLE 80804991 80804991 + +POWER_ITLB_ACCESS 33907335 33907335 + +POWER_DTLB_ACCESS 16925353 16925353 + +POWER_ICACHE_ACCESS 33907335 33907335 + +POWER_ICACHE_MISS 391787 391787 + +POWER_BTB_READ 33907335 33907335 + +POWER_BTB_WRITE 688745 688745 + +POWER_ROB_READ 128794928 128794928 + +POWER_ROB_WRITE 128794928 128794928 + +POWER_RENAME_READ 257589856 257589856 + +POWER_RENAME_WRITE 128794928 128794928 + +POWER_FP_RENAME_READ 0 0 + +POWER_FP_RENAME_WRITE 0 0 + +POWER_FUNCTION_CALL 2502717 2502717 + +POWER_INST_WINDOW_READ 128794928 128794928 + +POWER_INST_WINDOW_WRITE 128794928 128794928 + +POWER_INT_REGFILE_READ 141145453 141145453 + +POWER_INT_REGFILE_WRITE 96927234 96927234 + +POWER_IALU_ACCESS 128745902 128745902 + +POWER_CDB_IALU_ACCESS 128745902 128745902 + +POWER_MUL_ACCESS 49026 49026 + +POWER_CDB_MUL_ACCESS 49026 49026 + +POWER_FP_INST_WINDOW_WRITE 0 0 + +POWER_FP_INST_WINDOW_READ 0 0 + +POWER_FP_REGFILE_READ 0 0 + +POWER_FP_REGFILE_WRITE 0 0 + +POWER_FPU_ACCESS 0 0 + +POWER_CDB_FPU_ACCESS 0 0 + +POWER_DCACHE_READ_ACCESS 30704567 30704567 + +POWER_DCACHE_WRITE_ACCESS 16925347 16925347 + +POWER_DCACHE_READ_MISS 2256756 2256756 + +POWER_DCACHE_WRITE_MISS 904848 904848 + +POWER_MLC_READ_ACCESS 0 0 + +POWER_MLC_WRITE_ACCESS 0 0 + +POWER_MLC_READ_MISS 0 0 + +POWER_MLC_WRITE_MISS 0 0 + +POWER_LLC_READ_ACCESS 2005730 2005730 + +POWER_LLC_WRITE_ACCESS 711267 711267 + +POWER_LLC_READ_MISS 591225 591225 + +POWER_LLC_WRITE_MISS 129 129 + +POWER_MEMORY_ACCESS 0 0 + +POWER_MEMORY_READ_ACCESS 0 0 + +POWER_MEMORY_WRITE_ACCESS 0 0 + +POWER_INST_WINDOW_WAKEUP_ACCESS 128794928 128794928 + +POWER_FP_INST_WINDOW_WAKEUP_ACCESS 0 0 + +POWER_L1DIREC_READ_ACCESS 0 0 + +POWER_L1DIREC_WRITE_ACCESS 0 0 + +POWER_L1DIREC_READ_MISS 0 0 + +POWER_L1DIREC_WRITE_MISS 0 0 + +POWER_L2DIREC_READ_ACCESS 0 0 + +POWER_L2DIREC_WRITE_ACCESS 0 0 + +POWER_L2DIREC_READ_MISS 0 0 + +POWER_L2DIREC_WRITE_MISS 0 0 + +POWER_MEMORY_CTRL_ACCESS 873803 873803 + +POWER_MEMORY_CTRL_READ 591225 591225 + +POWER_MEMORY_CTRL_WRITE 282578 282578 + +POWER_OP 128794928 128794928 + +POWER_INT_OP 123010749 123010749 + +POWER_FP_OP 2017082 2017082 + +POWER_LD_OP 30704567 30704567 + +POWER_ST_OP 16925353 16925353 + +POWER_BRANCH_MISPREDICT 688745 688745 + +POWER_COMMITTED_OP 128794928 128794928 + +POWER_COMMITTED_INT_OP 123010749 123010749 + +POWER_COMMITTED_FP_OP 5784179 5784179 + +POWER_BRANCH_OP 20648070 20648070 + +POWER_DRAM_PRECHARGE 470591 470591 + +POWER_DRAM_ACTIVATE 513687 513687 + +POWER_DRAM_READ 591030 591030 + +POWER_DRAM_WRITE 282568 282568 + +POWER_STATS_END 0 0 + +ENERGY 0.000000 0.000000 + +ENERGY_CORE 0.000000 0.000000 + +ENERGY_UNCORE 0.000000 0.000000 + +ENERGY_MEMORY 0.000000 0.000000 + +ENERGY_OTHER 0.000000 0.000000 + +ENERGY_CORE_STATIC 0.000000 0.000000 + +ENERGY_CORE_DYNAMIC 0.000000 0.000000 + +ENERGY_UNCORE_STATIC 0.000000 0.000000 + +ENERGY_UNCORE_DYNAMIC 0.000000 0.000000 + +ENERGY_MEMORY_STATIC 0.000000 0.000000 + +ENERGY_MEMORY_DYNAMIC 0.000000 0.000000 + +ENERGY_OTHER_STATIC 0.000000 0.000000 + +ENERGY_OTHER_DYNAMIC 0.000000 0.000000 + +TIME 0.000000 0.000000 + +ENERGY_STATS_END 0 0 + + + diff --git a/labs/LAB5/runs/omnetpp-sms0/pref.stat.0.out b/labs/LAB5/runs/omnetpp-sms0/pref.stat.0.out new file mode 100644 index 00000000..0bd54e56 --- /dev/null +++ b/labs/LAB5/runs/omnetpp-sms0/pref.stat.0.out @@ -0,0 +1,208 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 80804991 Instructions: 100000000 IPC: 1.23755 + +PREF_DL0REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UMLC_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UL1REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_DL0REQ_QUEUE_FULL 0 0 + +PREF_UMLC_REQ_QUEUE_FULL 0 0 + +PREF_UL1REQ_QUEUE_FULL 0 0 + +PREF_DC_HIT_NOSEND 0 0 + +PREF_WBQDC_HIT_NOSEND 0 0 + +PREF_MLCQ_STALL 0 0 + +PREF_L1Q_STALL 0 0 + +PREF_UMLC_REQ_SEND_QUEUE_STALL 0 0 + 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5.714% +PREF_DISTANCE_5 0 0.000% 0 0.000% +PREF_DISTANCE_6 0 0.000% 0 0.000% +PREF_DISTANCE_7 0 0.000% 0 0.000% +PREF_DISTANCE_8 0 0.000% 0 0.000% +PREF_DISTANCE_9 0 0.000% 0 0.000% +PREF_DISTANCE_10 0 0.000% 0 0.000% + 70 100.000% 70 100.000% + 0.84 0.74 0.84 0.74 + +PREF_REPL_MRU 0 -nan% 0 -nan% +PREF_REPL_MID 0 -nan% 0 -nan% +PREF_REPL_LOWQTR 0 -nan% 0 -nan% +PREF_REPL_LRU 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_REPL_MOVEDOWN 0 -nan% 0 -nan% +PREF_REPL_MOVEUP 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_COV_1 0 -nan% 0 -nan% +PREF_COV_2 0 -nan% 0 -nan% +PREF_COV_3 0 -nan% 0 -nan% +PREF_COV_4 0 -nan% 0 -nan% +PREF_COV_5 0 -nan% 0 -nan% +PREF_COV_6 0 -nan% 0 -nan% +PREF_COV_7 0 -nan% 0 -nan% +PREF_COV_8 0 -nan% 0 -nan% +PREF_COV_9 0 -nan% 0 -nan% +PREF_COV_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_POL_1 0 0.000% 0 0.000% +PREF_POL_2 0 0.000% 0 0.000% +PREF_POL_3 0 0.000% 0 0.000% +PREF_POL_4 0 0.000% 0 0.000% +PREF_POL_5 0 0.000% 0 0.000% +PREF_POL_6 0 0.000% 0 0.000% +PREF_POL_7 0 0.000% 0 0.000% +PREF_POL_8 0 0.000% 0 0.000% +PREF_POL_9 0 0.000% 0 0.000% +PREF_POL_10 70 100.000% 70 100.000% + 70 100.000% 70 100.000% + 9.00 9.06 9.00 9.06 + +PREF_ACC_1 0 0.000% 0 0.000% +PREF_ACC_2 0 0.000% 0 0.000% +PREF_ACC_3 0 0.000% 0 0.000% +PREF_ACC_4 0 0.000% 0 0.000% +PREF_ACC_5 1 1.429% 1 1.429% +PREF_ACC_6 22 31.429% 22 31.429% +PREF_ACC_7 43 61.429% 43 61.429% +PREF_ACC_8 4 5.714% 4 5.714% +PREF_ACC_9 0 0.000% 0 0.000% +PREF_ACC_10 0 0.000% 0 0.000% + 70 100.000% 70 100.000% + 5.71 0.59 5.71 0.59 + +PREF_TIMELY_1 0 0.000% 0 0.000% +PREF_TIMELY_2 0 0.000% 0 0.000% +PREF_TIMELY_3 0 0.000% 0 0.000% +PREF_TIMELY_4 0 0.000% 0 0.000% +PREF_TIMELY_5 0 0.000% 0 0.000% +PREF_TIMELY_6 0 0.000% 0 0.000% +PREF_TIMELY_7 0 0.000% 0 0.000% +PREF_TIMELY_8 5 7.143% 5 7.143% +PREF_TIMELY_9 53 75.714% 53 75.714% +PREF_TIMELY_10 12 17.143% 12 17.143% + 70 100.000% 70 100.000% + 8.10 3.41 8.10 3.41 + +PREF_UNUSED_EVICT 46765 46765 + +PREF_REGION_SENT 0 0 + +PREF_REGION_USEFUL 0 0 + +PREF_REGION_EVICT 0 0 + +PREF_PFPOL 0 0 + +PREF_PHASE_NEWPHASE_DET 0 0 + +PREF_PHASE_NEWPHASE_NOTVALID 0 0 + +PREF_PHASE_SENTPREF 0 0 + +PREF_PHASE_OVERWRITE_PAGE 0 0 + +PREF_UPDATE_COUNT 70 70 + +PREF_ACC1_HT_HP 0 0.000% 0 0.000% +PREF_ACC1_HT_LP 0 0.000% 0 0.000% +PREF_ACC1_LT_HP 0 0.000% 0 0.000% +PREF_ACC1_LT_LP 0 0.000% 0 0.000% +PREF_ACC2_HT_HP 0 0.000% 0 0.000% +PREF_ACC2_HT_LP 0 0.000% 0 0.000% +PREF_ACC2_LT_HP 0 0.000% 0 0.000% +PREF_ACC2_LT_LP 23 32.857% 23 32.857% +PREF_ACC3_HT_HP 0 0.000% 0 0.000% +PREF_ACC3_HT_LP 0 0.000% 0 0.000% +PREF_ACC3_LT_HP 0 0.000% 0 0.000% +PREF_ACC3_LT_LP 0 0.000% 0 0.000% +PREF_ACC4_HT_HP 0 0.000% 0 0.000% +PREF_ACC4_HT_LP 0 0.000% 0 0.000% +PREF_ACC4_LT_HP 0 0.000% 0 0.000% +PREF_ACC4_LT_LP 47 67.143% 47 67.143% + 70 100.000% 70 100.000% + 12.37 10.89 12.37 10.89 + + + diff --git a/labs/LAB5/runs/omnetpp-sms0/ramulator.stat.out b/labs/LAB5/runs/omnetpp-sms0/ramulator.stat.out new file mode 100644 index 00000000..303c596f --- /dev/null +++ b/labs/LAB5/runs/omnetpp-sms0/ramulator.stat.out @@ -0,0 +1,150 @@ + ramulator.active_cycles_0 22844517 # Total active cycles for level _0 + ramulator.busy_cycles_0 22844517 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0 + ramulator.serving_requests_0 56200780 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.average_serving_requests_0 1.854696 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.active_cycles_0_0 22844517 # Total active cycles for level _0_0 + ramulator.busy_cycles_0_0 23302317 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0 + ramulator.serving_requests_0_0 56200780 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.average_serving_requests_0_0 1.854696 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.active_cycles_0_0_0 10508179 # Total active cycles for level _0_0_0 + ramulator.busy_cycles_0_0_0 10508179 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0 + ramulator.serving_requests_0_0_0 14436341 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 +ramulator.average_serving_requests_0_0_0 0.476417 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 + ramulator.active_cycles_0_0_0_0 3212061 # Total active cycles for level _0_0_0_0 + ramulator.busy_cycles_0_0_0_0 3212061 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_0 + ramulator.serving_requests_0_0_0_0 3441284 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 +ramulator.average_serving_requests_0_0_0_0 0.113567 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 + ramulator.active_cycles_0_0_0_1 3473502 # Total active cycles for level _0_0_0_1 + ramulator.busy_cycles_0_0_0_1 3473502 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_1 + ramulator.serving_requests_0_0_0_1 3726296 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 +ramulator.average_serving_requests_0_0_0_1 0.122972 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 + ramulator.active_cycles_0_0_0_2 3077495 # Total active cycles for level _0_0_0_2 + ramulator.busy_cycles_0_0_0_2 3077495 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_2 + ramulator.serving_requests_0_0_0_2 3304060 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 +ramulator.average_serving_requests_0_0_0_2 0.109038 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 + ramulator.active_cycles_0_0_0_3 3693596 # Total active cycles for level _0_0_0_3 + ramulator.busy_cycles_0_0_0_3 3693596 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_3 + ramulator.serving_requests_0_0_0_3 3964701 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 +ramulator.average_serving_requests_0_0_0_3 0.130840 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 + ramulator.active_cycles_0_0_1 9900972 # Total active cycles for level _0_0_1 + ramulator.busy_cycles_0_0_1 9900972 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1 + ramulator.serving_requests_0_0_1 13504725 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 +ramulator.average_serving_requests_0_0_1 0.445673 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 + ramulator.active_cycles_0_0_1_0 2862875 # Total active cycles for level _0_0_1_0 + ramulator.busy_cycles_0_0_1_0 2862875 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_0 + ramulator.serving_requests_0_0_1_0 3070742 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 +ramulator.average_serving_requests_0_0_1_0 0.101338 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 + ramulator.active_cycles_0_0_1_1 3001973 # Total active cycles for level _0_0_1_1 + ramulator.busy_cycles_0_0_1_1 3001973 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_1 + ramulator.serving_requests_0_0_1_1 3222960 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 +ramulator.average_serving_requests_0_0_1_1 0.106362 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 + ramulator.active_cycles_0_0_1_2 3426529 # Total active cycles for level _0_0_1_2 + ramulator.busy_cycles_0_0_1_2 3426529 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_2 + ramulator.serving_requests_0_0_1_2 3675032 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 +ramulator.average_serving_requests_0_0_1_2 0.121281 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 + ramulator.active_cycles_0_0_1_3 3295388 # Total active cycles for level _0_0_1_3 + ramulator.busy_cycles_0_0_1_3 3295388 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_3 + ramulator.serving_requests_0_0_1_3 3535991 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 +ramulator.average_serving_requests_0_0_1_3 0.116692 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 + ramulator.active_cycles_0_0_2 10489849 # Total active cycles for level _0_0_2 + ramulator.busy_cycles_0_0_2 10489849 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2 + ramulator.serving_requests_0_0_2 14358243 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 +ramulator.average_serving_requests_0_0_2 0.473840 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 + ramulator.active_cycles_0_0_2_0 3112630 # Total active cycles for level _0_0_2_0 + ramulator.busy_cycles_0_0_2_0 3112630 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_0 + ramulator.serving_requests_0_0_2_0 3344679 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 +ramulator.average_serving_requests_0_0_2_0 0.110379 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 + ramulator.active_cycles_0_0_2_1 3402563 # Total active cycles for level _0_0_2_1 + ramulator.busy_cycles_0_0_2_1 3402563 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_1 + ramulator.serving_requests_0_0_2_1 3651677 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 +ramulator.average_serving_requests_0_0_2_1 0.120510 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 + ramulator.active_cycles_0_0_2_2 3457934 # Total active cycles for level _0_0_2_2 + ramulator.busy_cycles_0_0_2_2 3457934 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_2 + ramulator.serving_requests_0_0_2_2 3701327 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 +ramulator.average_serving_requests_0_0_2_2 0.122148 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 + ramulator.active_cycles_0_0_2_3 3399895 # Total active cycles for level _0_0_2_3 + ramulator.busy_cycles_0_0_2_3 3399895 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_3 + ramulator.serving_requests_0_0_2_3 3660560 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 +ramulator.average_serving_requests_0_0_2_3 0.120803 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 + ramulator.active_cycles_0_0_3 10220427 # Total active cycles for level _0_0_3 + ramulator.busy_cycles_0_0_3 10220427 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3 + ramulator.serving_requests_0_0_3 13901471 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 +ramulator.average_serving_requests_0_0_3 0.458766 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 + ramulator.active_cycles_0_0_3_0 3299532 # Total active cycles for level _0_0_3_0 + ramulator.busy_cycles_0_0_3_0 3299532 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_0 + ramulator.serving_requests_0_0_3_0 3538302 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 +ramulator.average_serving_requests_0_0_3_0 0.116768 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 + ramulator.active_cycles_0_0_3_1 3358426 # Total active cycles for level _0_0_3_1 + ramulator.busy_cycles_0_0_3_1 3358426 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_1 + ramulator.serving_requests_0_0_3_1 3600392 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 +ramulator.average_serving_requests_0_0_3_1 0.118817 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 + ramulator.active_cycles_0_0_3_2 3239399 # Total active cycles for level _0_0_3_2 + ramulator.busy_cycles_0_0_3_2 3239399 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_2 + ramulator.serving_requests_0_0_3_2 3478269 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 +ramulator.average_serving_requests_0_0_3_2 0.114787 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 + ramulator.active_cycles_0_0_3_3 3070828 # Total active cycles for level _0_0_3_3 + ramulator.busy_cycles_0_0_3_3 3070828 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_3 + ramulator.serving_requests_0_0_3_3 3284508 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 +ramulator.average_serving_requests_0_0_3_3 0.108393 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 + ramulator.read_transaction_bytes_0 37825920 # The total byte of read transaction per channel + ramulator.write_transaction_bytes_0 18084352 # The total byte of write transaction per channel + ramulator.row_hits_channel_0_core 359962 # Number of row hits per channel per core + ramulator.row_misses_channel_0_core 55227 # Number of row misses per channel per core + ramulator.row_conflicts_channel_0_core 458409 # Number of row conflicts per channel per core + ramulator.read_row_hits_channel_0_core 340199 # Number of row hits for read requests per channel per core + [0] 340199.0 # +ramulator.read_row_misses_channel_0_core 33818 # Number of row misses for read requests per channel per core + [0] 33818.0 # +ramulator.read_row_conflicts_channel_0_core 217013 # Number of row conflicts for read requests per channel per core + [0] 217013.0 # + ramulator.write_row_hits_channel_0_core 19763 # Number of row hits for write requests per channel per core + [0] 19763.0 # +ramulator.write_row_misses_channel_0_core 21409 # Number of row misses for write requests per channel per core + [0] 21409.0 # +ramulator.write_row_conflicts_channel_0_core 241396 # Number of row conflicts for write requests per channel per core + [0] 241396.0 # + ramulator.useless_activates_0_core 88 # Number of useless activations. E.g, ACT -> PRE w/o RD or WR + ramulator.read_latency_avg_0 54.966197 # The average memory latency cycles (in memory time domain) per request for all read requests in this channel + ramulator.read_latency_sum_0 32497390 # The memory latency cycles (in memory time domain) sum for all read requests in this channel + ramulator.req_queue_length_avg_0 15.202344 # Average of read and write queue length per memory cycle per channel. + ramulator.req_queue_length_sum_0 460659664 # Sum of read and write queue length per memory cycle per channel. + ramulator.read_req_queue_length_avg_0 0.937347 # Read queue length average per memory cycle per channel. + ramulator.read_req_queue_length_sum_0 28403387 # Read queue length sum per memory cycle per channel. + ramulator.write_req_queue_length_avg_0 14.264997 # Write queue length average per memory cycle per channel. + ramulator.write_req_queue_length_sum_0 432256277 # Write queue length sum per memory cycle per channel. + ramulator.record_read_hits 0.0 # record read hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_misses 0.0 # record_read_miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_conflicts 0.0 # record read conflict count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_hits 0.0 # record write hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_misses 0.0 # record write miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_conflicts 0.0 # record write conflict for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.dram_capacity 8589934592 # Number of bytes in simulated DRAM + ramulator.dram_cycles 30301883 # Number of DRAM cycles simulated + ramulator.incoming_requests 873803 # Number of incoming requests to DRAM + ramulator.read_requests 591225 # Number of incoming read requests to DRAM per core + [0] 591225.0 # + ramulator.write_requests 282578 # Number of incoming write requests to DRAM per core + [0] 282578.0 # + ramulator.ramulator_active_cycles 22844517 # The total number of cycles that the DRAM part is active (serving R/W) + ramulator.incoming_requests_per_channel 873803.0 # Number of incoming requests to each DRAM channel + [0] 873803.0 # +ramulator.incoming_read_reqs_per_channel 591225.0 # Number of incoming read requests to each DRAM channel + [0] 591225.0 # + ramulator.physical_page_replacement 0 # The number of times that physical page replacement happens. + ramulator.maximum_bandwidth 19200000000 # The theoretical maximum bandwidth (Bps) + ramulator.in_queue_req_num_sum 460659664 # Sum of read/write queue length + ramulator.in_queue_read_req_num_sum 28403387 # Sum of read queue length + ramulator.in_queue_write_req_num_sum 432256277 # Sum of write queue length + ramulator.in_queue_req_num_avg 15.202344 # Average of read/write queue length per memory cycle + ramulator.in_queue_read_req_num_avg 0.937347 # Average of read queue length per memory cycle + ramulator.in_queue_write_req_num_avg 14.264997 # Average of write queue length per memory cycle + ramulator.record_read_requests 0.0 # record read requests for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_requests 0.0 # record write requests for this core when it reaches request limit or to the end + [0] 0.0 # diff --git a/labs/LAB5/runs/omnetpp-sms0/run.err b/labs/LAB5/runs/omnetpp-sms0/run.err new file mode 100644 index 00000000..e69de29b diff --git a/labs/LAB5/runs/omnetpp-sms0/run.out b/labs/LAB5/runs/omnetpp-sms0/run.out new file mode 100644 index 00000000..ae421c3e --- /dev/null +++ b/labs/LAB5/runs/omnetpp-sms0/run.out @@ -0,0 +1,107 @@ +Scarab gitrev: 7ab9e17 +Scarab started at Sun Jun 11 08:08:38 2023 + +Initialized Ramulator. +** Heartbeat: 1% -- { 1000001 } -- 0.00 KIPS (333.33 KIPS) +** Heartbeat: 2% -- { 2000001 } -- 500.00 KIPS (400.00 KIPS) +** Heartbeat: 3% -- { 3000006 } -- 500.00 KIPS (428.57 KIPS) +** Heartbeat: 4% -- { 4000009 } -- 333.33 KIPS (400.00 KIPS) +** Heartbeat: 5% -- { 5000011 } -- 500.00 KIPS (416.67 KIPS) +** Heartbeat: 6% -- { 6000014 } -- 500.00 KIPS (428.57 KIPS) +** Heartbeat: 7% -- { 7000016 } -- 500.00 KIPS (437.50 KIPS) +** Heartbeat: 8% -- { 8000020 } -- 333.33 KIPS (421.05 KIPS) +** Heartbeat: 9% -- { 9000020 } -- 500.00 KIPS (428.57 KIPS) +** Heartbeat: 10% -- { 10000023 } -- 500.00 KIPS (434.78 KIPS) +** Heartbeat: 11% -- { 11000025 } -- 333.33 KIPS (423.08 KIPS) +** Heartbeat: 12% -- { 12000025 } -- 500.00 KIPS (428.57 KIPS) +** Heartbeat: 13% -- { 13000027 } -- 500.00 KIPS (433.33 KIPS) +** Heartbeat: 14% -- { 14000030 } -- 333.33 KIPS (424.24 KIPS) +** Heartbeat: 15% -- { 15000030 } -- 500.00 KIPS (428.57 KIPS) +** Heartbeat: 16% -- { 16000035 } -- 500.00 KIPS (432.43 KIPS) +** Heartbeat: 17% -- { 17000036 } -- 500.00 KIPS (435.90 KIPS) +** Heartbeat: 18% -- { 18000037 } -- 333.33 KIPS (428.57 KIPS) +** Heartbeat: 19% -- { 19000040 } -- 500.00 KIPS (431.82 KIPS) +** Heartbeat: 20% -- { 20000045 } -- 500.00 KIPS (434.78 KIPS) +** Heartbeat: 21% -- { 21000049 } -- 333.33 KIPS (428.57 KIPS) +** Heartbeat: 22% -- { 22000049 } -- 500.00 KIPS (431.37 KIPS) +** Heartbeat: 23% -- { 23000054 } -- 500.00 KIPS (433.96 KIPS) +** Heartbeat: 24% -- { 24000054 } -- 333.33 KIPS (428.57 KIPS) +** Heartbeat: 25% -- { 25000055 } -- 500.00 KIPS (431.04 KIPS) +** Heartbeat: 26% -- { 26000055 } -- 500.00 KIPS (433.33 KIPS) +** Heartbeat: 27% -- { 27000055 } -- 333.33 KIPS (428.57 KIPS) +** Heartbeat: 28% -- { 28000055 } -- 500.00 KIPS (430.77 KIPS) +** Heartbeat: 29% -- { 29000055 } -- 500.00 KIPS (432.84 KIPS) +** Heartbeat: 30% -- { 30000057 } -- 333.33 KIPS (428.57 KIPS) +** Heartbeat: 31% -- { 31000057 } -- 500.00 KIPS (430.56 KIPS) +** Heartbeat: 32% -- { 32000060 } -- 500.00 KIPS (432.43 KIPS) +** Heartbeat: 33% -- { 33000063 } -- 333.33 KIPS (428.57 KIPS) +** Heartbeat: 34% -- { 34000063 } -- 500.00 KIPS (430.38 KIPS) +** Heartbeat: 35% -- { 35000065 } -- 333.33 KIPS (426.83 KIPS) +** Heartbeat: 36% -- { 36000070 } -- 500.00 KIPS (428.57 KIPS) +** Heartbeat: 37% -- { 37000071 } -- 500.00 KIPS (430.23 KIPS) +** Heartbeat: 38% -- { 38000071 } -- 333.33 KIPS (426.97 KIPS) +** Heartbeat: 39% -- { 39000075 } -- 500.00 KIPS (428.57 KIPS) +** Heartbeat: 40% -- { 40000075 } -- 500.00 KIPS (430.11 KIPS) +** Heartbeat: 41% -- { 41000078 } -- 500.00 KIPS (431.58 KIPS) +** Heartbeat: 42% -- { 42000079 } -- 333.33 KIPS (428.57 KIPS) +** Heartbeat: 43% -- { 43000081 } -- 500.00 KIPS (430.00 KIPS) +** Heartbeat: 44% -- { 44000084 } -- 500.00 KIPS (431.37 KIPS) +** Heartbeat: 45% -- { 45000086 } -- 500.00 KIPS (432.69 KIPS) +** Heartbeat: 46% -- { 46000091 } -- 500.00 KIPS (433.96 KIPS) +** Heartbeat: 47% -- { 47000092 } -- 333.33 KIPS (431.19 KIPS) +** Heartbeat: 48% -- { 48000092 } -- 500.00 KIPS (432.43 KIPS) +** Heartbeat: 49% -- { 49000093 } -- 333.33 KIPS (429.83 KIPS) +** Heartbeat: 50% -- { 50000095 } -- 500.00 KIPS (431.04 KIPS) +** Heartbeat: 51% -- { 51000099 } -- 500.00 KIPS (432.20 KIPS) +** Heartbeat: 52% -- { 52000102 } -- 500.00 KIPS (433.33 KIPS) +** Heartbeat: 53% -- { 53000102 } -- 333.33 KIPS (430.90 KIPS) +** Heartbeat: 54% -- { 54000104 } -- 500.00 KIPS (432.00 KIPS) +** Heartbeat: 55% -- { 55000104 } -- 500.00 KIPS (433.07 KIPS) +** Heartbeat: 56% -- { 56000104 } -- 333.33 KIPS (430.77 KIPS) +** Heartbeat: 57% -- { 57000107 } -- 500.00 KIPS (431.82 KIPS) +** Heartbeat: 58% -- { 58000107 } -- 500.00 KIPS (432.84 KIPS) +** Heartbeat: 59% -- { 59000107 } -- 500.00 KIPS (433.82 KIPS) +** Heartbeat: 60% -- { 60000108 } -- 333.33 KIPS (431.66 KIPS) +** Heartbeat: 61% -- { 61000108 } -- 500.00 KIPS (432.62 KIPS) +** Heartbeat: 62% -- { 62000111 } -- 500.00 KIPS (433.57 KIPS) +** Heartbeat: 63% -- { 63000112 } -- 333.33 KIPS (431.51 KIPS) +** Heartbeat: 64% -- { 64000114 } -- 500.00 KIPS (432.43 KIPS) +** Heartbeat: 65% -- { 65000114 } -- 500.00 KIPS (433.33 KIPS) +** Heartbeat: 66% -- { 66000116 } -- 333.33 KIPS (431.37 KIPS) +** Heartbeat: 67% -- { 67000117 } -- 500.00 KIPS (432.26 KIPS) +** Heartbeat: 68% -- { 68000117 } -- 500.00 KIPS (433.12 KIPS) +** Heartbeat: 69% -- { 69000121 } -- 500.00 KIPS (433.96 KIPS) +** Heartbeat: 70% -- { 70000123 } -- 333.33 KIPS (432.10 KIPS) +** Heartbeat: 71% -- { 71000125 } -- 500.00 KIPS (432.93 KIPS) +** Heartbeat: 72% -- { 72000129 } -- 500.00 KIPS (433.74 KIPS) +** Heartbeat: 73% -- { 73000129 } -- 333.33 KIPS (431.95 KIPS) +** Heartbeat: 74% -- { 74000130 } -- 500.00 KIPS (432.75 KIPS) +** Heartbeat: 75% -- { 75000131 } -- 500.00 KIPS (433.53 KIPS) +** Heartbeat: 76% -- { 76000131 } -- 333.33 KIPS (431.82 KIPS) +** Heartbeat: 77% -- { 77000132 } -- 500.00 KIPS (432.59 KIPS) +** Heartbeat: 78% -- { 78000134 } -- 500.00 KIPS (433.33 KIPS) +** Heartbeat: 79% -- { 79000135 } -- 500.00 KIPS (434.07 KIPS) +** Heartbeat: 80% -- { 80000136 } -- 333.33 KIPS (432.43 KIPS) +** Heartbeat: 81% -- { 81000138 } -- 500.00 KIPS (433.16 KIPS) +** Heartbeat: 82% -- { 82000138 } -- 500.00 KIPS (433.86 KIPS) +** Heartbeat: 83% -- { 83000140 } -- 333.33 KIPS (432.29 KIPS) +** Heartbeat: 84% -- { 84000142 } -- 500.00 KIPS (432.99 KIPS) +** Heartbeat: 85% -- { 85000142 } -- 500.00 KIPS (433.67 KIPS) +** Heartbeat: 86% -- { 86000147 } -- 333.33 KIPS (432.16 KIPS) +** Heartbeat: 87% -- { 87000147 } -- 500.00 KIPS (432.84 KIPS) +** Heartbeat: 88% -- { 88000149 } -- 500.00 KIPS (433.50 KIPS) +** Heartbeat: 89% -- { 89000150 } -- 500.00 KIPS (434.15 KIPS) +** Heartbeat: 90% -- { 90000153 } -- 333.33 KIPS (432.69 KIPS) +** Heartbeat: 91% -- { 91000155 } -- 500.00 KIPS (433.33 KIPS) +** Heartbeat: 92% -- { 92000158 } -- 500.00 KIPS (433.96 KIPS) +** Heartbeat: 93% -- { 93000159 } -- 333.33 KIPS (432.56 KIPS) +** Heartbeat: 94% -- { 94000160 } -- 500.00 KIPS (433.18 KIPS) +** Heartbeat: 95% -- { 95000160 } -- 500.00 KIPS (433.79 KIPS) +** Heartbeat: 96% -- { 96000164 } -- 500.00 KIPS (434.39 KIPS) +** Heartbeat: 97% -- { 97000167 } -- 333.33 KIPS (433.04 KIPS) +** Heartbeat: 98% -- { 98000167 } -- 500.00 KIPS (433.63 KIPS) +** Heartbeat: 99% -- { 99000167 } -- 500.00 KIPS (434.21 KIPS) +** Core 0 Finished: insts:100000000 cycles:80804991 time:25251559687500 -- 1.24 IPC (1.24 IPC) -- N/A KIPS (434.78 KIPS) +done +Scarab finished at Sun Jun 11 08:12:28 2023 + diff --git a/labs/LAB5/runs/omnetpp-sms0/stream.stat.0.out b/labs/LAB5/runs/omnetpp-sms0/stream.stat.0.out new file mode 100644 index 00000000..b11add17 --- /dev/null +++ b/labs/LAB5/runs/omnetpp-sms0/stream.stat.0.out @@ -0,0 +1,188 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 80804991 Instructions: 100000000 IPC: 1.23755 + +DCACHE_PREF_HIT 0 0 + +IFETCH_WB_FIRST_SCHEDULE 0 -nan% 0 -nan% +PREFETCH_LAST_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_PREF_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_LOW_OP_SCHEDULE 0 -nan% 0 -nan% +DEMAND_LAST_SCHEDULE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +SEND_MISS_REQ_QUEUE 591225 591225 + +L1_DATA_EVICT 574970 574970 + +STREAM_BUFFER_REQ 0 0 + +PREF_SEND_TO_MEM_REQ 0 -nan% 0 -nan% +PREF_SEND_TO_MEM_REQ_FAIL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +HIT_TRAIN_STREAM 84669 14.511% 84669 14.511% +MISS_TRAIN_STREAM 498798 85.489% 498798 85.489% + 583467 100.000% 583467 100.000% + 0.85 0.80 0.85 0.80 + +STREAM_TRAIN_CREATE 243682 243682 + +MEM_REQ_MISS_HWP_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_SW_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_IFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DSTORE_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DPRF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_WB_Q 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_BY_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_WB 0 -nan% 0 -nan% +PREF_HIT_BY_PREF 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_WB 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_L1_FILL 0 -nan% 0 -nan% +DEMAND_L1_FILL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TOUCH_L1_REPLACE 0 0.000% 0 0.000% +NO_TOUCH_L1_REPLACE 574970 100.000% 574970 100.000% + 574970 100.000% 574970 100.000% + 1.00 1.00 1.00 1.00 + +PREF_REQ_QUE_FULL 0 0 + +STREAM_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +L2HIT_STREAM_PREF_REQ_QUE_FULL 0 0 + +L2HIT_HIT_TRAIN_STREAM 0 -nan% 0 -nan% +L2HIT_MISS_TRAIN_STREAM 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_TRAIN_CREATE 0 0 + +L2HIT_STREAM_BUFFER_REQ 0 0 + +L2HIT_STREAM_PREF_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_STREAM_PREF_DCACHE_INSERT 0 -nan% 0 -nan% +L2HIT_STREAM_L2_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_DCACHE_PORT_FULL 0 0 + +L2HIT_STREAM_PREF_L1_PORT_FULL 0 0 + +L2HIT_TRAIN_HIT_DEMAND 0 -nan% 0 -nan% +L2HIT_TRAIN_MISS_REQ 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_TRAIN_FILTER_MISS 0 -nan% 0 -nan% +L2HIT_TRAIN_FILTER_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_PREF_REQ_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_PREF_REQ_DCACHE_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_L2SEND_Q_FULL 0 -nan% 0 -nan% +L2HIT_L2SEND_Q_ENTER 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_MEM_REQ 0 0 + +REMOVE_REDUNDANT_STREAM_STAT 0 0 + +REPLACE_OLD_STREAM 243666 243666 + +REQ_SEND_QUEUE_STALL 0 0 + +STREAM_ENTER_RA 0 0 + +CORE_STREAM_LENGTH_0 11200 36.334% 11200 36.334% +CORE_STREAM_LENGTH_10 15447 50.112% 15447 50.112% +CORE_STREAM_LENGTH_20 3408 11.056% 3408 11.056% +CORE_STREAM_LENGTH_30 492 1.596% 492 1.596% +CORE_STREAM_LENGTH_40 187 0.607% 187 0.607% +CORE_STREAM_LENGTH_50 40 0.130% 40 0.130% +CORE_STREAM_LENGTH_60 13 0.042% 13 0.042% +CORE_STREAM_LENGTH_70 4 0.013% 4 0.013% +CORE_STREAM_LENGTH_80 4 0.013% 4 0.013% +CORE_STREAM_LENGTH_90 5 0.016% 5 0.016% +CORE_STREAM_LENGTH_100_P 25 0.081% 25 0.081% + 30825 100.000% 30825 100.000% + 0.81 0.66 0.81 0.66 + +CORE_CUM_STREAM_LENGTH_0 67674 17.389% 67674 17.389% +CORE_CUM_STREAM_LENGTH_10 211779 54.418% 211779 54.418% +CORE_CUM_STREAM_LENGTH_20 76936 19.769% 76936 19.769% +CORE_CUM_STREAM_LENGTH_30 15891 4.083% 15891 4.083% +CORE_CUM_STREAM_LENGTH_40 8272 2.126% 8272 2.126% +CORE_CUM_STREAM_LENGTH_50 2113 0.543% 2113 0.543% +CORE_CUM_STREAM_LENGTH_60 824 0.212% 824 0.212% +CORE_CUM_STREAM_LENGTH_70 294 0.076% 294 0.076% +CORE_CUM_STREAM_LENGTH_80 338 0.087% 338 0.087% +CORE_CUM_STREAM_LENGTH_90 480 0.123% 480 0.123% +CORE_CUM_STREAM_LENGTH_100_P 4569 1.174% 4569 1.174% + 389170 100.000% 389170 100.000% + 1.33 1.25 1.33 1.25 + +CORE_STREAM_TRAIN_HITS_0 26779 86.874% 26779 86.874% +CORE_STREAM_TRAIN_HITS_10 3905 12.668% 3905 12.668% +CORE_STREAM_TRAIN_HITS_20 57 0.185% 57 0.185% +CORE_STREAM_TRAIN_HITS_30 22 0.071% 22 0.071% +CORE_STREAM_TRAIN_HITS_40 26 0.084% 26 0.084% +CORE_STREAM_TRAIN_HITS_50 4 0.013% 4 0.013% +CORE_STREAM_TRAIN_HITS_60 7 0.023% 7 0.023% +CORE_STREAM_TRAIN_HITS_70 3 0.010% 3 0.010% +CORE_STREAM_TRAIN_HITS_80 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_90 4 0.013% 4 0.013% +CORE_STREAM_TRAIN_HITS_100_P 18 0.058% 18 0.058% + 30825 100.000% 30825 100.000% + 0.15 0.45 0.15 0.45 + +CORE_CUM_STREAM_TRAIN_HITS_0 156019 75.020% 156019 75.020% +CORE_CUM_STREAM_TRAIN_HITS_10 43968 21.142% 43968 21.142% +CORE_CUM_STREAM_TRAIN_HITS_20 1300 0.625% 1300 0.625% +CORE_CUM_STREAM_TRAIN_HITS_30 773 0.372% 773 0.372% +CORE_CUM_STREAM_TRAIN_HITS_40 1166 0.561% 1166 0.561% +CORE_CUM_STREAM_TRAIN_HITS_50 224 0.108% 224 0.108% +CORE_CUM_STREAM_TRAIN_HITS_60 449 0.216% 449 0.216% +CORE_CUM_STREAM_TRAIN_HITS_70 225 0.108% 225 0.108% +CORE_CUM_STREAM_TRAIN_HITS_80 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_90 375 0.180% 375 0.180% +CORE_CUM_STREAM_TRAIN_HITS_100_P 3470 1.669% 3470 1.669% + 207969 100.000% 207969 100.000% + 0.47 1.40 0.47 1.40 + +CORE_STREAM_TRAIN_CREATE 243682 243682 + + + diff --git a/labs/LAB5/runs/omnetpp-sms1/PARAMS.in b/labs/LAB5/runs/omnetpp-sms1/PARAMS.in new file mode 100644 index 00000000..2593c2b8 --- /dev/null +++ b/labs/LAB5/runs/omnetpp-sms1/PARAMS.in @@ -0,0 +1,226 @@ +# File : PARAMS.kaby_lake +# Date : 03/06/19 +# Description : Kaby Lake Configuration +# +# Based on documentation found here: +# https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake + +## Simulation Parameters +--mode full +--model cmp +--sim_limit none + +## Core Parameters + +# Femptoseconds, 3.2GHz, used for energy estimates. +--chip_cycle_time 312500 + + +### Fetch Stage +--fetch_off_path_ops 1 +--fetch_across_cache_lines 1 + +# Will break the packet upon a taken branch. +--fetch_break_on_taken 1 + +# Number of bubble cycles to wait after taken branch. +--fetch_taken_bubble_cycles 0 + + +#### ICache +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 + +### Branch Predictor +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_mech tagescl + + +#### BTB + +# BTB model to use. +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 + +# Allow the BTB to be updated by off path ops. +--btb_off_path_writes 1 + + +#### CRS + +# Enable return stack +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 + +### iBP +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged + # iBTB Model. tc_tagless, tc_tagged, tc_hybrid. +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 + +### Decode Stage +--decode_cycles 5 + + +### Map Stage +--map_cycles 5 + + +### Issue Stage + +# Max number of instructions to be fetched, decoded, renamed, and issued per cycle. +--issue_width 6 + +--rs_fill_width 0 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 + + +### Exec Stage + +### DCache +--dcache_size 32768 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--dcache_assoc 4 +--dcache_line_size 64 + +### Reorder/Retire Stage + +# Max number of instructions to be retired per cycle. +--node_ret_width 6 +--node_table_size 224 + +# Do not keep stores in RSVs on cache misses; TODO: confirm what this knob does +--stores_do_not_block_window 1 + +# TODO: confirm what this knob does +--prefs_do_not_block_window 1 + + +## Uncore + +### Mid-level cache + +# Enable use of a midlevel cache between i/d and L1 +--mlc_present 0 + +### LLC +--l1_size 1048576 +--l1_banks 1 +--l1_cycles 18 +--l1_assoc 8 +--l1_line_size 64 +--l1_interleave_factor 64 + + +### Prefetcher +--pref_framework_on 1 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--pref_shared_queues 0 +--pref_train_on_pref_misses 0 +--pref_oracle_train 0 +--pref_ul1req_queue_overwrite_on_full 1 + +--stream_length 64 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 + +--pref_throttlefb_on=1 +--pref_acc_thresh_1=0.75 +--pref_acc_thresh_2=0.4 +--pref_acc_thresh_3=0.4 +--pref_timely_thresh=0.01 +--pref_polpf_thresh=0.005 +--pref_update_interval=8192 + +--mem_req_buffer_pref_watermark 4 +--promote_to_higher_priority_mem_req_type 1 + +### Memory +--addr_translation random + +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 + +--mem_req_buffer_entries 32 +--mem_l1_fill_queue_entries 32 +--va_page_size_bytes 4096 +--bus_width_in_bytes 8 + +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 + +## Other + + +### Debug +--debug_inst_start 0 +--debug_inst_stop -1 +--debug_cycle_start 0 +--debug_cycle_stop -1 + + +## Stats and Params +--dump_params 1 +--dump_stats 1 +--dump_trace 0 + +#################################### +--set_off_path_confirmed 1 + +--order_beyond_bus 1 + +--mem_ooo_stores 1 +--mem_obey_store_dep 1 diff --git a/labs/LAB5/runs/omnetpp-sms1/PARAMS.out b/labs/LAB5/runs/omnetpp-sms1/PARAMS.out new file mode 100644 index 00000000..1bfa4fd2 --- /dev/null +++ b/labs/LAB5/runs/omnetpp-sms1/PARAMS.out @@ -0,0 +1,908 @@ +--mode full +--model cmp +--frontend memtrace +--inst_limit 100000000 +--sim_limit none +--dump_params 1 +--dump_stats 1 +--dump_trace 0 +--mlc_present 0 +--l1_size 1048576 +--l1_assoc 8 +--l1_line_size 64 +--l1_cycles 18 +--l1_banks 1 +--l1_interleave_factor 64 +--va_page_size_bytes 4096 +--addr_translation random +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 +--dcache_size 32768 +--dcache_assoc 4 +--dcache_line_size 64 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--mem_ooo_stores 1 +--mem_obey_store_dep 1 +--mem_req_buffer_entries 32 +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 +--promote_to_higher_priority_mem_req_type 1 +--mem_req_buffer_pref_watermark 4 +--mem_l1_fill_queue_entries 32 +--order_beyond_bus 1 +--set_off_path_confirmed 1 +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--bus_width_in_bytes 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 +--chip_cycle_time 312500 +--issue_width 6 +--rs_fill_width 0 +--node_table_size 224 +--node_ret_width 6 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 +--decode_cycles 5 +--map_cycles 5 +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--fetch_across_cache_lines 1 +--fetch_off_path_ops 0 +--fetch_break_on_taken 1 +--fetch_taken_bubble_cycles 0 +--stores_do_not_block_window 1 +--prefs_do_not_block_window 1 +--cbp_trace_r0 /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir/trace/drmemtrace.omnetpp.552936.3514.trace.gz +--memtrace_modules_log /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir/raw +--debug_cycle_start 0 +--debug_cycle_stop -1 +--debug_inst_start 0 +--debug_inst_stop -1 +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--bp_mech tagescl +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 +--btb_off_path_writes 1 +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_length 64 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 +--pref_framework_on 1 +--pref_shared_queues 0 +--pref_ul1req_queue_overwrite_on_full 1 +--pref_train_on_pref_misses 0 +--pref_oracle_train_on 0 +--pref_throttlefb_on 1 +--pref_acc_thresh_1 0.75 +--pref_acc_thresh_2 0.4 +--pref_acc_thresh_3 0.4 +--pref_update_interval 8192 +--pref_timely_thresh 0.01 +--pref_polpf_thresh 0.005 +--pref_sms_on 1 +1 1 1 1 1 1 1 + +--- Cut out everything below to use this file as PARAMS.in --- + +Parameter status at compile time and values supplied on the command line: + +SIM_MODE 0 full +SIM_MODEL 0 cmp +FRONTEND FE_PIN_EXEC_DRIVEN memtrace +INST_LIMIT NULL 100000000 +SIM_LIMIT "none" none +FORWARD_PROGRESS_LIMIT 100000000 +FORWARD_PROGRESS_INTERVAL 10000 +FAST_FORWARD 0 +FAST_FORWARD_UNTIL_ADDR 0 +FAST_FORWARD_TRACE_INS 0 +WARMUP 0 +HEARTBEAT_INTERVAL 1000000 +NUM_HEARTBEATS 0 +FILE_TAG "" +OUTPUT_DIR "." +STATUS_FILE NULL +BINDIR NULL +DUMP_PARAMS TRUE 1 +DUMP_STATS TRUE 1 +DUMP_TRACE FALSE 0 +CLEAR_STATS "never" +STATS_TO_TRACE NULL +STAT_TRACE_FILE "stats.trace" +STAT_TRACE_INTERVAL "i:100000" +PIPEVIEW FALSE +PIPEVIEW_FILE "pipeview" +MEMVIEW FALSE +MEMVIEW_FILE "memview.out" +MEMVIEW_START "never" +INST_HASH_TABLE_SIZE 500021 const +STDOUT_FILE NULL +STDERR_FILE NULL +PIN_EXEC_DRIVEN_FE_SOCKET "./pin_exec_driven_fe_socket.temp" +PRINT_PID FALSE +USE_UNSURE_FREE_LISTS FALSE +OPTIMIZER2_MAX_NUM_SLAVES 64 +OPTIMIZER2_PERFECT_MEMORYLESS FALSE +EXIT_COND 0 +ENABLE_SWPRF FALSE +MLC_PRESENT FALSE 0 +MLC_SIZE (512 * 1024) +MLC_ASSOC 4 +MLC_LINE_SIZE 64 +MLC_CYCLES 12 +PERFECT_MLC FALSE +MLC_READ_PORTS 1 +MLC_WRITE_PORTS 1 +MLC_BANKS 8 +MLC_INTERLEAVE_FACTOR 64 +MLC_CACHE_REPL_POLICY 0 +MLC_WRITE_THROUGH FALSE +PREFETCH_UPDATE_LRU_MLC TRUE +FORCE_L1_MISS FALSE +L1_SIZE (4 * 1024 * 1024) 1048576 +L1_ASSOC 8 8 +L1_LINE_SIZE 64 64 +L1_CYCLES 24 18 +PERFECT_L1 FALSE +PRIVATE_L1 FALSE +L1_READ_PORTS 1 +L1_WRITE_PORTS 1 +L1_BANKS 8 1 +L1_INTERLEAVE_FACTOR 64 64 +L1_CACHE_REPL_POLICY 0 +L1_WRITE_THROUGH FALSE +L1_IGNORE_WB FALSE +L1_USE_CORE_FREQ FALSE +MARK_L1_MISSES TRUE +PREFETCH_UPDATE_LRU_L1 TRUE +MEMORY_RANDOM_ADDR FALSE +VA_PAGE_SIZE_BYTES 4096 4096 +NUM_ADDR_NON_SIGN_EXTEND_BITS 48 +ADDR_TRANSLATION 0 random +CONSTANT_MEMORY_LATENCY FALSE +MEMORY_CYCLES 100 +STALL_MEM_REQS_ONLY FALSE +ICACHE_SIZE (64 * 1024) 32768 +ICACHE_ASSOC 4 4 +ICACHE_LINE_SIZE 64 64 +PERFECT_ICACHE FALSE +ICACHE_READ_PORTS 2 +ICACHE_WRITE_PORTS 1 +ICACHE_BANKS 8 +ICACHE_REPL 0 +DCACHE_SIZE (64 * 1024) 32768 +DCACHE_ASSOC 1 4 +DCACHE_LINE_SIZE 64 64 +DCACHE_CYCLES 2 +PERFECT_DCACHE FALSE +DCACHE_READ_PORTS 8 2 +DCACHE_WRITE_PORTS 1 1 +DCACHE_BANKS 1 1 +DCACHE_REPL 0 +DCACHE_REPL_PREF_THRESH 1 +MEM_OOO_STORES TRUE 1 +MEM_OBEY_STORE_DEP TRUE 1 +PREF_INSERT_LRU FALSE +PREF_INSERT_MIDDLE FALSE +PREF_INSERT_LOWQTR FALSE +PREF_INSERT_DYNACC FALSE +MEM_REQ_BUFFER_ENTRIES 32 32 +PRIVATE_MSHR_ON TRUE +MEM_PRIORITY_IFETCH 0 0 +MEM_PRIORITY_DFETCH 0 1 +MEM_PRIORITY_DSTORE 0 2 +MEM_PRIORITY_IPRF 9 3 +MEM_PRIORITY_DPRF 10 4 +MEM_PRIORITY_WB 0 5 +MEM_PRIORITY_WB_NODIRTY 0 5 +PROMOTE_TO_HIGHER_PRIORITY_MEM_REQ_TYPE FALSE 1 +MEM_REQ_BUFFER_PREF_WATERMARK 0 4 +MEM_REQ_BUFFER_WB_VALVE 2 +MEM_L1_FILL_QUEUE_ENTRIES 32 32 +MEM_BUS_OUT_QUEUE_PARTITION_ENABLE FALSE +MEM_MEM_QUEUE_PARTITION_ENABLE FALSE +MEM_BUS_OUT_QUEUE_AS_FIFO TRUE +OLDEST_FIRST_TO_MEM_QUEUE TRUE +ROUND_ROBIN_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE_TH 0 +L1_CYCLE_TIME 312500 +MLCQ_TO_L1Q_TRANSFER_LATENCY 1 +L1Q_TO_FSB_TRANSFER_LATENCY 1 +PRIORITIZE_PREFETCHES_WITH_UNIQUE FALSE +KICKOUT_PREFETCHES FALSE +KICKOUT_LOOK_FOR_OLDEST_FIRST FALSE +KICKOUT_OLDEST_PREFETCH FALSE +KICKOUT_OLDEST_PREFETCH_WITHIN_BANK FALSE +ORDER_BEYOND_BUS FALSE 1 +ALL_FIFO_QUEUES FALSE +QUEUE_MLC_SIZE 0 +QUEUE_L1_SIZE 0 +QUEUE_BUS_OUT_SIZE 0 +QUEUE_CORE_FILL_SIZE 0 +ALLOW_TYPE_MATCHES FALSE +STREAM_PREFETCH_ON FALSE +DC_PREF_CACHE_ENABLE FALSE +DC_PREF_CACHE_CYCLE 0 +PREF_INSERT_DCACHE_IMM TRUE +DC_PREF_CACHE_SIZE (64 * 1024) +DC_PREF_CACHE_ASSOC 4 +DC_PREF_ONLY_L1HIT FALSE +PREF_CACHE_USE_RDY_CYCLE FALSE +IC_PREF_CACHE_ENABLE FALSE +IC_PREF_CACHE_SIZE (64 * 1024) +IC_PREF_CACHE_ASSOC 4 +L1_PREF_CACHE_ENABLE FALSE +L1_PREF_CACHE_SIZE (1024 * 1024) +L1_PREF_CACHE_ASSOC 8 +SET_OFF_PATH_CONFIRMED FALSE 1 +USE_CONFIRMED_OFF FALSE +PREFCACHE_MOVE_OFFPATH FALSE +CACHE_STAT_ENABLE FALSE +PREF_DCACHE_HIT_FILL_L1 TRUE +PREF_ICACHE_HIT_FILL_L1 TRUE +CRITICAL_ACCESS_PLOT_ENABLE FALSE +CRITICAL_ACCESS_PLOT_FILE "critical_access_plot.dat" +ROUND_ROBIN_TO_L1 FALSE +PREF_I_TOGETHER FALSE +ONE_MORE_CACHE_LINE_ENABLE FALSE +L1_STATIC_PARTITION_ENABLE 0 +L1_STATIC_PARTITION NULL +L1_DYNAMIC_PARTITION_ENABLE FALSE +L1_DYNAMIC_PARTITION_POLICY 0 +PARTITION_UMON_DSS_PREF_ENABLE FALSE +L1_CACHE_HIT_POSITION_COLLECT FALSE +L1_PART_ON FALSE +L1_PART_TRIGGER "c:1000000" +L1_PART_START "t:0" +L1_PART_WARMUP FALSE +L1_PART_SHADOW_WARMUP FALSE +L1_PART_METRIC 0 +L1_PART_SEARCH 0 +L1_PART_USE_STALLING TRUE +L1_PART_FILL_DELAY 0 +L1_SHADOW_TAGS_MODULO 1 +HIER_MSHR_ON FALSE +PERF_PRED_ENABLE FALSE +PERF_PRED_MECH PERF_PRED_CP +PERF_PRED_REQ_LATENCY_MECH PERF_PRED_REQ_LATENCY_MECH_REQ_LATENCY +PERF_PRED_COUNT_ALL FALSE +PERF_PRED_COUNT_INST_MISSES TRUE +PERF_PRED_COUNT_PREFETCHES FALSE +PERF_PRED_COUNT_OFFPATH_REQS FALSE +PERF_PRED_COUNT_BW_REQS TRUE +PERF_PRED_UPDATE_MEM_REQ_TYPE FALSE +PERF_PRED_SLACK_PERIOD_SIZE 32 +PERF_PRED_REQS_FINISH_AT_FILL FALSE +PERF_PRED_MEM_UTIL_VIA_BUS_BW FALSE +PERF_PRED_CHIP_UTIL_VIA_MEM_STALL FALSE +DUMB_MODEL_AVG_REQ_DISTANCE 100 +DUMB_MODEL_RANDOMIZE_DISTANCE FALSE +DUMB_MODEL_AVG_REQ_DISTANCE_PER_CORE NULL +DUMB_MODEL_AVG_ROW_HITS 1 +DUMB_MODEL_AVG_ROW_HITS_PER_CORE NULL +DUMB_MODEL_MLP 1 +DUMB_MODEL_MLP_PER_CORE NULL +RAMULATOR_STANDARD "DDR4" DDR4 +RAMULATOR_SPEED "DDR4_2400R" DDR4_2400R +RAMULATOR_ORG "DDR4_8Gb_x8" DDR4_8Gb_x8 +RAMULATOR_CHANNELS 1 1 +RAMULATOR_RANKS 1 1 +RAMULATOR_BANKGROUPS 4 4 +RAMULATOR_BANKS 4 4 +RAMULATOR_CHIP_WIDTH 8 8 +BUS_WIDTH_IN_BYTES 8 8 +RAMULATOR_ROWS 65536 65536 +RAMULATOR_COLS 1024 1024 +RAMULATOR_SCHEDULING_POLICY "FRFCFS_Cap" FRFCFS_Cap +RAMULATOR_READQ_ENTRIES 32 32 +RAMULATOR_WRITEQ_ENTRIES 32 32 +RAMULATOR_REC_CMD_TRACE "off" FALSE +RAMULATOR_PRINT_CMD_TRACE "off" FALSE +RAMULATOR_USE_REST_OF_ADDR_AS_ROW_ADDR "on" +RAMULATOR_TCK 833333 833333 +RAMULATOR_TCL 16 16 +RAMULATOR_TCCD 6 6 +RAMULATOR_TCCDS 4 4 +RAMULATOR_TCCDL 6 6 +RAMULATOR_TCWL 12 12 +RAMULATOR_TBL 4 4 +RAMULATOR_TWTR 9 9 +RAMULATOR_TWTRS 3 3 +RAMULATOR_TWTRL 9 9 +RAMULATOR_TRP 16 16 +RAMULATOR_TRPpb 16 16 +RAMULATOR_TRPab 16 16 +RAMULATOR_TRCD 16 16 +RAMULATOR_TRCDR 16 16 +RAMULATOR_TRCDW 16 16 +RAMULATOR_TRAS 39 39 +DRAM_TECH_IN_NM 32 32 +DVFS_ON FALSE +DVFS_METRIC DVFS_METRIC_NUM_ELEMS +DVFS_CONFIGS NULL +DVFS_CONFIG_FILE NULL +DVFS_START "t:0" +DVFS_PERIOD "t:312500000000" +DVFS_LOG TRUE +DVFS_INDIVIDUAL_CORES FALSE +DVFS_CHIP_LEVEL FALSE +DVFS_STATIC NULL +DVFS_FORCE_CONFIG NULL +DVFS_REPLAY_CONFIG_TRACE NULL +DVFS_USE_ORACLE FALSE +DVFS_USE_BW_SHARING FALSE +DVFS_USE_DRAM_SHARING FALSE +DVFS_USE_STALL_TIME FALSE +DVFS_DRAM_SHARING_SOLVER_BIN NULL +DVFS_DRAM_SHARING_SOLVER_STRICT TRUE +DVFS_BW_SHARING_BUS_UTIL_THRESH 0.95 +DVFS_BW_SHARING_MAX_REQS 28.0 +DVFS_BW_SHARING_MAX_RW_COST 0.25 +DVFS_BW_SHARING_NO_PREF_STALL TRUE +DVFS_BW_SHARING_CRIT_STATS TRUE +DVFS_COUNT_L1_ACCESS_STALL FALSE +NUM_CORES 1 +CHIP_CYCLE_TIME 312500 312500 +CORE_0_CYCLE_TIME 312500 +CORE_1_CYCLE_TIME 312500 +CORE_2_CYCLE_TIME 312500 +CORE_3_CYCLE_TIME 312500 +CORE_4_CYCLE_TIME 312500 +CORE_5_CYCLE_TIME 312500 +CORE_6_CYCLE_TIME 312500 +CORE_7_CYCLE_TIME 312500 +CORE_8_CYCLE_TIME 312500 +CORE_9_CYCLE_TIME 312500 +CORE_10_CYCLE_TIME 312500 +CORE_11_CYCLE_TIME 312500 +CORE_12_CYCLE_TIME 312500 +CORE_13_CYCLE_TIME 312500 +CORE_14_CYCLE_TIME 312500 +CORE_15_CYCLE_TIME 312500 +CORE_16_CYCLE_TIME 312500 +CORE_17_CYCLE_TIME 312500 +CORE_18_CYCLE_TIME 312500 +CORE_19_CYCLE_TIME 312500 +CORE_20_CYCLE_TIME 312500 +CORE_21_CYCLE_TIME 312500 +CORE_22_CYCLE_TIME 312500 +CORE_23_CYCLE_TIME 312500 +CORE_24_CYCLE_TIME 312500 +CORE_25_CYCLE_TIME 312500 +CORE_26_CYCLE_TIME 312500 +CORE_27_CYCLE_TIME 312500 +CORE_28_CYCLE_TIME 312500 +CORE_29_CYCLE_TIME 312500 +CORE_30_CYCLE_TIME 312500 +CORE_31_CYCLE_TIME 312500 +CORE_32_CYCLE_TIME 312500 +CORE_33_CYCLE_TIME 312500 +CORE_34_CYCLE_TIME 312500 +CORE_35_CYCLE_TIME 312500 +CORE_36_CYCLE_TIME 312500 +CORE_37_CYCLE_TIME 312500 +CORE_38_CYCLE_TIME 312500 +CORE_39_CYCLE_TIME 312500 +CORE_40_CYCLE_TIME 312500 +CORE_41_CYCLE_TIME 312500 +CORE_42_CYCLE_TIME 312500 +CORE_43_CYCLE_TIME 312500 +CORE_44_CYCLE_TIME 312500 +CORE_45_CYCLE_TIME 312500 +CORE_46_CYCLE_TIME 312500 +CORE_47_CYCLE_TIME 312500 +CORE_48_CYCLE_TIME 312500 +CORE_49_CYCLE_TIME 312500 +CORE_50_CYCLE_TIME 312500 +CORE_51_CYCLE_TIME 312500 +CORE_52_CYCLE_TIME 312500 +CORE_53_CYCLE_TIME 312500 +CORE_54_CYCLE_TIME 312500 +CORE_55_CYCLE_TIME 312500 +CORE_56_CYCLE_TIME 312500 +CORE_57_CYCLE_TIME 312500 +CORE_58_CYCLE_TIME 312500 +CORE_59_CYCLE_TIME 312500 +CORE_60_CYCLE_TIME 312500 +CORE_61_CYCLE_TIME 312500 +CORE_62_CYCLE_TIME 312500 +CORE_63_CYCLE_TIME 312500 +ISSUE_WIDTH 4 6 +RS_FILL_WIDTH 8 0 +NODE_TABLE_SIZE 256 224 +NODE_RET_WIDTH 4 6 +NODE_RETIRE_RATE 10 +RS_SIZES "256" 97 +RS_CONNECTIONS "xF" 0 +FU_TYPES "0, 0, 0, 0" 0 0 0 0 0 0 0 0 +DECODE_CYCLES 1 5 +MAP_CYCLES 1 5 +EXTRA_RECOVERY_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after recovery. +EXTRA_REDIRECT_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after redirect. +EXTRA_CALLSYS_CYCLES 20 const +DIE_ON_CALLSYS FALSE +DIE_ON_RET_STALL_THRESH 0 +DIE_ON_RET_STALL_CORE 0 +DIE_ON_MEM_BLOCK_THRESH 0 +DIE_ON_MEM_BLOCK_CORE 0 +FETCH_ACROSS_CACHE_LINES FALSE 1 +FETCH_OFF_PATH_OPS TRUE 0 +FETCH_BREAK_ON_TAKEN FALSE 1 +FETCH_TAKEN_BUBBLE_CYCLES 0 0 +WP_COLLECT_STATS FALSE +SWITCH_IC_FETCH_ON_RECOVERY TRUE +OP_INV_DELAY 1 +OP_NOP_DELAY 1 +OP_CF_DELAY 1 +OP_MOV_DELAY 1 +OP_CMOV_DELAY 1 +OP_LDA_DELAY 1 +OP_IMEM_DELAY 1 +OP_IADD_DELAY 1 +OP_IMUL_DELAY 3 +OP_IDIV_DELAY -20 +OP_ICMP_DELAY 1 +OP_LOGIC_DELAY 1 +OP_SHIFT_DELAY 1 +OP_FMEM_DELAY 1 +OP_FCVT_DELAY 3 +OP_FADD_DELAY 3 +OP_FMUL_DELAY 5 +OP_FMA_DELAY 5 +OP_FDIV_DELAY -20 +OP_FCMP_DELAY 3 +OP_FCMOV_DELAY 1 +OP_GATHER_DELAY 12 +OP_SCATTER_DELAY 18 +OP_PIPELINED_FAST_DELAY 2 +OP_PIPELINED_MEDIUM_DELAY 5 +OP_PIPELINED_SLOW_DELAY 10 +OP_NOTPIPELINED_MEDIUM_DELAY -5 +OP_NOTPIPELINED_SLOW_DELAY -20 +OP_NOTPIPELINED_VERY_SLOW_DELAY -100 +UNIFORM_OP_DELAY 0 +STALL_ON_WAIT_MEM TRUE +STORES_DO_NOT_BLOCK_WINDOW FALSE 1 +PREFS_DO_NOT_BLOCK_WINDOW FALSE 1 +OBEY_REG_DEP TRUE +OLDEST_FIRST_SCHED FALSE +FIND_EMPTIEST_RS FALSE +TRACK_L1_MISS_DEPS FALSE +CBP_TRACE_R0 NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir/trace/drmemtrace.omnetpp.552936.3514.trace.gz +CBP_TRACE_R1 NULL +CBP_TRACE_R2 NULL +CBP_TRACE_R3 NULL +CBP_TRACE_R4 NULL +CBP_TRACE_R5 NULL +CBP_TRACE_R6 NULL +CBP_TRACE_R7 NULL +CBP_TRACE_R8 NULL +CBP_TRACE_R9 NULL +CBP_TRACE_R10 NULL +CBP_TRACE_R11 NULL +CBP_TRACE_R12 NULL +CBP_TRACE_R13 NULL +CBP_TRACE_R14 NULL +CBP_TRACE_R15 NULL +CBP_TRACE_R16 NULL +CBP_TRACE_R17 NULL +CBP_TRACE_R18 NULL +CBP_TRACE_R19 NULL +CBP_TRACE_R20 NULL +CBP_TRACE_R21 NULL +CBP_TRACE_R22 NULL +CBP_TRACE_R23 NULL +CBP_TRACE_R24 NULL +CBP_TRACE_R25 NULL +CBP_TRACE_R26 NULL +CBP_TRACE_R27 NULL +CBP_TRACE_R28 NULL +CBP_TRACE_R29 NULL +CBP_TRACE_R30 NULL +CBP_TRACE_R31 NULL +CBP_TRACE_R32 NULL +CBP_TRACE_R33 NULL +CBP_TRACE_R34 NULL +CBP_TRACE_R35 NULL +CBP_TRACE_R36 NULL +CBP_TRACE_R37 NULL +CBP_TRACE_R38 NULL +CBP_TRACE_R39 NULL +CBP_TRACE_R40 NULL +CBP_TRACE_R41 NULL +CBP_TRACE_R42 NULL +CBP_TRACE_R43 NULL +CBP_TRACE_R44 NULL +CBP_TRACE_R45 NULL +CBP_TRACE_R46 NULL +CBP_TRACE_R47 NULL +CBP_TRACE_R48 NULL +CBP_TRACE_R49 NULL +CBP_TRACE_R50 NULL +CBP_TRACE_R51 NULL +CBP_TRACE_R52 NULL +CBP_TRACE_R53 NULL +CBP_TRACE_R54 NULL +CBP_TRACE_R55 NULL +CBP_TRACE_R56 NULL +CBP_TRACE_R57 NULL +CBP_TRACE_R58 NULL +CBP_TRACE_R59 NULL +CBP_TRACE_R60 NULL +CBP_TRACE_R61 NULL +CBP_TRACE_R62 NULL +CBP_TRACE_R63 NULL +MEMTRACE_MODULES_LOG NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.omnetpp.552936.5555.dir/raw +DUMB_CORE_ON FALSE +DUMB_CORE 1 +DEBUG_CYCLE_START 0 0 +DEBUG_CYCLE_STOP 0 -1 +DEBUG_TIME_START 0 +DEBUG_TIME_STOP 0 +DEBUG_INST_START 0 0 +DEBUG_INST_STOP 0 -1 +DEBUG_OP_START 0 +DEBUG_OP_STOP 0 +DEBUG_CACHE_LIB FALSE +DEBUG_HASH_LIB FALSE +DEBUG_LIST_LIB FALSE +DEBUG_PORT_LIB FALSE +DEBUG_BUS_LIB FALSE +DEBUG_OP_POOL FALSE +DEBUG_ORACLE FALSE +DEBUG_FRONTEND FALSE +DEBUG_ADDR_TRANS FALSE +DEBUG_BP FALSE +DEBUG_BP_DIR FALSE +DEBUG_BTB FALSE +DEBUG_CRS FALSE +DEBUG_MAP FALSE +DEBUG_MEMORY FALSE +DEBUG_REPLAY FALSE +DEBUG_FREQ FALSE +DEBUG_MODEL FALSE +DEBUG_THREAD FALSE +DEBUG_ICACHE_STAGE FALSE +DEBUG_DECODE_STAGE FALSE +DEBUG_MAP_STAGE FALSE +DEBUG_NODE_STAGE FALSE +DEBUG_EXEC_STAGE FALSE +DEBUG_DCACHE_STAGE FALSE +DEBUG_RETIRED_UOPS FALSE +DEBUG_EXC_INSERTS FALSE +DEBUG_BP_CONF FALSE +DEBUG_ONPATH_CONF FALSE +DEBUG_STREAM FALSE +DEBUG_STREAM_MEM FALSE +DEBUG_WAY FALSE +DEBUG_L2MARKV FALSE +DEBUG_L2L1PREF FALSE +DEBUG_PERF_PRED FALSE +DEBUG_POWER_UTILS FALSE +DEBUG_DVFS FALSE +DEBUG_TRACE_READ FALSE +DEBUG_INST_FIELDS FALSE +DEBUG_OP_FIELDS FALSE +DEBUG_PIN_EXEC_DRIVEN FALSE +DEBUG_CACHE_PART FALSE +DEBUG_OPTIMIZER2 FALSE +DEBUG_PREF FALSE +PERFECT_BP FALSE +PERFECT_BTB FALSE +PERFECT_IBP FALSE +PERFECT_CRS FALSE +PERFECT_CBR_BTB FALSE +PERFECT_NT_BTB FALSE +CFS_PER_CYCLE 3 6 # Number of branches that can be predicted in a single cycle +UPDATE_BP_OFF_PATH FALSE 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +BP_UPDATE_AT_RETIRE FALSE 0 # Update the BP at retire. If false, update at the end of exec. +BP_MECH 0 tagescl +LATE_BP_MECH NUM_BP +LATE_BP_LATENCY 5 +HIST_LENGTH 16 +PHT_CTR_BITS 2 const +BHT_ENTRIES (4 * 1024) +BHT_ASSOC 4 +HYBRIDS_INDEX_LENGTH 16 +HYBRIDG_HIST_LENGTH 16 +HYBRIDP_HIST_LENGTH 16 +FILTER_INDEX_LENGTH 16 +USE_FILTER FALSE +INF_HYBRIDGP FALSE +BP_HASH_TOS FALSE +IBTB_HASH_TOS FALSE +BTB_MECH 0 generic +BTB_ENTRIES (4 * 1024) 4096 +BTB_ASSOC 4 4 +BTB_OFF_PATH_WRITES TRUE 1 +ENABLE_CRS TRUE 1 +CRS_ENTRIES 32 32 +CRS_REALISTIC 0 1 +ENABLE_IBP TRUE 1 # Enable the indirect branch predictor +USE_PAT_HIST TRUE +IBTB_MECH 1 tc_tagged +IBTB_HIST_LENGTH 16 +IBTB_OFF_PATH_WRITES TRUE 1 # Allow off path ops to update the ibtb. +TARGETS_IN_HIST 4 +TC_ENTRIES (4 * 1024) 4096 +TC_ASSOC 4 4 +NUM_CORR_BRANCHES 3 +SEL_HIST_BP_ENTRIES 8192 +SEL_HIST_LENGTH 16 +SEL_HIST_DYN_CNT_TH 16 +SEL_HIST_MISPRED_TH 4 +ENABLE_BP_CONF FALSE +CONF_MECH 0 +PERF_BP_CONF_PRED FALSE +BPC_BITS 16 +BPC_MECH 1 +BPC_CTR_RESET TRUE +BPC_CIT_BITS 8 +BPC_CIT_TH 50 +BPC_CTR_BITS 3 +OPC_COUNT_ZEROS FALSE +OPC_COUNT_THRESH 10 +INF_LOOP FALSE +INF_LOOP_BUCKETS 811 +LOOP_ENTRIES (4 * 1024) +LOOP_ASSOC 4 +LOOP_COUNT_MAX 127 +LOOP_REPEAT_MAX 15 +KNOB_PRINT_BRINFO FALSE +BR_MISPRED_FILE NULL +CONF_PERCEPTRON_TH 0 +CONF_PERCEPTRON_CTR_BITS 8 +CONF_PERCEPTRON_ENTRIES 127 +CONF_PERCEPTRON_THRESH_OVRD 0 +CONF_HIST_LENGTH 32 +PERCEPTRON_CONF_USE_CONF FALSE +PERCEPTRON_CONF_TRAIN_HIS FALSE +PERCEPTRON_CONF_TRAIN_CONF FALSE +PERCEPTRON_CONF_TRAIN_OFFSET_CONF FALSE +PERCEPTRON_TRAIN_MISP_FACTOR 1 +PERCEPTRON_TRAIN_CORR_FACTOR 1 +PERCEPTRON_CONF_HIS_BOTH FALSE +PERCEPTRON_CONF_HIS_BOTH_LENGTH 4 +ENABLE_ICACHE_PACKET_BREAKING TRUE +NUM_LOAD_STORE_PER_PACKET 0 +PACKET_BREAK_ON_FUS FALSE +PACKET_BREAK_FU_TYPES "G,G,G,G,G,G,G,G,G,G,G,G" +POWER_INTF_ON FALSE +POWER_INTF_ENABLE_SCALING FALSE +POWER_INTF_EXEC "power/power_intf.py" +POWER_INTF_REF_CHIP_TECH_NM 22 +POWER_INTF_REF_CHIP_FREQ (3.2e9) +POWER_INTF_REF_MEMORY_FREQ (0.8e9) +POWER_OTHER (0.0) +PREF_STREAM_ON FALSE 1 +PREF_STREAM_PER_CORE_ENABLE FALSE 1 +STREAM_BUFFER_N 16 +STREAM_PREFETCH_N 2 4 +STREAM_START_DIS 5 1 +STREAM_LENGTH 16 64 +STREAM_FULL_N 1 +STREAM_TRAIN_LENGTH 16 +STREAM_TRAIN_NUM 1 4 +PREF_ACC_USE_CACHE FALSE +STREAM_STALL_ON_QUEUE_FULL FALSE +PREF_SCHEDULE_NUM 4 +TRAIN_FILTER_SIZE 32 +PREF_REQ_Q_SIZE 64 +STREAM_CREATE_ON_DC_MISS FALSE 0 +STREAM_CREATE_ON_L1_MISS TRUE 1 +STREAM_TRAIN_ON_WRONGPATH TRUE +STREAM_CREATE_ON_WRONGPATH TRUE +STREAM_PREF_INTO_DCACHE FALSE +REMOVE_REDUNDANT_STREAM FALSE +L2HIT_STREAM_SCHEDULE_NUM 4 +PREF_REQ_QUEUE_FILTER_ON FALSE +HW_PREF_HIT_TRAIN_STREAM FALSE +L2HIT_STREAM_BUFFER_N 32 +L2HIT_STREAM_PREFETCH_N 2 +L2HIT_STREAM_START_DIS 2 +L2HIT_STREAM_LENGTH 8 +L2HIT_PREF_REQ_Q_SIZE 128 +L2HIT_L2ACCESS_REQ_Q_SIZE 64 +PREF_STREAM_ACCPERSTREAM FALSE +PREF_ACC_DISTANCE_10 128 +PREF_FRAMEWORK_ON FALSE 1 +PREF_TRACE_ON FALSE +PREF_DL0REQ_QUEUE_SIZE 32 +PREF_UMLC_REQ_QUEUE_SIZE 64 +PREF_UL1REQ_QUEUE_SIZE 128 +PREF_SHARED_QUEUES TRUE 0 +PREF_DL0_MISS_ON TRUE +PREF_DL0_HIT_ON TRUE +PREF_DL0REQ_QUEUE_FILTER_ON TRUE +PREF_UMLC_REQ_QUEUE_FILTER_ON TRUE +PREF_UL1REQ_QUEUE_FILTER_ON TRUE +PREF_DL0REQ_ADD_FILTER_ON TRUE +PREF_UMLC_REQ_ADD_FILTER_ON TRUE +PREF_UL1REQ_ADD_FILTER_ON TRUE +PREF_DL0REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UMLC_REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UL1REQ_QUEUE_OVERWRITE_ON_FULL FALSE 1 +PREF_DL0SCHEDULE_NUM 4 +PREF_UMLC_SCHEDULE_NUM 4 +PREF_UL1SCHEDULE_NUM 4 +PREF_L1Q_DEMAND_RESERVE 0 +PREF_REPORT_PREF_MATCH_AS_MISS FALSE +PREF_REPORT_PREF_MATCH_AS_HIT TRUE +PREF_UPDATE_ON_WRONGPATH TRUE +PREF_TRAIN_ON_PREF_MISSES FALSE 0 +PREF_ORACLE_TRAIN_ON FALSE 0 +PREF_REQ_DROP FALSE +PREF_THROTTLE_ON FALSE +PREF_THROTTLEFB_ON FALSE 1 +PREF_ACC_THRESH_1 0.90 0.75 +PREF_ACC_THRESH_2 0.70 0.4 +PREF_ACC_THRESH_3 0.60 0.4 +PREF_ACC_THRESH_4 0.40 +PREF_UPDATE_INTERVAL 0 8192 +PREF_ANALYZE_LOAD FALSE +PREF_POL_THRESH_1 0.25 +PREF_POL_THRESH_2 0.10 +PREF_POLBV_ON FALSE +PREF_POLBV_SIZE 1024 +PREF_TIMELY_THRESH 0.05 0.01 +PREF_POLPF_THRESH 0.01 0.005 +PREF_DEGFB_USEONLYACC FALSE +PREF_DEGFB_USEONLYPOL FALSE +PREF_DEGFB_USEONLYLATE FALSE +PREF_TIMELY_THRESH_2 0.005 +PREF_DEGFB_STATPHASEFILE FALSE +PREF_MAX_DEGFB 4 +PREF_DHAL FALSE +PREF_DHAL_SENTTHRESH 16 +PREF_DHAL_USETHRESH_MAX 12 +PREF_DHAL_USETHRESH_MIN2 8 +PREF_DHAL_USETHRESH_MIN1 4 +PREF_DHAL_MAXDEG 64 +PREF_HFILTER_ON FALSE +PREF_HFILTER_INDEX_BITS 12 +PREF_HFILTER_USE_PC FALSE +PREF_HFILTER_PRED_USELESS_THRES 2 +PREF_HFILTER_RESET_ENABLE FALSE +PREF_HFILTER_RESET_INTERVAL 100000 +L2L1PREF_ON FALSE +L2WAY_PREF FALSE +L2MARKV_PREF_ON FALSE +L2NEXT_PREF_ON FALSE +L2HIT_STREAM_PREF_ON FALSE +L2L1_DC_HIT_TRAIN FALSE +L1_HIT_DUMP_FILE_ON FALSE +L1_HIT_DUMP_WO_TXT FALSE +L1_HIT_DUMPFILE "l1hit_dump.out" +IDEAL_L2_L1_PREFETCHER FALSE +IDEAL_L2_ICACHE_PREFETCHER FALSE +L1WAY_PREF_SEND_QUEUE 4 +L1PREF_REQ_QUEUE_SIZE 1024 +L1PREF_IMMEDIATE FALSE +L1WAY_PREF_TIMER_DIS 1000 +L1MARKV_PREF_SEND_QUEUE 4 +L1PREF_MARKV_REQ_QUEUE_SIZE 1024 +MARKV_L2ACCESS_REQ_Q_SIZE 64 +L1MARKV_PREF_IMMEDIATE FALSE +L1MARKV_PREF_TIMER_DIS 1 +L2L1_HIT_TRAIN TRUE +L1MARKV_REQ_TH 1 +L2L1_IMMEDIATE_PREF_CACHE FALSE +L2L1_FILL_PREF_CACHE FALSE +L2L1_L2_HIT_STAT FALSE +PREF_GHB_ON FALSE +DEBUG_PREF_GHB FALSE +PREF_GHB_BUFFER_N 1024 +PREF_GHB_INDEX_N 128 +PREF_GHB_CZONE_BITS 12 +PREF_GHB_DEGREE 16 +PREF_GHB_MAX_DEGREE 32 +PREF_STRIDE_ON FALSE +DEBUG_PREF_STRIDE FALSE +PREF_STRIDE_TABLE_N 1024 +PREF_STRIDE_REGION_BITS 16 +PREF_STRIDE_DEGREE 4 +PREF_STRIDE_DISTANCE 16 +PREF_STRIDE_STARTDISTANCE 1 +PREF_STRIDE_SINGLE_THRESH 6 +PREF_STRIDE_MULTI_THRESH 6 +PREF_STRIDE_SINGLE_STRIDE_MODE FALSE +PREF_STRIDEPC_ON FALSE +DEBUG_PREF_STRIDEPC FALSE +PREF_STRIDEPC_TABLE_N 1024 +PREF_STRIDEPC_DEGREE 4 +PREF_STRIDEPC_DISTANCE 16 +PREF_STRIDEPC_USELOADADDR FALSE +PREF_STRIDEPC_TRAINNUM 2 +PREF_STRIDEPC_STARTDIS 4 +PREF_PHASE_ON FALSE +PREF_PHASE_STUDY FALSE +DEBUG_PREF_PHASE FALSE +PREF_PHASE_PRIME_HASH 16381 +PREF_PHASE_INFOSIZE 16384 +PREF_PHASE_LOG2REGIONSIZE 12 +PREF_PHASE_REGIONENTRIES 64 +PREF_PHASE_TRACKEDREGIONS 32 +PREF_PHASE_INTERVAL 100000 +PREF_PHASE_TABLE_SIZE 64 +PREF_PHASE_MAXDIFF_THRESH 64 +PREF_PHASE_MIN_MISSES 64 +PREF_PHASE_MISSPER 0.4 +PREF_2DC_ON FALSE +DEBUG_PREF_2DC FALSE +PREF_2DC_CACHE_SIZE (1 * 1024) +PREF_2DC_CACHE_ASSOC 4 +PREF_2DC_CACHE_LINE_SIZE 1 +PREF_2DC_DEGREE 16 +PREF_2DC_ZONE_SHIFT 10 +PREF_2DC_TAG_SIZE 16 +PREF_2DC_NUM_REGIONS 64 +PREF_2DC_REGION_HASH 61 +PREF_MARKOV_ON FALSE +DEBUG_PREF_MARKOV FALSE +PREF_MARKOV_NUM_ENTRIES 65536 +PREF_MARKOV_NUM_NEXT_STATES 8 +PREF_MARKOV_SEND_ON_PREF_HIT TRUE +PREF_MARKOV_UPDATE_ON_PREF_HIT TRUE +PREF_MARKOV_TABLE_UPDATE_POLICY 0 +PREF_MARKOV_SEND_THRESHOLD 0 +PREF_SMS_ON FALSE 1 +PREF_SMS_AT_SIZE 64 +PREF_SMS_FT_SIZE 64 +PREF_SMS_PHT_SIZE 16384 +PREF_SMS_PRF_SIZE 1024 +PREF_SMS_REGION_SIZE 2048 diff --git a/labs/LAB5/runs/omnetpp-sms1/bp.stat.0.out b/labs/LAB5/runs/omnetpp-sms1/bp.stat.0.out new file mode 100644 index 00000000..8330cd7a --- /dev/null +++ b/labs/LAB5/runs/omnetpp-sms1/bp.stat.0.out @@ -0,0 +1,752 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 80804991 Instructions: 100000000 IPC: 1.23755 + +BTB_ON_PATH_MISS 10364 0.050% 10364 0.050% +BTB_ON_PATH_HIT 20637713 99.950% 20637713 99.950% + 20648077 100.000% 20648077 100.000% + 1.00 1.00 1.00 1.00 + +BTB_OFF_PATH_MISS 0 -nan% 0 -nan% +BTB_OFF_PATH_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BTB_ON_PATH_WRITE 10364 100.000% 10364 100.000% +BTB_OFF_PATH_WRITE 0 0.000% 0 0.000% + 10364 100.000% 10364 100.000% + 0.00 0.00 0.00 0.00 + +BP_ON_PATH_CORRECT 19959332 96.664% 19959332 96.664% +BP_ON_PATH_MISPREDICT 241183 1.168% 241183 1.168% +BP_ON_PATH_MISFETCH 447562 2.168% 447562 2.168% + 20648077 100.000% 20648077 100.000% + 0.06 0.30 0.06 0.30 + +BP_OFF_PATH_CORRECT 0 -nan% 0 -nan% +BP_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% +BP_OFF_PATH_MISFETCH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +LATE_BP_ON_PATH_CORRECT 20648077 100.000% 20648077 100.000% +LATE_BP_ON_PATH_MISPREDICT 0 0.000% 0 0.000% +LATE_BP_ON_PATH_MISFETCH 0 0.000% 0 0.000% + 20648077 100.000% 20648077 100.000% + 0.00 0.00 0.00 0.00 + +LATE_BP_OFF_PATH_CORRECT 0 -nan% 0 -nan% +LATE_BP_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% +LATE_BP_OFF_PATH_MISFETCH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_PVN 0 -nan% 0 -nan% +BP_ON_PATH_CONF_PVN_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_PVP 0 -nan% 0 -nan% +BP_ON_PATH_CONF_PVP_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_SPEC 0 -nan% 0 -nan% +BP_ON_PATH_CONF_SPEC_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CRS_MISS_ON_PATH 63615 2.542% 63615 2.542% +CRS_HIT_ON_PATH 2439104 97.458% 2439104 97.458% + 2502719 100.000% 2502719 100.000% + 0.97 0.96 0.97 0.96 + +CRS_MISS_OFF_PATH 0 -nan% 0 -nan% +CRS_HIT_OFF_PATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CRS_CLOBBER 0 0 + +TARG_ON_PATH_MISS 285060 16.021% 285060 16.021% +TARG_ON_PATH_HIT 1494285 83.979% 1494285 83.979% + 1779345 100.000% 1779345 100.000% + 0.84 0.78 0.84 0.78 + +TARG_OFF_PATH_MISS 0 -nan% 0 -nan% +TARG_OFF_PATH_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_ON_PATH_WRITE 1779345 100.000% 1779345 100.000% +TARG_OFF_PATH_WRITE 0 0.000% 0 0.000% + 1779345 100.000% 1779345 100.000% + 0.00 0.00 0.00 0.00 + +TARG_HYBRID_CORRECT_TAGLESS 0 -nan% 0 -nan% +TARG_HYBRID_CORRECT_TAGGED 0 -nan% 0 -nan% +TARG_HYBRID_MISPRED_TAGLESS 0 -nan% 0 -nan% +TARG_HYBRID_MISPRED_TAGGED 0 -nan% 0 -nan% +TARG_HYBRID_NO_PRED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_VP_INDIRECT_MISPRED 0 -nan% 0 -nan% +TARG_VP_INDIRECT_NOPRED 0 -nan% 0 -nan% +TARG_VP_INDIRECT_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CBR_ON_PATH_CORRECT 13113453 98.194% 13113453 98.194% +CBR_ON_PATH_MISPREDICT 241183 1.806% 241183 1.806% + 13354636 100.000% 13354636 100.000% + 0.02 0.13 0.02 0.13 + +CBR_ON_PATH_CORRECT_PER1000INST 13113453 131.1345 13113453 131.1345 + +CBR_ON_PATH_MISPREDICT_PER1000INST 241183 2.4118 241183 2.4118 + +CBR_OFF_PATH_CORRECT 0 -nan% 0 -nan% +CBR_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PRED_TO_UPDATE_CYCLES_0 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_1 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_2 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_3 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_4 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_5 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_6 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_7 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_8 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_9 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_10 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_11 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_12 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_13 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_14 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_15 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_16 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_17 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_18 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_19 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_20 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_21 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_22 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_23 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_24 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_25 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_26 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_27 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_28 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_29 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_30 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_CORRECTED 0 -nan% 0 -nan% +BP_NOT_CORRECTED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_CORRECTED 0 -nan% 0 -nan% +TARG_NOT_CORRECTED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_MISP_PENALTY 24283698 24283698 + +BP_ON_PATH_CONF_MISPRED 0 -nan% 0 -nan% +BP_ON_PATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_OFF_PATH_CONF_MISPRED 0 -nan% 0 -nan% +BP_OFF_PATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_PRED_MIS_CONF_MISPRED 0 -nan% 0 -nan% +BP_ON_PATH_PRED_MIS_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_PRED_COR_CONF_MISPRED 0 -nan% 0 -nan% +BP_ON_PATH_PRED_COR_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_OFF_PATH_PRED_MIS_CONF_MISPRED 0 -nan% 0 -nan% +BP_OFF_PATH_PRED_MIS_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_OFF_PATH_PRED_COR_CONF_MISPRED 0 -nan% 0 -nan% +BP_OFF_PATH_PRED_COR_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ONPATH_CONF_MISPRED 0 -nan% 0 -nan% +ONPATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ONPATH_ON_PATH_CONF_MISPRED 0 -nan% 0 -nan% +ONPATH_ON_PATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ONPATH_OFF_PATH_CONF_MISPRED 0 -nan% 0 -nan% +ONPATH_OFF_PATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PRED_ONPATH_CONF_MISPRED 0 -nan% 0 -nan% +PRED_ONPATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PRED_OFFPATH_CONF_MISPRED 0 -nan% 0 -nan% +PRED_OFFPATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +LONG_OVWT_MIS 0 -nan% 0 -nan% +LONG_OVWT_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_0_7_MIS 0 -nan% 0 -nan% +OPC_LENGTH_0_7_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_8_15_MIS 0 -nan% 0 -nan% +OPC_LENGTH_8_15_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_16_23_MIS 0 -nan% 0 -nan% +OPC_LENGTH_16_23_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_24_31_MIS 0 -nan% 0 -nan% +OPC_LENGTH_24_31_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_32_39_MIS 0 -nan% 0 -nan% +OPC_LENGTH_32_39_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_40_47_MIS 0 -nan% 0 -nan% +OPC_LENGTH_40_47_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_48_55_MIS 0 -nan% 0 -nan% +OPC_LENGTH_48_55_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_56_63_MIS 0 -nan% 0 -nan% +OPC_LENGTH_56_63_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_64_71_MIS 0 -nan% 0 -nan% +OPC_LENGTH_64_71_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_72_79_MIS 0 -nan% 0 -nan% +OPC_LENGTH_72_79_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_80_MIS 0 -nan% 0 -nan% +OPC_LENGTH_80_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ALL_ONES_MIS 0 -nan% 0 -nan% +ALL_ONES_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan 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0 0 + +CHIP_UTILIZATION_UNDER_MEM_REQ 0 -nan 0 -nan + +CHIP_UTILIZATION_UNDER_NO_MEM_REQ 0 -nan 0 -nan + +CHIP_UTILIZATION_UNDER_CRITICAL_MEM_REQ 0 -nan 0 -nan + +CHIP_UTILIZATION_UNDER_NONCRITICAL_MEM_REQ 0 -nan 0 -nan + +CYCLES_NOT_WAITING_FOR_OFF_CHIP 0 0.0000 0 0.0000 + +FUS_BUSY_NOT_WAITING_FOR_OFF_CHIP 0 -nan 0 -nan + +CYCLES_WAITING_FOR_OFF_CHIP 0 0.0000 0 0.0000 + +FUS_BUSY_WAITING_FOR_OFF_CHIP 0 -nan 0 -nan + +TOTAL_OFF_CHIP_DELAYS_LEFT 0 0 + +WRONG_IO_SCHED 0 0 + +DVFS_CONFIG_SWITCH 0 0 + + + diff --git a/labs/LAB5/runs/omnetpp-sms1/fetch.stat.0.out b/labs/LAB5/runs/omnetpp-sms1/fetch.stat.0.out new file mode 100644 index 00000000..fe330050 --- /dev/null +++ b/labs/LAB5/runs/omnetpp-sms1/fetch.stat.0.out @@ -0,0 +1,248 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 80804991 Instructions: 100000000 IPC: 1.23755 + +ICACHE_CYCLE 80804991 80804991 + +TCACHE_CYCLE 0 0 + +ICACHE_CYCLE_ONPATH 44047698 54.511% 44047698 54.511% +ICACHE_CYCLE_OFFPATH 36757293 45.489% 36757293 45.489% + 80804991 100.000% 80804991 100.000% + 0.45 0.48 0.45 0.48 + +FETCH_ON_PATH 26446473 100.000% 26446473 100.000% +FETCH_OFF_PATH 0 0.000% 0 0.000% + 26446473 100.000% 26446473 100.000% + 0.00 0.00 0.00 0.00 + +FETCHED_OPS_ON_PATH 0 -nan% 0 -nan% +FETCHED_OPS_OFF_PATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +INST_LOST_WAIT_FOR_MISP_RECOVERY 0 0.000% 0 0.000% +INST_LOST_WAIT_FOR_TIMER 0 0.000% 0 0.000% +INST_LOST_WAIT_FOR_EMPTY_ROB 0 0.000% 0 0.000% +INST_LOST_WAIT_FOR_REDIRECT 701274 0.260% 701274 0.260% +INST_LOST_FETCH 128794978 47.787% 128794978 47.787% +INST_LOST_OFF_PATH 0 0.000% 0 0.000% +INST_LOST_FULL_WINDOW 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_OTHER 2873268 1.066% 2873268 1.066% +INST_LOST_ROB_STALL_WAIT_FOR_RECOVERY 0 0.000% 0 0.000% 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+LOW_CONF_COUNT_RET_19 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_20 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + + + diff --git a/labs/LAB5/runs/omnetpp-sms1/inst.stat.0.out b/labs/LAB5/runs/omnetpp-sms1/inst.stat.0.out new file mode 100644 index 00000000..b33ed648 --- /dev/null +++ b/labs/LAB5/runs/omnetpp-sms1/inst.stat.0.out @@ -0,0 +1,103 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 80804991 Instructions: 100000000 IPC: 1.23755 + +ST_OP_INV 0 0.000% 0 0.000% +ST_OP_NOP 3767097 2.925% 3767097 2.925% +ST_OP_CF 20648077 16.032% 20648077 16.032% +ST_OP_MOV 11427755 8.873% 11427755 8.873% +ST_OP_CMOV 131149 0.102% 131149 0.102% +ST_OP_LDA 4577584 3.554% 4577584 3.554% +ST_OP_IMEM 46557190 36.148% 46557190 36.148% +ST_OP_IADD 21401620 16.617% 21401620 16.617% +ST_OP_IMUL 49026 0.038% 49026 0.038% +ST_OP_IDIV 0 0.000% 0 0.000% +ST_OP_ICMP 8294421 6.440% 8294421 6.440% +ST_OP_LOGIC 8896172 6.907% 8896172 6.907% +ST_OP_SHIFT 1027803 0.798% 1027803 0.798% +ST_OP_FMEM 1072759 0.833% 1072759 0.833% +ST_OP_FCVT 185482 0.144% 185482 0.144% +ST_OP_FADD 2 0.000% 2 0.000% +ST_OP_FMUL 121551 0.094% 121551 0.094% +ST_OP_FMA 2 0.000% 2 0.000% +ST_OP_FDIV 0 0.000% 0 0.000% +ST_OP_FCMP 0 0.000% 0 0.000% +ST_OP_FCMOV 0 0.000% 0 0.000% +ST_OP_GATHER 0 0.000% 0 0.000% +ST_OP_SCATTER 0 0.000% 0 0.000% +ST_OP_PIPELINED_FAST 319006 0.248% 319006 0.248% +ST_OP_PIPELINED_MEDIUM 0 0.000% 0 0.000% +ST_OP_PIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_MEDIUM 318282 0.247% 318282 0.247% +ST_OP_NOTPIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_VERY_SLOW 0 0.000% 0 0.000% + 128794978 100.000% 128794978 100.000% + 5.90 3.10 5.90 3.10 + +ST_NOT_CF 108146901 83.968% 108146901 83.968% +ST_CF_BR 1425785 1.107% 1425785 1.107% +ST_CF_CBR 13354636 10.369% 13354636 10.369% +ST_CF_CALL 1585592 1.231% 1585592 1.231% +ST_CF_IBR 862220 0.669% 862220 0.669% +ST_CF_ICALL 917125 0.712% 917125 0.712% +ST_CF_ICO 0 0.000% 0 0.000% +ST_CF_RET 2502719 1.943% 2502719 1.943% +ST_CF_SYS 0 0.000% 0 0.000% + 128794978 100.000% 128794978 100.000% + 0.45 1.18 0.45 1.18 + +ST_BAR_NONE 128794978 100.000% 128794978 100.000% +ST_BAR_FETCH 0 0.000% 0 0.000% +ST_BAR_ISSUE 0 0.000% 0 0.000% +ST_BAR_BOTH 0 0.000% 0 0.000% + 128794978 100.000% 128794978 100.000% + 0.00 0.00 0.00 0.00 + +ST_NOT_MEM 81165029 63.019% 81165029 63.019% +ST_MEM_LD 30704585 23.840% 30704585 23.840% +ST_MEM_ST 16925364 13.141% 16925364 13.141% +ST_MEM_PF 0 0.000% 0 0.000% +ST_MEM_WH 0 0.000% 0 0.000% +ST_MEM_EVICT 0 0.000% 0 0.000% + 128794978 100.000% 128794978 100.000% + 0.50 0.60 0.50 0.60 + +ST_NOT_MEM_OFFPATH 0 -nan% 0 -nan% +ST_MEM_LD_OFFPATH 0 -nan% 0 -nan% +ST_MEM_ST_OFFPATH 0 -nan% 0 -nan% +ST_MEM_PF_OFFPATH 0 -nan% 0 -nan% +ST_MEM_WH_OFFPATH 0 -nan% 0 -nan% +ST_MEM_EVIC_OFFPATHT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ST_OP_ONPATH 128794978 128794978 + +ST_OP_OFFPATH 0 0 + +ST_FAKE_OP_OFFPATH 0 -nan% 0 -nan% +ST_NOT_FAKE_OP_OFFPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ST_FAKE_REASON_NOT_FAKE 0 -nan% 0 -nan% +ST_FAKE_REASON_REDIRECT_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_RETURN_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_NONRET_CF_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_NOT_TAKEN_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_WRONG_PATH_STORE_TO_NEW_REGION 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ST_INST_ONPATH 100000072 100000072 + +ST_INST_OFFPATH 0 0 + +STATIC_PIN_NOP 0 0 + +DYNAMIC_PIN_REP_GREATER_256 0 0 + + + diff --git a/labs/LAB5/runs/omnetpp-sms1/l2l1pref.stat.0.out b/labs/LAB5/runs/omnetpp-sms1/l2l1pref.stat.0.out new file mode 100644 index 00000000..02950f42 --- /dev/null +++ b/labs/LAB5/runs/omnetpp-sms1/l2l1pref.stat.0.out @@ -0,0 +1,140 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 80804991 Instructions: 100000000 IPC: 1.23755 + +L2WAY_FILL_L1 0 0 + +L2WAY_WAY_HIT 0 -nan% 0 -nan% +L2WAY_WAY_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_PREF_REQ 0 0 + +L2WAY_PREF_HIT_DATA_IN_CACHE 0 -nan% 0 -nan% +L2WAY_PREF_HIT_DATA_REQ 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_TRAIN_HIT 0 -nan% 0 -nan% +L2WAY_TRAIN_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L1_HIT_REQ_TYPE_IFETCH 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DFETCH 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DSTORE 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_IPRF 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DPRF 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_WB 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2_ACCESS_INTERVAL__0 0 -nan% 0 -nan% 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0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + + + diff --git a/labs/LAB5/runs/omnetpp-sms1/memory.stat.0.out b/labs/LAB5/runs/omnetpp-sms1/memory.stat.0.out new file mode 100644 index 00000000..ddb99076 --- /dev/null +++ b/labs/LAB5/runs/omnetpp-sms1/memory.stat.0.out @@ -0,0 +1,3416 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 80804991 Instructions: 100000000 IPC: 1.23755 + +ICACHE_MISS 391787 1.155% 391787 1.155% +ICACHE_HIT 33515548 98.845% 33515548 98.845% + 33907335 100.000% 33907335 100.000% + 0.99 0.98 0.99 0.98 + +ICACHE_MISS_ONPATH 391787 100.000% 391787 100.000% +ICACHE_MISS_OFFPATH 0 0.000% 0 0.000% + 391787 100.000% 391787 100.000% + 0.00 0.00 0.00 0.00 + +ICACHE_HIT_ONPATH 33515548 100.000% 33515548 100.000% +ICACHE_HIT_OFFPATH 0 0.000% 0 0.000% + 33515548 100.000% 33515548 100.000% + 0.00 0.00 0.00 0.00 + +ICACHE_HIT_ONPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +ICACHE_HIT_ONPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ICACHE_HIT_OFFPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +ICACHE_HIT_OFFPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DCACHE_MISS 3089015 6.485% 3089015 6.485% +DCACHE_ST_BUFFER_HIT 72589 0.152% 72589 0.152% +DCACHE_HIT 44468310 93.362% 44468310 93.362% + 47629914 100.000% 47629914 100.000% + 1.87 1.81 1.87 1.81 + +DCACHE_MISS_COMPULSORY 293163 0.0949 293163 0.0949 + +DCACHE_MISS_CAPACITY 2793769 0.9044 2793769 0.9044 + +DCACHE_MISS_CONFLICT 2083 0.0007 2083 0.0007 + +DCACHE_MISS_ONPATH 3089015 100.000% 3089015 100.000% +DCACHE_MISS_OFFPATH 0 0.000% 0 0.000% + 3089015 100.000% 3089015 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_ST_BUFFER_HIT_ONPATH 72589 100.000% 72589 100.000% +DCACHE_ST_BUFFER_HIT_OFFPATH 0 0.000% 0 0.000% + 72589 100.000% 72589 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_HIT_ONPATH 44468310 100.000% 44468310 100.000% +DCACHE_HIT_OFFPATH 0 0.000% 0 0.000% + 44468310 100.000% 44468310 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_HIT_ONPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +DCACHE_HIT_ONPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DCACHE_HIT_OFFPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +DCACHE_HIT_OFFPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DCACHE_MISS_LD 2184167 70.708% 2184167 70.708% +DCACHE_MISS_ST 904848 29.292% 904848 29.292% + 3089015 100.000% 3089015 100.000% + 0.29 0.41 0.29 0.41 + +DCACHE_MISS_LD_ONPATH 2184167 100.000% 2184167 100.000% +DCACHE_MISS_LD_OFFPATH 0 0.000% 0 0.000% + 2184167 100.000% 2184167 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_MISS_ST_ONPATH 904848 100.000% 904848 100.000% +DCACHE_MISS_ST_OFFPATH 0 0.000% 0 0.000% + 904848 100.000% 904848 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_MISS_WAITMEM 0 0 + +MEM_REQ_ROW_BUFFER_HITS 0 -nan% 0 -nan% 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5.239% +CORE_PREF_L1_NOT_USED_LATENCY800 1351 2.889% 1351 2.889% +CORE_PREF_L1_NOT_USED_LATENCY1000 175 0.374% 175 0.374% +CORE_PREF_L1_NOT_USED_LATENCY1200 190 0.406% 190 0.406% +CORE_PREF_L1_NOT_USED_LATENCY1400 280 0.599% 280 0.599% +CORE_PREF_L1_NOT_USED_LATENCY1600 29 0.062% 29 0.062% +CORE_PREF_L1_NOT_USED_LATENCY1600MORE 140 0.299% 140 0.299% + 46765 100.000% 46765 100.000% + 0.34 0.95 0.34 0.95 + +CORE_PREF_L1_NOT_USED_DISTANCE_1 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_DISTANCE_2 2103 4.497% 2103 4.497% +CORE_PREF_L1_NOT_USED_DISTANCE_4 11404 24.386% 11404 24.386% +CORE_PREF_L1_NOT_USED_DISTANCE_8 18141 38.792% 18141 38.792% +CORE_PREF_L1_NOT_USED_DISTANCE_16 13236 28.303% 13236 28.303% +CORE_PREF_L1_NOT_USED_DISTANCE_32 1881 4.022% 1881 4.022% +CORE_PREF_L1_NOT_USED_DISTANCE_MORE 0 0.000% 0 0.000% + 46765 100.000% 46765 100.000% + 3.03 0.93 3.03 0.93 + +CORE_PREF_L1_USED_LATENCY200 24461 89.821% 24461 89.821% +CORE_PREF_L1_USED_LATENCY400 910 3.342% 910 3.342% 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-nan% +DRAM_BOTTLENECK_FAW_90 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_100 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DRAM_ROW_HIT_GEN_AFTER_ROW_OPEN_STALLING 0 0 + +KNOWN_BAD_ADDRESS 0 0.000% 0 0.000% +GOOD_ADDRESS 6588691 100.000% 6588691 100.000% + 6588691 100.000% 6588691 100.000% + 1.00 1.00 1.00 1.00 + + + diff --git a/labs/LAB5/runs/omnetpp-sms1/power.stat.0.out b/labs/LAB5/runs/omnetpp-sms1/power.stat.0.out new file mode 100644 index 00000000..1e998cac --- /dev/null +++ b/labs/LAB5/runs/omnetpp-sms1/power.stat.0.out @@ -0,0 +1,184 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 80804991 Instructions: 100000000 IPC: 1.23755 + +POWER_STATS_BEGIN 0 0 + +POWER_TIME 25251559687500 25251559687500 + +POWER_CYCLE 80804991 80804991 + +POWER_ITLB_ACCESS 33907335 33907335 + +POWER_DTLB_ACCESS 16925353 16925353 + +POWER_ICACHE_ACCESS 33907335 33907335 + +POWER_ICACHE_MISS 391787 391787 + +POWER_BTB_READ 33907335 33907335 + +POWER_BTB_WRITE 688745 688745 + +POWER_ROB_READ 128794928 128794928 + +POWER_ROB_WRITE 128794928 128794928 + +POWER_RENAME_READ 257589856 257589856 + +POWER_RENAME_WRITE 128794928 128794928 + +POWER_FP_RENAME_READ 0 0 + +POWER_FP_RENAME_WRITE 0 0 + +POWER_FUNCTION_CALL 2502717 2502717 + +POWER_INST_WINDOW_READ 128794928 128794928 + +POWER_INST_WINDOW_WRITE 128794928 128794928 + +POWER_INT_REGFILE_READ 141145453 141145453 + +POWER_INT_REGFILE_WRITE 96927234 96927234 + +POWER_IALU_ACCESS 128745902 128745902 + +POWER_CDB_IALU_ACCESS 128745902 128745902 + +POWER_MUL_ACCESS 49026 49026 + +POWER_CDB_MUL_ACCESS 49026 49026 + +POWER_FP_INST_WINDOW_WRITE 0 0 + +POWER_FP_INST_WINDOW_READ 0 0 + +POWER_FP_REGFILE_READ 0 0 + +POWER_FP_REGFILE_WRITE 0 0 + +POWER_FPU_ACCESS 0 0 + +POWER_CDB_FPU_ACCESS 0 0 + +POWER_DCACHE_READ_ACCESS 30704567 30704567 + +POWER_DCACHE_WRITE_ACCESS 16925347 16925347 + +POWER_DCACHE_READ_MISS 2256756 2256756 + +POWER_DCACHE_WRITE_MISS 904848 904848 + +POWER_MLC_READ_ACCESS 0 0 + +POWER_MLC_WRITE_ACCESS 0 0 + +POWER_MLC_READ_MISS 0 0 + +POWER_MLC_WRITE_MISS 0 0 + +POWER_LLC_READ_ACCESS 2005730 2005730 + +POWER_LLC_WRITE_ACCESS 711267 711267 + +POWER_LLC_READ_MISS 591225 591225 + +POWER_LLC_WRITE_MISS 129 129 + +POWER_MEMORY_ACCESS 0 0 + +POWER_MEMORY_READ_ACCESS 0 0 + +POWER_MEMORY_WRITE_ACCESS 0 0 + +POWER_INST_WINDOW_WAKEUP_ACCESS 128794928 128794928 + +POWER_FP_INST_WINDOW_WAKEUP_ACCESS 0 0 + +POWER_L1DIREC_READ_ACCESS 0 0 + +POWER_L1DIREC_WRITE_ACCESS 0 0 + +POWER_L1DIREC_READ_MISS 0 0 + +POWER_L1DIREC_WRITE_MISS 0 0 + +POWER_L2DIREC_READ_ACCESS 0 0 + +POWER_L2DIREC_WRITE_ACCESS 0 0 + +POWER_L2DIREC_READ_MISS 0 0 + +POWER_L2DIREC_WRITE_MISS 0 0 + +POWER_MEMORY_CTRL_ACCESS 873803 873803 + +POWER_MEMORY_CTRL_READ 591225 591225 + +POWER_MEMORY_CTRL_WRITE 282578 282578 + +POWER_OP 128794928 128794928 + +POWER_INT_OP 123010749 123010749 + +POWER_FP_OP 2017082 2017082 + +POWER_LD_OP 30704567 30704567 + +POWER_ST_OP 16925353 16925353 + +POWER_BRANCH_MISPREDICT 688745 688745 + +POWER_COMMITTED_OP 128794928 128794928 + +POWER_COMMITTED_INT_OP 123010749 123010749 + +POWER_COMMITTED_FP_OP 5784179 5784179 + +POWER_BRANCH_OP 20648070 20648070 + +POWER_DRAM_PRECHARGE 470591 470591 + +POWER_DRAM_ACTIVATE 513687 513687 + +POWER_DRAM_READ 591030 591030 + +POWER_DRAM_WRITE 282568 282568 + +POWER_STATS_END 0 0 + +ENERGY 0.000000 0.000000 + +ENERGY_CORE 0.000000 0.000000 + +ENERGY_UNCORE 0.000000 0.000000 + +ENERGY_MEMORY 0.000000 0.000000 + +ENERGY_OTHER 0.000000 0.000000 + +ENERGY_CORE_STATIC 0.000000 0.000000 + +ENERGY_CORE_DYNAMIC 0.000000 0.000000 + +ENERGY_UNCORE_STATIC 0.000000 0.000000 + +ENERGY_UNCORE_DYNAMIC 0.000000 0.000000 + +ENERGY_MEMORY_STATIC 0.000000 0.000000 + +ENERGY_MEMORY_DYNAMIC 0.000000 0.000000 + +ENERGY_OTHER_STATIC 0.000000 0.000000 + +ENERGY_OTHER_DYNAMIC 0.000000 0.000000 + +TIME 0.000000 0.000000 + +ENERGY_STATS_END 0 0 + + + diff --git a/labs/LAB5/runs/omnetpp-sms1/pref.stat.0.out b/labs/LAB5/runs/omnetpp-sms1/pref.stat.0.out new file mode 100644 index 00000000..0bd54e56 --- /dev/null +++ b/labs/LAB5/runs/omnetpp-sms1/pref.stat.0.out @@ -0,0 +1,208 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 80804991 Instructions: 100000000 IPC: 1.23755 + +PREF_DL0REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UMLC_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UL1REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_DL0REQ_QUEUE_FULL 0 0 + +PREF_UMLC_REQ_QUEUE_FULL 0 0 + +PREF_UL1REQ_QUEUE_FULL 0 0 + +PREF_DC_HIT_NOSEND 0 0 + +PREF_WBQDC_HIT_NOSEND 0 0 + +PREF_MLCQ_STALL 0 0 + +PREF_L1Q_STALL 0 0 + +PREF_UMLC_REQ_SEND_QUEUE_STALL 0 0 + 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5.714% +PREF_DISTANCE_5 0 0.000% 0 0.000% +PREF_DISTANCE_6 0 0.000% 0 0.000% +PREF_DISTANCE_7 0 0.000% 0 0.000% +PREF_DISTANCE_8 0 0.000% 0 0.000% +PREF_DISTANCE_9 0 0.000% 0 0.000% +PREF_DISTANCE_10 0 0.000% 0 0.000% + 70 100.000% 70 100.000% + 0.84 0.74 0.84 0.74 + +PREF_REPL_MRU 0 -nan% 0 -nan% +PREF_REPL_MID 0 -nan% 0 -nan% +PREF_REPL_LOWQTR 0 -nan% 0 -nan% +PREF_REPL_LRU 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_REPL_MOVEDOWN 0 -nan% 0 -nan% +PREF_REPL_MOVEUP 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_COV_1 0 -nan% 0 -nan% +PREF_COV_2 0 -nan% 0 -nan% +PREF_COV_3 0 -nan% 0 -nan% +PREF_COV_4 0 -nan% 0 -nan% +PREF_COV_5 0 -nan% 0 -nan% +PREF_COV_6 0 -nan% 0 -nan% +PREF_COV_7 0 -nan% 0 -nan% +PREF_COV_8 0 -nan% 0 -nan% +PREF_COV_9 0 -nan% 0 -nan% +PREF_COV_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_POL_1 0 0.000% 0 0.000% +PREF_POL_2 0 0.000% 0 0.000% +PREF_POL_3 0 0.000% 0 0.000% +PREF_POL_4 0 0.000% 0 0.000% +PREF_POL_5 0 0.000% 0 0.000% +PREF_POL_6 0 0.000% 0 0.000% +PREF_POL_7 0 0.000% 0 0.000% +PREF_POL_8 0 0.000% 0 0.000% +PREF_POL_9 0 0.000% 0 0.000% +PREF_POL_10 70 100.000% 70 100.000% + 70 100.000% 70 100.000% + 9.00 9.06 9.00 9.06 + +PREF_ACC_1 0 0.000% 0 0.000% +PREF_ACC_2 0 0.000% 0 0.000% +PREF_ACC_3 0 0.000% 0 0.000% +PREF_ACC_4 0 0.000% 0 0.000% +PREF_ACC_5 1 1.429% 1 1.429% +PREF_ACC_6 22 31.429% 22 31.429% +PREF_ACC_7 43 61.429% 43 61.429% +PREF_ACC_8 4 5.714% 4 5.714% +PREF_ACC_9 0 0.000% 0 0.000% +PREF_ACC_10 0 0.000% 0 0.000% + 70 100.000% 70 100.000% + 5.71 0.59 5.71 0.59 + +PREF_TIMELY_1 0 0.000% 0 0.000% +PREF_TIMELY_2 0 0.000% 0 0.000% +PREF_TIMELY_3 0 0.000% 0 0.000% +PREF_TIMELY_4 0 0.000% 0 0.000% +PREF_TIMELY_5 0 0.000% 0 0.000% +PREF_TIMELY_6 0 0.000% 0 0.000% +PREF_TIMELY_7 0 0.000% 0 0.000% +PREF_TIMELY_8 5 7.143% 5 7.143% +PREF_TIMELY_9 53 75.714% 53 75.714% +PREF_TIMELY_10 12 17.143% 12 17.143% + 70 100.000% 70 100.000% + 8.10 3.41 8.10 3.41 + +PREF_UNUSED_EVICT 46765 46765 + +PREF_REGION_SENT 0 0 + +PREF_REGION_USEFUL 0 0 + +PREF_REGION_EVICT 0 0 + +PREF_PFPOL 0 0 + +PREF_PHASE_NEWPHASE_DET 0 0 + +PREF_PHASE_NEWPHASE_NOTVALID 0 0 + +PREF_PHASE_SENTPREF 0 0 + +PREF_PHASE_OVERWRITE_PAGE 0 0 + +PREF_UPDATE_COUNT 70 70 + +PREF_ACC1_HT_HP 0 0.000% 0 0.000% +PREF_ACC1_HT_LP 0 0.000% 0 0.000% +PREF_ACC1_LT_HP 0 0.000% 0 0.000% +PREF_ACC1_LT_LP 0 0.000% 0 0.000% +PREF_ACC2_HT_HP 0 0.000% 0 0.000% +PREF_ACC2_HT_LP 0 0.000% 0 0.000% +PREF_ACC2_LT_HP 0 0.000% 0 0.000% +PREF_ACC2_LT_LP 23 32.857% 23 32.857% +PREF_ACC3_HT_HP 0 0.000% 0 0.000% +PREF_ACC3_HT_LP 0 0.000% 0 0.000% +PREF_ACC3_LT_HP 0 0.000% 0 0.000% +PREF_ACC3_LT_LP 0 0.000% 0 0.000% +PREF_ACC4_HT_HP 0 0.000% 0 0.000% +PREF_ACC4_HT_LP 0 0.000% 0 0.000% +PREF_ACC4_LT_HP 0 0.000% 0 0.000% +PREF_ACC4_LT_LP 47 67.143% 47 67.143% + 70 100.000% 70 100.000% + 12.37 10.89 12.37 10.89 + + + diff --git a/labs/LAB5/runs/omnetpp-sms1/ramulator.stat.out b/labs/LAB5/runs/omnetpp-sms1/ramulator.stat.out new file mode 100644 index 00000000..303c596f --- /dev/null +++ b/labs/LAB5/runs/omnetpp-sms1/ramulator.stat.out @@ -0,0 +1,150 @@ + ramulator.active_cycles_0 22844517 # Total active cycles for level _0 + ramulator.busy_cycles_0 22844517 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0 + ramulator.serving_requests_0 56200780 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.average_serving_requests_0 1.854696 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.active_cycles_0_0 22844517 # Total active cycles for level _0_0 + ramulator.busy_cycles_0_0 23302317 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0 + ramulator.serving_requests_0_0 56200780 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.average_serving_requests_0_0 1.854696 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.active_cycles_0_0_0 10508179 # Total active cycles for level _0_0_0 + ramulator.busy_cycles_0_0_0 10508179 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0 + ramulator.serving_requests_0_0_0 14436341 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 +ramulator.average_serving_requests_0_0_0 0.476417 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 + ramulator.active_cycles_0_0_0_0 3212061 # Total active cycles for level _0_0_0_0 + ramulator.busy_cycles_0_0_0_0 3212061 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_0 + ramulator.serving_requests_0_0_0_0 3441284 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 +ramulator.average_serving_requests_0_0_0_0 0.113567 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 + ramulator.active_cycles_0_0_0_1 3473502 # Total active cycles for level _0_0_0_1 + ramulator.busy_cycles_0_0_0_1 3473502 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_1 + ramulator.serving_requests_0_0_0_1 3726296 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 +ramulator.average_serving_requests_0_0_0_1 0.122972 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 + ramulator.active_cycles_0_0_0_2 3077495 # Total active cycles for level _0_0_0_2 + ramulator.busy_cycles_0_0_0_2 3077495 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_2 + ramulator.serving_requests_0_0_0_2 3304060 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 +ramulator.average_serving_requests_0_0_0_2 0.109038 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 + ramulator.active_cycles_0_0_0_3 3693596 # Total active cycles for level _0_0_0_3 + ramulator.busy_cycles_0_0_0_3 3693596 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_3 + ramulator.serving_requests_0_0_0_3 3964701 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 +ramulator.average_serving_requests_0_0_0_3 0.130840 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 + ramulator.active_cycles_0_0_1 9900972 # Total active cycles for level _0_0_1 + ramulator.busy_cycles_0_0_1 9900972 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1 + ramulator.serving_requests_0_0_1 13504725 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 +ramulator.average_serving_requests_0_0_1 0.445673 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 + ramulator.active_cycles_0_0_1_0 2862875 # Total active cycles for level _0_0_1_0 + ramulator.busy_cycles_0_0_1_0 2862875 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_0 + ramulator.serving_requests_0_0_1_0 3070742 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 +ramulator.average_serving_requests_0_0_1_0 0.101338 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 + ramulator.active_cycles_0_0_1_1 3001973 # Total active cycles for level _0_0_1_1 + ramulator.busy_cycles_0_0_1_1 3001973 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_1 + ramulator.serving_requests_0_0_1_1 3222960 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 +ramulator.average_serving_requests_0_0_1_1 0.106362 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 + ramulator.active_cycles_0_0_1_2 3426529 # Total active cycles for level _0_0_1_2 + ramulator.busy_cycles_0_0_1_2 3426529 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_2 + ramulator.serving_requests_0_0_1_2 3675032 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 +ramulator.average_serving_requests_0_0_1_2 0.121281 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 + ramulator.active_cycles_0_0_1_3 3295388 # Total active cycles for level _0_0_1_3 + ramulator.busy_cycles_0_0_1_3 3295388 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_3 + ramulator.serving_requests_0_0_1_3 3535991 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 +ramulator.average_serving_requests_0_0_1_3 0.116692 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 + ramulator.active_cycles_0_0_2 10489849 # Total active cycles for level _0_0_2 + ramulator.busy_cycles_0_0_2 10489849 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2 + ramulator.serving_requests_0_0_2 14358243 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 +ramulator.average_serving_requests_0_0_2 0.473840 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 + ramulator.active_cycles_0_0_2_0 3112630 # Total active cycles for level _0_0_2_0 + ramulator.busy_cycles_0_0_2_0 3112630 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_0 + ramulator.serving_requests_0_0_2_0 3344679 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 +ramulator.average_serving_requests_0_0_2_0 0.110379 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 + ramulator.active_cycles_0_0_2_1 3402563 # Total active cycles for level _0_0_2_1 + ramulator.busy_cycles_0_0_2_1 3402563 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_1 + ramulator.serving_requests_0_0_2_1 3651677 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 +ramulator.average_serving_requests_0_0_2_1 0.120510 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 + ramulator.active_cycles_0_0_2_2 3457934 # Total active cycles for level _0_0_2_2 + ramulator.busy_cycles_0_0_2_2 3457934 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_2 + ramulator.serving_requests_0_0_2_2 3701327 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 +ramulator.average_serving_requests_0_0_2_2 0.122148 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 + ramulator.active_cycles_0_0_2_3 3399895 # Total active cycles for level _0_0_2_3 + ramulator.busy_cycles_0_0_2_3 3399895 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_3 + ramulator.serving_requests_0_0_2_3 3660560 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 +ramulator.average_serving_requests_0_0_2_3 0.120803 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 + ramulator.active_cycles_0_0_3 10220427 # Total active cycles for level _0_0_3 + ramulator.busy_cycles_0_0_3 10220427 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3 + ramulator.serving_requests_0_0_3 13901471 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 +ramulator.average_serving_requests_0_0_3 0.458766 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 + ramulator.active_cycles_0_0_3_0 3299532 # Total active cycles for level _0_0_3_0 + ramulator.busy_cycles_0_0_3_0 3299532 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_0 + ramulator.serving_requests_0_0_3_0 3538302 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 +ramulator.average_serving_requests_0_0_3_0 0.116768 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 + ramulator.active_cycles_0_0_3_1 3358426 # Total active cycles for level _0_0_3_1 + ramulator.busy_cycles_0_0_3_1 3358426 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_1 + ramulator.serving_requests_0_0_3_1 3600392 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 +ramulator.average_serving_requests_0_0_3_1 0.118817 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 + ramulator.active_cycles_0_0_3_2 3239399 # Total active cycles for level _0_0_3_2 + ramulator.busy_cycles_0_0_3_2 3239399 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_2 + ramulator.serving_requests_0_0_3_2 3478269 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 +ramulator.average_serving_requests_0_0_3_2 0.114787 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 + ramulator.active_cycles_0_0_3_3 3070828 # Total active cycles for level _0_0_3_3 + ramulator.busy_cycles_0_0_3_3 3070828 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_3 + ramulator.serving_requests_0_0_3_3 3284508 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 +ramulator.average_serving_requests_0_0_3_3 0.108393 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 + ramulator.read_transaction_bytes_0 37825920 # The total byte of read transaction per channel + ramulator.write_transaction_bytes_0 18084352 # The total byte of write transaction per channel + ramulator.row_hits_channel_0_core 359962 # Number of row hits per channel per core + ramulator.row_misses_channel_0_core 55227 # Number of row misses per channel per core + ramulator.row_conflicts_channel_0_core 458409 # Number of row conflicts per channel per core + ramulator.read_row_hits_channel_0_core 340199 # Number of row hits for read requests per channel per core + [0] 340199.0 # +ramulator.read_row_misses_channel_0_core 33818 # Number of row misses for read requests per channel per core + [0] 33818.0 # +ramulator.read_row_conflicts_channel_0_core 217013 # Number of row conflicts for read requests per channel per core + [0] 217013.0 # + ramulator.write_row_hits_channel_0_core 19763 # Number of row hits for write requests per channel per core + [0] 19763.0 # +ramulator.write_row_misses_channel_0_core 21409 # Number of row misses for write requests per channel per core + [0] 21409.0 # +ramulator.write_row_conflicts_channel_0_core 241396 # Number of row conflicts for write requests per channel per core + [0] 241396.0 # + ramulator.useless_activates_0_core 88 # Number of useless activations. E.g, ACT -> PRE w/o RD or WR + ramulator.read_latency_avg_0 54.966197 # The average memory latency cycles (in memory time domain) per request for all read requests in this channel + ramulator.read_latency_sum_0 32497390 # The memory latency cycles (in memory time domain) sum for all read requests in this channel + ramulator.req_queue_length_avg_0 15.202344 # Average of read and write queue length per memory cycle per channel. + ramulator.req_queue_length_sum_0 460659664 # Sum of read and write queue length per memory cycle per channel. + ramulator.read_req_queue_length_avg_0 0.937347 # Read queue length average per memory cycle per channel. + ramulator.read_req_queue_length_sum_0 28403387 # Read queue length sum per memory cycle per channel. + ramulator.write_req_queue_length_avg_0 14.264997 # Write queue length average per memory cycle per channel. + ramulator.write_req_queue_length_sum_0 432256277 # Write queue length sum per memory cycle per channel. + ramulator.record_read_hits 0.0 # record read hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_misses 0.0 # record_read_miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_conflicts 0.0 # record read conflict count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_hits 0.0 # record write hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_misses 0.0 # record write miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_conflicts 0.0 # record write conflict for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.dram_capacity 8589934592 # Number of bytes in simulated DRAM + ramulator.dram_cycles 30301883 # Number of DRAM cycles simulated + ramulator.incoming_requests 873803 # Number of incoming requests to DRAM + ramulator.read_requests 591225 # Number of incoming read requests to DRAM per core + [0] 591225.0 # + ramulator.write_requests 282578 # Number of incoming write requests to DRAM per core + [0] 282578.0 # + ramulator.ramulator_active_cycles 22844517 # The total number of cycles that the DRAM part is active (serving R/W) + ramulator.incoming_requests_per_channel 873803.0 # Number of incoming requests to each DRAM channel + [0] 873803.0 # +ramulator.incoming_read_reqs_per_channel 591225.0 # Number of incoming read requests to each DRAM channel + [0] 591225.0 # + ramulator.physical_page_replacement 0 # The number of times that physical page replacement happens. + ramulator.maximum_bandwidth 19200000000 # The theoretical maximum bandwidth (Bps) + ramulator.in_queue_req_num_sum 460659664 # Sum of read/write queue length + ramulator.in_queue_read_req_num_sum 28403387 # Sum of read queue length + ramulator.in_queue_write_req_num_sum 432256277 # Sum of write queue length + ramulator.in_queue_req_num_avg 15.202344 # Average of read/write queue length per memory cycle + ramulator.in_queue_read_req_num_avg 0.937347 # Average of read queue length per memory cycle + ramulator.in_queue_write_req_num_avg 14.264997 # Average of write queue length per memory cycle + ramulator.record_read_requests 0.0 # record read requests for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_requests 0.0 # record write requests for this core when it reaches request limit or to the end + [0] 0.0 # diff --git a/labs/LAB5/runs/omnetpp-sms1/run.err b/labs/LAB5/runs/omnetpp-sms1/run.err new file mode 100644 index 00000000..e69de29b diff --git a/labs/LAB5/runs/omnetpp-sms1/run.out b/labs/LAB5/runs/omnetpp-sms1/run.out new file mode 100644 index 00000000..692107ec --- /dev/null +++ b/labs/LAB5/runs/omnetpp-sms1/run.out @@ -0,0 +1,107 @@ +Scarab gitrev: 7ab9e17 +Scarab started at Sun Jun 11 08:08:38 2023 + +Initialized Ramulator. +** Heartbeat: 1% -- { 1000001 } -- 0.00 KIPS (333.33 KIPS) +** Heartbeat: 2% -- { 2000001 } -- 333.33 KIPS (333.33 KIPS) +** Heartbeat: 3% -- { 3000006 } -- 500.00 KIPS (375.00 KIPS) +** Heartbeat: 4% -- { 4000009 } -- 500.00 KIPS (400.00 KIPS) +** Heartbeat: 5% -- { 5000011 } -- 333.33 KIPS (384.62 KIPS) +** Heartbeat: 6% -- { 6000014 } -- 500.00 KIPS (400.00 KIPS) +** Heartbeat: 7% -- { 7000016 } -- 333.33 KIPS (388.89 KIPS) +** Heartbeat: 8% -- { 8000020 } -- 500.00 KIPS (400.00 KIPS) +** Heartbeat: 9% -- { 9000020 } -- 333.33 KIPS (391.31 KIPS) +** Heartbeat: 10% -- { 10000023 } -- 500.00 KIPS (400.00 KIPS) +** Heartbeat: 11% -- { 11000025 } -- 333.33 KIPS (392.86 KIPS) +** Heartbeat: 12% -- { 12000025 } -- 500.00 KIPS (400.00 KIPS) +** Heartbeat: 13% -- { 13000027 } -- 333.33 KIPS (393.94 KIPS) +** Heartbeat: 14% -- { 14000030 } -- 500.00 KIPS (400.00 KIPS) +** Heartbeat: 15% -- { 15000030 } -- 333.33 KIPS (394.74 KIPS) +** Heartbeat: 16% -- { 16000035 } -- 500.00 KIPS (400.00 KIPS) +** Heartbeat: 17% -- { 17000036 } -- 333.33 KIPS (395.35 KIPS) +** Heartbeat: 18% -- { 18000037 } -- 500.00 KIPS (400.00 KIPS) +** Heartbeat: 19% -- { 19000040 } -- 500.00 KIPS (404.26 KIPS) +** Heartbeat: 20% -- { 20000045 } -- 333.33 KIPS (400.00 KIPS) +** Heartbeat: 21% -- { 21000049 } -- 333.33 KIPS (396.23 KIPS) +** Heartbeat: 22% -- { 22000049 } -- 500.00 KIPS (400.00 KIPS) +** Heartbeat: 23% -- { 23000054 } -- 333.33 KIPS (396.55 KIPS) +** Heartbeat: 24% -- { 24000054 } -- 500.00 KIPS (400.00 KIPS) +** Heartbeat: 25% -- { 25000055 } -- 333.33 KIPS (396.83 KIPS) +** Heartbeat: 26% -- { 26000055 } -- 333.33 KIPS (393.94 KIPS) +** Heartbeat: 27% -- { 27000055 } -- 500.00 KIPS (397.06 KIPS) +** Heartbeat: 28% -- { 28000055 } -- 333.33 KIPS (394.37 KIPS) +** Heartbeat: 29% -- { 29000055 } -- 500.00 KIPS (397.26 KIPS) +** Heartbeat: 30% -- { 30000057 } -- 333.33 KIPS (394.74 KIPS) +** Heartbeat: 31% -- { 31000057 } -- 500.00 KIPS (397.44 KIPS) +** Heartbeat: 32% -- { 32000060 } -- 333.33 KIPS (395.06 KIPS) +** Heartbeat: 33% -- { 33000063 } -- 333.33 KIPS (392.86 KIPS) +** Heartbeat: 34% -- { 34000063 } -- 500.00 KIPS (395.35 KIPS) +** Heartbeat: 35% -- { 35000065 } -- 333.33 KIPS (393.26 KIPS) +** Heartbeat: 36% -- { 36000070 } -- 333.33 KIPS (391.31 KIPS) +** Heartbeat: 37% -- { 37000071 } -- 500.00 KIPS (393.62 KIPS) +** Heartbeat: 38% -- { 38000071 } -- 333.33 KIPS (391.75 KIPS) +** Heartbeat: 39% -- { 39000075 } -- 500.00 KIPS (393.94 KIPS) +** Heartbeat: 40% -- { 40000075 } -- 333.33 KIPS (392.16 KIPS) +** Heartbeat: 41% -- { 41000078 } -- 333.33 KIPS (390.48 KIPS) +** Heartbeat: 42% -- { 42000079 } -- 500.00 KIPS (392.52 KIPS) +** Heartbeat: 43% -- { 43000081 } -- 333.33 KIPS (390.91 KIPS) +** Heartbeat: 44% -- { 44000084 } -- 500.00 KIPS (392.86 KIPS) +** Heartbeat: 45% -- { 45000086 } -- 500.00 KIPS (394.74 KIPS) +** Heartbeat: 46% -- { 46000091 } -- 333.33 KIPS (393.16 KIPS) +** Heartbeat: 47% -- { 47000092 } -- 500.00 KIPS (394.96 KIPS) +** Heartbeat: 48% -- { 48000092 } -- 333.33 KIPS (393.44 KIPS) +** Heartbeat: 49% -- { 49000093 } -- 333.33 KIPS (392.00 KIPS) +** Heartbeat: 50% -- { 50000095 } -- 500.00 KIPS (393.70 KIPS) +** Heartbeat: 51% -- { 51000099 } -- 333.33 KIPS (392.31 KIPS) +** Heartbeat: 52% -- { 52000102 } -- 500.00 KIPS (393.94 KIPS) +** Heartbeat: 53% -- { 53000102 } -- 333.33 KIPS (392.59 KIPS) +** Heartbeat: 54% -- { 54000104 } -- 500.00 KIPS (394.16 KIPS) +** Heartbeat: 55% -- { 55000104 } -- 333.33 KIPS (392.86 KIPS) +** Heartbeat: 56% -- { 56000104 } -- 333.33 KIPS (391.61 KIPS) +** Heartbeat: 57% -- { 57000107 } -- 500.00 KIPS (393.10 KIPS) +** Heartbeat: 58% -- { 58000107 } -- 333.33 KIPS (391.89 KIPS) +** Heartbeat: 59% -- { 59000107 } -- 500.00 KIPS (393.33 KIPS) +** Heartbeat: 60% -- { 60000108 } -- 333.33 KIPS (392.16 KIPS) +** Heartbeat: 61% -- { 61000108 } -- 500.00 KIPS (393.55 KIPS) +** Heartbeat: 62% -- { 62000111 } -- 333.33 KIPS (392.41 KIPS) +** Heartbeat: 63% -- { 63000112 } -- 333.33 KIPS (391.31 KIPS) +** Heartbeat: 64% -- { 64000114 } -- 500.00 KIPS (392.64 KIPS) +** Heartbeat: 65% -- { 65000114 } -- 333.33 KIPS (391.57 KIPS) +** Heartbeat: 66% -- { 66000116 } -- 500.00 KIPS (392.86 KIPS) +** Heartbeat: 67% -- { 67000117 } -- 333.33 KIPS (391.81 KIPS) +** Heartbeat: 68% -- { 68000117 } -- 500.00 KIPS (393.06 KIPS) +** Heartbeat: 69% -- { 69000121 } -- 333.33 KIPS (392.05 KIPS) +** Heartbeat: 70% -- { 70000123 } -- 500.00 KIPS (393.26 KIPS) +** Heartbeat: 71% -- { 71000125 } -- 333.33 KIPS (392.27 KIPS) +** Heartbeat: 72% -- { 72000129 } -- 500.00 KIPS (393.44 KIPS) +** Heartbeat: 73% -- { 73000129 } -- 333.33 KIPS (392.47 KIPS) +** Heartbeat: 74% -- { 74000130 } -- 500.00 KIPS (393.62 KIPS) +** Heartbeat: 75% -- { 75000131 } -- 333.33 KIPS (392.67 KIPS) +** Heartbeat: 76% -- { 76000131 } -- 500.00 KIPS (393.78 KIPS) +** Heartbeat: 77% -- { 77000132 } -- 333.33 KIPS (392.86 KIPS) +** Heartbeat: 78% -- { 78000134 } -- 500.00 KIPS (393.94 KIPS) +** Heartbeat: 79% -- { 79000135 } -- 333.33 KIPS (393.04 KIPS) +** Heartbeat: 80% -- { 80000136 } -- 500.00 KIPS (394.09 KIPS) +** Heartbeat: 81% -- { 81000138 } -- 333.33 KIPS (393.20 KIPS) +** Heartbeat: 82% -- { 82000138 } -- 500.00 KIPS (394.23 KIPS) +** Heartbeat: 83% -- { 83000140 } -- 333.33 KIPS (393.37 KIPS) +** Heartbeat: 84% -- { 84000142 } -- 500.00 KIPS (394.37 KIPS) +** Heartbeat: 85% -- { 85000142 } -- 333.33 KIPS (393.52 KIPS) +** Heartbeat: 86% -- { 86000147 } -- 500.00 KIPS (394.50 KIPS) +** Heartbeat: 87% -- { 87000147 } -- 333.33 KIPS (393.67 KIPS) +** Heartbeat: 88% -- { 88000149 } -- 500.00 KIPS (394.62 KIPS) +** Heartbeat: 89% -- { 89000150 } -- 333.33 KIPS (393.81 KIPS) +** Heartbeat: 90% -- { 90000153 } -- 500.00 KIPS (394.74 KIPS) +** Heartbeat: 91% -- { 91000155 } -- 333.33 KIPS (393.94 KIPS) +** Heartbeat: 92% -- { 92000158 } -- 500.00 KIPS (394.85 KIPS) +** Heartbeat: 93% -- { 93000159 } -- 333.33 KIPS (394.07 KIPS) +** Heartbeat: 94% -- { 94000160 } -- 500.00 KIPS (394.96 KIPS) +** Heartbeat: 95% -- { 95000160 } -- 500.00 KIPS (395.83 KIPS) +** Heartbeat: 96% -- { 96000164 } -- 333.33 KIPS (395.06 KIPS) +** Heartbeat: 97% -- { 97000167 } -- 500.00 KIPS (395.92 KIPS) +** Heartbeat: 98% -- { 98000167 } -- 333.33 KIPS (395.16 KIPS) +** Heartbeat: 99% -- { 99000167 } -- 500.00 KIPS (396.00 KIPS) +** Core 0 Finished: insts:100000000 cycles:80804991 time:25251559687500 -- 1.24 IPC (1.24 IPC) -- N/A KIPS (395.26 KIPS) +done +Scarab finished at Sun Jun 11 08:12:51 2023 + diff --git a/labs/LAB5/runs/omnetpp-sms1/stream.stat.0.out b/labs/LAB5/runs/omnetpp-sms1/stream.stat.0.out new file mode 100644 index 00000000..b11add17 --- /dev/null +++ b/labs/LAB5/runs/omnetpp-sms1/stream.stat.0.out @@ -0,0 +1,188 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 80804991 Instructions: 100000000 IPC: 1.23755 + +DCACHE_PREF_HIT 0 0 + +IFETCH_WB_FIRST_SCHEDULE 0 -nan% 0 -nan% +PREFETCH_LAST_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_PREF_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_LOW_OP_SCHEDULE 0 -nan% 0 -nan% +DEMAND_LAST_SCHEDULE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +SEND_MISS_REQ_QUEUE 591225 591225 + +L1_DATA_EVICT 574970 574970 + +STREAM_BUFFER_REQ 0 0 + +PREF_SEND_TO_MEM_REQ 0 -nan% 0 -nan% +PREF_SEND_TO_MEM_REQ_FAIL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +HIT_TRAIN_STREAM 84669 14.511% 84669 14.511% +MISS_TRAIN_STREAM 498798 85.489% 498798 85.489% + 583467 100.000% 583467 100.000% + 0.85 0.80 0.85 0.80 + +STREAM_TRAIN_CREATE 243682 243682 + +MEM_REQ_MISS_HWP_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_SW_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_IFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DSTORE_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DPRF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_WB_Q 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_BY_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_WB 0 -nan% 0 -nan% +PREF_HIT_BY_PREF 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_WB 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_L1_FILL 0 -nan% 0 -nan% +DEMAND_L1_FILL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TOUCH_L1_REPLACE 0 0.000% 0 0.000% +NO_TOUCH_L1_REPLACE 574970 100.000% 574970 100.000% + 574970 100.000% 574970 100.000% + 1.00 1.00 1.00 1.00 + +PREF_REQ_QUE_FULL 0 0 + +STREAM_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +L2HIT_STREAM_PREF_REQ_QUE_FULL 0 0 + +L2HIT_HIT_TRAIN_STREAM 0 -nan% 0 -nan% +L2HIT_MISS_TRAIN_STREAM 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_TRAIN_CREATE 0 0 + +L2HIT_STREAM_BUFFER_REQ 0 0 + +L2HIT_STREAM_PREF_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_STREAM_PREF_DCACHE_INSERT 0 -nan% 0 -nan% +L2HIT_STREAM_L2_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_DCACHE_PORT_FULL 0 0 + +L2HIT_STREAM_PREF_L1_PORT_FULL 0 0 + +L2HIT_TRAIN_HIT_DEMAND 0 -nan% 0 -nan% +L2HIT_TRAIN_MISS_REQ 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_TRAIN_FILTER_MISS 0 -nan% 0 -nan% +L2HIT_TRAIN_FILTER_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_PREF_REQ_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_PREF_REQ_DCACHE_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_L2SEND_Q_FULL 0 -nan% 0 -nan% +L2HIT_L2SEND_Q_ENTER 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_MEM_REQ 0 0 + +REMOVE_REDUNDANT_STREAM_STAT 0 0 + +REPLACE_OLD_STREAM 243666 243666 + +REQ_SEND_QUEUE_STALL 0 0 + +STREAM_ENTER_RA 0 0 + +CORE_STREAM_LENGTH_0 11200 36.334% 11200 36.334% +CORE_STREAM_LENGTH_10 15447 50.112% 15447 50.112% +CORE_STREAM_LENGTH_20 3408 11.056% 3408 11.056% +CORE_STREAM_LENGTH_30 492 1.596% 492 1.596% +CORE_STREAM_LENGTH_40 187 0.607% 187 0.607% +CORE_STREAM_LENGTH_50 40 0.130% 40 0.130% +CORE_STREAM_LENGTH_60 13 0.042% 13 0.042% +CORE_STREAM_LENGTH_70 4 0.013% 4 0.013% +CORE_STREAM_LENGTH_80 4 0.013% 4 0.013% +CORE_STREAM_LENGTH_90 5 0.016% 5 0.016% +CORE_STREAM_LENGTH_100_P 25 0.081% 25 0.081% + 30825 100.000% 30825 100.000% + 0.81 0.66 0.81 0.66 + +CORE_CUM_STREAM_LENGTH_0 67674 17.389% 67674 17.389% +CORE_CUM_STREAM_LENGTH_10 211779 54.418% 211779 54.418% +CORE_CUM_STREAM_LENGTH_20 76936 19.769% 76936 19.769% +CORE_CUM_STREAM_LENGTH_30 15891 4.083% 15891 4.083% +CORE_CUM_STREAM_LENGTH_40 8272 2.126% 8272 2.126% +CORE_CUM_STREAM_LENGTH_50 2113 0.543% 2113 0.543% +CORE_CUM_STREAM_LENGTH_60 824 0.212% 824 0.212% +CORE_CUM_STREAM_LENGTH_70 294 0.076% 294 0.076% +CORE_CUM_STREAM_LENGTH_80 338 0.087% 338 0.087% +CORE_CUM_STREAM_LENGTH_90 480 0.123% 480 0.123% +CORE_CUM_STREAM_LENGTH_100_P 4569 1.174% 4569 1.174% + 389170 100.000% 389170 100.000% + 1.33 1.25 1.33 1.25 + +CORE_STREAM_TRAIN_HITS_0 26779 86.874% 26779 86.874% +CORE_STREAM_TRAIN_HITS_10 3905 12.668% 3905 12.668% +CORE_STREAM_TRAIN_HITS_20 57 0.185% 57 0.185% +CORE_STREAM_TRAIN_HITS_30 22 0.071% 22 0.071% +CORE_STREAM_TRAIN_HITS_40 26 0.084% 26 0.084% +CORE_STREAM_TRAIN_HITS_50 4 0.013% 4 0.013% +CORE_STREAM_TRAIN_HITS_60 7 0.023% 7 0.023% +CORE_STREAM_TRAIN_HITS_70 3 0.010% 3 0.010% +CORE_STREAM_TRAIN_HITS_80 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_90 4 0.013% 4 0.013% +CORE_STREAM_TRAIN_HITS_100_P 18 0.058% 18 0.058% + 30825 100.000% 30825 100.000% + 0.15 0.45 0.15 0.45 + +CORE_CUM_STREAM_TRAIN_HITS_0 156019 75.020% 156019 75.020% +CORE_CUM_STREAM_TRAIN_HITS_10 43968 21.142% 43968 21.142% +CORE_CUM_STREAM_TRAIN_HITS_20 1300 0.625% 1300 0.625% +CORE_CUM_STREAM_TRAIN_HITS_30 773 0.372% 773 0.372% +CORE_CUM_STREAM_TRAIN_HITS_40 1166 0.561% 1166 0.561% +CORE_CUM_STREAM_TRAIN_HITS_50 224 0.108% 224 0.108% +CORE_CUM_STREAM_TRAIN_HITS_60 449 0.216% 449 0.216% +CORE_CUM_STREAM_TRAIN_HITS_70 225 0.108% 225 0.108% +CORE_CUM_STREAM_TRAIN_HITS_80 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_90 375 0.180% 375 0.180% +CORE_CUM_STREAM_TRAIN_HITS_100_P 3470 1.669% 3470 1.669% + 207969 100.000% 207969 100.000% + 0.47 1.40 0.47 1.40 + +CORE_STREAM_TRAIN_CREATE 243682 243682 + + + diff --git a/labs/LAB5/runs/perlbench_s_base-sms0/PARAMS.in b/labs/LAB5/runs/perlbench_s_base-sms0/PARAMS.in new file mode 100644 index 00000000..2593c2b8 --- /dev/null +++ b/labs/LAB5/runs/perlbench_s_base-sms0/PARAMS.in @@ -0,0 +1,226 @@ +# File : PARAMS.kaby_lake +# Date : 03/06/19 +# Description : Kaby Lake Configuration +# +# Based on documentation found here: +# https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake + +## Simulation Parameters +--mode full +--model cmp +--sim_limit none + +## Core Parameters + +# Femptoseconds, 3.2GHz, used for energy estimates. +--chip_cycle_time 312500 + + +### Fetch Stage +--fetch_off_path_ops 1 +--fetch_across_cache_lines 1 + +# Will break the packet upon a taken branch. +--fetch_break_on_taken 1 + +# Number of bubble cycles to wait after taken branch. +--fetch_taken_bubble_cycles 0 + + +#### ICache +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 + +### Branch Predictor +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_mech tagescl + + +#### BTB + +# BTB model to use. +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 + +# Allow the BTB to be updated by off path ops. +--btb_off_path_writes 1 + + +#### CRS + +# Enable return stack +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 + +### iBP +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged + # iBTB Model. tc_tagless, tc_tagged, tc_hybrid. +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 + +### Decode Stage +--decode_cycles 5 + + +### Map Stage +--map_cycles 5 + + +### Issue Stage + +# Max number of instructions to be fetched, decoded, renamed, and issued per cycle. +--issue_width 6 + +--rs_fill_width 0 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 + + +### Exec Stage + +### DCache +--dcache_size 32768 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--dcache_assoc 4 +--dcache_line_size 64 + +### Reorder/Retire Stage + +# Max number of instructions to be retired per cycle. +--node_ret_width 6 +--node_table_size 224 + +# Do not keep stores in RSVs on cache misses; TODO: confirm what this knob does +--stores_do_not_block_window 1 + +# TODO: confirm what this knob does +--prefs_do_not_block_window 1 + + +## Uncore + +### Mid-level cache + +# Enable use of a midlevel cache between i/d and L1 +--mlc_present 0 + +### LLC +--l1_size 1048576 +--l1_banks 1 +--l1_cycles 18 +--l1_assoc 8 +--l1_line_size 64 +--l1_interleave_factor 64 + + +### Prefetcher +--pref_framework_on 1 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--pref_shared_queues 0 +--pref_train_on_pref_misses 0 +--pref_oracle_train 0 +--pref_ul1req_queue_overwrite_on_full 1 + +--stream_length 64 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 + +--pref_throttlefb_on=1 +--pref_acc_thresh_1=0.75 +--pref_acc_thresh_2=0.4 +--pref_acc_thresh_3=0.4 +--pref_timely_thresh=0.01 +--pref_polpf_thresh=0.005 +--pref_update_interval=8192 + +--mem_req_buffer_pref_watermark 4 +--promote_to_higher_priority_mem_req_type 1 + +### Memory +--addr_translation random + +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 + +--mem_req_buffer_entries 32 +--mem_l1_fill_queue_entries 32 +--va_page_size_bytes 4096 +--bus_width_in_bytes 8 + +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 + +## Other + + +### Debug +--debug_inst_start 0 +--debug_inst_stop -1 +--debug_cycle_start 0 +--debug_cycle_stop -1 + + +## Stats and Params +--dump_params 1 +--dump_stats 1 +--dump_trace 0 + +#################################### +--set_off_path_confirmed 1 + +--order_beyond_bus 1 + +--mem_ooo_stores 1 +--mem_obey_store_dep 1 diff --git a/labs/LAB5/runs/perlbench_s_base-sms0/PARAMS.out b/labs/LAB5/runs/perlbench_s_base-sms0/PARAMS.out new file mode 100644 index 00000000..8c5b830e --- /dev/null +++ b/labs/LAB5/runs/perlbench_s_base-sms0/PARAMS.out @@ -0,0 +1,908 @@ +--mode full +--model cmp +--frontend memtrace +--inst_limit 100000000 +--sim_limit none +--dump_params 1 +--dump_stats 1 +--dump_trace 0 +--mlc_present 0 +--l1_size 1048576 +--l1_assoc 8 +--l1_line_size 64 +--l1_cycles 18 +--l1_banks 1 +--l1_interleave_factor 64 +--va_page_size_bytes 4096 +--addr_translation random +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 +--dcache_size 32768 +--dcache_assoc 4 +--dcache_line_size 64 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--mem_ooo_stores 1 +--mem_obey_store_dep 1 +--mem_req_buffer_entries 32 +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 +--promote_to_higher_priority_mem_req_type 1 +--mem_req_buffer_pref_watermark 4 +--mem_l1_fill_queue_entries 32 +--order_beyond_bus 1 +--set_off_path_confirmed 1 +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--bus_width_in_bytes 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 +--chip_cycle_time 312500 +--issue_width 6 +--rs_fill_width 0 +--node_table_size 224 +--node_ret_width 6 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 +--decode_cycles 5 +--map_cycles 5 +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--fetch_across_cache_lines 1 +--fetch_off_path_ops 0 +--fetch_break_on_taken 1 +--fetch_taken_bubble_cycles 0 +--stores_do_not_block_window 1 +--prefs_do_not_block_window 1 +--cbp_trace_r0 /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir/trace/drmemtrace.perlbench_s_base.mytest-m64.554262.9223.trace.gz +--memtrace_modules_log /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir/raw +--debug_cycle_start 0 +--debug_cycle_stop -1 +--debug_inst_start 0 +--debug_inst_stop -1 +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--bp_mech tagescl +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 +--btb_off_path_writes 1 +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_length 64 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 +--pref_framework_on 1 +--pref_shared_queues 0 +--pref_ul1req_queue_overwrite_on_full 1 +--pref_train_on_pref_misses 0 +--pref_oracle_train_on 0 +--pref_throttlefb_on 1 +--pref_acc_thresh_1 0.75 +--pref_acc_thresh_2 0.4 +--pref_acc_thresh_3 0.4 +--pref_update_interval 8192 +--pref_timely_thresh 0.01 +--pref_polpf_thresh 0.005 +--pref_sms_on 0 +1 1 1 1 1 1 1 + +--- Cut out everything below to use this file as PARAMS.in --- + +Parameter status at compile time and values supplied on the command line: + +SIM_MODE 0 full +SIM_MODEL 0 cmp +FRONTEND FE_PIN_EXEC_DRIVEN memtrace +INST_LIMIT NULL 100000000 +SIM_LIMIT "none" none +FORWARD_PROGRESS_LIMIT 100000000 +FORWARD_PROGRESS_INTERVAL 10000 +FAST_FORWARD 0 +FAST_FORWARD_UNTIL_ADDR 0 +FAST_FORWARD_TRACE_INS 0 +WARMUP 0 +HEARTBEAT_INTERVAL 1000000 +NUM_HEARTBEATS 0 +FILE_TAG "" +OUTPUT_DIR "." +STATUS_FILE NULL +BINDIR NULL +DUMP_PARAMS TRUE 1 +DUMP_STATS TRUE 1 +DUMP_TRACE FALSE 0 +CLEAR_STATS "never" +STATS_TO_TRACE NULL +STAT_TRACE_FILE "stats.trace" +STAT_TRACE_INTERVAL "i:100000" +PIPEVIEW FALSE +PIPEVIEW_FILE "pipeview" +MEMVIEW FALSE +MEMVIEW_FILE "memview.out" +MEMVIEW_START "never" +INST_HASH_TABLE_SIZE 500021 const +STDOUT_FILE NULL +STDERR_FILE NULL +PIN_EXEC_DRIVEN_FE_SOCKET "./pin_exec_driven_fe_socket.temp" +PRINT_PID FALSE +USE_UNSURE_FREE_LISTS FALSE +OPTIMIZER2_MAX_NUM_SLAVES 64 +OPTIMIZER2_PERFECT_MEMORYLESS FALSE +EXIT_COND 0 +ENABLE_SWPRF FALSE +MLC_PRESENT FALSE 0 +MLC_SIZE (512 * 1024) +MLC_ASSOC 4 +MLC_LINE_SIZE 64 +MLC_CYCLES 12 +PERFECT_MLC FALSE +MLC_READ_PORTS 1 +MLC_WRITE_PORTS 1 +MLC_BANKS 8 +MLC_INTERLEAVE_FACTOR 64 +MLC_CACHE_REPL_POLICY 0 +MLC_WRITE_THROUGH FALSE +PREFETCH_UPDATE_LRU_MLC TRUE +FORCE_L1_MISS FALSE +L1_SIZE (4 * 1024 * 1024) 1048576 +L1_ASSOC 8 8 +L1_LINE_SIZE 64 64 +L1_CYCLES 24 18 +PERFECT_L1 FALSE +PRIVATE_L1 FALSE +L1_READ_PORTS 1 +L1_WRITE_PORTS 1 +L1_BANKS 8 1 +L1_INTERLEAVE_FACTOR 64 64 +L1_CACHE_REPL_POLICY 0 +L1_WRITE_THROUGH FALSE +L1_IGNORE_WB FALSE +L1_USE_CORE_FREQ FALSE +MARK_L1_MISSES TRUE +PREFETCH_UPDATE_LRU_L1 TRUE +MEMORY_RANDOM_ADDR FALSE +VA_PAGE_SIZE_BYTES 4096 4096 +NUM_ADDR_NON_SIGN_EXTEND_BITS 48 +ADDR_TRANSLATION 0 random +CONSTANT_MEMORY_LATENCY FALSE +MEMORY_CYCLES 100 +STALL_MEM_REQS_ONLY FALSE +ICACHE_SIZE (64 * 1024) 32768 +ICACHE_ASSOC 4 4 +ICACHE_LINE_SIZE 64 64 +PERFECT_ICACHE FALSE +ICACHE_READ_PORTS 2 +ICACHE_WRITE_PORTS 1 +ICACHE_BANKS 8 +ICACHE_REPL 0 +DCACHE_SIZE (64 * 1024) 32768 +DCACHE_ASSOC 1 4 +DCACHE_LINE_SIZE 64 64 +DCACHE_CYCLES 2 +PERFECT_DCACHE FALSE +DCACHE_READ_PORTS 8 2 +DCACHE_WRITE_PORTS 1 1 +DCACHE_BANKS 1 1 +DCACHE_REPL 0 +DCACHE_REPL_PREF_THRESH 1 +MEM_OOO_STORES TRUE 1 +MEM_OBEY_STORE_DEP TRUE 1 +PREF_INSERT_LRU FALSE +PREF_INSERT_MIDDLE FALSE +PREF_INSERT_LOWQTR FALSE +PREF_INSERT_DYNACC FALSE +MEM_REQ_BUFFER_ENTRIES 32 32 +PRIVATE_MSHR_ON TRUE +MEM_PRIORITY_IFETCH 0 0 +MEM_PRIORITY_DFETCH 0 1 +MEM_PRIORITY_DSTORE 0 2 +MEM_PRIORITY_IPRF 9 3 +MEM_PRIORITY_DPRF 10 4 +MEM_PRIORITY_WB 0 5 +MEM_PRIORITY_WB_NODIRTY 0 5 +PROMOTE_TO_HIGHER_PRIORITY_MEM_REQ_TYPE FALSE 1 +MEM_REQ_BUFFER_PREF_WATERMARK 0 4 +MEM_REQ_BUFFER_WB_VALVE 2 +MEM_L1_FILL_QUEUE_ENTRIES 32 32 +MEM_BUS_OUT_QUEUE_PARTITION_ENABLE FALSE +MEM_MEM_QUEUE_PARTITION_ENABLE FALSE +MEM_BUS_OUT_QUEUE_AS_FIFO TRUE +OLDEST_FIRST_TO_MEM_QUEUE TRUE +ROUND_ROBIN_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE_TH 0 +L1_CYCLE_TIME 312500 +MLCQ_TO_L1Q_TRANSFER_LATENCY 1 +L1Q_TO_FSB_TRANSFER_LATENCY 1 +PRIORITIZE_PREFETCHES_WITH_UNIQUE FALSE +KICKOUT_PREFETCHES FALSE +KICKOUT_LOOK_FOR_OLDEST_FIRST FALSE +KICKOUT_OLDEST_PREFETCH FALSE +KICKOUT_OLDEST_PREFETCH_WITHIN_BANK FALSE +ORDER_BEYOND_BUS FALSE 1 +ALL_FIFO_QUEUES FALSE +QUEUE_MLC_SIZE 0 +QUEUE_L1_SIZE 0 +QUEUE_BUS_OUT_SIZE 0 +QUEUE_CORE_FILL_SIZE 0 +ALLOW_TYPE_MATCHES FALSE +STREAM_PREFETCH_ON FALSE +DC_PREF_CACHE_ENABLE FALSE +DC_PREF_CACHE_CYCLE 0 +PREF_INSERT_DCACHE_IMM TRUE +DC_PREF_CACHE_SIZE (64 * 1024) +DC_PREF_CACHE_ASSOC 4 +DC_PREF_ONLY_L1HIT FALSE +PREF_CACHE_USE_RDY_CYCLE FALSE +IC_PREF_CACHE_ENABLE FALSE +IC_PREF_CACHE_SIZE (64 * 1024) +IC_PREF_CACHE_ASSOC 4 +L1_PREF_CACHE_ENABLE FALSE +L1_PREF_CACHE_SIZE (1024 * 1024) +L1_PREF_CACHE_ASSOC 8 +SET_OFF_PATH_CONFIRMED FALSE 1 +USE_CONFIRMED_OFF FALSE +PREFCACHE_MOVE_OFFPATH FALSE +CACHE_STAT_ENABLE FALSE +PREF_DCACHE_HIT_FILL_L1 TRUE +PREF_ICACHE_HIT_FILL_L1 TRUE +CRITICAL_ACCESS_PLOT_ENABLE FALSE +CRITICAL_ACCESS_PLOT_FILE "critical_access_plot.dat" +ROUND_ROBIN_TO_L1 FALSE +PREF_I_TOGETHER FALSE +ONE_MORE_CACHE_LINE_ENABLE FALSE +L1_STATIC_PARTITION_ENABLE 0 +L1_STATIC_PARTITION NULL +L1_DYNAMIC_PARTITION_ENABLE FALSE +L1_DYNAMIC_PARTITION_POLICY 0 +PARTITION_UMON_DSS_PREF_ENABLE FALSE +L1_CACHE_HIT_POSITION_COLLECT FALSE +L1_PART_ON FALSE +L1_PART_TRIGGER "c:1000000" +L1_PART_START "t:0" +L1_PART_WARMUP FALSE +L1_PART_SHADOW_WARMUP FALSE +L1_PART_METRIC 0 +L1_PART_SEARCH 0 +L1_PART_USE_STALLING TRUE +L1_PART_FILL_DELAY 0 +L1_SHADOW_TAGS_MODULO 1 +HIER_MSHR_ON FALSE +PERF_PRED_ENABLE FALSE +PERF_PRED_MECH PERF_PRED_CP +PERF_PRED_REQ_LATENCY_MECH PERF_PRED_REQ_LATENCY_MECH_REQ_LATENCY +PERF_PRED_COUNT_ALL FALSE +PERF_PRED_COUNT_INST_MISSES TRUE +PERF_PRED_COUNT_PREFETCHES FALSE +PERF_PRED_COUNT_OFFPATH_REQS FALSE +PERF_PRED_COUNT_BW_REQS TRUE +PERF_PRED_UPDATE_MEM_REQ_TYPE FALSE +PERF_PRED_SLACK_PERIOD_SIZE 32 +PERF_PRED_REQS_FINISH_AT_FILL FALSE +PERF_PRED_MEM_UTIL_VIA_BUS_BW FALSE +PERF_PRED_CHIP_UTIL_VIA_MEM_STALL FALSE +DUMB_MODEL_AVG_REQ_DISTANCE 100 +DUMB_MODEL_RANDOMIZE_DISTANCE FALSE +DUMB_MODEL_AVG_REQ_DISTANCE_PER_CORE NULL +DUMB_MODEL_AVG_ROW_HITS 1 +DUMB_MODEL_AVG_ROW_HITS_PER_CORE NULL +DUMB_MODEL_MLP 1 +DUMB_MODEL_MLP_PER_CORE NULL +RAMULATOR_STANDARD "DDR4" DDR4 +RAMULATOR_SPEED "DDR4_2400R" DDR4_2400R +RAMULATOR_ORG "DDR4_8Gb_x8" DDR4_8Gb_x8 +RAMULATOR_CHANNELS 1 1 +RAMULATOR_RANKS 1 1 +RAMULATOR_BANKGROUPS 4 4 +RAMULATOR_BANKS 4 4 +RAMULATOR_CHIP_WIDTH 8 8 +BUS_WIDTH_IN_BYTES 8 8 +RAMULATOR_ROWS 65536 65536 +RAMULATOR_COLS 1024 1024 +RAMULATOR_SCHEDULING_POLICY "FRFCFS_Cap" FRFCFS_Cap +RAMULATOR_READQ_ENTRIES 32 32 +RAMULATOR_WRITEQ_ENTRIES 32 32 +RAMULATOR_REC_CMD_TRACE "off" FALSE +RAMULATOR_PRINT_CMD_TRACE "off" FALSE +RAMULATOR_USE_REST_OF_ADDR_AS_ROW_ADDR "on" +RAMULATOR_TCK 833333 833333 +RAMULATOR_TCL 16 16 +RAMULATOR_TCCD 6 6 +RAMULATOR_TCCDS 4 4 +RAMULATOR_TCCDL 6 6 +RAMULATOR_TCWL 12 12 +RAMULATOR_TBL 4 4 +RAMULATOR_TWTR 9 9 +RAMULATOR_TWTRS 3 3 +RAMULATOR_TWTRL 9 9 +RAMULATOR_TRP 16 16 +RAMULATOR_TRPpb 16 16 +RAMULATOR_TRPab 16 16 +RAMULATOR_TRCD 16 16 +RAMULATOR_TRCDR 16 16 +RAMULATOR_TRCDW 16 16 +RAMULATOR_TRAS 39 39 +DRAM_TECH_IN_NM 32 32 +DVFS_ON FALSE +DVFS_METRIC DVFS_METRIC_NUM_ELEMS +DVFS_CONFIGS NULL +DVFS_CONFIG_FILE NULL +DVFS_START "t:0" +DVFS_PERIOD "t:312500000000" +DVFS_LOG TRUE +DVFS_INDIVIDUAL_CORES FALSE +DVFS_CHIP_LEVEL FALSE +DVFS_STATIC NULL +DVFS_FORCE_CONFIG NULL +DVFS_REPLAY_CONFIG_TRACE NULL +DVFS_USE_ORACLE FALSE +DVFS_USE_BW_SHARING FALSE +DVFS_USE_DRAM_SHARING FALSE +DVFS_USE_STALL_TIME FALSE +DVFS_DRAM_SHARING_SOLVER_BIN NULL +DVFS_DRAM_SHARING_SOLVER_STRICT TRUE +DVFS_BW_SHARING_BUS_UTIL_THRESH 0.95 +DVFS_BW_SHARING_MAX_REQS 28.0 +DVFS_BW_SHARING_MAX_RW_COST 0.25 +DVFS_BW_SHARING_NO_PREF_STALL TRUE +DVFS_BW_SHARING_CRIT_STATS TRUE +DVFS_COUNT_L1_ACCESS_STALL FALSE +NUM_CORES 1 +CHIP_CYCLE_TIME 312500 312500 +CORE_0_CYCLE_TIME 312500 +CORE_1_CYCLE_TIME 312500 +CORE_2_CYCLE_TIME 312500 +CORE_3_CYCLE_TIME 312500 +CORE_4_CYCLE_TIME 312500 +CORE_5_CYCLE_TIME 312500 +CORE_6_CYCLE_TIME 312500 +CORE_7_CYCLE_TIME 312500 +CORE_8_CYCLE_TIME 312500 +CORE_9_CYCLE_TIME 312500 +CORE_10_CYCLE_TIME 312500 +CORE_11_CYCLE_TIME 312500 +CORE_12_CYCLE_TIME 312500 +CORE_13_CYCLE_TIME 312500 +CORE_14_CYCLE_TIME 312500 +CORE_15_CYCLE_TIME 312500 +CORE_16_CYCLE_TIME 312500 +CORE_17_CYCLE_TIME 312500 +CORE_18_CYCLE_TIME 312500 +CORE_19_CYCLE_TIME 312500 +CORE_20_CYCLE_TIME 312500 +CORE_21_CYCLE_TIME 312500 +CORE_22_CYCLE_TIME 312500 +CORE_23_CYCLE_TIME 312500 +CORE_24_CYCLE_TIME 312500 +CORE_25_CYCLE_TIME 312500 +CORE_26_CYCLE_TIME 312500 +CORE_27_CYCLE_TIME 312500 +CORE_28_CYCLE_TIME 312500 +CORE_29_CYCLE_TIME 312500 +CORE_30_CYCLE_TIME 312500 +CORE_31_CYCLE_TIME 312500 +CORE_32_CYCLE_TIME 312500 +CORE_33_CYCLE_TIME 312500 +CORE_34_CYCLE_TIME 312500 +CORE_35_CYCLE_TIME 312500 +CORE_36_CYCLE_TIME 312500 +CORE_37_CYCLE_TIME 312500 +CORE_38_CYCLE_TIME 312500 +CORE_39_CYCLE_TIME 312500 +CORE_40_CYCLE_TIME 312500 +CORE_41_CYCLE_TIME 312500 +CORE_42_CYCLE_TIME 312500 +CORE_43_CYCLE_TIME 312500 +CORE_44_CYCLE_TIME 312500 +CORE_45_CYCLE_TIME 312500 +CORE_46_CYCLE_TIME 312500 +CORE_47_CYCLE_TIME 312500 +CORE_48_CYCLE_TIME 312500 +CORE_49_CYCLE_TIME 312500 +CORE_50_CYCLE_TIME 312500 +CORE_51_CYCLE_TIME 312500 +CORE_52_CYCLE_TIME 312500 +CORE_53_CYCLE_TIME 312500 +CORE_54_CYCLE_TIME 312500 +CORE_55_CYCLE_TIME 312500 +CORE_56_CYCLE_TIME 312500 +CORE_57_CYCLE_TIME 312500 +CORE_58_CYCLE_TIME 312500 +CORE_59_CYCLE_TIME 312500 +CORE_60_CYCLE_TIME 312500 +CORE_61_CYCLE_TIME 312500 +CORE_62_CYCLE_TIME 312500 +CORE_63_CYCLE_TIME 312500 +ISSUE_WIDTH 4 6 +RS_FILL_WIDTH 8 0 +NODE_TABLE_SIZE 256 224 +NODE_RET_WIDTH 4 6 +NODE_RETIRE_RATE 10 +RS_SIZES "256" 97 +RS_CONNECTIONS "xF" 0 +FU_TYPES "0, 0, 0, 0" 0 0 0 0 0 0 0 0 +DECODE_CYCLES 1 5 +MAP_CYCLES 1 5 +EXTRA_RECOVERY_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after recovery. +EXTRA_REDIRECT_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after redirect. +EXTRA_CALLSYS_CYCLES 20 const +DIE_ON_CALLSYS FALSE +DIE_ON_RET_STALL_THRESH 0 +DIE_ON_RET_STALL_CORE 0 +DIE_ON_MEM_BLOCK_THRESH 0 +DIE_ON_MEM_BLOCK_CORE 0 +FETCH_ACROSS_CACHE_LINES FALSE 1 +FETCH_OFF_PATH_OPS TRUE 0 +FETCH_BREAK_ON_TAKEN FALSE 1 +FETCH_TAKEN_BUBBLE_CYCLES 0 0 +WP_COLLECT_STATS FALSE +SWITCH_IC_FETCH_ON_RECOVERY TRUE +OP_INV_DELAY 1 +OP_NOP_DELAY 1 +OP_CF_DELAY 1 +OP_MOV_DELAY 1 +OP_CMOV_DELAY 1 +OP_LDA_DELAY 1 +OP_IMEM_DELAY 1 +OP_IADD_DELAY 1 +OP_IMUL_DELAY 3 +OP_IDIV_DELAY -20 +OP_ICMP_DELAY 1 +OP_LOGIC_DELAY 1 +OP_SHIFT_DELAY 1 +OP_FMEM_DELAY 1 +OP_FCVT_DELAY 3 +OP_FADD_DELAY 3 +OP_FMUL_DELAY 5 +OP_FMA_DELAY 5 +OP_FDIV_DELAY -20 +OP_FCMP_DELAY 3 +OP_FCMOV_DELAY 1 +OP_GATHER_DELAY 12 +OP_SCATTER_DELAY 18 +OP_PIPELINED_FAST_DELAY 2 +OP_PIPELINED_MEDIUM_DELAY 5 +OP_PIPELINED_SLOW_DELAY 10 +OP_NOTPIPELINED_MEDIUM_DELAY -5 +OP_NOTPIPELINED_SLOW_DELAY -20 +OP_NOTPIPELINED_VERY_SLOW_DELAY -100 +UNIFORM_OP_DELAY 0 +STALL_ON_WAIT_MEM TRUE +STORES_DO_NOT_BLOCK_WINDOW FALSE 1 +PREFS_DO_NOT_BLOCK_WINDOW FALSE 1 +OBEY_REG_DEP TRUE +OLDEST_FIRST_SCHED FALSE +FIND_EMPTIEST_RS FALSE +TRACK_L1_MISS_DEPS FALSE +CBP_TRACE_R0 NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir/trace/drmemtrace.perlbench_s_base.mytest-m64.554262.9223.trace.gz +CBP_TRACE_R1 NULL +CBP_TRACE_R2 NULL +CBP_TRACE_R3 NULL +CBP_TRACE_R4 NULL +CBP_TRACE_R5 NULL +CBP_TRACE_R6 NULL +CBP_TRACE_R7 NULL +CBP_TRACE_R8 NULL +CBP_TRACE_R9 NULL +CBP_TRACE_R10 NULL +CBP_TRACE_R11 NULL +CBP_TRACE_R12 NULL +CBP_TRACE_R13 NULL +CBP_TRACE_R14 NULL +CBP_TRACE_R15 NULL +CBP_TRACE_R16 NULL +CBP_TRACE_R17 NULL +CBP_TRACE_R18 NULL +CBP_TRACE_R19 NULL +CBP_TRACE_R20 NULL +CBP_TRACE_R21 NULL +CBP_TRACE_R22 NULL +CBP_TRACE_R23 NULL +CBP_TRACE_R24 NULL +CBP_TRACE_R25 NULL +CBP_TRACE_R26 NULL +CBP_TRACE_R27 NULL +CBP_TRACE_R28 NULL +CBP_TRACE_R29 NULL +CBP_TRACE_R30 NULL +CBP_TRACE_R31 NULL +CBP_TRACE_R32 NULL +CBP_TRACE_R33 NULL +CBP_TRACE_R34 NULL +CBP_TRACE_R35 NULL +CBP_TRACE_R36 NULL +CBP_TRACE_R37 NULL +CBP_TRACE_R38 NULL +CBP_TRACE_R39 NULL +CBP_TRACE_R40 NULL +CBP_TRACE_R41 NULL +CBP_TRACE_R42 NULL +CBP_TRACE_R43 NULL +CBP_TRACE_R44 NULL +CBP_TRACE_R45 NULL +CBP_TRACE_R46 NULL +CBP_TRACE_R47 NULL +CBP_TRACE_R48 NULL +CBP_TRACE_R49 NULL +CBP_TRACE_R50 NULL +CBP_TRACE_R51 NULL +CBP_TRACE_R52 NULL +CBP_TRACE_R53 NULL +CBP_TRACE_R54 NULL +CBP_TRACE_R55 NULL +CBP_TRACE_R56 NULL +CBP_TRACE_R57 NULL +CBP_TRACE_R58 NULL +CBP_TRACE_R59 NULL +CBP_TRACE_R60 NULL +CBP_TRACE_R61 NULL +CBP_TRACE_R62 NULL +CBP_TRACE_R63 NULL +MEMTRACE_MODULES_LOG NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir/raw +DUMB_CORE_ON FALSE +DUMB_CORE 1 +DEBUG_CYCLE_START 0 0 +DEBUG_CYCLE_STOP 0 -1 +DEBUG_TIME_START 0 +DEBUG_TIME_STOP 0 +DEBUG_INST_START 0 0 +DEBUG_INST_STOP 0 -1 +DEBUG_OP_START 0 +DEBUG_OP_STOP 0 +DEBUG_CACHE_LIB FALSE +DEBUG_HASH_LIB FALSE +DEBUG_LIST_LIB FALSE +DEBUG_PORT_LIB FALSE +DEBUG_BUS_LIB FALSE +DEBUG_OP_POOL FALSE +DEBUG_ORACLE FALSE +DEBUG_FRONTEND FALSE +DEBUG_ADDR_TRANS FALSE +DEBUG_BP FALSE +DEBUG_BP_DIR FALSE +DEBUG_BTB FALSE +DEBUG_CRS FALSE +DEBUG_MAP FALSE +DEBUG_MEMORY FALSE +DEBUG_REPLAY FALSE +DEBUG_FREQ FALSE +DEBUG_MODEL FALSE +DEBUG_THREAD FALSE +DEBUG_ICACHE_STAGE FALSE +DEBUG_DECODE_STAGE FALSE +DEBUG_MAP_STAGE FALSE +DEBUG_NODE_STAGE FALSE +DEBUG_EXEC_STAGE FALSE +DEBUG_DCACHE_STAGE FALSE +DEBUG_RETIRED_UOPS FALSE +DEBUG_EXC_INSERTS FALSE +DEBUG_BP_CONF FALSE +DEBUG_ONPATH_CONF FALSE +DEBUG_STREAM FALSE +DEBUG_STREAM_MEM FALSE +DEBUG_WAY FALSE +DEBUG_L2MARKV FALSE +DEBUG_L2L1PREF FALSE +DEBUG_PERF_PRED FALSE +DEBUG_POWER_UTILS FALSE +DEBUG_DVFS FALSE +DEBUG_TRACE_READ FALSE +DEBUG_INST_FIELDS FALSE +DEBUG_OP_FIELDS FALSE +DEBUG_PIN_EXEC_DRIVEN FALSE +DEBUG_CACHE_PART FALSE +DEBUG_OPTIMIZER2 FALSE +DEBUG_PREF FALSE +PERFECT_BP FALSE +PERFECT_BTB FALSE +PERFECT_IBP FALSE +PERFECT_CRS FALSE +PERFECT_CBR_BTB FALSE +PERFECT_NT_BTB FALSE +CFS_PER_CYCLE 3 6 # Number of branches that can be predicted in a single cycle +UPDATE_BP_OFF_PATH FALSE 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +BP_UPDATE_AT_RETIRE FALSE 0 # Update the BP at retire. If false, update at the end of exec. +BP_MECH 0 tagescl +LATE_BP_MECH NUM_BP +LATE_BP_LATENCY 5 +HIST_LENGTH 16 +PHT_CTR_BITS 2 const +BHT_ENTRIES (4 * 1024) +BHT_ASSOC 4 +HYBRIDS_INDEX_LENGTH 16 +HYBRIDG_HIST_LENGTH 16 +HYBRIDP_HIST_LENGTH 16 +FILTER_INDEX_LENGTH 16 +USE_FILTER FALSE +INF_HYBRIDGP FALSE +BP_HASH_TOS FALSE +IBTB_HASH_TOS FALSE +BTB_MECH 0 generic +BTB_ENTRIES (4 * 1024) 4096 +BTB_ASSOC 4 4 +BTB_OFF_PATH_WRITES TRUE 1 +ENABLE_CRS TRUE 1 +CRS_ENTRIES 32 32 +CRS_REALISTIC 0 1 +ENABLE_IBP TRUE 1 # Enable the indirect branch predictor +USE_PAT_HIST TRUE +IBTB_MECH 1 tc_tagged +IBTB_HIST_LENGTH 16 +IBTB_OFF_PATH_WRITES TRUE 1 # Allow off path ops to update the ibtb. +TARGETS_IN_HIST 4 +TC_ENTRIES (4 * 1024) 4096 +TC_ASSOC 4 4 +NUM_CORR_BRANCHES 3 +SEL_HIST_BP_ENTRIES 8192 +SEL_HIST_LENGTH 16 +SEL_HIST_DYN_CNT_TH 16 +SEL_HIST_MISPRED_TH 4 +ENABLE_BP_CONF FALSE +CONF_MECH 0 +PERF_BP_CONF_PRED FALSE +BPC_BITS 16 +BPC_MECH 1 +BPC_CTR_RESET TRUE +BPC_CIT_BITS 8 +BPC_CIT_TH 50 +BPC_CTR_BITS 3 +OPC_COUNT_ZEROS FALSE +OPC_COUNT_THRESH 10 +INF_LOOP FALSE +INF_LOOP_BUCKETS 811 +LOOP_ENTRIES (4 * 1024) +LOOP_ASSOC 4 +LOOP_COUNT_MAX 127 +LOOP_REPEAT_MAX 15 +KNOB_PRINT_BRINFO FALSE +BR_MISPRED_FILE NULL +CONF_PERCEPTRON_TH 0 +CONF_PERCEPTRON_CTR_BITS 8 +CONF_PERCEPTRON_ENTRIES 127 +CONF_PERCEPTRON_THRESH_OVRD 0 +CONF_HIST_LENGTH 32 +PERCEPTRON_CONF_USE_CONF FALSE +PERCEPTRON_CONF_TRAIN_HIS FALSE +PERCEPTRON_CONF_TRAIN_CONF FALSE +PERCEPTRON_CONF_TRAIN_OFFSET_CONF FALSE +PERCEPTRON_TRAIN_MISP_FACTOR 1 +PERCEPTRON_TRAIN_CORR_FACTOR 1 +PERCEPTRON_CONF_HIS_BOTH FALSE +PERCEPTRON_CONF_HIS_BOTH_LENGTH 4 +ENABLE_ICACHE_PACKET_BREAKING TRUE +NUM_LOAD_STORE_PER_PACKET 0 +PACKET_BREAK_ON_FUS FALSE +PACKET_BREAK_FU_TYPES "G,G,G,G,G,G,G,G,G,G,G,G" +POWER_INTF_ON FALSE +POWER_INTF_ENABLE_SCALING FALSE +POWER_INTF_EXEC "power/power_intf.py" +POWER_INTF_REF_CHIP_TECH_NM 22 +POWER_INTF_REF_CHIP_FREQ (3.2e9) +POWER_INTF_REF_MEMORY_FREQ (0.8e9) +POWER_OTHER (0.0) +PREF_STREAM_ON FALSE 1 +PREF_STREAM_PER_CORE_ENABLE FALSE 1 +STREAM_BUFFER_N 16 +STREAM_PREFETCH_N 2 4 +STREAM_START_DIS 5 1 +STREAM_LENGTH 16 64 +STREAM_FULL_N 1 +STREAM_TRAIN_LENGTH 16 +STREAM_TRAIN_NUM 1 4 +PREF_ACC_USE_CACHE FALSE +STREAM_STALL_ON_QUEUE_FULL FALSE +PREF_SCHEDULE_NUM 4 +TRAIN_FILTER_SIZE 32 +PREF_REQ_Q_SIZE 64 +STREAM_CREATE_ON_DC_MISS FALSE 0 +STREAM_CREATE_ON_L1_MISS TRUE 1 +STREAM_TRAIN_ON_WRONGPATH TRUE +STREAM_CREATE_ON_WRONGPATH TRUE +STREAM_PREF_INTO_DCACHE FALSE +REMOVE_REDUNDANT_STREAM FALSE +L2HIT_STREAM_SCHEDULE_NUM 4 +PREF_REQ_QUEUE_FILTER_ON FALSE +HW_PREF_HIT_TRAIN_STREAM FALSE +L2HIT_STREAM_BUFFER_N 32 +L2HIT_STREAM_PREFETCH_N 2 +L2HIT_STREAM_START_DIS 2 +L2HIT_STREAM_LENGTH 8 +L2HIT_PREF_REQ_Q_SIZE 128 +L2HIT_L2ACCESS_REQ_Q_SIZE 64 +PREF_STREAM_ACCPERSTREAM FALSE +PREF_ACC_DISTANCE_10 128 +PREF_FRAMEWORK_ON FALSE 1 +PREF_TRACE_ON FALSE +PREF_DL0REQ_QUEUE_SIZE 32 +PREF_UMLC_REQ_QUEUE_SIZE 64 +PREF_UL1REQ_QUEUE_SIZE 128 +PREF_SHARED_QUEUES TRUE 0 +PREF_DL0_MISS_ON TRUE +PREF_DL0_HIT_ON TRUE +PREF_DL0REQ_QUEUE_FILTER_ON TRUE +PREF_UMLC_REQ_QUEUE_FILTER_ON TRUE +PREF_UL1REQ_QUEUE_FILTER_ON TRUE +PREF_DL0REQ_ADD_FILTER_ON TRUE +PREF_UMLC_REQ_ADD_FILTER_ON TRUE +PREF_UL1REQ_ADD_FILTER_ON TRUE +PREF_DL0REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UMLC_REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UL1REQ_QUEUE_OVERWRITE_ON_FULL FALSE 1 +PREF_DL0SCHEDULE_NUM 4 +PREF_UMLC_SCHEDULE_NUM 4 +PREF_UL1SCHEDULE_NUM 4 +PREF_L1Q_DEMAND_RESERVE 0 +PREF_REPORT_PREF_MATCH_AS_MISS FALSE +PREF_REPORT_PREF_MATCH_AS_HIT TRUE +PREF_UPDATE_ON_WRONGPATH TRUE +PREF_TRAIN_ON_PREF_MISSES FALSE 0 +PREF_ORACLE_TRAIN_ON FALSE 0 +PREF_REQ_DROP FALSE +PREF_THROTTLE_ON FALSE +PREF_THROTTLEFB_ON FALSE 1 +PREF_ACC_THRESH_1 0.90 0.75 +PREF_ACC_THRESH_2 0.70 0.4 +PREF_ACC_THRESH_3 0.60 0.4 +PREF_ACC_THRESH_4 0.40 +PREF_UPDATE_INTERVAL 0 8192 +PREF_ANALYZE_LOAD FALSE +PREF_POL_THRESH_1 0.25 +PREF_POL_THRESH_2 0.10 +PREF_POLBV_ON FALSE +PREF_POLBV_SIZE 1024 +PREF_TIMELY_THRESH 0.05 0.01 +PREF_POLPF_THRESH 0.01 0.005 +PREF_DEGFB_USEONLYACC FALSE +PREF_DEGFB_USEONLYPOL FALSE +PREF_DEGFB_USEONLYLATE FALSE +PREF_TIMELY_THRESH_2 0.005 +PREF_DEGFB_STATPHASEFILE FALSE +PREF_MAX_DEGFB 4 +PREF_DHAL FALSE +PREF_DHAL_SENTTHRESH 16 +PREF_DHAL_USETHRESH_MAX 12 +PREF_DHAL_USETHRESH_MIN2 8 +PREF_DHAL_USETHRESH_MIN1 4 +PREF_DHAL_MAXDEG 64 +PREF_HFILTER_ON FALSE +PREF_HFILTER_INDEX_BITS 12 +PREF_HFILTER_USE_PC FALSE +PREF_HFILTER_PRED_USELESS_THRES 2 +PREF_HFILTER_RESET_ENABLE FALSE +PREF_HFILTER_RESET_INTERVAL 100000 +L2L1PREF_ON FALSE +L2WAY_PREF FALSE +L2MARKV_PREF_ON FALSE +L2NEXT_PREF_ON FALSE +L2HIT_STREAM_PREF_ON FALSE +L2L1_DC_HIT_TRAIN FALSE +L1_HIT_DUMP_FILE_ON FALSE +L1_HIT_DUMP_WO_TXT FALSE +L1_HIT_DUMPFILE "l1hit_dump.out" +IDEAL_L2_L1_PREFETCHER FALSE +IDEAL_L2_ICACHE_PREFETCHER FALSE +L1WAY_PREF_SEND_QUEUE 4 +L1PREF_REQ_QUEUE_SIZE 1024 +L1PREF_IMMEDIATE FALSE +L1WAY_PREF_TIMER_DIS 1000 +L1MARKV_PREF_SEND_QUEUE 4 +L1PREF_MARKV_REQ_QUEUE_SIZE 1024 +MARKV_L2ACCESS_REQ_Q_SIZE 64 +L1MARKV_PREF_IMMEDIATE FALSE +L1MARKV_PREF_TIMER_DIS 1 +L2L1_HIT_TRAIN TRUE +L1MARKV_REQ_TH 1 +L2L1_IMMEDIATE_PREF_CACHE FALSE +L2L1_FILL_PREF_CACHE FALSE +L2L1_L2_HIT_STAT FALSE +PREF_GHB_ON FALSE +DEBUG_PREF_GHB FALSE +PREF_GHB_BUFFER_N 1024 +PREF_GHB_INDEX_N 128 +PREF_GHB_CZONE_BITS 12 +PREF_GHB_DEGREE 16 +PREF_GHB_MAX_DEGREE 32 +PREF_STRIDE_ON FALSE +DEBUG_PREF_STRIDE FALSE +PREF_STRIDE_TABLE_N 1024 +PREF_STRIDE_REGION_BITS 16 +PREF_STRIDE_DEGREE 4 +PREF_STRIDE_DISTANCE 16 +PREF_STRIDE_STARTDISTANCE 1 +PREF_STRIDE_SINGLE_THRESH 6 +PREF_STRIDE_MULTI_THRESH 6 +PREF_STRIDE_SINGLE_STRIDE_MODE FALSE +PREF_STRIDEPC_ON FALSE +DEBUG_PREF_STRIDEPC FALSE +PREF_STRIDEPC_TABLE_N 1024 +PREF_STRIDEPC_DEGREE 4 +PREF_STRIDEPC_DISTANCE 16 +PREF_STRIDEPC_USELOADADDR FALSE +PREF_STRIDEPC_TRAINNUM 2 +PREF_STRIDEPC_STARTDIS 4 +PREF_PHASE_ON FALSE +PREF_PHASE_STUDY FALSE +DEBUG_PREF_PHASE FALSE +PREF_PHASE_PRIME_HASH 16381 +PREF_PHASE_INFOSIZE 16384 +PREF_PHASE_LOG2REGIONSIZE 12 +PREF_PHASE_REGIONENTRIES 64 +PREF_PHASE_TRACKEDREGIONS 32 +PREF_PHASE_INTERVAL 100000 +PREF_PHASE_TABLE_SIZE 64 +PREF_PHASE_MAXDIFF_THRESH 64 +PREF_PHASE_MIN_MISSES 64 +PREF_PHASE_MISSPER 0.4 +PREF_2DC_ON FALSE +DEBUG_PREF_2DC FALSE +PREF_2DC_CACHE_SIZE (1 * 1024) +PREF_2DC_CACHE_ASSOC 4 +PREF_2DC_CACHE_LINE_SIZE 1 +PREF_2DC_DEGREE 16 +PREF_2DC_ZONE_SHIFT 10 +PREF_2DC_TAG_SIZE 16 +PREF_2DC_NUM_REGIONS 64 +PREF_2DC_REGION_HASH 61 +PREF_MARKOV_ON FALSE +DEBUG_PREF_MARKOV FALSE +PREF_MARKOV_NUM_ENTRIES 65536 +PREF_MARKOV_NUM_NEXT_STATES 8 +PREF_MARKOV_SEND_ON_PREF_HIT TRUE +PREF_MARKOV_UPDATE_ON_PREF_HIT TRUE +PREF_MARKOV_TABLE_UPDATE_POLICY 0 +PREF_MARKOV_SEND_THRESHOLD 0 +PREF_SMS_ON FALSE 0 +PREF_SMS_AT_SIZE 64 +PREF_SMS_FT_SIZE 64 +PREF_SMS_PHT_SIZE 16384 +PREF_SMS_PRF_SIZE 1024 +PREF_SMS_REGION_SIZE 2048 diff --git a/labs/LAB5/runs/perlbench_s_base-sms0/bp.stat.0.out b/labs/LAB5/runs/perlbench_s_base-sms0/bp.stat.0.out new file mode 100644 index 00000000..fc63b2af --- /dev/null +++ b/labs/LAB5/runs/perlbench_s_base-sms0/bp.stat.0.out @@ -0,0 +1,752 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 77430070 Instructions: 100000004 IPC: 1.29149 + +BTB_ON_PATH_MISS 406595 1.920% 406595 1.920% +BTB_ON_PATH_HIT 20765344 98.080% 20765344 98.080% + 21171939 100.000% 21171939 100.000% + 0.98 0.97 0.98 0.97 + +BTB_OFF_PATH_MISS 0 -nan% 0 -nan% +BTB_OFF_PATH_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BTB_ON_PATH_WRITE 406595 100.000% 406595 100.000% +BTB_OFF_PATH_WRITE 0 0.000% 0 0.000% + 406595 100.000% 406595 100.000% + 0.00 0.00 0.00 0.00 + +BP_ON_PATH_CORRECT 20231310 95.557% 20231310 95.557% +BP_ON_PATH_MISPREDICT 119560 0.565% 119560 0.565% +BP_ON_PATH_MISFETCH 821069 3.878% 821069 3.878% + 21171939 100.000% 21171939 100.000% + 0.08 0.38 0.08 0.38 + +BP_OFF_PATH_CORRECT 0 -nan% 0 -nan% +BP_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% +BP_OFF_PATH_MISFETCH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +LATE_BP_ON_PATH_CORRECT 21171939 100.000% 21171939 100.000% +LATE_BP_ON_PATH_MISPREDICT 0 0.000% 0 0.000% +LATE_BP_ON_PATH_MISFETCH 0 0.000% 0 0.000% + 21171939 100.000% 21171939 100.000% + 0.00 0.00 0.00 0.00 + +LATE_BP_OFF_PATH_CORRECT 0 -nan% 0 -nan% +LATE_BP_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% +LATE_BP_OFF_PATH_MISFETCH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_PVN 0 -nan% 0 -nan% +BP_ON_PATH_CONF_PVN_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_PVP 0 -nan% 0 -nan% +BP_ON_PATH_CONF_PVP_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_SPEC 0 -nan% 0 -nan% +BP_ON_PATH_CONF_SPEC_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CRS_MISS_ON_PATH 11965 0.926% 11965 0.926% +CRS_HIT_ON_PATH 1279813 99.074% 1279813 99.074% + 1291778 100.000% 1291778 100.000% + 0.99 0.99 0.99 0.99 + +CRS_MISS_OFF_PATH 0 -nan% 0 -nan% +CRS_HIT_OFF_PATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CRS_CLOBBER 0 0 + +TARG_ON_PATH_MISS 187022 18.287% 187022 18.287% +TARG_ON_PATH_HIT 835661 81.713% 835661 81.713% + 1022683 100.000% 1022683 100.000% + 0.82 0.76 0.82 0.76 + +TARG_OFF_PATH_MISS 0 -nan% 0 -nan% +TARG_OFF_PATH_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_ON_PATH_WRITE 1022682 100.000% 1022682 100.000% +TARG_OFF_PATH_WRITE 0 0.000% 0 0.000% + 1022682 100.000% 1022682 100.000% + 0.00 0.00 0.00 0.00 + +TARG_HYBRID_CORRECT_TAGLESS 0 -nan% 0 -nan% +TARG_HYBRID_CORRECT_TAGGED 0 -nan% 0 -nan% +TARG_HYBRID_MISPRED_TAGLESS 0 -nan% 0 -nan% +TARG_HYBRID_MISPRED_TAGGED 0 -nan% 0 -nan% +TARG_HYBRID_NO_PRED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_VP_INDIRECT_MISPRED 0 -nan% 0 -nan% +TARG_VP_INDIRECT_NOPRED 0 -nan% 0 -nan% +TARG_VP_INDIRECT_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CBR_ON_PATH_CORRECT 16321047 99.273% 16321047 99.273% +CBR_ON_PATH_MISPREDICT 119560 0.727% 119560 0.727% + 16440607 100.000% 16440607 100.000% + 0.01 0.08 0.01 0.08 + +CBR_ON_PATH_CORRECT_PER1000INST 16321047 163.2105 16321047 163.2105 + +CBR_ON_PATH_MISPREDICT_PER1000INST 119560 1.1956 119560 1.1956 + +CBR_OFF_PATH_CORRECT 0 -nan% 0 -nan% +CBR_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PRED_TO_UPDATE_CYCLES_0 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_1 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_2 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_3 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_4 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_5 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_6 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_7 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_8 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_9 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_10 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_11 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_12 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_13 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_14 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_15 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_16 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_17 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_18 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_19 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_20 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_21 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_22 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_23 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_24 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_25 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_26 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_27 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_28 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_29 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_30 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_CORRECTED 0 -nan% 0 -nan% +BP_NOT_CORRECTED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_CORRECTED 0 -nan% 0 -nan% +TARG_NOT_CORRECTED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_MISP_PENALTY 17562469 17562469 + +BP_ON_PATH_CONF_MISPRED 0 -nan% 0 -nan% +BP_ON_PATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_OFF_PATH_CONF_MISPRED 0 -nan% 0 -nan% +BP_OFF_PATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_PRED_MIS_CONF_MISPRED 0 -nan% 0 -nan% +BP_ON_PATH_PRED_MIS_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_PRED_COR_CONF_MISPRED 0 -nan% 0 -nan% +BP_ON_PATH_PRED_COR_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_OFF_PATH_PRED_MIS_CONF_MISPRED 0 -nan% 0 -nan% +BP_OFF_PATH_PRED_MIS_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_OFF_PATH_PRED_COR_CONF_MISPRED 0 -nan% 0 -nan% +BP_OFF_PATH_PRED_COR_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ONPATH_CONF_MISPRED 0 -nan% 0 -nan% +ONPATH_CONF_CORRECT 0 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-nan% + -nan -nan -nan -nan + +OPC_LENGTH_24_31_MIS 0 -nan% 0 -nan% +OPC_LENGTH_24_31_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_32_39_MIS 0 -nan% 0 -nan% +OPC_LENGTH_32_39_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_40_47_MIS 0 -nan% 0 -nan% +OPC_LENGTH_40_47_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_48_55_MIS 0 -nan% 0 -nan% +OPC_LENGTH_48_55_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_56_63_MIS 0 -nan% 0 -nan% +OPC_LENGTH_56_63_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_64_71_MIS 0 -nan% 0 -nan% +OPC_LENGTH_64_71_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_72_79_MIS 0 -nan% 0 -nan% +OPC_LENGTH_72_79_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_80_MIS 0 -nan% 0 -nan% +OPC_LENGTH_80_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ALL_ONES_MIS 0 -nan% 0 -nan% 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+#################################################################################################### +Cumulative: Cycles: 77430070 Instructions: 100000004 IPC: 1.29149 + +ST_OP_INV 0 0.000% 0 0.000% +ST_OP_NOP 1436724 1.188% 1436724 1.188% +ST_OP_CF 21171995 17.500% 21171995 17.500% +ST_OP_MOV 8743427 7.227% 8743427 7.227% +ST_OP_CMOV 581023 0.480% 581023 0.480% +ST_OP_LDA 3455348 2.856% 3455348 2.856% +ST_OP_IMEM 44030303 36.395% 44030303 36.395% +ST_OP_IADD 19119538 15.804% 19119538 15.804% +ST_OP_IMUL 112123 0.093% 112123 0.093% +ST_OP_IDIV 176 0.000% 176 0.000% +ST_OP_ICMP 9348536 7.727% 9348536 7.727% +ST_OP_LOGIC 11815904 9.767% 11815904 9.767% +ST_OP_SHIFT 892518 0.738% 892518 0.738% +ST_OP_FMEM 251195 0.208% 251195 0.208% +ST_OP_FCVT 201 0.000% 201 0.000% +ST_OP_FADD 186 0.000% 186 0.000% +ST_OP_FMUL 100 0.000% 100 0.000% +ST_OP_FMA 240 0.000% 240 0.000% +ST_OP_FDIV 3 0.000% 3 0.000% +ST_OP_FCMP 198 0.000% 198 0.000% +ST_OP_FCMOV 0 0.000% 0 0.000% +ST_OP_GATHER 0 0.000% 0 0.000% +ST_OP_SCATTER 0 0.000% 0 0.000% +ST_OP_PIPELINED_FAST 13685 0.011% 13685 0.011% +ST_OP_PIPELINED_MEDIUM 0 0.000% 0 0.000% +ST_OP_PIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_MEDIUM 7222 0.006% 7222 0.006% +ST_OP_NOTPIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_VERY_SLOW 0 0.000% 0 0.000% + 120980645 100.000% 120980645 100.000% + 6.00 2.84 6.00 2.84 + +ST_NOT_CF 99808650 82.500% 99808650 82.500% +ST_CF_BR 1516427 1.253% 1516427 1.253% +ST_CF_CBR 16440607 13.589% 16440607 13.589% +ST_CF_CALL 900444 0.744% 900444 0.744% +ST_CF_IBR 631358 0.522% 631358 0.522% +ST_CF_ICALL 391325 0.323% 391325 0.323% +ST_CF_ICO 0 0.000% 0 0.000% +ST_CF_RET 1291778 1.068% 1291778 1.068% +ST_CF_SYS 56 0.000% 56 0.000% + 120980645 100.000% 120980645 100.000% + 0.42 1.00 0.42 1.00 + +ST_BAR_NONE 120980589 100.000% 120980589 100.000% +ST_BAR_FETCH 56 0.000% 56 0.000% +ST_BAR_ISSUE 0 0.000% 0 0.000% +ST_BAR_BOTH 0 0.000% 0 0.000% + 120980645 100.000% 120980645 100.000% + 0.00 0.00 0.00 0.00 + +ST_NOT_MEM 76699147 63.398% 76699147 63.398% +ST_MEM_LD 28757686 23.770% 28757686 23.770% +ST_MEM_ST 15523812 12.832% 15523812 12.832% +ST_MEM_PF 0 0.000% 0 0.000% +ST_MEM_WH 0 0.000% 0 0.000% +ST_MEM_EVICT 0 0.000% 0 0.000% + 120980645 100.000% 120980645 100.000% + 0.49 0.59 0.49 0.59 + +ST_NOT_MEM_OFFPATH 0 -nan% 0 -nan% +ST_MEM_LD_OFFPATH 0 -nan% 0 -nan% +ST_MEM_ST_OFFPATH 0 -nan% 0 -nan% +ST_MEM_PF_OFFPATH 0 -nan% 0 -nan% +ST_MEM_WH_OFFPATH 0 -nan% 0 -nan% +ST_MEM_EVIC_OFFPATHT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ST_OP_ONPATH 120980645 120980645 + +ST_OP_OFFPATH 0 0 + +ST_FAKE_OP_OFFPATH 0 -nan% 0 -nan% +ST_NOT_FAKE_OP_OFFPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ST_FAKE_REASON_NOT_FAKE 0 -nan% 0 -nan% +ST_FAKE_REASON_REDIRECT_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_RETURN_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_NONRET_CF_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_NOT_TAKEN_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_WRONG_PATH_STORE_TO_NEW_REGION 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ST_INST_ONPATH 100000077 100000077 + +ST_INST_OFFPATH 0 0 + +STATIC_PIN_NOP 0 0 + +DYNAMIC_PIN_REP_GREATER_256 0 0 + + + diff --git a/labs/LAB5/runs/perlbench_s_base-sms0/l2l1pref.stat.0.out b/labs/LAB5/runs/perlbench_s_base-sms0/l2l1pref.stat.0.out new file mode 100644 index 00000000..ac36f1d4 --- /dev/null +++ b/labs/LAB5/runs/perlbench_s_base-sms0/l2l1pref.stat.0.out @@ -0,0 +1,140 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 77430070 Instructions: 100000004 IPC: 1.29149 + +L2WAY_FILL_L1 0 0 + +L2WAY_WAY_HIT 0 -nan% 0 -nan% +L2WAY_WAY_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_PREF_REQ 0 0 + +L2WAY_PREF_HIT_DATA_IN_CACHE 0 -nan% 0 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0 0 + +L2NEXT_PREF_HIT_DATA_REQ 0 -nan% 0 -nan% +L2NEXT_PREF_HIT_DATA_IN_CACHE 0 -nan% 0 -nan% +L2NEXT_PREF_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2NEXT_L1INSERT_PORT_READY 0 -nan% 0 -nan% +L2NEXT_L1INSERT_PORT_FULL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DCACHE_PREF_NOT_RDY 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_10 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_100 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_1000 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_10000 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_100000 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_1000000 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_10000000 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_100000000 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_MORE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_SAME_IP_DELTA__0 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__1 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__2 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__3 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__4 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__5 0 -nan% 0 -nan% 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+#################################################################################################### +Cumulative: Cycles: 77430070 Instructions: 100000004 IPC: 1.29149 + +ICACHE_MISS 925010 2.711% 925010 2.711% +ICACHE_HIT 33197590 97.289% 33197590 97.289% + 34122600 100.000% 34122600 100.000% + 0.97 0.96 0.97 0.96 + +ICACHE_MISS_ONPATH 925010 100.000% 925010 100.000% +ICACHE_MISS_OFFPATH 0 0.000% 0 0.000% + 925010 100.000% 925010 100.000% + 0.00 0.00 0.00 0.00 + +ICACHE_HIT_ONPATH 33197590 100.000% 33197590 100.000% +ICACHE_HIT_OFFPATH 0 0.000% 0 0.000% + 33197590 100.000% 33197590 100.000% + 0.00 0.00 0.00 0.00 + +ICACHE_HIT_ONPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +ICACHE_HIT_ONPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ICACHE_HIT_OFFPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +ICACHE_HIT_OFFPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DCACHE_MISS 1885733 4.259% 1885733 4.259% +DCACHE_ST_BUFFER_HIT 19194 0.043% 19194 0.043% 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-nan -nan -nan + +DCACHE_MISS_LD 1545282 81.946% 1545282 81.946% +DCACHE_MISS_ST 340451 18.054% 340451 18.054% + 1885733 100.000% 1885733 100.000% + 0.18 0.36 0.18 0.36 + +DCACHE_MISS_LD_ONPATH 1545282 100.000% 1545282 100.000% +DCACHE_MISS_LD_OFFPATH 0 0.000% 0 0.000% + 1545282 100.000% 1545282 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_MISS_ST_ONPATH 340451 100.000% 340451 100.000% +DCACHE_MISS_ST_OFFPATH 0 0.000% 0 0.000% + 340451 100.000% 340451 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_MISS_WAITMEM 8759 8759 + +MEM_REQ_ROW_BUFFER_HITS 0 -nan% 0 -nan% +MEM_REQ_ROW_BUFFER_MISSES 0 -nan% 0 -nan% +MEM_REQ_ROW_BUFFER_CONFLICTS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +SHADOW_ROW_BUFFER_HITS 0 0 + +SHADOW_ROW_HIT_STALL_TIME 0 0 + +CHANNEL0_BUS_BUSY_CYCLES 0 -nan% 0 -nan% +CHANNEL1_BUS_BUSY_CYCLES 0 -nan% 0 -nan% +CHANNEL2_BUS_BUSY_CYCLES 0 -nan% 0 -nan% +CHANNEL3_BUS_BUSY_CYCLES 0 -nan% 0 -nan% +CHANNEL4_BUS_BUSY_CYCLES 0 -nan% 0 -nan% +CHANNEL5_BUS_BUSY_CYCLES 0 -nan% 0 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17291064 118.3647 17291064 118.3647 + +CORE_MEM_LATENCY_PREF 11638004 153.5884 11638004 153.5884 + +CORE_MEM_LATENCY_IFETCH 1870638 6.466% 1870638 6.466% +CORE_MEM_LATENCY_DFETCH 13099934 45.283% 13099934 45.283% +CORE_MEM_LATENCY_DSTORE 2868396 9.915% 2868396 9.915% +CORE_MEM_LATENCY_IPRF 0 0.000% 0 0.000% +CORE_MEM_LATENCY_DPRF 11090100 38.335% 11090100 38.335% +CORE_MEM_LATENCY_WB 0 0.000% 0 0.000% +CORE_MEM_LATENCY_WB_NODIRTY 0 0.000% 0 0.000% + 28929068 100.000% 28929068 100.000% + 2.18 1.38 2.18 1.38 + +CORE_MEM_STALLING_LATENCY_IFETCH 0 -nan% 0 -nan% +CORE_MEM_STALLING_LATENCY_DFETCH 0 -nan% 0 -nan% +CORE_MEM_STALLING_LATENCY_DSTORE 0 -nan% 0 -nan% +CORE_MEM_STALLING_LATENCY_IPRF 0 -nan% 0 -nan% +CORE_MEM_STALLING_LATENCY_DPRF 0 -nan% 0 -nan% +CORE_MEM_STALLING_LATENCY_WB 0 -nan% 0 -nan% +CORE_MEM_STALLING_LATENCY_WB_NODIRTY 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TOTAL_L1_MISS_LATENCY 28929068 130.3951 28929068 130.3951 + +TOTAL_L1_MISS_LATENCY_DEMAND 17291064 118.3647 17291064 118.3647 + +TOTAL_L1_MISS_LATENCY_PREF 11638004 153.5884 11638004 153.5884 + +CORE_L1_MISS_LATENCY 28929068 130.3951 28929068 130.3951 + +CORE_L1_MISS_LATENCY_DEMAND 17291064 118.3647 17291064 118.3647 + +CORE_L1_MISS_LATENCY_PREF 11638004 153.5884 11638004 153.5884 + +CORE_EVICTED_L1_DEMAND 137768 67.027% 137768 67.027% +CORE_EVICTED_L1_PREF_USED 27910 13.579% 27910 13.579% +CORE_EVICTED_L1_PREF_NOT_USED 39864 19.395% 39864 19.395% + 205542 100.000% 205542 100.000% + 0.52 0.71 0.52 0.71 + +CORE_EVICTED_MLC_DEMAND 0 -nan% 0 -nan% +CORE_EVICTED_MLC_PREF_USED 0 -nan% 0 -nan% +CORE_EVICTED_MLC_PREF_NOT_USED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CORE_MEM_LATENCY_AVE_DEMAND 16269702 118.0949 16269702 118.0949 + +CORE_MEM_LATENCY_AVE_PREF_USED 3457482 123.8797 3457482 123.8797 + +CORE_MEM_LATENCY_AVE_PREF_NOT_USED 6573191 164.8904 6573191 164.8904 + +DRAM_LATENCY 0 0 + +TOTAL_DRAM_LATENCY 0 0 + +DRAM_CLOSED_PAGE_POLICY_CMD 0 0 + +DRAM_ACTIVATE_STALLING 0 0 + +DRAM_PRECHARGE_STALLING 0 0 + +DRAM_PRECHARGE_STALLING_WAIT_CYCLES 0 0 + +L1_STAY_DEMAND 751414207407 5454199.8679 751414207407 5454199.8679 + +L1_STAY_PREF_USED 152758627109 5473257.8685 152758627109 5473257.8685 + +L1_STAY_PREF_NOT_USED 165555202725 4153000.2690 165555202725 4153000.2690 + +TOTAL_DATA_MISS_LATENCY 15968330 15968330 + +TOTAL_DATA_MISS_COUNT 128330 128330 + +CORE_PREF_L1_NOT_USED_LATENCY200 32665 81.941% 32665 81.941% +CORE_PREF_L1_NOT_USED_LATENCY400 3876 9.723% 3876 9.723% +CORE_PREF_L1_NOT_USED_LATENCY600 1450 3.637% 1450 3.637% +CORE_PREF_L1_NOT_USED_LATENCY800 831 2.085% 831 2.085% +CORE_PREF_L1_NOT_USED_LATENCY1000 376 0.943% 376 0.943% +CORE_PREF_L1_NOT_USED_LATENCY1200 220 0.552% 220 0.552% +CORE_PREF_L1_NOT_USED_LATENCY1400 196 0.492% 196 0.492% +CORE_PREF_L1_NOT_USED_LATENCY1600 99 0.248% 99 0.248% +CORE_PREF_L1_NOT_USED_LATENCY1600MORE 151 0.379% 151 0.379% + 39864 100.000% 39864 100.000% + 0.38 1.00 0.38 1.00 + +CORE_PREF_L1_NOT_USED_DISTANCE_1 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_DISTANCE_2 397 0.996% 397 0.996% +CORE_PREF_L1_NOT_USED_DISTANCE_4 3516 8.820% 3516 8.820% +CORE_PREF_L1_NOT_USED_DISTANCE_8 13136 32.952% 13136 32.952% +CORE_PREF_L1_NOT_USED_DISTANCE_16 16703 41.900% 16703 41.900% +CORE_PREF_L1_NOT_USED_DISTANCE_32 6065 15.214% 6065 15.214% +CORE_PREF_L1_NOT_USED_DISTANCE_MORE 47 0.118% 47 0.118% + 39864 100.000% 39864 100.000% + 3.62 0.89 3.62 0.89 + +CORE_PREF_L1_USED_LATENCY200 24774 88.764% 24774 88.764% +CORE_PREF_L1_USED_LATENCY400 1626 5.826% 1626 5.826% +CORE_PREF_L1_USED_LATENCY600 832 2.981% 832 2.981% +CORE_PREF_L1_USED_LATENCY800 283 1.014% 283 1.014% +CORE_PREF_L1_USED_LATENCY1000 99 0.355% 99 0.355% +CORE_PREF_L1_USED_LATENCY1200 112 0.401% 112 0.401% +CORE_PREF_L1_USED_LATENCY1400 139 0.498% 139 0.498% +CORE_PREF_L1_USED_LATENCY1600 20 0.072% 20 0.072% +CORE_PREF_L1_USED_LATENCY1600MORE 25 0.090% 25 0.090% + 27910 100.000% 27910 100.000% + 0.22 0.78 0.22 0.78 + +CORE_PREF_L1_USED_DISTANCE_1 0 0.000% 0 0.000% +CORE_PREF_L1_USED_DISTANCE_2 148 0.530% 148 0.530% +CORE_PREF_L1_USED_DISTANCE_4 3182 11.401% 3182 11.401% +CORE_PREF_L1_USED_DISTANCE_8 11302 40.494% 11302 40.494% +CORE_PREF_L1_USED_DISTANCE_16 11145 39.932% 11145 39.932% +CORE_PREF_L1_USED_DISTANCE_32 2131 7.635% 2131 7.635% +CORE_PREF_L1_USED_DISTANCE_MORE 2 0.007% 2 0.007% + 27910 100.000% 27910 100.000% + 3.43 0.81 3.43 0.81 + +CORE_PREF_L1_DEMAND_LATENCY300 132864 96.440% 132864 96.440% +CORE_PREF_L1_DEMAND_LATENCY400 850 0.617% 850 0.617% +CORE_PREF_L1_DEMAND_LATENCY500 1212 0.880% 1212 0.880% +CORE_PREF_L1_DEMAND_LATENCY600 718 0.521% 718 0.521% +CORE_PREF_L1_DEMAND_LATENCY700 367 0.266% 367 0.266% +CORE_PREF_L1_DEMAND_LATENCY800 177 0.128% 177 0.128% +CORE_PREF_L1_DEMAND_LATENCY900 174 0.126% 174 0.126% +CORE_PREF_L1_DEMAND_LATENCY1000 160 0.116% 160 0.116% +CORE_PREF_L1_DEMAND_LATENCY1000MORE 1246 0.904% 1246 0.904% + 137768 100.000% 137768 100.000% + 0.14 0.90 0.14 0.90 + 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9870 3.964% +NUM_DCACHE_MISSES_IN_WINDOW_11 8598 3.453% 8598 3.453% +NUM_DCACHE_MISSES_IN_WINDOW_12 7373 2.961% 7373 2.961% +NUM_DCACHE_MISSES_IN_WINDOW_13 6125 2.460% 6125 2.460% +NUM_DCACHE_MISSES_IN_WINDOW_14 5291 2.125% 5291 2.125% +NUM_DCACHE_MISSES_IN_WINDOW_15 3779 1.518% 3779 1.518% +NUM_DCACHE_MISSES_IN_WINDOW_16_OR_MORE 18806 7.553% 18806 7.553% + 248994 100.000% 248994 100.000% + 5.39 4.39 5.39 4.39 + +DCACHE_MLP_IN_WINDOW_1_0 154855 62.192% 154855 62.192% +DCACHE_MLP_IN_WINDOW_1_5 69659 27.976% 69659 27.976% +DCACHE_MLP_IN_WINDOW_2_0 18866 7.577% 18866 7.577% +DCACHE_MLP_IN_WINDOW_2_5 3074 1.235% 3074 1.235% +DCACHE_MLP_IN_WINDOW_3_0 1750 0.703% 1750 0.703% +DCACHE_MLP_IN_WINDOW_3_5 274 0.110% 274 0.110% +DCACHE_MLP_IN_WINDOW_4_0 200 0.080% 200 0.080% +DCACHE_MLP_IN_WINDOW_4_5 96 0.039% 96 0.039% +DCACHE_MLP_IN_WINDOW_5_0 108 0.043% 108 0.043% +DCACHE_MLP_IN_WINDOW_5_5 17 0.007% 17 0.007% +DCACHE_MLP_IN_WINDOW_6_0 21 0.008% 21 0.008% +DCACHE_MLP_IN_WINDOW_6_5 20 0.008% 20 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b/labs/LAB5/runs/perlbench_s_base-sms0/power.stat.0.out new file mode 100644 index 00000000..22ada5f4 --- /dev/null +++ b/labs/LAB5/runs/perlbench_s_base-sms0/power.stat.0.out @@ -0,0 +1,184 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 77430070 Instructions: 100000004 IPC: 1.29149 + +POWER_STATS_BEGIN 0 0 + +POWER_TIME 24196896875000 24196896875000 + +POWER_CYCLE 77430070 77430070 + +POWER_ITLB_ACCESS 34122600 34122600 + +POWER_DTLB_ACCESS 15523805 15523805 + +POWER_ICACHE_ACCESS 34122600 34122600 + +POWER_ICACHE_MISS 925010 925010 + +POWER_BTB_READ 34122600 34122600 + +POWER_BTB_WRITE 940629 940629 + +POWER_ROB_READ 120980581 120980581 + +POWER_ROB_WRITE 120980581 120980581 + +POWER_RENAME_READ 241961162 241961162 + +POWER_RENAME_WRITE 120980581 120980581 + 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21171983 + +POWER_DRAM_PRECHARGE 81693 81693 + +POWER_DRAM_ACTIVATE 106224 106224 + +POWER_DRAM_READ 221644 221644 + +POWER_DRAM_WRITE 47794 47794 + +POWER_STATS_END 0 0 + +ENERGY 0.000000 0.000000 + +ENERGY_CORE 0.000000 0.000000 + +ENERGY_UNCORE 0.000000 0.000000 + +ENERGY_MEMORY 0.000000 0.000000 + +ENERGY_OTHER 0.000000 0.000000 + +ENERGY_CORE_STATIC 0.000000 0.000000 + +ENERGY_CORE_DYNAMIC 0.000000 0.000000 + +ENERGY_UNCORE_STATIC 0.000000 0.000000 + +ENERGY_UNCORE_DYNAMIC 0.000000 0.000000 + +ENERGY_MEMORY_STATIC 0.000000 0.000000 + +ENERGY_MEMORY_DYNAMIC 0.000000 0.000000 + +ENERGY_OTHER_STATIC 0.000000 0.000000 + +ENERGY_OTHER_DYNAMIC 0.000000 0.000000 + +TIME 0.000000 0.000000 + +ENERGY_STATS_END 0 0 + + + diff --git a/labs/LAB5/runs/perlbench_s_base-sms0/pref.stat.0.out b/labs/LAB5/runs/perlbench_s_base-sms0/pref.stat.0.out new file mode 100644 index 00000000..9cba0b31 --- /dev/null +++ b/labs/LAB5/runs/perlbench_s_base-sms0/pref.stat.0.out @@ -0,0 +1,208 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 77430070 Instructions: 100000004 IPC: 1.29149 + +PREF_DL0REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UMLC_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UL1REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_DL0REQ_QUEUE_FULL 0 0 + +PREF_UMLC_REQ_QUEUE_FULL 0 0 + +PREF_UL1REQ_QUEUE_FULL 0 0 + +PREF_DC_HIT_NOSEND 0 0 + +PREF_WBQDC_HIT_NOSEND 0 0 + +PREF_MLCQ_STALL 0 0 + +PREF_L1Q_STALL 0 0 + +PREF_UMLC_REQ_SEND_QUEUE_STALL 0 0 + +PREF_UL1REQ_SEND_QUEUE_STALL 47162 47162 + +PREF_UMLC_REQ_QUEUE_SENTREQ 0 0 + +PREF_UL1REQ_QUEUE_SENTREQ 114443 114443 + +PREF_NEWREQ_MATCHED 4690 4690 + +PREF_UMLC_REQ_QUEUE_MATCHED_REQ 0 0 + +PREF_UL1REQ_QUEUE_MATCHED_REQ 6964 6964 + +PREF_DL0REQ_QUEUE_MATCHED_REQ 0 0 + +L1_PREF_HIT 142771 142771 + +L1_PREF_UNIQUE_HIT 28448 28448 + +L1_PREF_LATE 2823 2823 + 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-nan% 0 -nan% +PREF_REPL_LRU 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_REPL_MOVEDOWN 0 -nan% 0 -nan% +PREF_REPL_MOVEUP 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_COV_1 0 -nan% 0 -nan% +PREF_COV_2 0 -nan% 0 -nan% +PREF_COV_3 0 -nan% 0 -nan% +PREF_COV_4 0 -nan% 0 -nan% +PREF_COV_5 0 -nan% 0 -nan% +PREF_COV_6 0 -nan% 0 -nan% +PREF_COV_7 0 -nan% 0 -nan% +PREF_COV_8 0 -nan% 0 -nan% +PREF_COV_9 0 -nan% 0 -nan% +PREF_COV_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_POL_1 0 0.000% 0 0.000% +PREF_POL_2 0 0.000% 0 0.000% +PREF_POL_3 0 0.000% 0 0.000% +PREF_POL_4 0 0.000% 0 0.000% +PREF_POL_5 0 0.000% 0 0.000% +PREF_POL_6 0 0.000% 0 0.000% +PREF_POL_7 0 0.000% 0 0.000% +PREF_POL_8 0 0.000% 0 0.000% +PREF_POL_9 0 0.000% 0 0.000% +PREF_POL_10 25 100.000% 25 100.000% + 25 100.000% 25 100.000% + 9.00 9.19 9.00 9.19 + +PREF_ACC_1 0 0.000% 0 0.000% +PREF_ACC_2 0 0.000% 0 0.000% +PREF_ACC_3 0 0.000% 0 0.000% +PREF_ACC_4 1 4.000% 1 4.000% +PREF_ACC_5 3 12.000% 3 12.000% +PREF_ACC_6 9 36.000% 9 36.000% +PREF_ACC_7 12 48.000% 12 48.000% +PREF_ACC_8 0 0.000% 0 0.000% +PREF_ACC_9 0 0.000% 0 0.000% +PREF_ACC_10 0 0.000% 0 0.000% + 25 100.000% 25 100.000% + 5.28 0.84 5.28 0.84 + +PREF_TIMELY_1 0 0.000% 0 0.000% +PREF_TIMELY_2 0 0.000% 0 0.000% +PREF_TIMELY_3 0 0.000% 0 0.000% +PREF_TIMELY_4 0 0.000% 0 0.000% +PREF_TIMELY_5 0 0.000% 0 0.000% +PREF_TIMELY_6 0 0.000% 0 0.000% +PREF_TIMELY_7 0 0.000% 0 0.000% +PREF_TIMELY_8 0 0.000% 0 0.000% +PREF_TIMELY_9 10 40.000% 10 40.000% +PREF_TIMELY_10 15 60.000% 15 60.000% + 25 100.000% 25 100.000% + 8.60 6.82 8.60 6.82 + +PREF_UNUSED_EVICT 39864 39864 + +PREF_REGION_SENT 0 0 + +PREF_REGION_USEFUL 0 0 + +PREF_REGION_EVICT 0 0 + +PREF_PFPOL 0 0 + +PREF_PHASE_NEWPHASE_DET 0 0 + +PREF_PHASE_NEWPHASE_NOTVALID 0 0 + +PREF_PHASE_SENTPREF 0 0 + +PREF_PHASE_OVERWRITE_PAGE 0 0 + +PREF_UPDATE_COUNT 25 25 + +PREF_ACC1_HT_HP 0 0.000% 0 0.000% +PREF_ACC1_HT_LP 0 0.000% 0 0.000% +PREF_ACC1_LT_HP 0 0.000% 0 0.000% +PREF_ACC1_LT_LP 0 0.000% 0 0.000% +PREF_ACC2_HT_HP 0 0.000% 0 0.000% +PREF_ACC2_HT_LP 0 0.000% 0 0.000% +PREF_ACC2_LT_HP 0 0.000% 0 0.000% +PREF_ACC2_LT_LP 13 52.000% 13 52.000% +PREF_ACC3_HT_HP 0 0.000% 0 0.000% +PREF_ACC3_HT_LP 0 0.000% 0 0.000% +PREF_ACC3_LT_HP 0 0.000% 0 0.000% +PREF_ACC3_LT_LP 0 0.000% 0 0.000% +PREF_ACC4_HT_HP 0 0.000% 0 0.000% +PREF_ACC4_HT_LP 0 0.000% 0 0.000% +PREF_ACC4_LT_HP 0 0.000% 0 0.000% +PREF_ACC4_LT_LP 12 48.000% 12 48.000% + 25 100.000% 25 100.000% + 10.84 8.68 10.84 8.68 + + + diff --git a/labs/LAB5/runs/perlbench_s_base-sms0/ramulator.stat.out b/labs/LAB5/runs/perlbench_s_base-sms0/ramulator.stat.out new file mode 100644 index 00000000..114953c9 --- /dev/null +++ b/labs/LAB5/runs/perlbench_s_base-sms0/ramulator.stat.out @@ -0,0 +1,150 @@ + ramulator.active_cycles_0 15842756 # Total active cycles for level _0 + ramulator.busy_cycles_0 15842756 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0 + ramulator.serving_requests_0 25029554 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.average_serving_requests_0 0.862009 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.active_cycles_0_0 15842756 # Total active cycles for level _0_0 + ramulator.busy_cycles_0_0 16510136 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0 + ramulator.serving_requests_0_0 25029554 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.average_serving_requests_0_0 0.862009 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.active_cycles_0_0_0 5527222 # Total active cycles for level _0_0_0 + ramulator.busy_cycles_0_0_0 5527222 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0 + ramulator.serving_requests_0_0_0 6391318 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 +ramulator.average_serving_requests_0_0_0 0.220115 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 + ramulator.active_cycles_0_0_0_0 1584948 # Total active cycles for level _0_0_0_0 + ramulator.busy_cycles_0_0_0_0 1584948 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_0 + ramulator.serving_requests_0_0_0_0 1674771 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 +ramulator.average_serving_requests_0_0_0_0 0.057679 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 + ramulator.active_cycles_0_0_0_1 1934400 # Total active cycles for level _0_0_0_1 + ramulator.busy_cycles_0_0_0_1 1934400 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_1 + ramulator.serving_requests_0_0_0_1 2017389 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 +ramulator.average_serving_requests_0_0_0_1 0.069478 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 + ramulator.active_cycles_0_0_0_2 1458433 # Total active cycles for level _0_0_0_2 + ramulator.busy_cycles_0_0_0_2 1458433 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_2 + ramulator.serving_requests_0_0_0_2 1538346 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 +ramulator.average_serving_requests_0_0_0_2 0.052980 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 + ramulator.active_cycles_0_0_0_3 1095055 # Total active cycles for level _0_0_0_3 + ramulator.busy_cycles_0_0_0_3 1095055 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_3 + ramulator.serving_requests_0_0_0_3 1160812 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 +ramulator.average_serving_requests_0_0_0_3 0.039978 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 + ramulator.active_cycles_0_0_1 6166596 # Total active cycles for level _0_0_1 + ramulator.busy_cycles_0_0_1 6166596 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1 + ramulator.serving_requests_0_0_1 7272521 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 +ramulator.average_serving_requests_0_0_1 0.250463 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 + ramulator.active_cycles_0_0_1_0 2265076 # Total active cycles for level _0_0_1_0 + ramulator.busy_cycles_0_0_1_0 2265076 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_0 + ramulator.serving_requests_0_0_1_0 2336129 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 +ramulator.average_serving_requests_0_0_1_0 0.080456 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 + ramulator.active_cycles_0_0_1_1 1612996 # Total active cycles for level _0_0_1_1 + ramulator.busy_cycles_0_0_1_1 1612996 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_1 + ramulator.serving_requests_0_0_1_1 1708075 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 +ramulator.average_serving_requests_0_0_1_1 0.058826 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 + ramulator.active_cycles_0_0_1_2 1583134 # Total active cycles for level _0_0_1_2 + ramulator.busy_cycles_0_0_1_2 1583134 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_2 + ramulator.serving_requests_0_0_1_2 1649974 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 +ramulator.average_serving_requests_0_0_1_2 0.056825 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 + ramulator.active_cycles_0_0_1_3 1496357 # Total active cycles for level _0_0_1_3 + ramulator.busy_cycles_0_0_1_3 1496357 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_3 + ramulator.serving_requests_0_0_1_3 1577599 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 +ramulator.average_serving_requests_0_0_1_3 0.054332 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 + ramulator.active_cycles_0_0_2 5123212 # Total active cycles for level _0_0_2 + ramulator.busy_cycles_0_0_2 5123212 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2 + ramulator.serving_requests_0_0_2 5952498 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 +ramulator.average_serving_requests_0_0_2 0.205002 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 + ramulator.active_cycles_0_0_2_0 1283790 # Total active cycles for level _0_0_2_0 + ramulator.busy_cycles_0_0_2_0 1283790 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_0 + ramulator.serving_requests_0_0_2_0 1372314 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 +ramulator.average_serving_requests_0_0_2_0 0.047262 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 + ramulator.active_cycles_0_0_2_1 1904315 # Total active cycles for level _0_0_2_1 + ramulator.busy_cycles_0_0_2_1 1904315 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_1 + ramulator.serving_requests_0_0_2_1 1973475 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 +ramulator.average_serving_requests_0_0_2_1 0.067966 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 + ramulator.active_cycles_0_0_2_2 1198017 # Total active cycles for level _0_0_2_2 + ramulator.busy_cycles_0_0_2_2 1198017 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_2 + ramulator.serving_requests_0_0_2_2 1264760 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 +ramulator.average_serving_requests_0_0_2_2 0.043558 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 + ramulator.active_cycles_0_0_2_3 1266385 # Total active cycles for level _0_0_2_3 + ramulator.busy_cycles_0_0_2_3 1266385 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_3 + ramulator.serving_requests_0_0_2_3 1341949 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 +ramulator.average_serving_requests_0_0_2_3 0.046216 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 + ramulator.active_cycles_0_0_3 4669022 # Total active cycles for level _0_0_3 + ramulator.busy_cycles_0_0_3 4669022 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3 + ramulator.serving_requests_0_0_3 5401650 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 +ramulator.average_serving_requests_0_0_3 0.186031 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 + ramulator.active_cycles_0_0_3_0 1152893 # Total active cycles for level _0_0_3_0 + ramulator.busy_cycles_0_0_3_0 1152893 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_0 + ramulator.serving_requests_0_0_3_0 1240610 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 +ramulator.average_serving_requests_0_0_3_0 0.042726 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 + ramulator.active_cycles_0_0_3_1 959639 # Total active cycles for level _0_0_3_1 + ramulator.busy_cycles_0_0_3_1 959639 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_1 + ramulator.serving_requests_0_0_3_1 1043461 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 +ramulator.average_serving_requests_0_0_3_1 0.035936 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 + ramulator.active_cycles_0_0_3_2 1869952 # Total active cycles for level _0_0_3_2 + ramulator.busy_cycles_0_0_3_2 1869952 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_2 + ramulator.serving_requests_0_0_3_2 1953467 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 +ramulator.average_serving_requests_0_0_3_2 0.067277 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 + ramulator.active_cycles_0_0_3_3 1087887 # Total active cycles for level _0_0_3_3 + ramulator.busy_cycles_0_0_3_3 1087887 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_3 + ramulator.serving_requests_0_0_3_3 1164112 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 +ramulator.average_serving_requests_0_0_3_3 0.040092 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 + ramulator.read_transaction_bytes_0 14185216 # The total byte of read transaction per channel + ramulator.write_transaction_bytes_0 3058880 # The total byte of write transaction per channel + ramulator.row_hits_channel_0_core 163224 # Number of row hits per channel per core + ramulator.row_misses_channel_0_core 28254 # Number of row misses per channel per core + ramulator.row_conflicts_channel_0_core 77961 # Number of row conflicts per channel per core + ramulator.read_row_hits_channel_0_core 152683 # Number of row hits for read requests per channel per core + [0] 152683.0 # +ramulator.read_row_misses_channel_0_core 20421 # Number of row misses for read requests per channel per core + [0] 20421.0 # +ramulator.read_row_conflicts_channel_0_core 48540 # Number of row conflicts for read requests per channel per core + [0] 48540.0 # + ramulator.write_row_hits_channel_0_core 10541 # Number of row hits for write requests per channel per core + [0] 10541.0 # +ramulator.write_row_misses_channel_0_core 7833 # Number of row misses for write requests per channel per core + [0] 7833.0 # +ramulator.write_row_conflicts_channel_0_core 29421 # Number of row conflicts for write requests per channel per core + [0] 29421.0 # + ramulator.useless_activates_0_core 14 # Number of useless activations. E.g, ACT -> PRE w/o RD or WR + ramulator.read_latency_avg_0 49.209856 # The average memory latency cycles (in memory time domain) per request for all read requests in this channel + ramulator.read_latency_sum_0 10917551 # The memory latency cycles (in memory time domain) sum for all read requests in this channel + ramulator.req_queue_length_avg_0 14.230174 # Average of read and write queue length per memory cycle per channel. + ramulator.req_queue_length_sum_0 413191428 # Sum of read and write queue length per memory cycle per channel. + ramulator.read_req_queue_length_avg_0 0.337602 # Read queue length average per memory cycle per channel. + ramulator.read_req_queue_length_sum_0 9802716 # Read queue length sum per memory cycle per channel. + ramulator.write_req_queue_length_avg_0 13.892572 # Write queue length average per memory cycle per channel. + ramulator.write_req_queue_length_sum_0 403388712 # Write queue length sum per memory cycle per channel. + ramulator.record_read_hits 0.0 # record read hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_misses 0.0 # record_read_miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_conflicts 0.0 # record read conflict count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_hits 0.0 # record write hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_misses 0.0 # record write miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_conflicts 0.0 # record write conflict for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.dram_capacity 8589934592 # Number of bytes in simulated DRAM + ramulator.dram_cycles 29036287 # Number of DRAM cycles simulated + ramulator.incoming_requests 269658 # Number of incoming requests to DRAM + ramulator.read_requests 221857 # Number of incoming read requests to DRAM per core + [0] 221857.0 # + ramulator.write_requests 47801 # Number of incoming write requests to DRAM per core + [0] 47801.0 # + ramulator.ramulator_active_cycles 15847412 # The total number of cycles that the DRAM part is active (serving R/W) + ramulator.incoming_requests_per_channel 269658.0 # Number of incoming requests to each DRAM channel + [0] 269658.0 # +ramulator.incoming_read_reqs_per_channel 221857.0 # Number of incoming read requests to each DRAM channel + [0] 221857.0 # + ramulator.physical_page_replacement 0 # The number of times that physical page replacement happens. + ramulator.maximum_bandwidth 19200000000 # The theoretical maximum bandwidth (Bps) + ramulator.in_queue_req_num_sum 413191428 # Sum of read/write queue length + ramulator.in_queue_read_req_num_sum 9802716 # Sum of read queue length + ramulator.in_queue_write_req_num_sum 403388712 # Sum of write queue length + ramulator.in_queue_req_num_avg 14.230174 # Average of read/write queue length per memory cycle + ramulator.in_queue_read_req_num_avg 0.337602 # Average of read queue length per memory cycle + ramulator.in_queue_write_req_num_avg 13.892572 # Average of write queue length per memory cycle + ramulator.record_read_requests 0.0 # record read requests for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_requests 0.0 # record write requests for this core when it reaches request limit or to the end + [0] 0.0 # diff --git a/labs/LAB5/runs/perlbench_s_base-sms0/run.err b/labs/LAB5/runs/perlbench_s_base-sms0/run.err new file mode 100644 index 00000000..e69de29b diff --git a/labs/LAB5/runs/perlbench_s_base-sms0/run.out b/labs/LAB5/runs/perlbench_s_base-sms0/run.out new file mode 100644 index 00000000..243a08b1 --- /dev/null +++ b/labs/LAB5/runs/perlbench_s_base-sms0/run.out @@ -0,0 +1,107 @@ +Scarab gitrev: 7ab9e17 +Scarab started at Sun Jun 11 08:08:38 2023 + +Initialized Ramulator. +** Heartbeat: 1% -- { 1000001 } -- 0.00 KIPS (333.33 KIPS) +** Heartbeat: 2% -- { 2000001 } -- 500.00 KIPS (400.00 KIPS) +** Heartbeat: 3% -- { 3000004 } -- 333.33 KIPS (375.00 KIPS) +** Heartbeat: 4% -- { 4000004 } -- 500.00 KIPS (400.00 KIPS) +** Heartbeat: 5% -- { 5000005 } -- 500.00 KIPS (416.67 KIPS) +** Heartbeat: 6% -- { 6000006 } -- 500.00 KIPS (428.57 KIPS) +** Heartbeat: 7% -- { 7000007 } -- 500.00 KIPS (437.50 KIPS) +** Heartbeat: 8% -- { 8000010 } -- 500.00 KIPS (444.44 KIPS) +** Heartbeat: 9% -- { 9000013 } -- 500.00 KIPS (450.00 KIPS) +** Heartbeat: 10% -- { 10000015 } -- 333.33 KIPS (434.78 KIPS) +** Heartbeat: 11% -- { 11000016 } -- 500.00 KIPS (440.00 KIPS) +** Heartbeat: 12% -- { 12000019 } -- 500.00 KIPS (444.45 KIPS) +** Heartbeat: 13% -- { 13000021 } -- 500.00 KIPS (448.28 KIPS) +** Heartbeat: 14% -- { 14000021 } -- 500.00 KIPS (451.61 KIPS) +** Heartbeat: 15% -- { 15000021 } -- 333.33 KIPS (441.18 KIPS) +** Heartbeat: 16% -- { 16000022 } -- 500.00 KIPS (444.45 KIPS) +** Heartbeat: 17% -- { 17000025 } -- 500.00 KIPS (447.37 KIPS) +** Heartbeat: 18% -- { 18000026 } -- 500.00 KIPS (450.00 KIPS) +** Heartbeat: 19% -- { 19000029 } -- 1000.00 KIPS (463.42 KIPS) +** Heartbeat: 20% -- { 20000030 } -- 500.00 KIPS (465.12 KIPS) +** Heartbeat: 21% -- { 21000033 } -- 333.33 KIPS (456.52 KIPS) +** Heartbeat: 22% -- { 22000034 } -- 500.00 KIPS (458.33 KIPS) +** Heartbeat: 23% -- { 23000036 } -- 500.00 KIPS (460.00 KIPS) +** Heartbeat: 24% -- { 24000040 } -- 1000.00 KIPS (470.59 KIPS) +** Heartbeat: 25% -- { 25000041 } -- 500.00 KIPS (471.70 KIPS) +** Heartbeat: 26% -- { 26000045 } -- 333.33 KIPS (464.29 KIPS) +** Heartbeat: 27% -- { 27000047 } -- 500.00 KIPS (465.52 KIPS) +** Heartbeat: 28% -- { 28000047 } -- 500.00 KIPS (466.67 KIPS) +** Heartbeat: 29% -- { 29000048 } -- 500.00 KIPS (467.74 KIPS) +** Heartbeat: 30% -- { 30000049 } -- 500.00 KIPS (468.75 KIPS) +** Heartbeat: 31% -- { 31000052 } -- 500.00 KIPS (469.70 KIPS) +** Heartbeat: 32% -- { 32000053 } -- 333.33 KIPS (463.77 KIPS) +** Heartbeat: 33% -- { 33000055 } -- 500.00 KIPS (464.79 KIPS) +** Heartbeat: 34% -- { 34000057 } -- 500.00 KIPS (465.75 KIPS) +** Heartbeat: 35% -- { 35000061 } -- 500.00 KIPS (466.67 KIPS) +** Heartbeat: 36% -- { 36000063 } -- 500.00 KIPS (467.53 KIPS) +** Heartbeat: 37% -- { 37000065 } -- 333.33 KIPS (462.50 KIPS) +** Heartbeat: 38% -- { 38000067 } -- 500.00 KIPS (463.42 KIPS) +** Heartbeat: 39% -- { 39000071 } -- 500.00 KIPS (464.29 KIPS) +** Heartbeat: 40% -- { 40000073 } -- 500.00 KIPS (465.12 KIPS) +** Heartbeat: 41% -- { 41000074 } -- 500.00 KIPS (465.91 KIPS) +** Heartbeat: 42% -- { 42000075 } -- 500.00 KIPS (466.67 KIPS) +** Heartbeat: 43% -- { 43000079 } -- 500.00 KIPS (467.39 KIPS) +** Heartbeat: 44% -- { 44000083 } -- 500.00 KIPS (468.09 KIPS) +** Heartbeat: 45% -- { 45000084 } -- 500.00 KIPS (468.75 KIPS) +** Heartbeat: 46% -- { 46000084 } -- 500.00 KIPS (469.39 KIPS) +** Heartbeat: 47% -- { 47000089 } -- 500.00 KIPS (470.00 KIPS) +** Heartbeat: 48% -- { 48000091 } -- 333.33 KIPS (466.02 KIPS) +** Heartbeat: 49% -- { 49000092 } -- 500.00 KIPS (466.67 KIPS) +** Heartbeat: 50% -- { 50000094 } -- 500.00 KIPS (467.29 KIPS) +** Heartbeat: 51% -- { 51000097 } -- 500.00 KIPS (467.89 KIPS) +** Heartbeat: 52% -- { 52000097 } -- 500.00 KIPS (468.47 KIPS) +** Heartbeat: 53% -- { 53000101 } -- 500.00 KIPS (469.03 KIPS) +** Heartbeat: 54% -- { 54000104 } -- 500.00 KIPS (469.57 KIPS) +** Heartbeat: 55% -- { 55000106 } -- 500.00 KIPS (470.09 KIPS) +** Heartbeat: 56% -- { 56000107 } -- 500.00 KIPS (470.59 KIPS) +** Heartbeat: 57% -- { 57000109 } -- 500.00 KIPS (471.08 KIPS) +** Heartbeat: 58% -- { 58000112 } -- 500.00 KIPS (471.55 KIPS) +** Heartbeat: 59% -- { 59000112 } -- 500.00 KIPS (472.00 KIPS) +** Heartbeat: 60% -- { 60000112 } -- 500.00 KIPS (472.44 KIPS) +** Heartbeat: 61% -- { 61000114 } -- 500.00 KIPS (472.87 KIPS) +** Heartbeat: 62% -- { 62000114 } -- 333.33 KIPS (469.70 KIPS) +** Heartbeat: 63% -- { 63000116 } -- 500.00 KIPS (470.15 KIPS) +** Heartbeat: 64% -- { 64000120 } -- 500.00 KIPS (470.59 KIPS) +** Heartbeat: 65% -- { 65000123 } -- 500.00 KIPS (471.02 KIPS) +** Heartbeat: 66% -- { 66000128 } -- 500.00 KIPS (471.43 KIPS) +** Heartbeat: 67% -- { 67000129 } -- 500.00 KIPS (471.83 KIPS) +** Heartbeat: 68% -- { 68000129 } -- 333.33 KIPS (468.97 KIPS) +** Heartbeat: 69% -- { 69000130 } -- 500.00 KIPS (469.39 KIPS) +** Heartbeat: 70% -- { 70000134 } -- 500.00 KIPS (469.80 KIPS) +** Heartbeat: 71% -- { 71000134 } -- 500.00 KIPS (470.20 KIPS) +** Heartbeat: 72% -- { 72000134 } -- 500.00 KIPS (470.59 KIPS) +** Heartbeat: 73% -- { 73000136 } -- 333.33 KIPS (467.95 KIPS) +** Heartbeat: 74% -- { 74000136 } -- 500.00 KIPS (468.36 KIPS) +** Heartbeat: 75% -- { 75000136 } -- 500.00 KIPS (468.75 KIPS) +** Heartbeat: 76% -- { 76000137 } -- 500.00 KIPS (469.14 KIPS) +** Heartbeat: 77% -- { 77000140 } -- 333.33 KIPS (466.67 KIPS) +** Heartbeat: 78% -- { 78000143 } -- 500.00 KIPS (467.07 KIPS) +** Heartbeat: 79% -- { 79000143 } -- 500.00 KIPS (467.46 KIPS) +** Heartbeat: 80% -- { 80000144 } -- 500.00 KIPS (467.84 KIPS) +** Heartbeat: 81% -- { 81000148 } -- 333.33 KIPS (465.52 KIPS) +** Heartbeat: 82% -- { 82000151 } -- 500.00 KIPS (465.91 KIPS) +** Heartbeat: 83% -- { 83000154 } -- 500.00 KIPS (466.29 KIPS) +** Heartbeat: 84% -- { 84000156 } -- 500.00 KIPS (466.67 KIPS) +** Heartbeat: 85% -- { 85000159 } -- 500.00 KIPS (467.03 KIPS) +** Heartbeat: 86% -- { 86000161 } -- 500.00 KIPS (467.39 KIPS) +** Heartbeat: 87% -- { 87000161 } -- 500.00 KIPS (467.74 KIPS) +** Heartbeat: 88% -- { 88000164 } -- 500.00 KIPS (468.09 KIPS) +** Heartbeat: 89% -- { 89000167 } -- 500.00 KIPS (468.42 KIPS) +** Heartbeat: 90% -- { 90000168 } -- 500.00 KIPS (468.75 KIPS) +** Heartbeat: 91% -- { 91000170 } -- 500.00 KIPS (469.07 KIPS) +** Heartbeat: 92% -- { 92000170 } -- 1000.00 KIPS (471.80 KIPS) +** Heartbeat: 93% -- { 93000172 } -- 333.33 KIPS (469.70 KIPS) +** Heartbeat: 94% -- { 94000173 } -- 500.00 KIPS (470.00 KIPS) +** Heartbeat: 95% -- { 95000173 } -- 500.00 KIPS (470.30 KIPS) +** Heartbeat: 96% -- { 96000173 } -- 500.00 KIPS (470.59 KIPS) +** Heartbeat: 97% -- { 97000173 } -- 500.00 KIPS (470.87 KIPS) +** Heartbeat: 98% -- { 98000177 } -- 500.00 KIPS (471.15 KIPS) +** Heartbeat: 99% -- { 99000181 } -- 500.00 KIPS (471.43 KIPS) +** Core 0 Finished: insts:100000004 cycles:77430070 time:24196896875000 -- 1.29 IPC (1.29 IPC) -- N/A KIPS (471.70 KIPS) +done +Scarab finished at Sun Jun 11 08:12:10 2023 + diff --git a/labs/LAB5/runs/perlbench_s_base-sms0/stream.stat.0.out b/labs/LAB5/runs/perlbench_s_base-sms0/stream.stat.0.out new file mode 100644 index 00000000..e7fcc60b --- /dev/null +++ b/labs/LAB5/runs/perlbench_s_base-sms0/stream.stat.0.out @@ -0,0 +1,188 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 77430070 Instructions: 100000004 IPC: 1.29149 + +DCACHE_PREF_HIT 0 0 + +IFETCH_WB_FIRST_SCHEDULE 0 -nan% 0 -nan% +PREFETCH_LAST_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_PREF_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_LOW_OP_SCHEDULE 0 -nan% 0 -nan% +DEMAND_LAST_SCHEDULE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +SEND_MISS_REQ_QUEUE 221857 221857 + +L1_DATA_EVICT 205542 205542 + +STREAM_BUFFER_REQ 0 0 + +PREF_SEND_TO_MEM_REQ 0 -nan% 0 -nan% +PREF_SEND_TO_MEM_REQ_FAIL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +HIT_TRAIN_STREAM 64025 35.186% 64025 35.186% +MISS_TRAIN_STREAM 117939 64.814% 117939 64.814% + 181964 100.000% 181964 100.000% + 0.65 0.59 0.65 0.59 + +STREAM_TRAIN_CREATE 54585 54585 + +MEM_REQ_MISS_HWP_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_SW_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_IFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DSTORE_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DPRF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_WB_Q 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_BY_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_WB 0 -nan% 0 -nan% +PREF_HIT_BY_PREF 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_WB 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_L1_FILL 0 -nan% 0 -nan% +DEMAND_L1_FILL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TOUCH_L1_REPLACE 0 0.000% 0 0.000% +NO_TOUCH_L1_REPLACE 205542 100.000% 205542 100.000% + 205542 100.000% 205542 100.000% + 1.00 1.00 1.00 1.00 + +PREF_REQ_QUE_FULL 0 0 + +STREAM_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +L2HIT_STREAM_PREF_REQ_QUE_FULL 0 0 + +L2HIT_HIT_TRAIN_STREAM 0 -nan% 0 -nan% +L2HIT_MISS_TRAIN_STREAM 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_TRAIN_CREATE 0 0 + +L2HIT_STREAM_BUFFER_REQ 0 0 + +L2HIT_STREAM_PREF_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_STREAM_PREF_DCACHE_INSERT 0 -nan% 0 -nan% +L2HIT_STREAM_L2_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_DCACHE_PORT_FULL 0 0 + +L2HIT_STREAM_PREF_L1_PORT_FULL 0 0 + +L2HIT_TRAIN_HIT_DEMAND 0 -nan% 0 -nan% +L2HIT_TRAIN_MISS_REQ 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_TRAIN_FILTER_MISS 0 -nan% 0 -nan% +L2HIT_TRAIN_FILTER_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_PREF_REQ_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_PREF_REQ_DCACHE_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_L2SEND_Q_FULL 0 -nan% 0 -nan% +L2HIT_L2SEND_Q_ENTER 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_MEM_REQ 0 0 + +REMOVE_REDUNDANT_STREAM_STAT 0 0 + +REPLACE_OLD_STREAM 54569 54569 + +REQ_SEND_QUEUE_STALL 0 0 + +STREAM_ENTER_RA 0 0 + +CORE_STREAM_LENGTH_0 3144 28.558% 3144 28.558% +CORE_STREAM_LENGTH_10 4414 40.094% 4414 40.094% +CORE_STREAM_LENGTH_20 2030 18.439% 2030 18.439% +CORE_STREAM_LENGTH_30 615 5.586% 615 5.586% +CORE_STREAM_LENGTH_40 327 2.970% 327 2.970% +CORE_STREAM_LENGTH_50 147 1.335% 147 1.335% +CORE_STREAM_LENGTH_60 100 0.908% 100 0.908% +CORE_STREAM_LENGTH_70 56 0.509% 56 0.509% +CORE_STREAM_LENGTH_80 32 0.291% 32 0.291% +CORE_STREAM_LENGTH_90 26 0.236% 26 0.236% +CORE_STREAM_LENGTH_100_P 118 1.072% 118 1.072% + 11009 100.000% 11009 100.000% + 1.36 1.45 1.36 1.45 + +CORE_CUM_STREAM_LENGTH_0 20982 10.040% 20982 10.040% +CORE_CUM_STREAM_LENGTH_10 62552 29.932% 62552 29.932% +CORE_CUM_STREAM_LENGTH_20 47529 22.743% 47529 22.743% +CORE_CUM_STREAM_LENGTH_30 20888 9.995% 20888 9.995% +CORE_CUM_STREAM_LENGTH_40 14491 6.934% 14491 6.934% +CORE_CUM_STREAM_LENGTH_50 7986 3.821% 7986 3.821% +CORE_CUM_STREAM_LENGTH_60 6445 3.084% 6445 3.084% +CORE_CUM_STREAM_LENGTH_70 4128 1.975% 4128 1.975% +CORE_CUM_STREAM_LENGTH_80 2704 1.294% 2704 1.294% +CORE_CUM_STREAM_LENGTH_90 2439 1.167% 2439 1.167% +CORE_CUM_STREAM_LENGTH_100_P 18835 9.013% 18835 9.013% + 208979 100.000% 208979 100.000% + 2.96 2.87 2.96 2.87 + +CORE_STREAM_TRAIN_HITS_0 7597 69.007% 7597 69.007% +CORE_STREAM_TRAIN_HITS_10 2738 24.871% 2738 24.871% +CORE_STREAM_TRAIN_HITS_20 381 3.461% 381 3.461% +CORE_STREAM_TRAIN_HITS_30 138 1.254% 138 1.254% +CORE_STREAM_TRAIN_HITS_40 53 0.481% 53 0.481% +CORE_STREAM_TRAIN_HITS_50 25 0.227% 25 0.227% +CORE_STREAM_TRAIN_HITS_60 4 0.036% 4 0.036% +CORE_STREAM_TRAIN_HITS_70 8 0.073% 8 0.073% +CORE_STREAM_TRAIN_HITS_80 12 0.109% 12 0.109% +CORE_STREAM_TRAIN_HITS_90 4 0.036% 4 0.036% +CORE_STREAM_TRAIN_HITS_100_P 49 0.445% 49 0.445% + 11009 100.000% 11009 100.000% + 0.45 0.94 0.45 0.94 + +CORE_CUM_STREAM_TRAIN_HITS_0 48477 44.861% 48477 44.861% +CORE_CUM_STREAM_TRAIN_HITS_10 33531 31.030% 33531 31.030% +CORE_CUM_STREAM_TRAIN_HITS_20 8942 8.275% 8942 8.275% +CORE_CUM_STREAM_TRAIN_HITS_30 4645 4.298% 4645 4.298% +CORE_CUM_STREAM_TRAIN_HITS_40 2323 2.150% 2323 2.150% +CORE_CUM_STREAM_TRAIN_HITS_50 1350 1.249% 1350 1.249% +CORE_CUM_STREAM_TRAIN_HITS_60 256 0.237% 256 0.237% +CORE_CUM_STREAM_TRAIN_HITS_70 596 0.552% 596 0.552% +CORE_CUM_STREAM_TRAIN_HITS_80 1021 0.945% 1021 0.945% +CORE_CUM_STREAM_TRAIN_HITS_90 375 0.347% 375 0.347% +CORE_CUM_STREAM_TRAIN_HITS_100_P 6545 6.057% 6545 6.057% + 108061 100.000% 108061 100.000% + 1.52 2.40 1.52 2.40 + +CORE_STREAM_TRAIN_CREATE 54585 54585 + + + diff --git a/labs/LAB5/runs/perlbench_s_base-sms1/PARAMS.in b/labs/LAB5/runs/perlbench_s_base-sms1/PARAMS.in new file mode 100644 index 00000000..2593c2b8 --- /dev/null +++ b/labs/LAB5/runs/perlbench_s_base-sms1/PARAMS.in @@ -0,0 +1,226 @@ +# File : PARAMS.kaby_lake +# Date : 03/06/19 +# Description : Kaby Lake Configuration +# +# Based on documentation found here: +# https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake + +## Simulation Parameters +--mode full +--model cmp +--sim_limit none + +## Core Parameters + +# Femptoseconds, 3.2GHz, used for energy estimates. +--chip_cycle_time 312500 + + +### Fetch Stage +--fetch_off_path_ops 1 +--fetch_across_cache_lines 1 + +# Will break the packet upon a taken branch. +--fetch_break_on_taken 1 + +# Number of bubble cycles to wait after taken branch. +--fetch_taken_bubble_cycles 0 + + +#### ICache +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 + +### Branch Predictor +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_mech tagescl + + +#### BTB + +# BTB model to use. +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 + +# Allow the BTB to be updated by off path ops. +--btb_off_path_writes 1 + + +#### CRS + +# Enable return stack +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 + +### iBP +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged + # iBTB Model. tc_tagless, tc_tagged, tc_hybrid. +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 + +### Decode Stage +--decode_cycles 5 + + +### Map Stage +--map_cycles 5 + + +### Issue Stage + +# Max number of instructions to be fetched, decoded, renamed, and issued per cycle. +--issue_width 6 + +--rs_fill_width 0 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 + + +### Exec Stage + +### DCache +--dcache_size 32768 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--dcache_assoc 4 +--dcache_line_size 64 + +### Reorder/Retire Stage + +# Max number of instructions to be retired per cycle. +--node_ret_width 6 +--node_table_size 224 + +# Do not keep stores in RSVs on cache misses; TODO: confirm what this knob does +--stores_do_not_block_window 1 + +# TODO: confirm what this knob does +--prefs_do_not_block_window 1 + + +## Uncore + +### Mid-level cache + +# Enable use of a midlevel cache between i/d and L1 +--mlc_present 0 + +### LLC +--l1_size 1048576 +--l1_banks 1 +--l1_cycles 18 +--l1_assoc 8 +--l1_line_size 64 +--l1_interleave_factor 64 + + +### Prefetcher +--pref_framework_on 1 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--pref_shared_queues 0 +--pref_train_on_pref_misses 0 +--pref_oracle_train 0 +--pref_ul1req_queue_overwrite_on_full 1 + +--stream_length 64 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 + +--pref_throttlefb_on=1 +--pref_acc_thresh_1=0.75 +--pref_acc_thresh_2=0.4 +--pref_acc_thresh_3=0.4 +--pref_timely_thresh=0.01 +--pref_polpf_thresh=0.005 +--pref_update_interval=8192 + +--mem_req_buffer_pref_watermark 4 +--promote_to_higher_priority_mem_req_type 1 + +### Memory +--addr_translation random + +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 + +--mem_req_buffer_entries 32 +--mem_l1_fill_queue_entries 32 +--va_page_size_bytes 4096 +--bus_width_in_bytes 8 + +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 + +## Other + + +### Debug +--debug_inst_start 0 +--debug_inst_stop -1 +--debug_cycle_start 0 +--debug_cycle_stop -1 + + +## Stats and Params +--dump_params 1 +--dump_stats 1 +--dump_trace 0 + +#################################### +--set_off_path_confirmed 1 + +--order_beyond_bus 1 + +--mem_ooo_stores 1 +--mem_obey_store_dep 1 diff --git a/labs/LAB5/runs/perlbench_s_base-sms1/PARAMS.out b/labs/LAB5/runs/perlbench_s_base-sms1/PARAMS.out new file mode 100644 index 00000000..9b2fc81d --- /dev/null +++ b/labs/LAB5/runs/perlbench_s_base-sms1/PARAMS.out @@ -0,0 +1,908 @@ +--mode full +--model cmp +--frontend memtrace +--inst_limit 100000000 +--sim_limit none +--dump_params 1 +--dump_stats 1 +--dump_trace 0 +--mlc_present 0 +--l1_size 1048576 +--l1_assoc 8 +--l1_line_size 64 +--l1_cycles 18 +--l1_banks 1 +--l1_interleave_factor 64 +--va_page_size_bytes 4096 +--addr_translation random +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 +--dcache_size 32768 +--dcache_assoc 4 +--dcache_line_size 64 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--mem_ooo_stores 1 +--mem_obey_store_dep 1 +--mem_req_buffer_entries 32 +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 +--promote_to_higher_priority_mem_req_type 1 +--mem_req_buffer_pref_watermark 4 +--mem_l1_fill_queue_entries 32 +--order_beyond_bus 1 +--set_off_path_confirmed 1 +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--bus_width_in_bytes 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 +--chip_cycle_time 312500 +--issue_width 6 +--rs_fill_width 0 +--node_table_size 224 +--node_ret_width 6 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 +--decode_cycles 5 +--map_cycles 5 +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--fetch_across_cache_lines 1 +--fetch_off_path_ops 0 +--fetch_break_on_taken 1 +--fetch_taken_bubble_cycles 0 +--stores_do_not_block_window 1 +--prefs_do_not_block_window 1 +--cbp_trace_r0 /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir/trace/drmemtrace.perlbench_s_base.mytest-m64.554262.9223.trace.gz +--memtrace_modules_log /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir/raw +--debug_cycle_start 0 +--debug_cycle_stop -1 +--debug_inst_start 0 +--debug_inst_stop -1 +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--bp_mech tagescl +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 +--btb_off_path_writes 1 +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_length 64 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 +--pref_framework_on 1 +--pref_shared_queues 0 +--pref_ul1req_queue_overwrite_on_full 1 +--pref_train_on_pref_misses 0 +--pref_oracle_train_on 0 +--pref_throttlefb_on 1 +--pref_acc_thresh_1 0.75 +--pref_acc_thresh_2 0.4 +--pref_acc_thresh_3 0.4 +--pref_update_interval 8192 +--pref_timely_thresh 0.01 +--pref_polpf_thresh 0.005 +--pref_sms_on 1 +1 1 1 1 1 1 1 + +--- Cut out everything below to use this file as PARAMS.in --- + +Parameter status at compile time and values supplied on the command line: + +SIM_MODE 0 full +SIM_MODEL 0 cmp +FRONTEND FE_PIN_EXEC_DRIVEN memtrace +INST_LIMIT NULL 100000000 +SIM_LIMIT "none" none +FORWARD_PROGRESS_LIMIT 100000000 +FORWARD_PROGRESS_INTERVAL 10000 +FAST_FORWARD 0 +FAST_FORWARD_UNTIL_ADDR 0 +FAST_FORWARD_TRACE_INS 0 +WARMUP 0 +HEARTBEAT_INTERVAL 1000000 +NUM_HEARTBEATS 0 +FILE_TAG "" +OUTPUT_DIR "." +STATUS_FILE NULL +BINDIR NULL +DUMP_PARAMS TRUE 1 +DUMP_STATS TRUE 1 +DUMP_TRACE FALSE 0 +CLEAR_STATS "never" +STATS_TO_TRACE NULL +STAT_TRACE_FILE "stats.trace" +STAT_TRACE_INTERVAL "i:100000" +PIPEVIEW FALSE +PIPEVIEW_FILE "pipeview" +MEMVIEW FALSE +MEMVIEW_FILE "memview.out" +MEMVIEW_START "never" +INST_HASH_TABLE_SIZE 500021 const +STDOUT_FILE NULL +STDERR_FILE NULL +PIN_EXEC_DRIVEN_FE_SOCKET "./pin_exec_driven_fe_socket.temp" +PRINT_PID FALSE +USE_UNSURE_FREE_LISTS FALSE +OPTIMIZER2_MAX_NUM_SLAVES 64 +OPTIMIZER2_PERFECT_MEMORYLESS FALSE +EXIT_COND 0 +ENABLE_SWPRF FALSE +MLC_PRESENT FALSE 0 +MLC_SIZE (512 * 1024) +MLC_ASSOC 4 +MLC_LINE_SIZE 64 +MLC_CYCLES 12 +PERFECT_MLC FALSE +MLC_READ_PORTS 1 +MLC_WRITE_PORTS 1 +MLC_BANKS 8 +MLC_INTERLEAVE_FACTOR 64 +MLC_CACHE_REPL_POLICY 0 +MLC_WRITE_THROUGH FALSE +PREFETCH_UPDATE_LRU_MLC TRUE +FORCE_L1_MISS FALSE +L1_SIZE (4 * 1024 * 1024) 1048576 +L1_ASSOC 8 8 +L1_LINE_SIZE 64 64 +L1_CYCLES 24 18 +PERFECT_L1 FALSE +PRIVATE_L1 FALSE +L1_READ_PORTS 1 +L1_WRITE_PORTS 1 +L1_BANKS 8 1 +L1_INTERLEAVE_FACTOR 64 64 +L1_CACHE_REPL_POLICY 0 +L1_WRITE_THROUGH FALSE +L1_IGNORE_WB FALSE +L1_USE_CORE_FREQ FALSE +MARK_L1_MISSES TRUE +PREFETCH_UPDATE_LRU_L1 TRUE +MEMORY_RANDOM_ADDR FALSE +VA_PAGE_SIZE_BYTES 4096 4096 +NUM_ADDR_NON_SIGN_EXTEND_BITS 48 +ADDR_TRANSLATION 0 random +CONSTANT_MEMORY_LATENCY FALSE +MEMORY_CYCLES 100 +STALL_MEM_REQS_ONLY FALSE +ICACHE_SIZE (64 * 1024) 32768 +ICACHE_ASSOC 4 4 +ICACHE_LINE_SIZE 64 64 +PERFECT_ICACHE FALSE +ICACHE_READ_PORTS 2 +ICACHE_WRITE_PORTS 1 +ICACHE_BANKS 8 +ICACHE_REPL 0 +DCACHE_SIZE (64 * 1024) 32768 +DCACHE_ASSOC 1 4 +DCACHE_LINE_SIZE 64 64 +DCACHE_CYCLES 2 +PERFECT_DCACHE FALSE +DCACHE_READ_PORTS 8 2 +DCACHE_WRITE_PORTS 1 1 +DCACHE_BANKS 1 1 +DCACHE_REPL 0 +DCACHE_REPL_PREF_THRESH 1 +MEM_OOO_STORES TRUE 1 +MEM_OBEY_STORE_DEP TRUE 1 +PREF_INSERT_LRU FALSE +PREF_INSERT_MIDDLE FALSE +PREF_INSERT_LOWQTR FALSE +PREF_INSERT_DYNACC FALSE +MEM_REQ_BUFFER_ENTRIES 32 32 +PRIVATE_MSHR_ON TRUE +MEM_PRIORITY_IFETCH 0 0 +MEM_PRIORITY_DFETCH 0 1 +MEM_PRIORITY_DSTORE 0 2 +MEM_PRIORITY_IPRF 9 3 +MEM_PRIORITY_DPRF 10 4 +MEM_PRIORITY_WB 0 5 +MEM_PRIORITY_WB_NODIRTY 0 5 +PROMOTE_TO_HIGHER_PRIORITY_MEM_REQ_TYPE FALSE 1 +MEM_REQ_BUFFER_PREF_WATERMARK 0 4 +MEM_REQ_BUFFER_WB_VALVE 2 +MEM_L1_FILL_QUEUE_ENTRIES 32 32 +MEM_BUS_OUT_QUEUE_PARTITION_ENABLE FALSE +MEM_MEM_QUEUE_PARTITION_ENABLE FALSE +MEM_BUS_OUT_QUEUE_AS_FIFO TRUE +OLDEST_FIRST_TO_MEM_QUEUE TRUE +ROUND_ROBIN_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE_TH 0 +L1_CYCLE_TIME 312500 +MLCQ_TO_L1Q_TRANSFER_LATENCY 1 +L1Q_TO_FSB_TRANSFER_LATENCY 1 +PRIORITIZE_PREFETCHES_WITH_UNIQUE FALSE +KICKOUT_PREFETCHES FALSE +KICKOUT_LOOK_FOR_OLDEST_FIRST FALSE +KICKOUT_OLDEST_PREFETCH FALSE +KICKOUT_OLDEST_PREFETCH_WITHIN_BANK FALSE +ORDER_BEYOND_BUS FALSE 1 +ALL_FIFO_QUEUES FALSE +QUEUE_MLC_SIZE 0 +QUEUE_L1_SIZE 0 +QUEUE_BUS_OUT_SIZE 0 +QUEUE_CORE_FILL_SIZE 0 +ALLOW_TYPE_MATCHES FALSE +STREAM_PREFETCH_ON FALSE +DC_PREF_CACHE_ENABLE FALSE +DC_PREF_CACHE_CYCLE 0 +PREF_INSERT_DCACHE_IMM TRUE +DC_PREF_CACHE_SIZE (64 * 1024) +DC_PREF_CACHE_ASSOC 4 +DC_PREF_ONLY_L1HIT FALSE +PREF_CACHE_USE_RDY_CYCLE FALSE +IC_PREF_CACHE_ENABLE FALSE +IC_PREF_CACHE_SIZE (64 * 1024) +IC_PREF_CACHE_ASSOC 4 +L1_PREF_CACHE_ENABLE FALSE +L1_PREF_CACHE_SIZE (1024 * 1024) +L1_PREF_CACHE_ASSOC 8 +SET_OFF_PATH_CONFIRMED FALSE 1 +USE_CONFIRMED_OFF FALSE +PREFCACHE_MOVE_OFFPATH FALSE +CACHE_STAT_ENABLE FALSE +PREF_DCACHE_HIT_FILL_L1 TRUE +PREF_ICACHE_HIT_FILL_L1 TRUE +CRITICAL_ACCESS_PLOT_ENABLE FALSE +CRITICAL_ACCESS_PLOT_FILE "critical_access_plot.dat" +ROUND_ROBIN_TO_L1 FALSE +PREF_I_TOGETHER FALSE +ONE_MORE_CACHE_LINE_ENABLE FALSE +L1_STATIC_PARTITION_ENABLE 0 +L1_STATIC_PARTITION NULL +L1_DYNAMIC_PARTITION_ENABLE FALSE +L1_DYNAMIC_PARTITION_POLICY 0 +PARTITION_UMON_DSS_PREF_ENABLE FALSE +L1_CACHE_HIT_POSITION_COLLECT FALSE +L1_PART_ON FALSE +L1_PART_TRIGGER "c:1000000" +L1_PART_START "t:0" +L1_PART_WARMUP FALSE +L1_PART_SHADOW_WARMUP FALSE +L1_PART_METRIC 0 +L1_PART_SEARCH 0 +L1_PART_USE_STALLING TRUE +L1_PART_FILL_DELAY 0 +L1_SHADOW_TAGS_MODULO 1 +HIER_MSHR_ON FALSE +PERF_PRED_ENABLE FALSE +PERF_PRED_MECH PERF_PRED_CP +PERF_PRED_REQ_LATENCY_MECH PERF_PRED_REQ_LATENCY_MECH_REQ_LATENCY +PERF_PRED_COUNT_ALL FALSE +PERF_PRED_COUNT_INST_MISSES TRUE +PERF_PRED_COUNT_PREFETCHES FALSE +PERF_PRED_COUNT_OFFPATH_REQS FALSE +PERF_PRED_COUNT_BW_REQS TRUE +PERF_PRED_UPDATE_MEM_REQ_TYPE FALSE +PERF_PRED_SLACK_PERIOD_SIZE 32 +PERF_PRED_REQS_FINISH_AT_FILL FALSE +PERF_PRED_MEM_UTIL_VIA_BUS_BW FALSE +PERF_PRED_CHIP_UTIL_VIA_MEM_STALL FALSE +DUMB_MODEL_AVG_REQ_DISTANCE 100 +DUMB_MODEL_RANDOMIZE_DISTANCE FALSE +DUMB_MODEL_AVG_REQ_DISTANCE_PER_CORE NULL +DUMB_MODEL_AVG_ROW_HITS 1 +DUMB_MODEL_AVG_ROW_HITS_PER_CORE NULL +DUMB_MODEL_MLP 1 +DUMB_MODEL_MLP_PER_CORE NULL +RAMULATOR_STANDARD "DDR4" DDR4 +RAMULATOR_SPEED "DDR4_2400R" DDR4_2400R +RAMULATOR_ORG "DDR4_8Gb_x8" DDR4_8Gb_x8 +RAMULATOR_CHANNELS 1 1 +RAMULATOR_RANKS 1 1 +RAMULATOR_BANKGROUPS 4 4 +RAMULATOR_BANKS 4 4 +RAMULATOR_CHIP_WIDTH 8 8 +BUS_WIDTH_IN_BYTES 8 8 +RAMULATOR_ROWS 65536 65536 +RAMULATOR_COLS 1024 1024 +RAMULATOR_SCHEDULING_POLICY "FRFCFS_Cap" FRFCFS_Cap +RAMULATOR_READQ_ENTRIES 32 32 +RAMULATOR_WRITEQ_ENTRIES 32 32 +RAMULATOR_REC_CMD_TRACE "off" FALSE +RAMULATOR_PRINT_CMD_TRACE "off" FALSE +RAMULATOR_USE_REST_OF_ADDR_AS_ROW_ADDR "on" +RAMULATOR_TCK 833333 833333 +RAMULATOR_TCL 16 16 +RAMULATOR_TCCD 6 6 +RAMULATOR_TCCDS 4 4 +RAMULATOR_TCCDL 6 6 +RAMULATOR_TCWL 12 12 +RAMULATOR_TBL 4 4 +RAMULATOR_TWTR 9 9 +RAMULATOR_TWTRS 3 3 +RAMULATOR_TWTRL 9 9 +RAMULATOR_TRP 16 16 +RAMULATOR_TRPpb 16 16 +RAMULATOR_TRPab 16 16 +RAMULATOR_TRCD 16 16 +RAMULATOR_TRCDR 16 16 +RAMULATOR_TRCDW 16 16 +RAMULATOR_TRAS 39 39 +DRAM_TECH_IN_NM 32 32 +DVFS_ON FALSE +DVFS_METRIC DVFS_METRIC_NUM_ELEMS +DVFS_CONFIGS NULL +DVFS_CONFIG_FILE NULL +DVFS_START "t:0" +DVFS_PERIOD "t:312500000000" +DVFS_LOG TRUE +DVFS_INDIVIDUAL_CORES FALSE +DVFS_CHIP_LEVEL FALSE +DVFS_STATIC NULL +DVFS_FORCE_CONFIG NULL +DVFS_REPLAY_CONFIG_TRACE NULL +DVFS_USE_ORACLE FALSE +DVFS_USE_BW_SHARING FALSE +DVFS_USE_DRAM_SHARING FALSE +DVFS_USE_STALL_TIME FALSE +DVFS_DRAM_SHARING_SOLVER_BIN NULL +DVFS_DRAM_SHARING_SOLVER_STRICT TRUE +DVFS_BW_SHARING_BUS_UTIL_THRESH 0.95 +DVFS_BW_SHARING_MAX_REQS 28.0 +DVFS_BW_SHARING_MAX_RW_COST 0.25 +DVFS_BW_SHARING_NO_PREF_STALL TRUE +DVFS_BW_SHARING_CRIT_STATS TRUE +DVFS_COUNT_L1_ACCESS_STALL FALSE +NUM_CORES 1 +CHIP_CYCLE_TIME 312500 312500 +CORE_0_CYCLE_TIME 312500 +CORE_1_CYCLE_TIME 312500 +CORE_2_CYCLE_TIME 312500 +CORE_3_CYCLE_TIME 312500 +CORE_4_CYCLE_TIME 312500 +CORE_5_CYCLE_TIME 312500 +CORE_6_CYCLE_TIME 312500 +CORE_7_CYCLE_TIME 312500 +CORE_8_CYCLE_TIME 312500 +CORE_9_CYCLE_TIME 312500 +CORE_10_CYCLE_TIME 312500 +CORE_11_CYCLE_TIME 312500 +CORE_12_CYCLE_TIME 312500 +CORE_13_CYCLE_TIME 312500 +CORE_14_CYCLE_TIME 312500 +CORE_15_CYCLE_TIME 312500 +CORE_16_CYCLE_TIME 312500 +CORE_17_CYCLE_TIME 312500 +CORE_18_CYCLE_TIME 312500 +CORE_19_CYCLE_TIME 312500 +CORE_20_CYCLE_TIME 312500 +CORE_21_CYCLE_TIME 312500 +CORE_22_CYCLE_TIME 312500 +CORE_23_CYCLE_TIME 312500 +CORE_24_CYCLE_TIME 312500 +CORE_25_CYCLE_TIME 312500 +CORE_26_CYCLE_TIME 312500 +CORE_27_CYCLE_TIME 312500 +CORE_28_CYCLE_TIME 312500 +CORE_29_CYCLE_TIME 312500 +CORE_30_CYCLE_TIME 312500 +CORE_31_CYCLE_TIME 312500 +CORE_32_CYCLE_TIME 312500 +CORE_33_CYCLE_TIME 312500 +CORE_34_CYCLE_TIME 312500 +CORE_35_CYCLE_TIME 312500 +CORE_36_CYCLE_TIME 312500 +CORE_37_CYCLE_TIME 312500 +CORE_38_CYCLE_TIME 312500 +CORE_39_CYCLE_TIME 312500 +CORE_40_CYCLE_TIME 312500 +CORE_41_CYCLE_TIME 312500 +CORE_42_CYCLE_TIME 312500 +CORE_43_CYCLE_TIME 312500 +CORE_44_CYCLE_TIME 312500 +CORE_45_CYCLE_TIME 312500 +CORE_46_CYCLE_TIME 312500 +CORE_47_CYCLE_TIME 312500 +CORE_48_CYCLE_TIME 312500 +CORE_49_CYCLE_TIME 312500 +CORE_50_CYCLE_TIME 312500 +CORE_51_CYCLE_TIME 312500 +CORE_52_CYCLE_TIME 312500 +CORE_53_CYCLE_TIME 312500 +CORE_54_CYCLE_TIME 312500 +CORE_55_CYCLE_TIME 312500 +CORE_56_CYCLE_TIME 312500 +CORE_57_CYCLE_TIME 312500 +CORE_58_CYCLE_TIME 312500 +CORE_59_CYCLE_TIME 312500 +CORE_60_CYCLE_TIME 312500 +CORE_61_CYCLE_TIME 312500 +CORE_62_CYCLE_TIME 312500 +CORE_63_CYCLE_TIME 312500 +ISSUE_WIDTH 4 6 +RS_FILL_WIDTH 8 0 +NODE_TABLE_SIZE 256 224 +NODE_RET_WIDTH 4 6 +NODE_RETIRE_RATE 10 +RS_SIZES "256" 97 +RS_CONNECTIONS "xF" 0 +FU_TYPES "0, 0, 0, 0" 0 0 0 0 0 0 0 0 +DECODE_CYCLES 1 5 +MAP_CYCLES 1 5 +EXTRA_RECOVERY_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after recovery. +EXTRA_REDIRECT_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after redirect. +EXTRA_CALLSYS_CYCLES 20 const +DIE_ON_CALLSYS FALSE +DIE_ON_RET_STALL_THRESH 0 +DIE_ON_RET_STALL_CORE 0 +DIE_ON_MEM_BLOCK_THRESH 0 +DIE_ON_MEM_BLOCK_CORE 0 +FETCH_ACROSS_CACHE_LINES FALSE 1 +FETCH_OFF_PATH_OPS TRUE 0 +FETCH_BREAK_ON_TAKEN FALSE 1 +FETCH_TAKEN_BUBBLE_CYCLES 0 0 +WP_COLLECT_STATS FALSE +SWITCH_IC_FETCH_ON_RECOVERY TRUE +OP_INV_DELAY 1 +OP_NOP_DELAY 1 +OP_CF_DELAY 1 +OP_MOV_DELAY 1 +OP_CMOV_DELAY 1 +OP_LDA_DELAY 1 +OP_IMEM_DELAY 1 +OP_IADD_DELAY 1 +OP_IMUL_DELAY 3 +OP_IDIV_DELAY -20 +OP_ICMP_DELAY 1 +OP_LOGIC_DELAY 1 +OP_SHIFT_DELAY 1 +OP_FMEM_DELAY 1 +OP_FCVT_DELAY 3 +OP_FADD_DELAY 3 +OP_FMUL_DELAY 5 +OP_FMA_DELAY 5 +OP_FDIV_DELAY -20 +OP_FCMP_DELAY 3 +OP_FCMOV_DELAY 1 +OP_GATHER_DELAY 12 +OP_SCATTER_DELAY 18 +OP_PIPELINED_FAST_DELAY 2 +OP_PIPELINED_MEDIUM_DELAY 5 +OP_PIPELINED_SLOW_DELAY 10 +OP_NOTPIPELINED_MEDIUM_DELAY -5 +OP_NOTPIPELINED_SLOW_DELAY -20 +OP_NOTPIPELINED_VERY_SLOW_DELAY -100 +UNIFORM_OP_DELAY 0 +STALL_ON_WAIT_MEM TRUE +STORES_DO_NOT_BLOCK_WINDOW FALSE 1 +PREFS_DO_NOT_BLOCK_WINDOW FALSE 1 +OBEY_REG_DEP TRUE +OLDEST_FIRST_SCHED FALSE +FIND_EMPTIEST_RS FALSE +TRACK_L1_MISS_DEPS FALSE +CBP_TRACE_R0 NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir/trace/drmemtrace.perlbench_s_base.mytest-m64.554262.9223.trace.gz +CBP_TRACE_R1 NULL +CBP_TRACE_R2 NULL +CBP_TRACE_R3 NULL +CBP_TRACE_R4 NULL +CBP_TRACE_R5 NULL +CBP_TRACE_R6 NULL +CBP_TRACE_R7 NULL +CBP_TRACE_R8 NULL +CBP_TRACE_R9 NULL +CBP_TRACE_R10 NULL +CBP_TRACE_R11 NULL +CBP_TRACE_R12 NULL +CBP_TRACE_R13 NULL +CBP_TRACE_R14 NULL +CBP_TRACE_R15 NULL +CBP_TRACE_R16 NULL +CBP_TRACE_R17 NULL +CBP_TRACE_R18 NULL +CBP_TRACE_R19 NULL +CBP_TRACE_R20 NULL +CBP_TRACE_R21 NULL +CBP_TRACE_R22 NULL +CBP_TRACE_R23 NULL +CBP_TRACE_R24 NULL +CBP_TRACE_R25 NULL +CBP_TRACE_R26 NULL +CBP_TRACE_R27 NULL +CBP_TRACE_R28 NULL +CBP_TRACE_R29 NULL +CBP_TRACE_R30 NULL +CBP_TRACE_R31 NULL +CBP_TRACE_R32 NULL +CBP_TRACE_R33 NULL +CBP_TRACE_R34 NULL +CBP_TRACE_R35 NULL +CBP_TRACE_R36 NULL +CBP_TRACE_R37 NULL +CBP_TRACE_R38 NULL +CBP_TRACE_R39 NULL +CBP_TRACE_R40 NULL +CBP_TRACE_R41 NULL +CBP_TRACE_R42 NULL +CBP_TRACE_R43 NULL +CBP_TRACE_R44 NULL +CBP_TRACE_R45 NULL +CBP_TRACE_R46 NULL +CBP_TRACE_R47 NULL +CBP_TRACE_R48 NULL +CBP_TRACE_R49 NULL +CBP_TRACE_R50 NULL +CBP_TRACE_R51 NULL +CBP_TRACE_R52 NULL +CBP_TRACE_R53 NULL +CBP_TRACE_R54 NULL +CBP_TRACE_R55 NULL +CBP_TRACE_R56 NULL +CBP_TRACE_R57 NULL +CBP_TRACE_R58 NULL +CBP_TRACE_R59 NULL +CBP_TRACE_R60 NULL +CBP_TRACE_R61 NULL +CBP_TRACE_R62 NULL +CBP_TRACE_R63 NULL +MEMTRACE_MODULES_LOG NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.perlbench_s_base.mytest-m64.554262.0160.dir/raw +DUMB_CORE_ON FALSE +DUMB_CORE 1 +DEBUG_CYCLE_START 0 0 +DEBUG_CYCLE_STOP 0 -1 +DEBUG_TIME_START 0 +DEBUG_TIME_STOP 0 +DEBUG_INST_START 0 0 +DEBUG_INST_STOP 0 -1 +DEBUG_OP_START 0 +DEBUG_OP_STOP 0 +DEBUG_CACHE_LIB FALSE +DEBUG_HASH_LIB FALSE +DEBUG_LIST_LIB FALSE +DEBUG_PORT_LIB FALSE +DEBUG_BUS_LIB FALSE +DEBUG_OP_POOL FALSE +DEBUG_ORACLE FALSE +DEBUG_FRONTEND FALSE +DEBUG_ADDR_TRANS FALSE +DEBUG_BP FALSE +DEBUG_BP_DIR FALSE +DEBUG_BTB FALSE +DEBUG_CRS FALSE +DEBUG_MAP FALSE +DEBUG_MEMORY FALSE +DEBUG_REPLAY FALSE +DEBUG_FREQ FALSE +DEBUG_MODEL FALSE +DEBUG_THREAD FALSE +DEBUG_ICACHE_STAGE FALSE +DEBUG_DECODE_STAGE FALSE +DEBUG_MAP_STAGE FALSE +DEBUG_NODE_STAGE FALSE +DEBUG_EXEC_STAGE FALSE +DEBUG_DCACHE_STAGE FALSE +DEBUG_RETIRED_UOPS FALSE +DEBUG_EXC_INSERTS FALSE +DEBUG_BP_CONF FALSE +DEBUG_ONPATH_CONF FALSE +DEBUG_STREAM FALSE +DEBUG_STREAM_MEM FALSE +DEBUG_WAY FALSE +DEBUG_L2MARKV FALSE +DEBUG_L2L1PREF FALSE +DEBUG_PERF_PRED FALSE +DEBUG_POWER_UTILS FALSE +DEBUG_DVFS FALSE +DEBUG_TRACE_READ FALSE +DEBUG_INST_FIELDS FALSE +DEBUG_OP_FIELDS FALSE +DEBUG_PIN_EXEC_DRIVEN FALSE +DEBUG_CACHE_PART FALSE +DEBUG_OPTIMIZER2 FALSE +DEBUG_PREF FALSE +PERFECT_BP FALSE +PERFECT_BTB FALSE +PERFECT_IBP FALSE +PERFECT_CRS FALSE +PERFECT_CBR_BTB FALSE +PERFECT_NT_BTB FALSE +CFS_PER_CYCLE 3 6 # Number of branches that can be predicted in a single cycle +UPDATE_BP_OFF_PATH FALSE 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +BP_UPDATE_AT_RETIRE FALSE 0 # Update the BP at retire. If false, update at the end of exec. +BP_MECH 0 tagescl +LATE_BP_MECH NUM_BP +LATE_BP_LATENCY 5 +HIST_LENGTH 16 +PHT_CTR_BITS 2 const +BHT_ENTRIES (4 * 1024) +BHT_ASSOC 4 +HYBRIDS_INDEX_LENGTH 16 +HYBRIDG_HIST_LENGTH 16 +HYBRIDP_HIST_LENGTH 16 +FILTER_INDEX_LENGTH 16 +USE_FILTER FALSE +INF_HYBRIDGP FALSE +BP_HASH_TOS FALSE +IBTB_HASH_TOS FALSE +BTB_MECH 0 generic +BTB_ENTRIES (4 * 1024) 4096 +BTB_ASSOC 4 4 +BTB_OFF_PATH_WRITES TRUE 1 +ENABLE_CRS TRUE 1 +CRS_ENTRIES 32 32 +CRS_REALISTIC 0 1 +ENABLE_IBP TRUE 1 # Enable the indirect branch predictor +USE_PAT_HIST TRUE +IBTB_MECH 1 tc_tagged +IBTB_HIST_LENGTH 16 +IBTB_OFF_PATH_WRITES TRUE 1 # Allow off path ops to update the ibtb. +TARGETS_IN_HIST 4 +TC_ENTRIES (4 * 1024) 4096 +TC_ASSOC 4 4 +NUM_CORR_BRANCHES 3 +SEL_HIST_BP_ENTRIES 8192 +SEL_HIST_LENGTH 16 +SEL_HIST_DYN_CNT_TH 16 +SEL_HIST_MISPRED_TH 4 +ENABLE_BP_CONF FALSE +CONF_MECH 0 +PERF_BP_CONF_PRED FALSE +BPC_BITS 16 +BPC_MECH 1 +BPC_CTR_RESET TRUE +BPC_CIT_BITS 8 +BPC_CIT_TH 50 +BPC_CTR_BITS 3 +OPC_COUNT_ZEROS FALSE +OPC_COUNT_THRESH 10 +INF_LOOP FALSE +INF_LOOP_BUCKETS 811 +LOOP_ENTRIES (4 * 1024) +LOOP_ASSOC 4 +LOOP_COUNT_MAX 127 +LOOP_REPEAT_MAX 15 +KNOB_PRINT_BRINFO FALSE +BR_MISPRED_FILE NULL +CONF_PERCEPTRON_TH 0 +CONF_PERCEPTRON_CTR_BITS 8 +CONF_PERCEPTRON_ENTRIES 127 +CONF_PERCEPTRON_THRESH_OVRD 0 +CONF_HIST_LENGTH 32 +PERCEPTRON_CONF_USE_CONF FALSE +PERCEPTRON_CONF_TRAIN_HIS FALSE +PERCEPTRON_CONF_TRAIN_CONF FALSE +PERCEPTRON_CONF_TRAIN_OFFSET_CONF FALSE +PERCEPTRON_TRAIN_MISP_FACTOR 1 +PERCEPTRON_TRAIN_CORR_FACTOR 1 +PERCEPTRON_CONF_HIS_BOTH FALSE +PERCEPTRON_CONF_HIS_BOTH_LENGTH 4 +ENABLE_ICACHE_PACKET_BREAKING TRUE +NUM_LOAD_STORE_PER_PACKET 0 +PACKET_BREAK_ON_FUS FALSE +PACKET_BREAK_FU_TYPES "G,G,G,G,G,G,G,G,G,G,G,G" +POWER_INTF_ON FALSE +POWER_INTF_ENABLE_SCALING FALSE +POWER_INTF_EXEC "power/power_intf.py" +POWER_INTF_REF_CHIP_TECH_NM 22 +POWER_INTF_REF_CHIP_FREQ (3.2e9) +POWER_INTF_REF_MEMORY_FREQ (0.8e9) +POWER_OTHER (0.0) +PREF_STREAM_ON FALSE 1 +PREF_STREAM_PER_CORE_ENABLE FALSE 1 +STREAM_BUFFER_N 16 +STREAM_PREFETCH_N 2 4 +STREAM_START_DIS 5 1 +STREAM_LENGTH 16 64 +STREAM_FULL_N 1 +STREAM_TRAIN_LENGTH 16 +STREAM_TRAIN_NUM 1 4 +PREF_ACC_USE_CACHE FALSE +STREAM_STALL_ON_QUEUE_FULL FALSE +PREF_SCHEDULE_NUM 4 +TRAIN_FILTER_SIZE 32 +PREF_REQ_Q_SIZE 64 +STREAM_CREATE_ON_DC_MISS FALSE 0 +STREAM_CREATE_ON_L1_MISS TRUE 1 +STREAM_TRAIN_ON_WRONGPATH TRUE +STREAM_CREATE_ON_WRONGPATH TRUE +STREAM_PREF_INTO_DCACHE FALSE +REMOVE_REDUNDANT_STREAM FALSE +L2HIT_STREAM_SCHEDULE_NUM 4 +PREF_REQ_QUEUE_FILTER_ON FALSE +HW_PREF_HIT_TRAIN_STREAM FALSE +L2HIT_STREAM_BUFFER_N 32 +L2HIT_STREAM_PREFETCH_N 2 +L2HIT_STREAM_START_DIS 2 +L2HIT_STREAM_LENGTH 8 +L2HIT_PREF_REQ_Q_SIZE 128 +L2HIT_L2ACCESS_REQ_Q_SIZE 64 +PREF_STREAM_ACCPERSTREAM FALSE +PREF_ACC_DISTANCE_10 128 +PREF_FRAMEWORK_ON FALSE 1 +PREF_TRACE_ON FALSE +PREF_DL0REQ_QUEUE_SIZE 32 +PREF_UMLC_REQ_QUEUE_SIZE 64 +PREF_UL1REQ_QUEUE_SIZE 128 +PREF_SHARED_QUEUES TRUE 0 +PREF_DL0_MISS_ON TRUE +PREF_DL0_HIT_ON TRUE +PREF_DL0REQ_QUEUE_FILTER_ON TRUE +PREF_UMLC_REQ_QUEUE_FILTER_ON TRUE +PREF_UL1REQ_QUEUE_FILTER_ON TRUE +PREF_DL0REQ_ADD_FILTER_ON TRUE +PREF_UMLC_REQ_ADD_FILTER_ON TRUE +PREF_UL1REQ_ADD_FILTER_ON TRUE +PREF_DL0REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UMLC_REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UL1REQ_QUEUE_OVERWRITE_ON_FULL FALSE 1 +PREF_DL0SCHEDULE_NUM 4 +PREF_UMLC_SCHEDULE_NUM 4 +PREF_UL1SCHEDULE_NUM 4 +PREF_L1Q_DEMAND_RESERVE 0 +PREF_REPORT_PREF_MATCH_AS_MISS FALSE +PREF_REPORT_PREF_MATCH_AS_HIT TRUE +PREF_UPDATE_ON_WRONGPATH TRUE +PREF_TRAIN_ON_PREF_MISSES FALSE 0 +PREF_ORACLE_TRAIN_ON FALSE 0 +PREF_REQ_DROP FALSE +PREF_THROTTLE_ON FALSE +PREF_THROTTLEFB_ON FALSE 1 +PREF_ACC_THRESH_1 0.90 0.75 +PREF_ACC_THRESH_2 0.70 0.4 +PREF_ACC_THRESH_3 0.60 0.4 +PREF_ACC_THRESH_4 0.40 +PREF_UPDATE_INTERVAL 0 8192 +PREF_ANALYZE_LOAD FALSE +PREF_POL_THRESH_1 0.25 +PREF_POL_THRESH_2 0.10 +PREF_POLBV_ON FALSE +PREF_POLBV_SIZE 1024 +PREF_TIMELY_THRESH 0.05 0.01 +PREF_POLPF_THRESH 0.01 0.005 +PREF_DEGFB_USEONLYACC FALSE +PREF_DEGFB_USEONLYPOL FALSE +PREF_DEGFB_USEONLYLATE FALSE +PREF_TIMELY_THRESH_2 0.005 +PREF_DEGFB_STATPHASEFILE FALSE +PREF_MAX_DEGFB 4 +PREF_DHAL FALSE +PREF_DHAL_SENTTHRESH 16 +PREF_DHAL_USETHRESH_MAX 12 +PREF_DHAL_USETHRESH_MIN2 8 +PREF_DHAL_USETHRESH_MIN1 4 +PREF_DHAL_MAXDEG 64 +PREF_HFILTER_ON FALSE +PREF_HFILTER_INDEX_BITS 12 +PREF_HFILTER_USE_PC FALSE +PREF_HFILTER_PRED_USELESS_THRES 2 +PREF_HFILTER_RESET_ENABLE FALSE +PREF_HFILTER_RESET_INTERVAL 100000 +L2L1PREF_ON FALSE +L2WAY_PREF FALSE +L2MARKV_PREF_ON FALSE +L2NEXT_PREF_ON FALSE +L2HIT_STREAM_PREF_ON FALSE +L2L1_DC_HIT_TRAIN FALSE +L1_HIT_DUMP_FILE_ON FALSE +L1_HIT_DUMP_WO_TXT FALSE +L1_HIT_DUMPFILE "l1hit_dump.out" +IDEAL_L2_L1_PREFETCHER FALSE +IDEAL_L2_ICACHE_PREFETCHER FALSE +L1WAY_PREF_SEND_QUEUE 4 +L1PREF_REQ_QUEUE_SIZE 1024 +L1PREF_IMMEDIATE FALSE +L1WAY_PREF_TIMER_DIS 1000 +L1MARKV_PREF_SEND_QUEUE 4 +L1PREF_MARKV_REQ_QUEUE_SIZE 1024 +MARKV_L2ACCESS_REQ_Q_SIZE 64 +L1MARKV_PREF_IMMEDIATE FALSE +L1MARKV_PREF_TIMER_DIS 1 +L2L1_HIT_TRAIN TRUE +L1MARKV_REQ_TH 1 +L2L1_IMMEDIATE_PREF_CACHE FALSE +L2L1_FILL_PREF_CACHE FALSE +L2L1_L2_HIT_STAT FALSE +PREF_GHB_ON FALSE +DEBUG_PREF_GHB FALSE +PREF_GHB_BUFFER_N 1024 +PREF_GHB_INDEX_N 128 +PREF_GHB_CZONE_BITS 12 +PREF_GHB_DEGREE 16 +PREF_GHB_MAX_DEGREE 32 +PREF_STRIDE_ON FALSE +DEBUG_PREF_STRIDE FALSE +PREF_STRIDE_TABLE_N 1024 +PREF_STRIDE_REGION_BITS 16 +PREF_STRIDE_DEGREE 4 +PREF_STRIDE_DISTANCE 16 +PREF_STRIDE_STARTDISTANCE 1 +PREF_STRIDE_SINGLE_THRESH 6 +PREF_STRIDE_MULTI_THRESH 6 +PREF_STRIDE_SINGLE_STRIDE_MODE FALSE +PREF_STRIDEPC_ON FALSE +DEBUG_PREF_STRIDEPC FALSE +PREF_STRIDEPC_TABLE_N 1024 +PREF_STRIDEPC_DEGREE 4 +PREF_STRIDEPC_DISTANCE 16 +PREF_STRIDEPC_USELOADADDR FALSE +PREF_STRIDEPC_TRAINNUM 2 +PREF_STRIDEPC_STARTDIS 4 +PREF_PHASE_ON FALSE +PREF_PHASE_STUDY FALSE +DEBUG_PREF_PHASE FALSE +PREF_PHASE_PRIME_HASH 16381 +PREF_PHASE_INFOSIZE 16384 +PREF_PHASE_LOG2REGIONSIZE 12 +PREF_PHASE_REGIONENTRIES 64 +PREF_PHASE_TRACKEDREGIONS 32 +PREF_PHASE_INTERVAL 100000 +PREF_PHASE_TABLE_SIZE 64 +PREF_PHASE_MAXDIFF_THRESH 64 +PREF_PHASE_MIN_MISSES 64 +PREF_PHASE_MISSPER 0.4 +PREF_2DC_ON FALSE +DEBUG_PREF_2DC FALSE +PREF_2DC_CACHE_SIZE (1 * 1024) +PREF_2DC_CACHE_ASSOC 4 +PREF_2DC_CACHE_LINE_SIZE 1 +PREF_2DC_DEGREE 16 +PREF_2DC_ZONE_SHIFT 10 +PREF_2DC_TAG_SIZE 16 +PREF_2DC_NUM_REGIONS 64 +PREF_2DC_REGION_HASH 61 +PREF_MARKOV_ON FALSE +DEBUG_PREF_MARKOV FALSE +PREF_MARKOV_NUM_ENTRIES 65536 +PREF_MARKOV_NUM_NEXT_STATES 8 +PREF_MARKOV_SEND_ON_PREF_HIT TRUE +PREF_MARKOV_UPDATE_ON_PREF_HIT TRUE +PREF_MARKOV_TABLE_UPDATE_POLICY 0 +PREF_MARKOV_SEND_THRESHOLD 0 +PREF_SMS_ON FALSE 1 +PREF_SMS_AT_SIZE 64 +PREF_SMS_FT_SIZE 64 +PREF_SMS_PHT_SIZE 16384 +PREF_SMS_PRF_SIZE 1024 +PREF_SMS_REGION_SIZE 2048 diff --git a/labs/LAB5/runs/perlbench_s_base-sms1/bp.stat.0.out b/labs/LAB5/runs/perlbench_s_base-sms1/bp.stat.0.out new file mode 100644 index 00000000..fc63b2af --- /dev/null +++ b/labs/LAB5/runs/perlbench_s_base-sms1/bp.stat.0.out @@ -0,0 +1,752 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 77430070 Instructions: 100000004 IPC: 1.29149 + +BTB_ON_PATH_MISS 406595 1.920% 406595 1.920% +BTB_ON_PATH_HIT 20765344 98.080% 20765344 98.080% + 21171939 100.000% 21171939 100.000% + 0.98 0.97 0.98 0.97 + +BTB_OFF_PATH_MISS 0 -nan% 0 -nan% +BTB_OFF_PATH_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BTB_ON_PATH_WRITE 406595 100.000% 406595 100.000% +BTB_OFF_PATH_WRITE 0 0.000% 0 0.000% + 406595 100.000% 406595 100.000% + 0.00 0.00 0.00 0.00 + +BP_ON_PATH_CORRECT 20231310 95.557% 20231310 95.557% +BP_ON_PATH_MISPREDICT 119560 0.565% 119560 0.565% +BP_ON_PATH_MISFETCH 821069 3.878% 821069 3.878% + 21171939 100.000% 21171939 100.000% + 0.08 0.38 0.08 0.38 + +BP_OFF_PATH_CORRECT 0 -nan% 0 -nan% +BP_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% +BP_OFF_PATH_MISFETCH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +LATE_BP_ON_PATH_CORRECT 21171939 100.000% 21171939 100.000% +LATE_BP_ON_PATH_MISPREDICT 0 0.000% 0 0.000% +LATE_BP_ON_PATH_MISFETCH 0 0.000% 0 0.000% + 21171939 100.000% 21171939 100.000% + 0.00 0.00 0.00 0.00 + +LATE_BP_OFF_PATH_CORRECT 0 -nan% 0 -nan% +LATE_BP_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% +LATE_BP_OFF_PATH_MISFETCH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_PVN 0 -nan% 0 -nan% +BP_ON_PATH_CONF_PVN_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_PVP 0 -nan% 0 -nan% +BP_ON_PATH_CONF_PVP_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_SPEC 0 -nan% 0 -nan% +BP_ON_PATH_CONF_SPEC_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CRS_MISS_ON_PATH 11965 0.926% 11965 0.926% +CRS_HIT_ON_PATH 1279813 99.074% 1279813 99.074% + 1291778 100.000% 1291778 100.000% + 0.99 0.99 0.99 0.99 + +CRS_MISS_OFF_PATH 0 -nan% 0 -nan% +CRS_HIT_OFF_PATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CRS_CLOBBER 0 0 + +TARG_ON_PATH_MISS 187022 18.287% 187022 18.287% +TARG_ON_PATH_HIT 835661 81.713% 835661 81.713% + 1022683 100.000% 1022683 100.000% + 0.82 0.76 0.82 0.76 + +TARG_OFF_PATH_MISS 0 -nan% 0 -nan% +TARG_OFF_PATH_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_ON_PATH_WRITE 1022682 100.000% 1022682 100.000% +TARG_OFF_PATH_WRITE 0 0.000% 0 0.000% + 1022682 100.000% 1022682 100.000% + 0.00 0.00 0.00 0.00 + +TARG_HYBRID_CORRECT_TAGLESS 0 -nan% 0 -nan% +TARG_HYBRID_CORRECT_TAGGED 0 -nan% 0 -nan% +TARG_HYBRID_MISPRED_TAGLESS 0 -nan% 0 -nan% +TARG_HYBRID_MISPRED_TAGGED 0 -nan% 0 -nan% +TARG_HYBRID_NO_PRED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_VP_INDIRECT_MISPRED 0 -nan% 0 -nan% +TARG_VP_INDIRECT_NOPRED 0 -nan% 0 -nan% +TARG_VP_INDIRECT_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CBR_ON_PATH_CORRECT 16321047 99.273% 16321047 99.273% +CBR_ON_PATH_MISPREDICT 119560 0.727% 119560 0.727% + 16440607 100.000% 16440607 100.000% + 0.01 0.08 0.01 0.08 + +CBR_ON_PATH_CORRECT_PER1000INST 16321047 163.2105 16321047 163.2105 + +CBR_ON_PATH_MISPREDICT_PER1000INST 119560 1.1956 119560 1.1956 + +CBR_OFF_PATH_CORRECT 0 -nan% 0 -nan% +CBR_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PRED_TO_UPDATE_CYCLES_0 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_1 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_2 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_3 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_4 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_5 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_6 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_7 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_8 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_9 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_10 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_11 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_12 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_13 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_14 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_15 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_16 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_17 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_18 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_19 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_20 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_21 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_22 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_23 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_24 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_25 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_26 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_27 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_28 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_29 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_30 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_CORRECTED 0 -nan% 0 -nan% +BP_NOT_CORRECTED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_CORRECTED 0 -nan% 0 -nan% +TARG_NOT_CORRECTED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_MISP_PENALTY 17562469 17562469 + +BP_ON_PATH_CONF_MISPRED 0 -nan% 0 -nan% +BP_ON_PATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_OFF_PATH_CONF_MISPRED 0 -nan% 0 -nan% +BP_OFF_PATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_PRED_MIS_CONF_MISPRED 0 -nan% 0 -nan% +BP_ON_PATH_PRED_MIS_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_PRED_COR_CONF_MISPRED 0 -nan% 0 -nan% +BP_ON_PATH_PRED_COR_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_OFF_PATH_PRED_MIS_CONF_MISPRED 0 -nan% 0 -nan% +BP_OFF_PATH_PRED_MIS_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_OFF_PATH_PRED_COR_CONF_MISPRED 0 -nan% 0 -nan% +BP_OFF_PATH_PRED_COR_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ONPATH_CONF_MISPRED 0 -nan% 0 -nan% +ONPATH_CONF_CORRECT 0 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-nan% + -nan -nan -nan -nan + +OPC_LENGTH_24_31_MIS 0 -nan% 0 -nan% +OPC_LENGTH_24_31_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_32_39_MIS 0 -nan% 0 -nan% +OPC_LENGTH_32_39_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_40_47_MIS 0 -nan% 0 -nan% +OPC_LENGTH_40_47_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_48_55_MIS 0 -nan% 0 -nan% +OPC_LENGTH_48_55_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_56_63_MIS 0 -nan% 0 -nan% +OPC_LENGTH_56_63_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_64_71_MIS 0 -nan% 0 -nan% +OPC_LENGTH_64_71_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_72_79_MIS 0 -nan% 0 -nan% +OPC_LENGTH_72_79_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_80_MIS 0 -nan% 0 -nan% +OPC_LENGTH_80_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ALL_ONES_MIS 0 -nan% 0 -nan% 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+#################################################################################################### +Cumulative: Cycles: 77430070 Instructions: 100000004 IPC: 1.29149 + +ST_OP_INV 0 0.000% 0 0.000% +ST_OP_NOP 1436724 1.188% 1436724 1.188% +ST_OP_CF 21171995 17.500% 21171995 17.500% +ST_OP_MOV 8743427 7.227% 8743427 7.227% +ST_OP_CMOV 581023 0.480% 581023 0.480% +ST_OP_LDA 3455348 2.856% 3455348 2.856% +ST_OP_IMEM 44030303 36.395% 44030303 36.395% +ST_OP_IADD 19119538 15.804% 19119538 15.804% +ST_OP_IMUL 112123 0.093% 112123 0.093% +ST_OP_IDIV 176 0.000% 176 0.000% +ST_OP_ICMP 9348536 7.727% 9348536 7.727% +ST_OP_LOGIC 11815904 9.767% 11815904 9.767% +ST_OP_SHIFT 892518 0.738% 892518 0.738% +ST_OP_FMEM 251195 0.208% 251195 0.208% +ST_OP_FCVT 201 0.000% 201 0.000% +ST_OP_FADD 186 0.000% 186 0.000% +ST_OP_FMUL 100 0.000% 100 0.000% +ST_OP_FMA 240 0.000% 240 0.000% +ST_OP_FDIV 3 0.000% 3 0.000% +ST_OP_FCMP 198 0.000% 198 0.000% +ST_OP_FCMOV 0 0.000% 0 0.000% +ST_OP_GATHER 0 0.000% 0 0.000% +ST_OP_SCATTER 0 0.000% 0 0.000% +ST_OP_PIPELINED_FAST 13685 0.011% 13685 0.011% +ST_OP_PIPELINED_MEDIUM 0 0.000% 0 0.000% +ST_OP_PIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_MEDIUM 7222 0.006% 7222 0.006% +ST_OP_NOTPIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_VERY_SLOW 0 0.000% 0 0.000% + 120980645 100.000% 120980645 100.000% + 6.00 2.84 6.00 2.84 + +ST_NOT_CF 99808650 82.500% 99808650 82.500% +ST_CF_BR 1516427 1.253% 1516427 1.253% +ST_CF_CBR 16440607 13.589% 16440607 13.589% +ST_CF_CALL 900444 0.744% 900444 0.744% +ST_CF_IBR 631358 0.522% 631358 0.522% +ST_CF_ICALL 391325 0.323% 391325 0.323% +ST_CF_ICO 0 0.000% 0 0.000% +ST_CF_RET 1291778 1.068% 1291778 1.068% +ST_CF_SYS 56 0.000% 56 0.000% + 120980645 100.000% 120980645 100.000% + 0.42 1.00 0.42 1.00 + +ST_BAR_NONE 120980589 100.000% 120980589 100.000% +ST_BAR_FETCH 56 0.000% 56 0.000% +ST_BAR_ISSUE 0 0.000% 0 0.000% +ST_BAR_BOTH 0 0.000% 0 0.000% + 120980645 100.000% 120980645 100.000% + 0.00 0.00 0.00 0.00 + +ST_NOT_MEM 76699147 63.398% 76699147 63.398% +ST_MEM_LD 28757686 23.770% 28757686 23.770% +ST_MEM_ST 15523812 12.832% 15523812 12.832% +ST_MEM_PF 0 0.000% 0 0.000% +ST_MEM_WH 0 0.000% 0 0.000% +ST_MEM_EVICT 0 0.000% 0 0.000% + 120980645 100.000% 120980645 100.000% + 0.49 0.59 0.49 0.59 + +ST_NOT_MEM_OFFPATH 0 -nan% 0 -nan% +ST_MEM_LD_OFFPATH 0 -nan% 0 -nan% +ST_MEM_ST_OFFPATH 0 -nan% 0 -nan% +ST_MEM_PF_OFFPATH 0 -nan% 0 -nan% +ST_MEM_WH_OFFPATH 0 -nan% 0 -nan% +ST_MEM_EVIC_OFFPATHT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ST_OP_ONPATH 120980645 120980645 + +ST_OP_OFFPATH 0 0 + +ST_FAKE_OP_OFFPATH 0 -nan% 0 -nan% +ST_NOT_FAKE_OP_OFFPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ST_FAKE_REASON_NOT_FAKE 0 -nan% 0 -nan% +ST_FAKE_REASON_REDIRECT_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_RETURN_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_NONRET_CF_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_NOT_TAKEN_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_WRONG_PATH_STORE_TO_NEW_REGION 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ST_INST_ONPATH 100000077 100000077 + +ST_INST_OFFPATH 0 0 + +STATIC_PIN_NOP 0 0 + +DYNAMIC_PIN_REP_GREATER_256 0 0 + + + diff --git a/labs/LAB5/runs/perlbench_s_base-sms1/l2l1pref.stat.0.out b/labs/LAB5/runs/perlbench_s_base-sms1/l2l1pref.stat.0.out new file mode 100644 index 00000000..ac36f1d4 --- /dev/null +++ b/labs/LAB5/runs/perlbench_s_base-sms1/l2l1pref.stat.0.out @@ -0,0 +1,140 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 77430070 Instructions: 100000004 IPC: 1.29149 + +L2WAY_FILL_L1 0 0 + +L2WAY_WAY_HIT 0 -nan% 0 -nan% +L2WAY_WAY_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_PREF_REQ 0 0 + +L2WAY_PREF_HIT_DATA_IN_CACHE 0 -nan% 0 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0 0 + +L2NEXT_PREF_HIT_DATA_REQ 0 -nan% 0 -nan% +L2NEXT_PREF_HIT_DATA_IN_CACHE 0 -nan% 0 -nan% +L2NEXT_PREF_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2NEXT_L1INSERT_PORT_READY 0 -nan% 0 -nan% +L2NEXT_L1INSERT_PORT_FULL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DCACHE_PREF_NOT_RDY 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_10 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_100 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_1000 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_10000 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_100000 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_1000000 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_10000000 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_100000000 0 -nan% 0 -nan% +DCACHE_PREF_FETCH_MORE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_SAME_IP_DELTA__0 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__1 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__2 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__3 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__4 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__5 0 -nan% 0 -nan% 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+#################################################################################################### +Cumulative: Cycles: 77430070 Instructions: 100000004 IPC: 1.29149 + +ICACHE_MISS 925010 2.711% 925010 2.711% +ICACHE_HIT 33197590 97.289% 33197590 97.289% + 34122600 100.000% 34122600 100.000% + 0.97 0.96 0.97 0.96 + +ICACHE_MISS_ONPATH 925010 100.000% 925010 100.000% +ICACHE_MISS_OFFPATH 0 0.000% 0 0.000% + 925010 100.000% 925010 100.000% + 0.00 0.00 0.00 0.00 + +ICACHE_HIT_ONPATH 33197590 100.000% 33197590 100.000% +ICACHE_HIT_OFFPATH 0 0.000% 0 0.000% + 33197590 100.000% 33197590 100.000% + 0.00 0.00 0.00 0.00 + +ICACHE_HIT_ONPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +ICACHE_HIT_ONPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ICACHE_HIT_OFFPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +ICACHE_HIT_OFFPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DCACHE_MISS 1885733 4.259% 1885733 4.259% +DCACHE_ST_BUFFER_HIT 19194 0.043% 19194 0.043% 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-nan -nan -nan + +DCACHE_MISS_LD 1545282 81.946% 1545282 81.946% +DCACHE_MISS_ST 340451 18.054% 340451 18.054% + 1885733 100.000% 1885733 100.000% + 0.18 0.36 0.18 0.36 + +DCACHE_MISS_LD_ONPATH 1545282 100.000% 1545282 100.000% +DCACHE_MISS_LD_OFFPATH 0 0.000% 0 0.000% + 1545282 100.000% 1545282 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_MISS_ST_ONPATH 340451 100.000% 340451 100.000% +DCACHE_MISS_ST_OFFPATH 0 0.000% 0 0.000% + 340451 100.000% 340451 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_MISS_WAITMEM 8759 8759 + +MEM_REQ_ROW_BUFFER_HITS 0 -nan% 0 -nan% +MEM_REQ_ROW_BUFFER_MISSES 0 -nan% 0 -nan% +MEM_REQ_ROW_BUFFER_CONFLICTS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +SHADOW_ROW_BUFFER_HITS 0 0 + +SHADOW_ROW_HIT_STALL_TIME 0 0 + +CHANNEL0_BUS_BUSY_CYCLES 0 -nan% 0 -nan% +CHANNEL1_BUS_BUSY_CYCLES 0 -nan% 0 -nan% +CHANNEL2_BUS_BUSY_CYCLES 0 -nan% 0 -nan% +CHANNEL3_BUS_BUSY_CYCLES 0 -nan% 0 -nan% +CHANNEL4_BUS_BUSY_CYCLES 0 -nan% 0 -nan% +CHANNEL5_BUS_BUSY_CYCLES 0 -nan% 0 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17291064 118.3647 17291064 118.3647 + +CORE_MEM_LATENCY_PREF 11638004 153.5884 11638004 153.5884 + +CORE_MEM_LATENCY_IFETCH 1870638 6.466% 1870638 6.466% +CORE_MEM_LATENCY_DFETCH 13099934 45.283% 13099934 45.283% +CORE_MEM_LATENCY_DSTORE 2868396 9.915% 2868396 9.915% +CORE_MEM_LATENCY_IPRF 0 0.000% 0 0.000% +CORE_MEM_LATENCY_DPRF 11090100 38.335% 11090100 38.335% +CORE_MEM_LATENCY_WB 0 0.000% 0 0.000% +CORE_MEM_LATENCY_WB_NODIRTY 0 0.000% 0 0.000% + 28929068 100.000% 28929068 100.000% + 2.18 1.38 2.18 1.38 + +CORE_MEM_STALLING_LATENCY_IFETCH 0 -nan% 0 -nan% +CORE_MEM_STALLING_LATENCY_DFETCH 0 -nan% 0 -nan% +CORE_MEM_STALLING_LATENCY_DSTORE 0 -nan% 0 -nan% +CORE_MEM_STALLING_LATENCY_IPRF 0 -nan% 0 -nan% +CORE_MEM_STALLING_LATENCY_DPRF 0 -nan% 0 -nan% +CORE_MEM_STALLING_LATENCY_WB 0 -nan% 0 -nan% +CORE_MEM_STALLING_LATENCY_WB_NODIRTY 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TOTAL_L1_MISS_LATENCY 28929068 130.3951 28929068 130.3951 + +TOTAL_L1_MISS_LATENCY_DEMAND 17291064 118.3647 17291064 118.3647 + +TOTAL_L1_MISS_LATENCY_PREF 11638004 153.5884 11638004 153.5884 + +CORE_L1_MISS_LATENCY 28929068 130.3951 28929068 130.3951 + +CORE_L1_MISS_LATENCY_DEMAND 17291064 118.3647 17291064 118.3647 + +CORE_L1_MISS_LATENCY_PREF 11638004 153.5884 11638004 153.5884 + +CORE_EVICTED_L1_DEMAND 137768 67.027% 137768 67.027% +CORE_EVICTED_L1_PREF_USED 27910 13.579% 27910 13.579% +CORE_EVICTED_L1_PREF_NOT_USED 39864 19.395% 39864 19.395% + 205542 100.000% 205542 100.000% + 0.52 0.71 0.52 0.71 + +CORE_EVICTED_MLC_DEMAND 0 -nan% 0 -nan% +CORE_EVICTED_MLC_PREF_USED 0 -nan% 0 -nan% +CORE_EVICTED_MLC_PREF_NOT_USED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CORE_MEM_LATENCY_AVE_DEMAND 16269702 118.0949 16269702 118.0949 + +CORE_MEM_LATENCY_AVE_PREF_USED 3457482 123.8797 3457482 123.8797 + +CORE_MEM_LATENCY_AVE_PREF_NOT_USED 6573191 164.8904 6573191 164.8904 + +DRAM_LATENCY 0 0 + +TOTAL_DRAM_LATENCY 0 0 + +DRAM_CLOSED_PAGE_POLICY_CMD 0 0 + +DRAM_ACTIVATE_STALLING 0 0 + +DRAM_PRECHARGE_STALLING 0 0 + +DRAM_PRECHARGE_STALLING_WAIT_CYCLES 0 0 + +L1_STAY_DEMAND 751414207407 5454199.8679 751414207407 5454199.8679 + +L1_STAY_PREF_USED 152758627109 5473257.8685 152758627109 5473257.8685 + +L1_STAY_PREF_NOT_USED 165555202725 4153000.2690 165555202725 4153000.2690 + +TOTAL_DATA_MISS_LATENCY 15968330 15968330 + +TOTAL_DATA_MISS_COUNT 128330 128330 + +CORE_PREF_L1_NOT_USED_LATENCY200 32665 81.941% 32665 81.941% +CORE_PREF_L1_NOT_USED_LATENCY400 3876 9.723% 3876 9.723% +CORE_PREF_L1_NOT_USED_LATENCY600 1450 3.637% 1450 3.637% +CORE_PREF_L1_NOT_USED_LATENCY800 831 2.085% 831 2.085% +CORE_PREF_L1_NOT_USED_LATENCY1000 376 0.943% 376 0.943% +CORE_PREF_L1_NOT_USED_LATENCY1200 220 0.552% 220 0.552% +CORE_PREF_L1_NOT_USED_LATENCY1400 196 0.492% 196 0.492% +CORE_PREF_L1_NOT_USED_LATENCY1600 99 0.248% 99 0.248% +CORE_PREF_L1_NOT_USED_LATENCY1600MORE 151 0.379% 151 0.379% + 39864 100.000% 39864 100.000% + 0.38 1.00 0.38 1.00 + +CORE_PREF_L1_NOT_USED_DISTANCE_1 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_DISTANCE_2 397 0.996% 397 0.996% +CORE_PREF_L1_NOT_USED_DISTANCE_4 3516 8.820% 3516 8.820% +CORE_PREF_L1_NOT_USED_DISTANCE_8 13136 32.952% 13136 32.952% +CORE_PREF_L1_NOT_USED_DISTANCE_16 16703 41.900% 16703 41.900% +CORE_PREF_L1_NOT_USED_DISTANCE_32 6065 15.214% 6065 15.214% +CORE_PREF_L1_NOT_USED_DISTANCE_MORE 47 0.118% 47 0.118% + 39864 100.000% 39864 100.000% + 3.62 0.89 3.62 0.89 + +CORE_PREF_L1_USED_LATENCY200 24774 88.764% 24774 88.764% +CORE_PREF_L1_USED_LATENCY400 1626 5.826% 1626 5.826% +CORE_PREF_L1_USED_LATENCY600 832 2.981% 832 2.981% +CORE_PREF_L1_USED_LATENCY800 283 1.014% 283 1.014% +CORE_PREF_L1_USED_LATENCY1000 99 0.355% 99 0.355% +CORE_PREF_L1_USED_LATENCY1200 112 0.401% 112 0.401% +CORE_PREF_L1_USED_LATENCY1400 139 0.498% 139 0.498% +CORE_PREF_L1_USED_LATENCY1600 20 0.072% 20 0.072% +CORE_PREF_L1_USED_LATENCY1600MORE 25 0.090% 25 0.090% + 27910 100.000% 27910 100.000% + 0.22 0.78 0.22 0.78 + +CORE_PREF_L1_USED_DISTANCE_1 0 0.000% 0 0.000% +CORE_PREF_L1_USED_DISTANCE_2 148 0.530% 148 0.530% +CORE_PREF_L1_USED_DISTANCE_4 3182 11.401% 3182 11.401% +CORE_PREF_L1_USED_DISTANCE_8 11302 40.494% 11302 40.494% +CORE_PREF_L1_USED_DISTANCE_16 11145 39.932% 11145 39.932% +CORE_PREF_L1_USED_DISTANCE_32 2131 7.635% 2131 7.635% +CORE_PREF_L1_USED_DISTANCE_MORE 2 0.007% 2 0.007% + 27910 100.000% 27910 100.000% + 3.43 0.81 3.43 0.81 + +CORE_PREF_L1_DEMAND_LATENCY300 132864 96.440% 132864 96.440% +CORE_PREF_L1_DEMAND_LATENCY400 850 0.617% 850 0.617% +CORE_PREF_L1_DEMAND_LATENCY500 1212 0.880% 1212 0.880% +CORE_PREF_L1_DEMAND_LATENCY600 718 0.521% 718 0.521% +CORE_PREF_L1_DEMAND_LATENCY700 367 0.266% 367 0.266% +CORE_PREF_L1_DEMAND_LATENCY800 177 0.128% 177 0.128% +CORE_PREF_L1_DEMAND_LATENCY900 174 0.126% 174 0.126% +CORE_PREF_L1_DEMAND_LATENCY1000 160 0.116% 160 0.116% +CORE_PREF_L1_DEMAND_LATENCY1000MORE 1246 0.904% 1246 0.904% + 137768 100.000% 137768 100.000% + 0.14 0.90 0.14 0.90 + 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9870 3.964% +NUM_DCACHE_MISSES_IN_WINDOW_11 8598 3.453% 8598 3.453% +NUM_DCACHE_MISSES_IN_WINDOW_12 7373 2.961% 7373 2.961% +NUM_DCACHE_MISSES_IN_WINDOW_13 6125 2.460% 6125 2.460% +NUM_DCACHE_MISSES_IN_WINDOW_14 5291 2.125% 5291 2.125% +NUM_DCACHE_MISSES_IN_WINDOW_15 3779 1.518% 3779 1.518% +NUM_DCACHE_MISSES_IN_WINDOW_16_OR_MORE 18806 7.553% 18806 7.553% + 248994 100.000% 248994 100.000% + 5.39 4.39 5.39 4.39 + +DCACHE_MLP_IN_WINDOW_1_0 154855 62.192% 154855 62.192% +DCACHE_MLP_IN_WINDOW_1_5 69659 27.976% 69659 27.976% +DCACHE_MLP_IN_WINDOW_2_0 18866 7.577% 18866 7.577% +DCACHE_MLP_IN_WINDOW_2_5 3074 1.235% 3074 1.235% +DCACHE_MLP_IN_WINDOW_3_0 1750 0.703% 1750 0.703% +DCACHE_MLP_IN_WINDOW_3_5 274 0.110% 274 0.110% +DCACHE_MLP_IN_WINDOW_4_0 200 0.080% 200 0.080% +DCACHE_MLP_IN_WINDOW_4_5 96 0.039% 96 0.039% +DCACHE_MLP_IN_WINDOW_5_0 108 0.043% 108 0.043% +DCACHE_MLP_IN_WINDOW_5_5 17 0.007% 17 0.007% +DCACHE_MLP_IN_WINDOW_6_0 21 0.008% 21 0.008% +DCACHE_MLP_IN_WINDOW_6_5 20 0.008% 20 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b/labs/LAB5/runs/perlbench_s_base-sms1/power.stat.0.out new file mode 100644 index 00000000..22ada5f4 --- /dev/null +++ b/labs/LAB5/runs/perlbench_s_base-sms1/power.stat.0.out @@ -0,0 +1,184 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 77430070 Instructions: 100000004 IPC: 1.29149 + +POWER_STATS_BEGIN 0 0 + +POWER_TIME 24196896875000 24196896875000 + +POWER_CYCLE 77430070 77430070 + +POWER_ITLB_ACCESS 34122600 34122600 + +POWER_DTLB_ACCESS 15523805 15523805 + +POWER_ICACHE_ACCESS 34122600 34122600 + +POWER_ICACHE_MISS 925010 925010 + +POWER_BTB_READ 34122600 34122600 + +POWER_BTB_WRITE 940629 940629 + +POWER_ROB_READ 120980581 120980581 + +POWER_ROB_WRITE 120980581 120980581 + +POWER_RENAME_READ 241961162 241961162 + +POWER_RENAME_WRITE 120980581 120980581 + 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21171983 + +POWER_DRAM_PRECHARGE 81693 81693 + +POWER_DRAM_ACTIVATE 106224 106224 + +POWER_DRAM_READ 221644 221644 + +POWER_DRAM_WRITE 47794 47794 + +POWER_STATS_END 0 0 + +ENERGY 0.000000 0.000000 + +ENERGY_CORE 0.000000 0.000000 + +ENERGY_UNCORE 0.000000 0.000000 + +ENERGY_MEMORY 0.000000 0.000000 + +ENERGY_OTHER 0.000000 0.000000 + +ENERGY_CORE_STATIC 0.000000 0.000000 + +ENERGY_CORE_DYNAMIC 0.000000 0.000000 + +ENERGY_UNCORE_STATIC 0.000000 0.000000 + +ENERGY_UNCORE_DYNAMIC 0.000000 0.000000 + +ENERGY_MEMORY_STATIC 0.000000 0.000000 + +ENERGY_MEMORY_DYNAMIC 0.000000 0.000000 + +ENERGY_OTHER_STATIC 0.000000 0.000000 + +ENERGY_OTHER_DYNAMIC 0.000000 0.000000 + +TIME 0.000000 0.000000 + +ENERGY_STATS_END 0 0 + + + diff --git a/labs/LAB5/runs/perlbench_s_base-sms1/pref.stat.0.out b/labs/LAB5/runs/perlbench_s_base-sms1/pref.stat.0.out new file mode 100644 index 00000000..9cba0b31 --- /dev/null +++ b/labs/LAB5/runs/perlbench_s_base-sms1/pref.stat.0.out @@ -0,0 +1,208 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 77430070 Instructions: 100000004 IPC: 1.29149 + +PREF_DL0REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UMLC_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UL1REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_DL0REQ_QUEUE_FULL 0 0 + +PREF_UMLC_REQ_QUEUE_FULL 0 0 + +PREF_UL1REQ_QUEUE_FULL 0 0 + +PREF_DC_HIT_NOSEND 0 0 + +PREF_WBQDC_HIT_NOSEND 0 0 + +PREF_MLCQ_STALL 0 0 + +PREF_L1Q_STALL 0 0 + +PREF_UMLC_REQ_SEND_QUEUE_STALL 0 0 + +PREF_UL1REQ_SEND_QUEUE_STALL 47162 47162 + +PREF_UMLC_REQ_QUEUE_SENTREQ 0 0 + +PREF_UL1REQ_QUEUE_SENTREQ 114443 114443 + +PREF_NEWREQ_MATCHED 4690 4690 + +PREF_UMLC_REQ_QUEUE_MATCHED_REQ 0 0 + +PREF_UL1REQ_QUEUE_MATCHED_REQ 6964 6964 + +PREF_DL0REQ_QUEUE_MATCHED_REQ 0 0 + +L1_PREF_HIT 142771 142771 + +L1_PREF_UNIQUE_HIT 28448 28448 + +L1_PREF_LATE 2823 2823 + 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-nan% 0 -nan% +PREF_REPL_LRU 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_REPL_MOVEDOWN 0 -nan% 0 -nan% +PREF_REPL_MOVEUP 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_COV_1 0 -nan% 0 -nan% +PREF_COV_2 0 -nan% 0 -nan% +PREF_COV_3 0 -nan% 0 -nan% +PREF_COV_4 0 -nan% 0 -nan% +PREF_COV_5 0 -nan% 0 -nan% +PREF_COV_6 0 -nan% 0 -nan% +PREF_COV_7 0 -nan% 0 -nan% +PREF_COV_8 0 -nan% 0 -nan% +PREF_COV_9 0 -nan% 0 -nan% +PREF_COV_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_POL_1 0 0.000% 0 0.000% +PREF_POL_2 0 0.000% 0 0.000% +PREF_POL_3 0 0.000% 0 0.000% +PREF_POL_4 0 0.000% 0 0.000% +PREF_POL_5 0 0.000% 0 0.000% +PREF_POL_6 0 0.000% 0 0.000% +PREF_POL_7 0 0.000% 0 0.000% +PREF_POL_8 0 0.000% 0 0.000% +PREF_POL_9 0 0.000% 0 0.000% +PREF_POL_10 25 100.000% 25 100.000% + 25 100.000% 25 100.000% + 9.00 9.19 9.00 9.19 + +PREF_ACC_1 0 0.000% 0 0.000% +PREF_ACC_2 0 0.000% 0 0.000% +PREF_ACC_3 0 0.000% 0 0.000% +PREF_ACC_4 1 4.000% 1 4.000% +PREF_ACC_5 3 12.000% 3 12.000% +PREF_ACC_6 9 36.000% 9 36.000% +PREF_ACC_7 12 48.000% 12 48.000% +PREF_ACC_8 0 0.000% 0 0.000% +PREF_ACC_9 0 0.000% 0 0.000% +PREF_ACC_10 0 0.000% 0 0.000% + 25 100.000% 25 100.000% + 5.28 0.84 5.28 0.84 + +PREF_TIMELY_1 0 0.000% 0 0.000% +PREF_TIMELY_2 0 0.000% 0 0.000% +PREF_TIMELY_3 0 0.000% 0 0.000% +PREF_TIMELY_4 0 0.000% 0 0.000% +PREF_TIMELY_5 0 0.000% 0 0.000% +PREF_TIMELY_6 0 0.000% 0 0.000% +PREF_TIMELY_7 0 0.000% 0 0.000% +PREF_TIMELY_8 0 0.000% 0 0.000% +PREF_TIMELY_9 10 40.000% 10 40.000% +PREF_TIMELY_10 15 60.000% 15 60.000% + 25 100.000% 25 100.000% + 8.60 6.82 8.60 6.82 + +PREF_UNUSED_EVICT 39864 39864 + +PREF_REGION_SENT 0 0 + +PREF_REGION_USEFUL 0 0 + +PREF_REGION_EVICT 0 0 + +PREF_PFPOL 0 0 + +PREF_PHASE_NEWPHASE_DET 0 0 + +PREF_PHASE_NEWPHASE_NOTVALID 0 0 + +PREF_PHASE_SENTPREF 0 0 + +PREF_PHASE_OVERWRITE_PAGE 0 0 + +PREF_UPDATE_COUNT 25 25 + +PREF_ACC1_HT_HP 0 0.000% 0 0.000% +PREF_ACC1_HT_LP 0 0.000% 0 0.000% +PREF_ACC1_LT_HP 0 0.000% 0 0.000% +PREF_ACC1_LT_LP 0 0.000% 0 0.000% +PREF_ACC2_HT_HP 0 0.000% 0 0.000% +PREF_ACC2_HT_LP 0 0.000% 0 0.000% +PREF_ACC2_LT_HP 0 0.000% 0 0.000% +PREF_ACC2_LT_LP 13 52.000% 13 52.000% +PREF_ACC3_HT_HP 0 0.000% 0 0.000% +PREF_ACC3_HT_LP 0 0.000% 0 0.000% +PREF_ACC3_LT_HP 0 0.000% 0 0.000% +PREF_ACC3_LT_LP 0 0.000% 0 0.000% +PREF_ACC4_HT_HP 0 0.000% 0 0.000% +PREF_ACC4_HT_LP 0 0.000% 0 0.000% +PREF_ACC4_LT_HP 0 0.000% 0 0.000% +PREF_ACC4_LT_LP 12 48.000% 12 48.000% + 25 100.000% 25 100.000% + 10.84 8.68 10.84 8.68 + + + diff --git a/labs/LAB5/runs/perlbench_s_base-sms1/ramulator.stat.out b/labs/LAB5/runs/perlbench_s_base-sms1/ramulator.stat.out new file mode 100644 index 00000000..114953c9 --- /dev/null +++ b/labs/LAB5/runs/perlbench_s_base-sms1/ramulator.stat.out @@ -0,0 +1,150 @@ + ramulator.active_cycles_0 15842756 # Total active cycles for level _0 + ramulator.busy_cycles_0 15842756 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0 + ramulator.serving_requests_0 25029554 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.average_serving_requests_0 0.862009 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.active_cycles_0_0 15842756 # Total active cycles for level _0_0 + ramulator.busy_cycles_0_0 16510136 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0 + ramulator.serving_requests_0_0 25029554 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.average_serving_requests_0_0 0.862009 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.active_cycles_0_0_0 5527222 # Total active cycles for level _0_0_0 + ramulator.busy_cycles_0_0_0 5527222 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0 + ramulator.serving_requests_0_0_0 6391318 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 +ramulator.average_serving_requests_0_0_0 0.220115 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 + ramulator.active_cycles_0_0_0_0 1584948 # Total active cycles for level _0_0_0_0 + ramulator.busy_cycles_0_0_0_0 1584948 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_0 + ramulator.serving_requests_0_0_0_0 1674771 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 +ramulator.average_serving_requests_0_0_0_0 0.057679 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 + ramulator.active_cycles_0_0_0_1 1934400 # Total active cycles for level _0_0_0_1 + ramulator.busy_cycles_0_0_0_1 1934400 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_1 + ramulator.serving_requests_0_0_0_1 2017389 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 +ramulator.average_serving_requests_0_0_0_1 0.069478 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 + ramulator.active_cycles_0_0_0_2 1458433 # Total active cycles for level _0_0_0_2 + ramulator.busy_cycles_0_0_0_2 1458433 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_2 + ramulator.serving_requests_0_0_0_2 1538346 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 +ramulator.average_serving_requests_0_0_0_2 0.052980 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 + ramulator.active_cycles_0_0_0_3 1095055 # Total active cycles for level _0_0_0_3 + ramulator.busy_cycles_0_0_0_3 1095055 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_3 + ramulator.serving_requests_0_0_0_3 1160812 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 +ramulator.average_serving_requests_0_0_0_3 0.039978 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 + ramulator.active_cycles_0_0_1 6166596 # Total active cycles for level _0_0_1 + ramulator.busy_cycles_0_0_1 6166596 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1 + ramulator.serving_requests_0_0_1 7272521 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 +ramulator.average_serving_requests_0_0_1 0.250463 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 + ramulator.active_cycles_0_0_1_0 2265076 # Total active cycles for level _0_0_1_0 + ramulator.busy_cycles_0_0_1_0 2265076 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_0 + ramulator.serving_requests_0_0_1_0 2336129 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 +ramulator.average_serving_requests_0_0_1_0 0.080456 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 + ramulator.active_cycles_0_0_1_1 1612996 # Total active cycles for level _0_0_1_1 + ramulator.busy_cycles_0_0_1_1 1612996 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_1 + ramulator.serving_requests_0_0_1_1 1708075 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 +ramulator.average_serving_requests_0_0_1_1 0.058826 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 + ramulator.active_cycles_0_0_1_2 1583134 # Total active cycles for level _0_0_1_2 + ramulator.busy_cycles_0_0_1_2 1583134 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_2 + ramulator.serving_requests_0_0_1_2 1649974 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 +ramulator.average_serving_requests_0_0_1_2 0.056825 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 + ramulator.active_cycles_0_0_1_3 1496357 # Total active cycles for level _0_0_1_3 + ramulator.busy_cycles_0_0_1_3 1496357 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_3 + ramulator.serving_requests_0_0_1_3 1577599 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 +ramulator.average_serving_requests_0_0_1_3 0.054332 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 + ramulator.active_cycles_0_0_2 5123212 # Total active cycles for level _0_0_2 + ramulator.busy_cycles_0_0_2 5123212 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2 + ramulator.serving_requests_0_0_2 5952498 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 +ramulator.average_serving_requests_0_0_2 0.205002 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 + ramulator.active_cycles_0_0_2_0 1283790 # Total active cycles for level _0_0_2_0 + ramulator.busy_cycles_0_0_2_0 1283790 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_0 + ramulator.serving_requests_0_0_2_0 1372314 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 +ramulator.average_serving_requests_0_0_2_0 0.047262 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 + ramulator.active_cycles_0_0_2_1 1904315 # Total active cycles for level _0_0_2_1 + ramulator.busy_cycles_0_0_2_1 1904315 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_1 + ramulator.serving_requests_0_0_2_1 1973475 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 +ramulator.average_serving_requests_0_0_2_1 0.067966 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 + ramulator.active_cycles_0_0_2_2 1198017 # Total active cycles for level _0_0_2_2 + ramulator.busy_cycles_0_0_2_2 1198017 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_2 + ramulator.serving_requests_0_0_2_2 1264760 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 +ramulator.average_serving_requests_0_0_2_2 0.043558 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 + ramulator.active_cycles_0_0_2_3 1266385 # Total active cycles for level _0_0_2_3 + ramulator.busy_cycles_0_0_2_3 1266385 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_3 + ramulator.serving_requests_0_0_2_3 1341949 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 +ramulator.average_serving_requests_0_0_2_3 0.046216 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 + ramulator.active_cycles_0_0_3 4669022 # Total active cycles for level _0_0_3 + ramulator.busy_cycles_0_0_3 4669022 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3 + ramulator.serving_requests_0_0_3 5401650 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 +ramulator.average_serving_requests_0_0_3 0.186031 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 + ramulator.active_cycles_0_0_3_0 1152893 # Total active cycles for level _0_0_3_0 + ramulator.busy_cycles_0_0_3_0 1152893 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_0 + ramulator.serving_requests_0_0_3_0 1240610 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 +ramulator.average_serving_requests_0_0_3_0 0.042726 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 + ramulator.active_cycles_0_0_3_1 959639 # Total active cycles for level _0_0_3_1 + ramulator.busy_cycles_0_0_3_1 959639 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_1 + ramulator.serving_requests_0_0_3_1 1043461 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 +ramulator.average_serving_requests_0_0_3_1 0.035936 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 + ramulator.active_cycles_0_0_3_2 1869952 # Total active cycles for level _0_0_3_2 + ramulator.busy_cycles_0_0_3_2 1869952 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_2 + ramulator.serving_requests_0_0_3_2 1953467 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 +ramulator.average_serving_requests_0_0_3_2 0.067277 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 + ramulator.active_cycles_0_0_3_3 1087887 # Total active cycles for level _0_0_3_3 + ramulator.busy_cycles_0_0_3_3 1087887 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_3 + ramulator.serving_requests_0_0_3_3 1164112 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 +ramulator.average_serving_requests_0_0_3_3 0.040092 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 + ramulator.read_transaction_bytes_0 14185216 # The total byte of read transaction per channel + ramulator.write_transaction_bytes_0 3058880 # The total byte of write transaction per channel + ramulator.row_hits_channel_0_core 163224 # Number of row hits per channel per core + ramulator.row_misses_channel_0_core 28254 # Number of row misses per channel per core + ramulator.row_conflicts_channel_0_core 77961 # Number of row conflicts per channel per core + ramulator.read_row_hits_channel_0_core 152683 # Number of row hits for read requests per channel per core + [0] 152683.0 # +ramulator.read_row_misses_channel_0_core 20421 # Number of row misses for read requests per channel per core + [0] 20421.0 # +ramulator.read_row_conflicts_channel_0_core 48540 # Number of row conflicts for read requests per channel per core + [0] 48540.0 # + ramulator.write_row_hits_channel_0_core 10541 # Number of row hits for write requests per channel per core + [0] 10541.0 # +ramulator.write_row_misses_channel_0_core 7833 # Number of row misses for write requests per channel per core + [0] 7833.0 # +ramulator.write_row_conflicts_channel_0_core 29421 # Number of row conflicts for write requests per channel per core + [0] 29421.0 # + ramulator.useless_activates_0_core 14 # Number of useless activations. E.g, ACT -> PRE w/o RD or WR + ramulator.read_latency_avg_0 49.209856 # The average memory latency cycles (in memory time domain) per request for all read requests in this channel + ramulator.read_latency_sum_0 10917551 # The memory latency cycles (in memory time domain) sum for all read requests in this channel + ramulator.req_queue_length_avg_0 14.230174 # Average of read and write queue length per memory cycle per channel. + ramulator.req_queue_length_sum_0 413191428 # Sum of read and write queue length per memory cycle per channel. + ramulator.read_req_queue_length_avg_0 0.337602 # Read queue length average per memory cycle per channel. + ramulator.read_req_queue_length_sum_0 9802716 # Read queue length sum per memory cycle per channel. + ramulator.write_req_queue_length_avg_0 13.892572 # Write queue length average per memory cycle per channel. + ramulator.write_req_queue_length_sum_0 403388712 # Write queue length sum per memory cycle per channel. + ramulator.record_read_hits 0.0 # record read hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_misses 0.0 # record_read_miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_conflicts 0.0 # record read conflict count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_hits 0.0 # record write hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_misses 0.0 # record write miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_conflicts 0.0 # record write conflict for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.dram_capacity 8589934592 # Number of bytes in simulated DRAM + ramulator.dram_cycles 29036287 # Number of DRAM cycles simulated + ramulator.incoming_requests 269658 # Number of incoming requests to DRAM + ramulator.read_requests 221857 # Number of incoming read requests to DRAM per core + [0] 221857.0 # + ramulator.write_requests 47801 # Number of incoming write requests to DRAM per core + [0] 47801.0 # + ramulator.ramulator_active_cycles 15847412 # The total number of cycles that the DRAM part is active (serving R/W) + ramulator.incoming_requests_per_channel 269658.0 # Number of incoming requests to each DRAM channel + [0] 269658.0 # +ramulator.incoming_read_reqs_per_channel 221857.0 # Number of incoming read requests to each DRAM channel + [0] 221857.0 # + ramulator.physical_page_replacement 0 # The number of times that physical page replacement happens. + ramulator.maximum_bandwidth 19200000000 # The theoretical maximum bandwidth (Bps) + ramulator.in_queue_req_num_sum 413191428 # Sum of read/write queue length + ramulator.in_queue_read_req_num_sum 9802716 # Sum of read queue length + ramulator.in_queue_write_req_num_sum 403388712 # Sum of write queue length + ramulator.in_queue_req_num_avg 14.230174 # Average of read/write queue length per memory cycle + ramulator.in_queue_read_req_num_avg 0.337602 # Average of read queue length per memory cycle + ramulator.in_queue_write_req_num_avg 13.892572 # Average of write queue length per memory cycle + ramulator.record_read_requests 0.0 # record read requests for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_requests 0.0 # record write requests for this core when it reaches request limit or to the end + [0] 0.0 # diff --git a/labs/LAB5/runs/perlbench_s_base-sms1/run.err b/labs/LAB5/runs/perlbench_s_base-sms1/run.err new file mode 100644 index 00000000..e69de29b diff --git a/labs/LAB5/runs/perlbench_s_base-sms1/run.out b/labs/LAB5/runs/perlbench_s_base-sms1/run.out new file mode 100644 index 00000000..a816c595 --- /dev/null +++ b/labs/LAB5/runs/perlbench_s_base-sms1/run.out @@ -0,0 +1,107 @@ +Scarab gitrev: 7ab9e17 +Scarab started at Sun Jun 11 08:08:38 2023 + +Initialized Ramulator. +** Heartbeat: 1% -- { 1000001 } -- 0.00 KIPS (333.33 KIPS) +** Heartbeat: 2% -- { 2000001 } -- 500.00 KIPS (400.00 KIPS) +** Heartbeat: 3% -- { 3000004 } -- 333.33 KIPS (375.00 KIPS) +** Heartbeat: 4% -- { 4000004 } -- 500.00 KIPS (400.00 KIPS) +** Heartbeat: 5% -- { 5000005 } -- 500.00 KIPS (416.67 KIPS) +** Heartbeat: 6% -- { 6000006 } -- 500.00 KIPS (428.57 KIPS) +** Heartbeat: 7% -- { 7000007 } -- 500.00 KIPS (437.50 KIPS) +** Heartbeat: 8% -- { 8000010 } -- 333.33 KIPS (421.05 KIPS) +** Heartbeat: 9% -- { 9000013 } -- 500.00 KIPS (428.57 KIPS) +** Heartbeat: 10% -- { 10000015 } -- 500.00 KIPS (434.78 KIPS) +** Heartbeat: 11% -- { 11000016 } -- 333.33 KIPS (423.08 KIPS) +** Heartbeat: 12% -- { 12000019 } -- 500.00 KIPS (428.57 KIPS) +** Heartbeat: 13% -- { 13000021 } -- 500.00 KIPS (433.33 KIPS) +** Heartbeat: 14% -- { 14000021 } -- 500.00 KIPS (437.50 KIPS) +** Heartbeat: 15% -- { 15000021 } -- 333.33 KIPS (428.57 KIPS) +** Heartbeat: 16% -- { 16000022 } -- 500.00 KIPS (432.43 KIPS) +** Heartbeat: 17% -- { 17000025 } -- 500.00 KIPS (435.90 KIPS) +** Heartbeat: 18% -- { 18000026 } -- 500.00 KIPS (439.03 KIPS) +** Heartbeat: 19% -- { 19000029 } -- 500.00 KIPS (441.86 KIPS) +** Heartbeat: 20% -- { 20000030 } -- 500.00 KIPS (444.45 KIPS) +** Heartbeat: 21% -- { 21000033 } -- 500.00 KIPS (446.81 KIPS) +** Heartbeat: 22% -- { 22000034 } -- 500.00 KIPS (448.98 KIPS) +** Heartbeat: 23% -- { 23000036 } -- 500.00 KIPS (450.98 KIPS) +** Heartbeat: 24% -- { 24000040 } -- 500.00 KIPS (452.83 KIPS) +** Heartbeat: 25% -- { 25000041 } -- 500.00 KIPS (454.55 KIPS) +** Heartbeat: 26% -- { 26000045 } -- 333.33 KIPS (448.28 KIPS) +** Heartbeat: 27% -- { 27000047 } -- 500.00 KIPS (450.00 KIPS) +** Heartbeat: 28% -- { 28000047 } -- 500.00 KIPS (451.61 KIPS) +** Heartbeat: 29% -- { 29000048 } -- 333.33 KIPS (446.15 KIPS) +** Heartbeat: 30% -- { 30000049 } -- 500.00 KIPS (447.76 KIPS) +** Heartbeat: 31% -- { 31000052 } -- 500.00 KIPS (449.28 KIPS) +** Heartbeat: 32% -- { 32000053 } -- 500.00 KIPS (450.70 KIPS) +** Heartbeat: 33% -- { 33000055 } -- 333.33 KIPS (445.95 KIPS) +** Heartbeat: 34% -- { 34000057 } -- 500.00 KIPS (447.37 KIPS) +** Heartbeat: 35% -- { 35000061 } -- 500.00 KIPS (448.72 KIPS) +** Heartbeat: 36% -- { 36000063 } -- 333.33 KIPS (444.45 KIPS) +** Heartbeat: 37% -- { 37000065 } -- 500.00 KIPS (445.78 KIPS) +** Heartbeat: 38% -- { 38000067 } -- 500.00 KIPS (447.06 KIPS) +** Heartbeat: 39% -- { 39000071 } -- 333.33 KIPS (443.18 KIPS) +** Heartbeat: 40% -- { 40000073 } -- 500.00 KIPS (444.45 KIPS) +** Heartbeat: 41% -- { 41000074 } -- 500.00 KIPS (445.65 KIPS) +** Heartbeat: 42% -- { 42000075 } -- 500.00 KIPS (446.81 KIPS) +** Heartbeat: 43% -- { 43000079 } -- 500.00 KIPS (447.92 KIPS) +** Heartbeat: 44% -- { 44000083 } -- 500.00 KIPS (448.98 KIPS) +** Heartbeat: 45% -- { 45000084 } -- 333.33 KIPS (445.55 KIPS) +** Heartbeat: 46% -- { 46000084 } -- 500.00 KIPS (446.60 KIPS) +** Heartbeat: 47% -- { 47000089 } -- 500.00 KIPS (447.62 KIPS) +** Heartbeat: 48% -- { 48000091 } -- 500.00 KIPS (448.60 KIPS) +** Heartbeat: 49% -- { 49000092 } -- 500.00 KIPS (449.54 KIPS) +** Heartbeat: 50% -- { 50000094 } -- 333.33 KIPS (446.43 KIPS) +** Heartbeat: 51% -- { 51000097 } -- 500.00 KIPS (447.37 KIPS) +** Heartbeat: 52% -- { 52000097 } -- 500.00 KIPS (448.28 KIPS) +** Heartbeat: 53% -- { 53000101 } -- 500.00 KIPS (449.15 KIPS) +** Heartbeat: 54% -- { 54000104 } -- 500.00 KIPS (450.00 KIPS) +** Heartbeat: 55% -- { 55000106 } -- 500.00 KIPS (450.82 KIPS) +** Heartbeat: 56% -- { 56000107 } -- 500.00 KIPS (451.61 KIPS) +** Heartbeat: 57% -- { 57000109 } -- 500.00 KIPS (452.38 KIPS) +** Heartbeat: 58% -- { 58000112 } -- 500.00 KIPS (453.13 KIPS) +** Heartbeat: 59% -- { 59000112 } -- 500.00 KIPS (453.85 KIPS) +** Heartbeat: 60% -- { 60000112 } -- 333.33 KIPS (451.13 KIPS) +** Heartbeat: 61% -- { 61000114 } -- 500.00 KIPS (451.85 KIPS) +** Heartbeat: 62% -- { 62000114 } -- 500.00 KIPS (452.56 KIPS) +** Heartbeat: 63% -- { 63000116 } -- 500.00 KIPS (453.24 KIPS) +** Heartbeat: 64% -- { 64000120 } -- 333.33 KIPS (450.71 KIPS) +** Heartbeat: 65% -- { 65000123 } -- 500.00 KIPS (451.39 KIPS) +** Heartbeat: 66% -- { 66000128 } -- 500.00 KIPS (452.06 KIPS) +** Heartbeat: 67% -- { 67000129 } -- 500.00 KIPS (452.70 KIPS) +** Heartbeat: 68% -- { 68000129 } -- 333.33 KIPS (450.33 KIPS) +** Heartbeat: 69% -- { 69000130 } -- 500.00 KIPS (450.98 KIPS) +** Heartbeat: 70% -- { 70000134 } -- 333.33 KIPS (448.72 KIPS) +** Heartbeat: 71% -- { 71000134 } -- 500.00 KIPS (449.37 KIPS) +** Heartbeat: 72% -- { 72000134 } -- 500.00 KIPS (450.00 KIPS) +** Heartbeat: 73% -- { 73000136 } -- 333.33 KIPS (447.85 KIPS) +** Heartbeat: 74% -- { 74000136 } -- 500.00 KIPS (448.49 KIPS) +** Heartbeat: 75% -- { 75000136 } -- 500.00 KIPS (449.10 KIPS) +** Heartbeat: 76% -- { 76000137 } -- 333.33 KIPS (447.06 KIPS) +** Heartbeat: 77% -- { 77000140 } -- 500.00 KIPS (447.68 KIPS) +** Heartbeat: 78% -- { 78000143 } -- 333.33 KIPS (445.72 KIPS) +** Heartbeat: 79% -- { 79000143 } -- 500.00 KIPS (446.33 KIPS) +** Heartbeat: 80% -- { 80000144 } -- 500.00 KIPS (446.93 KIPS) +** Heartbeat: 81% -- { 81000148 } -- 333.33 KIPS (445.06 KIPS) +** Heartbeat: 82% -- { 82000151 } -- 500.00 KIPS (445.65 KIPS) +** Heartbeat: 83% -- { 83000154 } -- 500.00 KIPS (446.24 KIPS) +** Heartbeat: 84% -- { 84000156 } -- 500.00 KIPS (446.81 KIPS) +** Heartbeat: 85% -- { 85000159 } -- 500.00 KIPS (447.37 KIPS) +** Heartbeat: 86% -- { 86000161 } -- 500.00 KIPS (447.92 KIPS) +** Heartbeat: 87% -- { 87000161 } -- 500.00 KIPS (448.45 KIPS) +** Heartbeat: 88% -- { 88000164 } -- 500.00 KIPS (448.98 KIPS) +** Heartbeat: 89% -- { 89000167 } -- 500.00 KIPS (449.50 KIPS) +** Heartbeat: 90% -- { 90000168 } -- 500.00 KIPS (450.00 KIPS) +** Heartbeat: 91% -- { 91000170 } -- 500.00 KIPS (450.50 KIPS) +** Heartbeat: 92% -- { 92000170 } -- 500.00 KIPS (450.98 KIPS) +** Heartbeat: 93% -- { 93000172 } -- 333.33 KIPS (449.28 KIPS) +** Heartbeat: 94% -- { 94000173 } -- 500.00 KIPS (449.76 KIPS) +** Heartbeat: 95% -- { 95000173 } -- 500.00 KIPS (450.24 KIPS) +** Heartbeat: 96% -- { 96000173 } -- 500.00 KIPS (450.71 KIPS) +** Heartbeat: 97% -- { 97000173 } -- 333.33 KIPS (449.07 KIPS) +** Heartbeat: 98% -- { 98000177 } -- 500.00 KIPS (449.54 KIPS) +** Heartbeat: 99% -- { 99000181 } -- 500.00 KIPS (450.00 KIPS) +** Core 0 Finished: insts:100000004 cycles:77430070 time:24196896875000 -- 1.29 IPC (1.29 IPC) -- N/A KIPS (450.45 KIPS) +done +Scarab finished at Sun Jun 11 08:12:20 2023 + diff --git a/labs/LAB5/runs/perlbench_s_base-sms1/stream.stat.0.out b/labs/LAB5/runs/perlbench_s_base-sms1/stream.stat.0.out new file mode 100644 index 00000000..e7fcc60b --- /dev/null +++ b/labs/LAB5/runs/perlbench_s_base-sms1/stream.stat.0.out @@ -0,0 +1,188 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 77430070 Instructions: 100000004 IPC: 1.29149 + +DCACHE_PREF_HIT 0 0 + +IFETCH_WB_FIRST_SCHEDULE 0 -nan% 0 -nan% +PREFETCH_LAST_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_PREF_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_LOW_OP_SCHEDULE 0 -nan% 0 -nan% +DEMAND_LAST_SCHEDULE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +SEND_MISS_REQ_QUEUE 221857 221857 + +L1_DATA_EVICT 205542 205542 + +STREAM_BUFFER_REQ 0 0 + +PREF_SEND_TO_MEM_REQ 0 -nan% 0 -nan% +PREF_SEND_TO_MEM_REQ_FAIL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +HIT_TRAIN_STREAM 64025 35.186% 64025 35.186% +MISS_TRAIN_STREAM 117939 64.814% 117939 64.814% + 181964 100.000% 181964 100.000% + 0.65 0.59 0.65 0.59 + +STREAM_TRAIN_CREATE 54585 54585 + +MEM_REQ_MISS_HWP_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_SW_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_IFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DSTORE_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DPRF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_WB_Q 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_BY_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_WB 0 -nan% 0 -nan% +PREF_HIT_BY_PREF 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_WB 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_L1_FILL 0 -nan% 0 -nan% +DEMAND_L1_FILL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TOUCH_L1_REPLACE 0 0.000% 0 0.000% +NO_TOUCH_L1_REPLACE 205542 100.000% 205542 100.000% + 205542 100.000% 205542 100.000% + 1.00 1.00 1.00 1.00 + +PREF_REQ_QUE_FULL 0 0 + +STREAM_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +L2HIT_STREAM_PREF_REQ_QUE_FULL 0 0 + +L2HIT_HIT_TRAIN_STREAM 0 -nan% 0 -nan% +L2HIT_MISS_TRAIN_STREAM 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_TRAIN_CREATE 0 0 + +L2HIT_STREAM_BUFFER_REQ 0 0 + +L2HIT_STREAM_PREF_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_STREAM_PREF_DCACHE_INSERT 0 -nan% 0 -nan% +L2HIT_STREAM_L2_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_DCACHE_PORT_FULL 0 0 + +L2HIT_STREAM_PREF_L1_PORT_FULL 0 0 + +L2HIT_TRAIN_HIT_DEMAND 0 -nan% 0 -nan% +L2HIT_TRAIN_MISS_REQ 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_TRAIN_FILTER_MISS 0 -nan% 0 -nan% +L2HIT_TRAIN_FILTER_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_PREF_REQ_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_PREF_REQ_DCACHE_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_L2SEND_Q_FULL 0 -nan% 0 -nan% +L2HIT_L2SEND_Q_ENTER 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_MEM_REQ 0 0 + +REMOVE_REDUNDANT_STREAM_STAT 0 0 + +REPLACE_OLD_STREAM 54569 54569 + +REQ_SEND_QUEUE_STALL 0 0 + +STREAM_ENTER_RA 0 0 + +CORE_STREAM_LENGTH_0 3144 28.558% 3144 28.558% +CORE_STREAM_LENGTH_10 4414 40.094% 4414 40.094% +CORE_STREAM_LENGTH_20 2030 18.439% 2030 18.439% +CORE_STREAM_LENGTH_30 615 5.586% 615 5.586% +CORE_STREAM_LENGTH_40 327 2.970% 327 2.970% +CORE_STREAM_LENGTH_50 147 1.335% 147 1.335% +CORE_STREAM_LENGTH_60 100 0.908% 100 0.908% +CORE_STREAM_LENGTH_70 56 0.509% 56 0.509% +CORE_STREAM_LENGTH_80 32 0.291% 32 0.291% +CORE_STREAM_LENGTH_90 26 0.236% 26 0.236% +CORE_STREAM_LENGTH_100_P 118 1.072% 118 1.072% + 11009 100.000% 11009 100.000% + 1.36 1.45 1.36 1.45 + +CORE_CUM_STREAM_LENGTH_0 20982 10.040% 20982 10.040% +CORE_CUM_STREAM_LENGTH_10 62552 29.932% 62552 29.932% +CORE_CUM_STREAM_LENGTH_20 47529 22.743% 47529 22.743% +CORE_CUM_STREAM_LENGTH_30 20888 9.995% 20888 9.995% +CORE_CUM_STREAM_LENGTH_40 14491 6.934% 14491 6.934% +CORE_CUM_STREAM_LENGTH_50 7986 3.821% 7986 3.821% +CORE_CUM_STREAM_LENGTH_60 6445 3.084% 6445 3.084% +CORE_CUM_STREAM_LENGTH_70 4128 1.975% 4128 1.975% +CORE_CUM_STREAM_LENGTH_80 2704 1.294% 2704 1.294% +CORE_CUM_STREAM_LENGTH_90 2439 1.167% 2439 1.167% +CORE_CUM_STREAM_LENGTH_100_P 18835 9.013% 18835 9.013% + 208979 100.000% 208979 100.000% + 2.96 2.87 2.96 2.87 + +CORE_STREAM_TRAIN_HITS_0 7597 69.007% 7597 69.007% +CORE_STREAM_TRAIN_HITS_10 2738 24.871% 2738 24.871% +CORE_STREAM_TRAIN_HITS_20 381 3.461% 381 3.461% +CORE_STREAM_TRAIN_HITS_30 138 1.254% 138 1.254% +CORE_STREAM_TRAIN_HITS_40 53 0.481% 53 0.481% +CORE_STREAM_TRAIN_HITS_50 25 0.227% 25 0.227% +CORE_STREAM_TRAIN_HITS_60 4 0.036% 4 0.036% +CORE_STREAM_TRAIN_HITS_70 8 0.073% 8 0.073% +CORE_STREAM_TRAIN_HITS_80 12 0.109% 12 0.109% +CORE_STREAM_TRAIN_HITS_90 4 0.036% 4 0.036% +CORE_STREAM_TRAIN_HITS_100_P 49 0.445% 49 0.445% + 11009 100.000% 11009 100.000% + 0.45 0.94 0.45 0.94 + +CORE_CUM_STREAM_TRAIN_HITS_0 48477 44.861% 48477 44.861% +CORE_CUM_STREAM_TRAIN_HITS_10 33531 31.030% 33531 31.030% +CORE_CUM_STREAM_TRAIN_HITS_20 8942 8.275% 8942 8.275% +CORE_CUM_STREAM_TRAIN_HITS_30 4645 4.298% 4645 4.298% +CORE_CUM_STREAM_TRAIN_HITS_40 2323 2.150% 2323 2.150% +CORE_CUM_STREAM_TRAIN_HITS_50 1350 1.249% 1350 1.249% +CORE_CUM_STREAM_TRAIN_HITS_60 256 0.237% 256 0.237% +CORE_CUM_STREAM_TRAIN_HITS_70 596 0.552% 596 0.552% +CORE_CUM_STREAM_TRAIN_HITS_80 1021 0.945% 1021 0.945% +CORE_CUM_STREAM_TRAIN_HITS_90 375 0.347% 375 0.347% +CORE_CUM_STREAM_TRAIN_HITS_100_P 6545 6.057% 6545 6.057% + 108061 100.000% 108061 100.000% + 1.52 2.40 1.52 2.40 + +CORE_STREAM_TRAIN_CREATE 54585 54585 + + + diff --git a/labs/LAB5/runs/sgcc_base-sms0/PARAMS.in b/labs/LAB5/runs/sgcc_base-sms0/PARAMS.in new file mode 100644 index 00000000..2593c2b8 --- /dev/null +++ b/labs/LAB5/runs/sgcc_base-sms0/PARAMS.in @@ -0,0 +1,226 @@ +# File : PARAMS.kaby_lake +# Date : 03/06/19 +# Description : Kaby Lake Configuration +# +# Based on documentation found here: +# https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake + +## Simulation Parameters +--mode full +--model cmp +--sim_limit none + +## Core Parameters + +# Femptoseconds, 3.2GHz, used for energy estimates. +--chip_cycle_time 312500 + + +### Fetch Stage +--fetch_off_path_ops 1 +--fetch_across_cache_lines 1 + +# Will break the packet upon a taken branch. +--fetch_break_on_taken 1 + +# Number of bubble cycles to wait after taken branch. +--fetch_taken_bubble_cycles 0 + + +#### ICache +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 + +### Branch Predictor +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_mech tagescl + + +#### BTB + +# BTB model to use. +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 + +# Allow the BTB to be updated by off path ops. +--btb_off_path_writes 1 + + +#### CRS + +# Enable return stack +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 + +### iBP +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged + # iBTB Model. tc_tagless, tc_tagged, tc_hybrid. +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 + +### Decode Stage +--decode_cycles 5 + + +### Map Stage +--map_cycles 5 + + +### Issue Stage + +# Max number of instructions to be fetched, decoded, renamed, and issued per cycle. +--issue_width 6 + +--rs_fill_width 0 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 + + +### Exec Stage + +### DCache +--dcache_size 32768 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--dcache_assoc 4 +--dcache_line_size 64 + +### Reorder/Retire Stage + +# Max number of instructions to be retired per cycle. +--node_ret_width 6 +--node_table_size 224 + +# Do not keep stores in RSVs on cache misses; TODO: confirm what this knob does +--stores_do_not_block_window 1 + +# TODO: confirm what this knob does +--prefs_do_not_block_window 1 + + +## Uncore + +### Mid-level cache + +# Enable use of a midlevel cache between i/d and L1 +--mlc_present 0 + +### LLC +--l1_size 1048576 +--l1_banks 1 +--l1_cycles 18 +--l1_assoc 8 +--l1_line_size 64 +--l1_interleave_factor 64 + + +### Prefetcher +--pref_framework_on 1 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--pref_shared_queues 0 +--pref_train_on_pref_misses 0 +--pref_oracle_train 0 +--pref_ul1req_queue_overwrite_on_full 1 + +--stream_length 64 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 + +--pref_throttlefb_on=1 +--pref_acc_thresh_1=0.75 +--pref_acc_thresh_2=0.4 +--pref_acc_thresh_3=0.4 +--pref_timely_thresh=0.01 +--pref_polpf_thresh=0.005 +--pref_update_interval=8192 + +--mem_req_buffer_pref_watermark 4 +--promote_to_higher_priority_mem_req_type 1 + +### Memory +--addr_translation random + +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 + +--mem_req_buffer_entries 32 +--mem_l1_fill_queue_entries 32 +--va_page_size_bytes 4096 +--bus_width_in_bytes 8 + +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 + +## Other + + +### Debug +--debug_inst_start 0 +--debug_inst_stop -1 +--debug_cycle_start 0 +--debug_cycle_stop -1 + + +## Stats and Params +--dump_params 1 +--dump_stats 1 +--dump_trace 0 + +#################################### +--set_off_path_confirmed 1 + +--order_beyond_bus 1 + +--mem_ooo_stores 1 +--mem_obey_store_dep 1 diff --git a/labs/LAB5/runs/sgcc_base-sms0/PARAMS.out b/labs/LAB5/runs/sgcc_base-sms0/PARAMS.out new file mode 100644 index 00000000..75da16f8 --- /dev/null +++ b/labs/LAB5/runs/sgcc_base-sms0/PARAMS.out @@ -0,0 +1,908 @@ +--mode full +--model cmp +--frontend memtrace +--inst_limit 100000000 +--sim_limit none +--dump_params 1 +--dump_stats 1 +--dump_trace 0 +--mlc_present 0 +--l1_size 1048576 +--l1_assoc 8 +--l1_line_size 64 +--l1_cycles 18 +--l1_banks 1 +--l1_interleave_factor 64 +--va_page_size_bytes 4096 +--addr_translation random +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 +--dcache_size 32768 +--dcache_assoc 4 +--dcache_line_size 64 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--mem_ooo_stores 1 +--mem_obey_store_dep 1 +--mem_req_buffer_entries 32 +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 +--promote_to_higher_priority_mem_req_type 1 +--mem_req_buffer_pref_watermark 4 +--mem_l1_fill_queue_entries 32 +--order_beyond_bus 1 +--set_off_path_confirmed 1 +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--bus_width_in_bytes 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 +--chip_cycle_time 312500 +--issue_width 6 +--rs_fill_width 0 +--node_table_size 224 +--node_ret_width 6 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 +--decode_cycles 5 +--map_cycles 5 +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--fetch_across_cache_lines 1 +--fetch_off_path_ops 0 +--fetch_break_on_taken 1 +--fetch_taken_bubble_cycles 0 +--stores_do_not_block_window 1 +--prefs_do_not_block_window 1 +--cbp_trace_r0 /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir/trace/drmemtrace.sgcc_base.mytest-m64.555062.3859.trace.gz +--memtrace_modules_log /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir/raw +--debug_cycle_start 0 +--debug_cycle_stop -1 +--debug_inst_start 0 +--debug_inst_stop -1 +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--bp_mech tagescl +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 +--btb_off_path_writes 1 +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_length 64 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 +--pref_framework_on 1 +--pref_shared_queues 0 +--pref_ul1req_queue_overwrite_on_full 1 +--pref_train_on_pref_misses 0 +--pref_oracle_train_on 0 +--pref_throttlefb_on 1 +--pref_acc_thresh_1 0.75 +--pref_acc_thresh_2 0.4 +--pref_acc_thresh_3 0.4 +--pref_update_interval 8192 +--pref_timely_thresh 0.01 +--pref_polpf_thresh 0.005 +--pref_sms_on 0 +1 1 1 1 1 1 1 + +--- Cut out everything below to use this file as PARAMS.in --- + +Parameter status at compile time and values supplied on the command line: + +SIM_MODE 0 full +SIM_MODEL 0 cmp +FRONTEND FE_PIN_EXEC_DRIVEN memtrace +INST_LIMIT NULL 100000000 +SIM_LIMIT "none" none +FORWARD_PROGRESS_LIMIT 100000000 +FORWARD_PROGRESS_INTERVAL 10000 +FAST_FORWARD 0 +FAST_FORWARD_UNTIL_ADDR 0 +FAST_FORWARD_TRACE_INS 0 +WARMUP 0 +HEARTBEAT_INTERVAL 1000000 +NUM_HEARTBEATS 0 +FILE_TAG "" +OUTPUT_DIR "." +STATUS_FILE NULL +BINDIR NULL +DUMP_PARAMS TRUE 1 +DUMP_STATS TRUE 1 +DUMP_TRACE FALSE 0 +CLEAR_STATS "never" +STATS_TO_TRACE NULL +STAT_TRACE_FILE "stats.trace" +STAT_TRACE_INTERVAL "i:100000" +PIPEVIEW FALSE +PIPEVIEW_FILE "pipeview" +MEMVIEW FALSE +MEMVIEW_FILE "memview.out" +MEMVIEW_START "never" +INST_HASH_TABLE_SIZE 500021 const +STDOUT_FILE NULL +STDERR_FILE NULL +PIN_EXEC_DRIVEN_FE_SOCKET "./pin_exec_driven_fe_socket.temp" +PRINT_PID FALSE +USE_UNSURE_FREE_LISTS FALSE +OPTIMIZER2_MAX_NUM_SLAVES 64 +OPTIMIZER2_PERFECT_MEMORYLESS FALSE +EXIT_COND 0 +ENABLE_SWPRF FALSE +MLC_PRESENT FALSE 0 +MLC_SIZE (512 * 1024) +MLC_ASSOC 4 +MLC_LINE_SIZE 64 +MLC_CYCLES 12 +PERFECT_MLC FALSE +MLC_READ_PORTS 1 +MLC_WRITE_PORTS 1 +MLC_BANKS 8 +MLC_INTERLEAVE_FACTOR 64 +MLC_CACHE_REPL_POLICY 0 +MLC_WRITE_THROUGH FALSE +PREFETCH_UPDATE_LRU_MLC TRUE +FORCE_L1_MISS FALSE +L1_SIZE (4 * 1024 * 1024) 1048576 +L1_ASSOC 8 8 +L1_LINE_SIZE 64 64 +L1_CYCLES 24 18 +PERFECT_L1 FALSE +PRIVATE_L1 FALSE +L1_READ_PORTS 1 +L1_WRITE_PORTS 1 +L1_BANKS 8 1 +L1_INTERLEAVE_FACTOR 64 64 +L1_CACHE_REPL_POLICY 0 +L1_WRITE_THROUGH FALSE +L1_IGNORE_WB FALSE +L1_USE_CORE_FREQ FALSE +MARK_L1_MISSES TRUE +PREFETCH_UPDATE_LRU_L1 TRUE +MEMORY_RANDOM_ADDR FALSE +VA_PAGE_SIZE_BYTES 4096 4096 +NUM_ADDR_NON_SIGN_EXTEND_BITS 48 +ADDR_TRANSLATION 0 random +CONSTANT_MEMORY_LATENCY FALSE +MEMORY_CYCLES 100 +STALL_MEM_REQS_ONLY FALSE +ICACHE_SIZE (64 * 1024) 32768 +ICACHE_ASSOC 4 4 +ICACHE_LINE_SIZE 64 64 +PERFECT_ICACHE FALSE +ICACHE_READ_PORTS 2 +ICACHE_WRITE_PORTS 1 +ICACHE_BANKS 8 +ICACHE_REPL 0 +DCACHE_SIZE (64 * 1024) 32768 +DCACHE_ASSOC 1 4 +DCACHE_LINE_SIZE 64 64 +DCACHE_CYCLES 2 +PERFECT_DCACHE FALSE +DCACHE_READ_PORTS 8 2 +DCACHE_WRITE_PORTS 1 1 +DCACHE_BANKS 1 1 +DCACHE_REPL 0 +DCACHE_REPL_PREF_THRESH 1 +MEM_OOO_STORES TRUE 1 +MEM_OBEY_STORE_DEP TRUE 1 +PREF_INSERT_LRU FALSE +PREF_INSERT_MIDDLE FALSE +PREF_INSERT_LOWQTR FALSE +PREF_INSERT_DYNACC FALSE +MEM_REQ_BUFFER_ENTRIES 32 32 +PRIVATE_MSHR_ON TRUE +MEM_PRIORITY_IFETCH 0 0 +MEM_PRIORITY_DFETCH 0 1 +MEM_PRIORITY_DSTORE 0 2 +MEM_PRIORITY_IPRF 9 3 +MEM_PRIORITY_DPRF 10 4 +MEM_PRIORITY_WB 0 5 +MEM_PRIORITY_WB_NODIRTY 0 5 +PROMOTE_TO_HIGHER_PRIORITY_MEM_REQ_TYPE FALSE 1 +MEM_REQ_BUFFER_PREF_WATERMARK 0 4 +MEM_REQ_BUFFER_WB_VALVE 2 +MEM_L1_FILL_QUEUE_ENTRIES 32 32 +MEM_BUS_OUT_QUEUE_PARTITION_ENABLE FALSE +MEM_MEM_QUEUE_PARTITION_ENABLE FALSE +MEM_BUS_OUT_QUEUE_AS_FIFO TRUE +OLDEST_FIRST_TO_MEM_QUEUE TRUE +ROUND_ROBIN_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE_TH 0 +L1_CYCLE_TIME 312500 +MLCQ_TO_L1Q_TRANSFER_LATENCY 1 +L1Q_TO_FSB_TRANSFER_LATENCY 1 +PRIORITIZE_PREFETCHES_WITH_UNIQUE FALSE +KICKOUT_PREFETCHES FALSE +KICKOUT_LOOK_FOR_OLDEST_FIRST FALSE +KICKOUT_OLDEST_PREFETCH FALSE +KICKOUT_OLDEST_PREFETCH_WITHIN_BANK FALSE +ORDER_BEYOND_BUS FALSE 1 +ALL_FIFO_QUEUES FALSE +QUEUE_MLC_SIZE 0 +QUEUE_L1_SIZE 0 +QUEUE_BUS_OUT_SIZE 0 +QUEUE_CORE_FILL_SIZE 0 +ALLOW_TYPE_MATCHES FALSE +STREAM_PREFETCH_ON FALSE +DC_PREF_CACHE_ENABLE FALSE +DC_PREF_CACHE_CYCLE 0 +PREF_INSERT_DCACHE_IMM TRUE +DC_PREF_CACHE_SIZE (64 * 1024) +DC_PREF_CACHE_ASSOC 4 +DC_PREF_ONLY_L1HIT FALSE +PREF_CACHE_USE_RDY_CYCLE FALSE +IC_PREF_CACHE_ENABLE FALSE +IC_PREF_CACHE_SIZE (64 * 1024) +IC_PREF_CACHE_ASSOC 4 +L1_PREF_CACHE_ENABLE FALSE +L1_PREF_CACHE_SIZE (1024 * 1024) +L1_PREF_CACHE_ASSOC 8 +SET_OFF_PATH_CONFIRMED FALSE 1 +USE_CONFIRMED_OFF FALSE +PREFCACHE_MOVE_OFFPATH FALSE +CACHE_STAT_ENABLE FALSE +PREF_DCACHE_HIT_FILL_L1 TRUE +PREF_ICACHE_HIT_FILL_L1 TRUE +CRITICAL_ACCESS_PLOT_ENABLE FALSE +CRITICAL_ACCESS_PLOT_FILE "critical_access_plot.dat" +ROUND_ROBIN_TO_L1 FALSE +PREF_I_TOGETHER FALSE +ONE_MORE_CACHE_LINE_ENABLE FALSE +L1_STATIC_PARTITION_ENABLE 0 +L1_STATIC_PARTITION NULL +L1_DYNAMIC_PARTITION_ENABLE FALSE +L1_DYNAMIC_PARTITION_POLICY 0 +PARTITION_UMON_DSS_PREF_ENABLE FALSE +L1_CACHE_HIT_POSITION_COLLECT FALSE +L1_PART_ON FALSE +L1_PART_TRIGGER "c:1000000" +L1_PART_START "t:0" +L1_PART_WARMUP FALSE +L1_PART_SHADOW_WARMUP FALSE +L1_PART_METRIC 0 +L1_PART_SEARCH 0 +L1_PART_USE_STALLING TRUE +L1_PART_FILL_DELAY 0 +L1_SHADOW_TAGS_MODULO 1 +HIER_MSHR_ON FALSE +PERF_PRED_ENABLE FALSE +PERF_PRED_MECH PERF_PRED_CP +PERF_PRED_REQ_LATENCY_MECH PERF_PRED_REQ_LATENCY_MECH_REQ_LATENCY +PERF_PRED_COUNT_ALL FALSE +PERF_PRED_COUNT_INST_MISSES TRUE +PERF_PRED_COUNT_PREFETCHES FALSE +PERF_PRED_COUNT_OFFPATH_REQS FALSE +PERF_PRED_COUNT_BW_REQS TRUE +PERF_PRED_UPDATE_MEM_REQ_TYPE FALSE +PERF_PRED_SLACK_PERIOD_SIZE 32 +PERF_PRED_REQS_FINISH_AT_FILL FALSE +PERF_PRED_MEM_UTIL_VIA_BUS_BW FALSE +PERF_PRED_CHIP_UTIL_VIA_MEM_STALL FALSE +DUMB_MODEL_AVG_REQ_DISTANCE 100 +DUMB_MODEL_RANDOMIZE_DISTANCE FALSE +DUMB_MODEL_AVG_REQ_DISTANCE_PER_CORE NULL +DUMB_MODEL_AVG_ROW_HITS 1 +DUMB_MODEL_AVG_ROW_HITS_PER_CORE NULL +DUMB_MODEL_MLP 1 +DUMB_MODEL_MLP_PER_CORE NULL +RAMULATOR_STANDARD "DDR4" DDR4 +RAMULATOR_SPEED "DDR4_2400R" DDR4_2400R +RAMULATOR_ORG "DDR4_8Gb_x8" DDR4_8Gb_x8 +RAMULATOR_CHANNELS 1 1 +RAMULATOR_RANKS 1 1 +RAMULATOR_BANKGROUPS 4 4 +RAMULATOR_BANKS 4 4 +RAMULATOR_CHIP_WIDTH 8 8 +BUS_WIDTH_IN_BYTES 8 8 +RAMULATOR_ROWS 65536 65536 +RAMULATOR_COLS 1024 1024 +RAMULATOR_SCHEDULING_POLICY "FRFCFS_Cap" FRFCFS_Cap +RAMULATOR_READQ_ENTRIES 32 32 +RAMULATOR_WRITEQ_ENTRIES 32 32 +RAMULATOR_REC_CMD_TRACE "off" FALSE +RAMULATOR_PRINT_CMD_TRACE "off" FALSE +RAMULATOR_USE_REST_OF_ADDR_AS_ROW_ADDR "on" +RAMULATOR_TCK 833333 833333 +RAMULATOR_TCL 16 16 +RAMULATOR_TCCD 6 6 +RAMULATOR_TCCDS 4 4 +RAMULATOR_TCCDL 6 6 +RAMULATOR_TCWL 12 12 +RAMULATOR_TBL 4 4 +RAMULATOR_TWTR 9 9 +RAMULATOR_TWTRS 3 3 +RAMULATOR_TWTRL 9 9 +RAMULATOR_TRP 16 16 +RAMULATOR_TRPpb 16 16 +RAMULATOR_TRPab 16 16 +RAMULATOR_TRCD 16 16 +RAMULATOR_TRCDR 16 16 +RAMULATOR_TRCDW 16 16 +RAMULATOR_TRAS 39 39 +DRAM_TECH_IN_NM 32 32 +DVFS_ON FALSE +DVFS_METRIC DVFS_METRIC_NUM_ELEMS +DVFS_CONFIGS NULL +DVFS_CONFIG_FILE NULL +DVFS_START "t:0" +DVFS_PERIOD "t:312500000000" +DVFS_LOG TRUE +DVFS_INDIVIDUAL_CORES FALSE +DVFS_CHIP_LEVEL FALSE +DVFS_STATIC NULL +DVFS_FORCE_CONFIG NULL +DVFS_REPLAY_CONFIG_TRACE NULL +DVFS_USE_ORACLE FALSE +DVFS_USE_BW_SHARING FALSE +DVFS_USE_DRAM_SHARING FALSE +DVFS_USE_STALL_TIME FALSE +DVFS_DRAM_SHARING_SOLVER_BIN NULL +DVFS_DRAM_SHARING_SOLVER_STRICT TRUE +DVFS_BW_SHARING_BUS_UTIL_THRESH 0.95 +DVFS_BW_SHARING_MAX_REQS 28.0 +DVFS_BW_SHARING_MAX_RW_COST 0.25 +DVFS_BW_SHARING_NO_PREF_STALL TRUE +DVFS_BW_SHARING_CRIT_STATS TRUE +DVFS_COUNT_L1_ACCESS_STALL FALSE +NUM_CORES 1 +CHIP_CYCLE_TIME 312500 312500 +CORE_0_CYCLE_TIME 312500 +CORE_1_CYCLE_TIME 312500 +CORE_2_CYCLE_TIME 312500 +CORE_3_CYCLE_TIME 312500 +CORE_4_CYCLE_TIME 312500 +CORE_5_CYCLE_TIME 312500 +CORE_6_CYCLE_TIME 312500 +CORE_7_CYCLE_TIME 312500 +CORE_8_CYCLE_TIME 312500 +CORE_9_CYCLE_TIME 312500 +CORE_10_CYCLE_TIME 312500 +CORE_11_CYCLE_TIME 312500 +CORE_12_CYCLE_TIME 312500 +CORE_13_CYCLE_TIME 312500 +CORE_14_CYCLE_TIME 312500 +CORE_15_CYCLE_TIME 312500 +CORE_16_CYCLE_TIME 312500 +CORE_17_CYCLE_TIME 312500 +CORE_18_CYCLE_TIME 312500 +CORE_19_CYCLE_TIME 312500 +CORE_20_CYCLE_TIME 312500 +CORE_21_CYCLE_TIME 312500 +CORE_22_CYCLE_TIME 312500 +CORE_23_CYCLE_TIME 312500 +CORE_24_CYCLE_TIME 312500 +CORE_25_CYCLE_TIME 312500 +CORE_26_CYCLE_TIME 312500 +CORE_27_CYCLE_TIME 312500 +CORE_28_CYCLE_TIME 312500 +CORE_29_CYCLE_TIME 312500 +CORE_30_CYCLE_TIME 312500 +CORE_31_CYCLE_TIME 312500 +CORE_32_CYCLE_TIME 312500 +CORE_33_CYCLE_TIME 312500 +CORE_34_CYCLE_TIME 312500 +CORE_35_CYCLE_TIME 312500 +CORE_36_CYCLE_TIME 312500 +CORE_37_CYCLE_TIME 312500 +CORE_38_CYCLE_TIME 312500 +CORE_39_CYCLE_TIME 312500 +CORE_40_CYCLE_TIME 312500 +CORE_41_CYCLE_TIME 312500 +CORE_42_CYCLE_TIME 312500 +CORE_43_CYCLE_TIME 312500 +CORE_44_CYCLE_TIME 312500 +CORE_45_CYCLE_TIME 312500 +CORE_46_CYCLE_TIME 312500 +CORE_47_CYCLE_TIME 312500 +CORE_48_CYCLE_TIME 312500 +CORE_49_CYCLE_TIME 312500 +CORE_50_CYCLE_TIME 312500 +CORE_51_CYCLE_TIME 312500 +CORE_52_CYCLE_TIME 312500 +CORE_53_CYCLE_TIME 312500 +CORE_54_CYCLE_TIME 312500 +CORE_55_CYCLE_TIME 312500 +CORE_56_CYCLE_TIME 312500 +CORE_57_CYCLE_TIME 312500 +CORE_58_CYCLE_TIME 312500 +CORE_59_CYCLE_TIME 312500 +CORE_60_CYCLE_TIME 312500 +CORE_61_CYCLE_TIME 312500 +CORE_62_CYCLE_TIME 312500 +CORE_63_CYCLE_TIME 312500 +ISSUE_WIDTH 4 6 +RS_FILL_WIDTH 8 0 +NODE_TABLE_SIZE 256 224 +NODE_RET_WIDTH 4 6 +NODE_RETIRE_RATE 10 +RS_SIZES "256" 97 +RS_CONNECTIONS "xF" 0 +FU_TYPES "0, 0, 0, 0" 0 0 0 0 0 0 0 0 +DECODE_CYCLES 1 5 +MAP_CYCLES 1 5 +EXTRA_RECOVERY_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after recovery. +EXTRA_REDIRECT_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after redirect. +EXTRA_CALLSYS_CYCLES 20 const +DIE_ON_CALLSYS FALSE +DIE_ON_RET_STALL_THRESH 0 +DIE_ON_RET_STALL_CORE 0 +DIE_ON_MEM_BLOCK_THRESH 0 +DIE_ON_MEM_BLOCK_CORE 0 +FETCH_ACROSS_CACHE_LINES FALSE 1 +FETCH_OFF_PATH_OPS TRUE 0 +FETCH_BREAK_ON_TAKEN FALSE 1 +FETCH_TAKEN_BUBBLE_CYCLES 0 0 +WP_COLLECT_STATS FALSE +SWITCH_IC_FETCH_ON_RECOVERY TRUE +OP_INV_DELAY 1 +OP_NOP_DELAY 1 +OP_CF_DELAY 1 +OP_MOV_DELAY 1 +OP_CMOV_DELAY 1 +OP_LDA_DELAY 1 +OP_IMEM_DELAY 1 +OP_IADD_DELAY 1 +OP_IMUL_DELAY 3 +OP_IDIV_DELAY -20 +OP_ICMP_DELAY 1 +OP_LOGIC_DELAY 1 +OP_SHIFT_DELAY 1 +OP_FMEM_DELAY 1 +OP_FCVT_DELAY 3 +OP_FADD_DELAY 3 +OP_FMUL_DELAY 5 +OP_FMA_DELAY 5 +OP_FDIV_DELAY -20 +OP_FCMP_DELAY 3 +OP_FCMOV_DELAY 1 +OP_GATHER_DELAY 12 +OP_SCATTER_DELAY 18 +OP_PIPELINED_FAST_DELAY 2 +OP_PIPELINED_MEDIUM_DELAY 5 +OP_PIPELINED_SLOW_DELAY 10 +OP_NOTPIPELINED_MEDIUM_DELAY -5 +OP_NOTPIPELINED_SLOW_DELAY -20 +OP_NOTPIPELINED_VERY_SLOW_DELAY -100 +UNIFORM_OP_DELAY 0 +STALL_ON_WAIT_MEM TRUE +STORES_DO_NOT_BLOCK_WINDOW FALSE 1 +PREFS_DO_NOT_BLOCK_WINDOW FALSE 1 +OBEY_REG_DEP TRUE +OLDEST_FIRST_SCHED FALSE +FIND_EMPTIEST_RS FALSE +TRACK_L1_MISS_DEPS FALSE +CBP_TRACE_R0 NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir/trace/drmemtrace.sgcc_base.mytest-m64.555062.3859.trace.gz +CBP_TRACE_R1 NULL +CBP_TRACE_R2 NULL +CBP_TRACE_R3 NULL +CBP_TRACE_R4 NULL +CBP_TRACE_R5 NULL +CBP_TRACE_R6 NULL +CBP_TRACE_R7 NULL +CBP_TRACE_R8 NULL +CBP_TRACE_R9 NULL +CBP_TRACE_R10 NULL +CBP_TRACE_R11 NULL +CBP_TRACE_R12 NULL +CBP_TRACE_R13 NULL +CBP_TRACE_R14 NULL +CBP_TRACE_R15 NULL +CBP_TRACE_R16 NULL +CBP_TRACE_R17 NULL +CBP_TRACE_R18 NULL +CBP_TRACE_R19 NULL +CBP_TRACE_R20 NULL +CBP_TRACE_R21 NULL +CBP_TRACE_R22 NULL +CBP_TRACE_R23 NULL +CBP_TRACE_R24 NULL +CBP_TRACE_R25 NULL +CBP_TRACE_R26 NULL +CBP_TRACE_R27 NULL +CBP_TRACE_R28 NULL +CBP_TRACE_R29 NULL +CBP_TRACE_R30 NULL +CBP_TRACE_R31 NULL +CBP_TRACE_R32 NULL +CBP_TRACE_R33 NULL +CBP_TRACE_R34 NULL +CBP_TRACE_R35 NULL +CBP_TRACE_R36 NULL +CBP_TRACE_R37 NULL +CBP_TRACE_R38 NULL +CBP_TRACE_R39 NULL +CBP_TRACE_R40 NULL +CBP_TRACE_R41 NULL +CBP_TRACE_R42 NULL +CBP_TRACE_R43 NULL +CBP_TRACE_R44 NULL +CBP_TRACE_R45 NULL +CBP_TRACE_R46 NULL +CBP_TRACE_R47 NULL +CBP_TRACE_R48 NULL +CBP_TRACE_R49 NULL +CBP_TRACE_R50 NULL +CBP_TRACE_R51 NULL +CBP_TRACE_R52 NULL +CBP_TRACE_R53 NULL +CBP_TRACE_R54 NULL +CBP_TRACE_R55 NULL +CBP_TRACE_R56 NULL +CBP_TRACE_R57 NULL +CBP_TRACE_R58 NULL +CBP_TRACE_R59 NULL +CBP_TRACE_R60 NULL +CBP_TRACE_R61 NULL +CBP_TRACE_R62 NULL +CBP_TRACE_R63 NULL +MEMTRACE_MODULES_LOG NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir/raw +DUMB_CORE_ON FALSE +DUMB_CORE 1 +DEBUG_CYCLE_START 0 0 +DEBUG_CYCLE_STOP 0 -1 +DEBUG_TIME_START 0 +DEBUG_TIME_STOP 0 +DEBUG_INST_START 0 0 +DEBUG_INST_STOP 0 -1 +DEBUG_OP_START 0 +DEBUG_OP_STOP 0 +DEBUG_CACHE_LIB FALSE +DEBUG_HASH_LIB FALSE +DEBUG_LIST_LIB FALSE +DEBUG_PORT_LIB FALSE +DEBUG_BUS_LIB FALSE +DEBUG_OP_POOL FALSE +DEBUG_ORACLE FALSE +DEBUG_FRONTEND FALSE +DEBUG_ADDR_TRANS FALSE +DEBUG_BP FALSE +DEBUG_BP_DIR FALSE +DEBUG_BTB FALSE +DEBUG_CRS FALSE +DEBUG_MAP FALSE +DEBUG_MEMORY FALSE +DEBUG_REPLAY FALSE +DEBUG_FREQ FALSE +DEBUG_MODEL FALSE +DEBUG_THREAD FALSE +DEBUG_ICACHE_STAGE FALSE +DEBUG_DECODE_STAGE FALSE +DEBUG_MAP_STAGE FALSE +DEBUG_NODE_STAGE FALSE +DEBUG_EXEC_STAGE FALSE +DEBUG_DCACHE_STAGE FALSE +DEBUG_RETIRED_UOPS FALSE +DEBUG_EXC_INSERTS FALSE +DEBUG_BP_CONF FALSE +DEBUG_ONPATH_CONF FALSE +DEBUG_STREAM FALSE +DEBUG_STREAM_MEM FALSE +DEBUG_WAY FALSE +DEBUG_L2MARKV FALSE +DEBUG_L2L1PREF FALSE +DEBUG_PERF_PRED FALSE +DEBUG_POWER_UTILS FALSE +DEBUG_DVFS FALSE +DEBUG_TRACE_READ FALSE +DEBUG_INST_FIELDS FALSE +DEBUG_OP_FIELDS FALSE +DEBUG_PIN_EXEC_DRIVEN FALSE +DEBUG_CACHE_PART FALSE +DEBUG_OPTIMIZER2 FALSE +DEBUG_PREF FALSE +PERFECT_BP FALSE +PERFECT_BTB FALSE +PERFECT_IBP FALSE +PERFECT_CRS FALSE +PERFECT_CBR_BTB FALSE +PERFECT_NT_BTB FALSE +CFS_PER_CYCLE 3 6 # Number of branches that can be predicted in a single cycle +UPDATE_BP_OFF_PATH FALSE 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +BP_UPDATE_AT_RETIRE FALSE 0 # Update the BP at retire. If false, update at the end of exec. +BP_MECH 0 tagescl +LATE_BP_MECH NUM_BP +LATE_BP_LATENCY 5 +HIST_LENGTH 16 +PHT_CTR_BITS 2 const +BHT_ENTRIES (4 * 1024) +BHT_ASSOC 4 +HYBRIDS_INDEX_LENGTH 16 +HYBRIDG_HIST_LENGTH 16 +HYBRIDP_HIST_LENGTH 16 +FILTER_INDEX_LENGTH 16 +USE_FILTER FALSE +INF_HYBRIDGP FALSE +BP_HASH_TOS FALSE +IBTB_HASH_TOS FALSE +BTB_MECH 0 generic +BTB_ENTRIES (4 * 1024) 4096 +BTB_ASSOC 4 4 +BTB_OFF_PATH_WRITES TRUE 1 +ENABLE_CRS TRUE 1 +CRS_ENTRIES 32 32 +CRS_REALISTIC 0 1 +ENABLE_IBP TRUE 1 # Enable the indirect branch predictor +USE_PAT_HIST TRUE +IBTB_MECH 1 tc_tagged +IBTB_HIST_LENGTH 16 +IBTB_OFF_PATH_WRITES TRUE 1 # Allow off path ops to update the ibtb. +TARGETS_IN_HIST 4 +TC_ENTRIES (4 * 1024) 4096 +TC_ASSOC 4 4 +NUM_CORR_BRANCHES 3 +SEL_HIST_BP_ENTRIES 8192 +SEL_HIST_LENGTH 16 +SEL_HIST_DYN_CNT_TH 16 +SEL_HIST_MISPRED_TH 4 +ENABLE_BP_CONF FALSE +CONF_MECH 0 +PERF_BP_CONF_PRED FALSE +BPC_BITS 16 +BPC_MECH 1 +BPC_CTR_RESET TRUE +BPC_CIT_BITS 8 +BPC_CIT_TH 50 +BPC_CTR_BITS 3 +OPC_COUNT_ZEROS FALSE +OPC_COUNT_THRESH 10 +INF_LOOP FALSE +INF_LOOP_BUCKETS 811 +LOOP_ENTRIES (4 * 1024) +LOOP_ASSOC 4 +LOOP_COUNT_MAX 127 +LOOP_REPEAT_MAX 15 +KNOB_PRINT_BRINFO FALSE +BR_MISPRED_FILE NULL +CONF_PERCEPTRON_TH 0 +CONF_PERCEPTRON_CTR_BITS 8 +CONF_PERCEPTRON_ENTRIES 127 +CONF_PERCEPTRON_THRESH_OVRD 0 +CONF_HIST_LENGTH 32 +PERCEPTRON_CONF_USE_CONF FALSE +PERCEPTRON_CONF_TRAIN_HIS FALSE +PERCEPTRON_CONF_TRAIN_CONF FALSE +PERCEPTRON_CONF_TRAIN_OFFSET_CONF FALSE +PERCEPTRON_TRAIN_MISP_FACTOR 1 +PERCEPTRON_TRAIN_CORR_FACTOR 1 +PERCEPTRON_CONF_HIS_BOTH FALSE +PERCEPTRON_CONF_HIS_BOTH_LENGTH 4 +ENABLE_ICACHE_PACKET_BREAKING TRUE +NUM_LOAD_STORE_PER_PACKET 0 +PACKET_BREAK_ON_FUS FALSE +PACKET_BREAK_FU_TYPES "G,G,G,G,G,G,G,G,G,G,G,G" +POWER_INTF_ON FALSE +POWER_INTF_ENABLE_SCALING FALSE +POWER_INTF_EXEC "power/power_intf.py" +POWER_INTF_REF_CHIP_TECH_NM 22 +POWER_INTF_REF_CHIP_FREQ (3.2e9) +POWER_INTF_REF_MEMORY_FREQ (0.8e9) +POWER_OTHER (0.0) +PREF_STREAM_ON FALSE 1 +PREF_STREAM_PER_CORE_ENABLE FALSE 1 +STREAM_BUFFER_N 16 +STREAM_PREFETCH_N 2 4 +STREAM_START_DIS 5 1 +STREAM_LENGTH 16 64 +STREAM_FULL_N 1 +STREAM_TRAIN_LENGTH 16 +STREAM_TRAIN_NUM 1 4 +PREF_ACC_USE_CACHE FALSE +STREAM_STALL_ON_QUEUE_FULL FALSE +PREF_SCHEDULE_NUM 4 +TRAIN_FILTER_SIZE 32 +PREF_REQ_Q_SIZE 64 +STREAM_CREATE_ON_DC_MISS FALSE 0 +STREAM_CREATE_ON_L1_MISS TRUE 1 +STREAM_TRAIN_ON_WRONGPATH TRUE +STREAM_CREATE_ON_WRONGPATH TRUE +STREAM_PREF_INTO_DCACHE FALSE +REMOVE_REDUNDANT_STREAM FALSE +L2HIT_STREAM_SCHEDULE_NUM 4 +PREF_REQ_QUEUE_FILTER_ON FALSE +HW_PREF_HIT_TRAIN_STREAM FALSE +L2HIT_STREAM_BUFFER_N 32 +L2HIT_STREAM_PREFETCH_N 2 +L2HIT_STREAM_START_DIS 2 +L2HIT_STREAM_LENGTH 8 +L2HIT_PREF_REQ_Q_SIZE 128 +L2HIT_L2ACCESS_REQ_Q_SIZE 64 +PREF_STREAM_ACCPERSTREAM FALSE +PREF_ACC_DISTANCE_10 128 +PREF_FRAMEWORK_ON FALSE 1 +PREF_TRACE_ON FALSE +PREF_DL0REQ_QUEUE_SIZE 32 +PREF_UMLC_REQ_QUEUE_SIZE 64 +PREF_UL1REQ_QUEUE_SIZE 128 +PREF_SHARED_QUEUES TRUE 0 +PREF_DL0_MISS_ON TRUE +PREF_DL0_HIT_ON TRUE +PREF_DL0REQ_QUEUE_FILTER_ON TRUE +PREF_UMLC_REQ_QUEUE_FILTER_ON TRUE +PREF_UL1REQ_QUEUE_FILTER_ON TRUE +PREF_DL0REQ_ADD_FILTER_ON TRUE +PREF_UMLC_REQ_ADD_FILTER_ON TRUE +PREF_UL1REQ_ADD_FILTER_ON TRUE +PREF_DL0REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UMLC_REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UL1REQ_QUEUE_OVERWRITE_ON_FULL FALSE 1 +PREF_DL0SCHEDULE_NUM 4 +PREF_UMLC_SCHEDULE_NUM 4 +PREF_UL1SCHEDULE_NUM 4 +PREF_L1Q_DEMAND_RESERVE 0 +PREF_REPORT_PREF_MATCH_AS_MISS FALSE +PREF_REPORT_PREF_MATCH_AS_HIT TRUE +PREF_UPDATE_ON_WRONGPATH TRUE +PREF_TRAIN_ON_PREF_MISSES FALSE 0 +PREF_ORACLE_TRAIN_ON FALSE 0 +PREF_REQ_DROP FALSE +PREF_THROTTLE_ON FALSE +PREF_THROTTLEFB_ON FALSE 1 +PREF_ACC_THRESH_1 0.90 0.75 +PREF_ACC_THRESH_2 0.70 0.4 +PREF_ACC_THRESH_3 0.60 0.4 +PREF_ACC_THRESH_4 0.40 +PREF_UPDATE_INTERVAL 0 8192 +PREF_ANALYZE_LOAD FALSE +PREF_POL_THRESH_1 0.25 +PREF_POL_THRESH_2 0.10 +PREF_POLBV_ON FALSE +PREF_POLBV_SIZE 1024 +PREF_TIMELY_THRESH 0.05 0.01 +PREF_POLPF_THRESH 0.01 0.005 +PREF_DEGFB_USEONLYACC FALSE +PREF_DEGFB_USEONLYPOL FALSE +PREF_DEGFB_USEONLYLATE FALSE +PREF_TIMELY_THRESH_2 0.005 +PREF_DEGFB_STATPHASEFILE FALSE +PREF_MAX_DEGFB 4 +PREF_DHAL FALSE +PREF_DHAL_SENTTHRESH 16 +PREF_DHAL_USETHRESH_MAX 12 +PREF_DHAL_USETHRESH_MIN2 8 +PREF_DHAL_USETHRESH_MIN1 4 +PREF_DHAL_MAXDEG 64 +PREF_HFILTER_ON FALSE +PREF_HFILTER_INDEX_BITS 12 +PREF_HFILTER_USE_PC FALSE +PREF_HFILTER_PRED_USELESS_THRES 2 +PREF_HFILTER_RESET_ENABLE FALSE +PREF_HFILTER_RESET_INTERVAL 100000 +L2L1PREF_ON FALSE +L2WAY_PREF FALSE +L2MARKV_PREF_ON FALSE +L2NEXT_PREF_ON FALSE +L2HIT_STREAM_PREF_ON FALSE +L2L1_DC_HIT_TRAIN FALSE +L1_HIT_DUMP_FILE_ON FALSE +L1_HIT_DUMP_WO_TXT FALSE +L1_HIT_DUMPFILE "l1hit_dump.out" +IDEAL_L2_L1_PREFETCHER FALSE +IDEAL_L2_ICACHE_PREFETCHER FALSE +L1WAY_PREF_SEND_QUEUE 4 +L1PREF_REQ_QUEUE_SIZE 1024 +L1PREF_IMMEDIATE FALSE +L1WAY_PREF_TIMER_DIS 1000 +L1MARKV_PREF_SEND_QUEUE 4 +L1PREF_MARKV_REQ_QUEUE_SIZE 1024 +MARKV_L2ACCESS_REQ_Q_SIZE 64 +L1MARKV_PREF_IMMEDIATE FALSE +L1MARKV_PREF_TIMER_DIS 1 +L2L1_HIT_TRAIN TRUE +L1MARKV_REQ_TH 1 +L2L1_IMMEDIATE_PREF_CACHE FALSE +L2L1_FILL_PREF_CACHE FALSE +L2L1_L2_HIT_STAT FALSE +PREF_GHB_ON FALSE +DEBUG_PREF_GHB FALSE +PREF_GHB_BUFFER_N 1024 +PREF_GHB_INDEX_N 128 +PREF_GHB_CZONE_BITS 12 +PREF_GHB_DEGREE 16 +PREF_GHB_MAX_DEGREE 32 +PREF_STRIDE_ON FALSE +DEBUG_PREF_STRIDE FALSE +PREF_STRIDE_TABLE_N 1024 +PREF_STRIDE_REGION_BITS 16 +PREF_STRIDE_DEGREE 4 +PREF_STRIDE_DISTANCE 16 +PREF_STRIDE_STARTDISTANCE 1 +PREF_STRIDE_SINGLE_THRESH 6 +PREF_STRIDE_MULTI_THRESH 6 +PREF_STRIDE_SINGLE_STRIDE_MODE FALSE +PREF_STRIDEPC_ON FALSE +DEBUG_PREF_STRIDEPC FALSE +PREF_STRIDEPC_TABLE_N 1024 +PREF_STRIDEPC_DEGREE 4 +PREF_STRIDEPC_DISTANCE 16 +PREF_STRIDEPC_USELOADADDR FALSE +PREF_STRIDEPC_TRAINNUM 2 +PREF_STRIDEPC_STARTDIS 4 +PREF_PHASE_ON FALSE +PREF_PHASE_STUDY FALSE +DEBUG_PREF_PHASE FALSE +PREF_PHASE_PRIME_HASH 16381 +PREF_PHASE_INFOSIZE 16384 +PREF_PHASE_LOG2REGIONSIZE 12 +PREF_PHASE_REGIONENTRIES 64 +PREF_PHASE_TRACKEDREGIONS 32 +PREF_PHASE_INTERVAL 100000 +PREF_PHASE_TABLE_SIZE 64 +PREF_PHASE_MAXDIFF_THRESH 64 +PREF_PHASE_MIN_MISSES 64 +PREF_PHASE_MISSPER 0.4 +PREF_2DC_ON FALSE +DEBUG_PREF_2DC FALSE +PREF_2DC_CACHE_SIZE (1 * 1024) +PREF_2DC_CACHE_ASSOC 4 +PREF_2DC_CACHE_LINE_SIZE 1 +PREF_2DC_DEGREE 16 +PREF_2DC_ZONE_SHIFT 10 +PREF_2DC_TAG_SIZE 16 +PREF_2DC_NUM_REGIONS 64 +PREF_2DC_REGION_HASH 61 +PREF_MARKOV_ON FALSE +DEBUG_PREF_MARKOV FALSE +PREF_MARKOV_NUM_ENTRIES 65536 +PREF_MARKOV_NUM_NEXT_STATES 8 +PREF_MARKOV_SEND_ON_PREF_HIT TRUE +PREF_MARKOV_UPDATE_ON_PREF_HIT TRUE +PREF_MARKOV_TABLE_UPDATE_POLICY 0 +PREF_MARKOV_SEND_THRESHOLD 0 +PREF_SMS_ON FALSE 0 +PREF_SMS_AT_SIZE 64 +PREF_SMS_FT_SIZE 64 +PREF_SMS_PHT_SIZE 16384 +PREF_SMS_PRF_SIZE 1024 +PREF_SMS_REGION_SIZE 2048 diff --git a/labs/LAB5/runs/sgcc_base-sms0/bp.stat.0.out b/labs/LAB5/runs/sgcc_base-sms0/bp.stat.0.out new file mode 100644 index 00000000..139d4160 --- /dev/null +++ b/labs/LAB5/runs/sgcc_base-sms0/bp.stat.0.out @@ -0,0 +1,752 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 80868545 Instructions: 100000000 IPC: 1.23657 + +BTB_ON_PATH_MISS 639615 3.161% 639615 3.161% +BTB_ON_PATH_HIT 19595833 96.839% 19595833 96.839% + 20235448 100.000% 20235448 100.000% + 0.97 0.95 0.97 0.95 + +BTB_OFF_PATH_MISS 0 -nan% 0 -nan% +BTB_OFF_PATH_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BTB_ON_PATH_WRITE 639615 100.000% 639615 100.000% +BTB_OFF_PATH_WRITE 0 0.000% 0 0.000% + 639615 100.000% 639615 100.000% + 0.00 0.00 0.00 0.00 + +BP_ON_PATH_CORRECT 19561758 96.671% 19561758 96.671% +BP_ON_PATH_MISPREDICT 13468 0.067% 13468 0.067% +BP_ON_PATH_MISFETCH 660222 3.263% 660222 3.263% + 20235448 100.000% 20235448 100.000% + 0.07 0.35 0.07 0.35 + +BP_OFF_PATH_CORRECT 0 -nan% 0 -nan% +BP_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% +BP_OFF_PATH_MISFETCH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +LATE_BP_ON_PATH_CORRECT 20235448 100.000% 20235448 100.000% +LATE_BP_ON_PATH_MISPREDICT 0 0.000% 0 0.000% +LATE_BP_ON_PATH_MISFETCH 0 0.000% 0 0.000% + 20235448 100.000% 20235448 100.000% + 0.00 0.00 0.00 0.00 + +LATE_BP_OFF_PATH_CORRECT 0 -nan% 0 -nan% +LATE_BP_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% +LATE_BP_OFF_PATH_MISFETCH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_PVN 0 -nan% 0 -nan% +BP_ON_PATH_CONF_PVN_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_PVP 0 -nan% 0 -nan% +BP_ON_PATH_CONF_PVP_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_SPEC 0 -nan% 0 -nan% +BP_ON_PATH_CONF_SPEC_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CRS_MISS_ON_PATH 139253 6.373% 139253 6.373% +CRS_HIT_ON_PATH 2045730 93.627% 2045730 93.627% + 2184983 100.000% 2184983 100.000% + 0.94 0.91 0.94 0.91 + +CRS_MISS_OFF_PATH 0 -nan% 0 -nan% +CRS_HIT_OFF_PATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CRS_CLOBBER 21001 21001 + +TARG_ON_PATH_MISS 95701 13.047% 95701 13.047% +TARG_ON_PATH_HIT 637781 86.953% 637781 86.953% + 733482 100.000% 733482 100.000% + 0.87 0.82 0.87 0.82 + +TARG_OFF_PATH_MISS 0 -nan% 0 -nan% +TARG_OFF_PATH_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_ON_PATH_WRITE 733482 100.000% 733482 100.000% +TARG_OFF_PATH_WRITE 0 0.000% 0 0.000% + 733482 100.000% 733482 100.000% + 0.00 0.00 0.00 0.00 + +TARG_HYBRID_CORRECT_TAGLESS 0 -nan% 0 -nan% +TARG_HYBRID_CORRECT_TAGGED 0 -nan% 0 -nan% +TARG_HYBRID_MISPRED_TAGLESS 0 -nan% 0 -nan% +TARG_HYBRID_MISPRED_TAGGED 0 -nan% 0 -nan% +TARG_HYBRID_NO_PRED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_VP_INDIRECT_MISPRED 0 -nan% 0 -nan% +TARG_VP_INDIRECT_NOPRED 0 -nan% 0 -nan% +TARG_VP_INDIRECT_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CBR_ON_PATH_CORRECT 13772940 99.902% 13772940 99.902% +CBR_ON_PATH_MISPREDICT 13468 0.098% 13468 0.098% + 13786408 100.000% 13786408 100.000% + 0.00 0.03 0.00 0.03 + +CBR_ON_PATH_CORRECT_PER1000INST 13772940 137.7294 13772940 137.7294 + +CBR_ON_PATH_MISPREDICT_PER1000INST 13468 0.1347 13468 0.1347 + +CBR_OFF_PATH_CORRECT 0 -nan% 0 -nan% +CBR_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PRED_TO_UPDATE_CYCLES_0 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_1 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_2 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_3 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_4 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_5 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_6 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_7 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_8 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_9 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_10 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_11 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_12 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_13 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_14 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_15 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_16 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_17 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_18 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_19 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_20 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_21 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_22 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_23 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_24 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_25 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_26 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_27 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_28 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_29 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_30 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_CORRECTED 0 -nan% 0 -nan% +BP_NOT_CORRECTED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_CORRECTED 0 -nan% 0 -nan% +TARG_NOT_CORRECTED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_MISP_PENALTY 6714504 6714504 + +BP_ON_PATH_CONF_MISPRED 0 -nan% 0 -nan% +BP_ON_PATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_OFF_PATH_CONF_MISPRED 0 -nan% 0 -nan% +BP_OFF_PATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_PRED_MIS_CONF_MISPRED 0 -nan% 0 -nan% +BP_ON_PATH_PRED_MIS_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_PRED_COR_CONF_MISPRED 0 -nan% 0 -nan% +BP_ON_PATH_PRED_COR_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_OFF_PATH_PRED_MIS_CONF_MISPRED 0 -nan% 0 -nan% +BP_OFF_PATH_PRED_MIS_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_OFF_PATH_PRED_COR_CONF_MISPRED 0 -nan% 0 -nan% +BP_OFF_PATH_PRED_COR_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ONPATH_CONF_MISPRED 0 -nan% 0 -nan% +ONPATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ONPATH_ON_PATH_CONF_MISPRED 0 -nan% 0 -nan% +ONPATH_ON_PATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ONPATH_OFF_PATH_CONF_MISPRED 0 -nan% 0 -nan% +ONPATH_OFF_PATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PRED_ONPATH_CONF_MISPRED 0 -nan% 0 -nan% +PRED_ONPATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PRED_OFFPATH_CONF_MISPRED 0 -nan% 0 -nan% +PRED_OFFPATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +LONG_OVWT_MIS 0 -nan% 0 -nan% +LONG_OVWT_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_0_7_MIS 0 -nan% 0 -nan% +OPC_LENGTH_0_7_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_8_15_MIS 0 -nan% 0 -nan% +OPC_LENGTH_8_15_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_16_23_MIS 0 -nan% 0 -nan% +OPC_LENGTH_16_23_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_24_31_MIS 0 -nan% 0 -nan% +OPC_LENGTH_24_31_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_32_39_MIS 0 -nan% 0 -nan% +OPC_LENGTH_32_39_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_40_47_MIS 0 -nan% 0 -nan% +OPC_LENGTH_40_47_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_48_55_MIS 0 -nan% 0 -nan% +OPC_LENGTH_48_55_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_56_63_MIS 0 -nan% 0 -nan% +OPC_LENGTH_56_63_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_64_71_MIS 0 -nan% 0 -nan% +OPC_LENGTH_64_71_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_72_79_MIS 0 -nan% 0 -nan% +OPC_LENGTH_72_79_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_80_MIS 0 -nan% 0 -nan% +OPC_LENGTH_80_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ALL_ONES_MIS 0 -nan% 0 -nan% +ALL_ONES_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan 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+CYCLES_UNDER_NONCRITICAL_MEM_REQ 0 0 + +CHIP_UTILIZATION_UNDER_MEM_REQ 0 -nan 0 -nan + +CHIP_UTILIZATION_UNDER_NO_MEM_REQ 0 -nan 0 -nan + +CHIP_UTILIZATION_UNDER_CRITICAL_MEM_REQ 0 -nan 0 -nan + +CHIP_UTILIZATION_UNDER_NONCRITICAL_MEM_REQ 0 -nan 0 -nan + +CYCLES_NOT_WAITING_FOR_OFF_CHIP 0 0.0000 0 0.0000 + +FUS_BUSY_NOT_WAITING_FOR_OFF_CHIP 0 -nan 0 -nan + +CYCLES_WAITING_FOR_OFF_CHIP 0 0.0000 0 0.0000 + +FUS_BUSY_WAITING_FOR_OFF_CHIP 0 -nan 0 -nan + +TOTAL_OFF_CHIP_DELAYS_LEFT 0 0 + +WRONG_IO_SCHED 0 0 + +DVFS_CONFIG_SWITCH 0 0 + + + diff --git a/labs/LAB5/runs/sgcc_base-sms0/fetch.stat.0.out b/labs/LAB5/runs/sgcc_base-sms0/fetch.stat.0.out new file mode 100644 index 00000000..619eb54f --- /dev/null +++ b/labs/LAB5/runs/sgcc_base-sms0/fetch.stat.0.out @@ -0,0 +1,248 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 80868545 Instructions: 100000000 IPC: 1.23657 + +ICACHE_CYCLE 80868545 80868545 + +TCACHE_CYCLE 0 0 + +ICACHE_CYCLE_ONPATH 66000389 81.614% 66000389 81.614% +ICACHE_CYCLE_OFFPATH 14868156 18.386% 14868156 18.386% + 80868545 100.000% 80868545 100.000% + 0.18 0.36 0.18 0.36 + +FETCH_ON_PATH 28608817 100.000% 28608817 100.000% +FETCH_OFF_PATH 0 0.000% 0 0.000% + 28608817 100.000% 28608817 100.000% + 0.00 0.00 0.00 0.00 + +FETCHED_OPS_ON_PATH 0 -nan% 0 -nan% +FETCHED_OPS_OFF_PATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +INST_LOST_WAIT_FOR_MISP_RECOVERY 0 0.000% 0 0.000% +INST_LOST_WAIT_FOR_TIMER 0 0.000% 0 0.000% +INST_LOST_WAIT_FOR_EMPTY_ROB 1404 0.000% 1404 0.000% +INST_LOST_WAIT_FOR_REDIRECT 24231354 6.049% 24231354 6.049% +INST_LOST_FETCH 132806100 33.153% 132806100 33.153% +INST_LOST_OFF_PATH 0 0.000% 0 0.000% +INST_LOST_FULL_WINDOW 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_OTHER 857394 0.214% 857394 0.214% +INST_LOST_ROB_STALL_WAIT_FOR_RECOVERY 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_REDIRECT 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_GAP_FILL 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_L1_MISS 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_MEMORY 126 0.000% 126 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_DC_MISS 700314 0.175% 700314 0.175% +INST_LOST_ROB_BLOCK_ISSUE_FULL 0 0.000% 0 0.000% +INST_LOST_ROB_BLOCK_ISSUE_GAP_TOO_LARGE 0 0.000% 0 0.000% +INST_LOST_BREAK_DONT 0 0.000% 0 0.000% +INST_LOST_BREAK_ISSUE_WIDTH 0 0.000% 0 0.000% +INST_LOST_BREAK_CF 0 0.000% 0 0.000% +INST_LOST_BREAK_BTB_MISS 1623485 0.405% 1623485 0.405% +INST_LOST_BREAK_ICACHE_MISS 213712628 53.349% 213712628 53.349% +INST_LOST_BREAK_LINE_END 0 0.000% 0 0.000% +INST_LOST_BREAK_STALL 0 0.000% 0 0.000% +INST_LOST_BREAK_BARRIER 36 0.000% 36 0.000% +INST_LOST_BREAK_OFFPATH 18473 0.005% 18473 0.005% +INST_LOST_BREAK_ALIGNMENT 0 0.000% 0 0.000% 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4.075% 5411217 4.075% +ST_OP_IMEM 46366344 34.913% 46366344 34.913% +ST_OP_IADD 27020418 20.346% 27020418 20.346% +ST_OP_IMUL 183565 0.138% 183565 0.138% +ST_OP_IDIV 10473 0.008% 10473 0.008% +ST_OP_ICMP 9950552 7.493% 9950552 7.493% +ST_OP_LOGIC 8145181 6.133% 8145181 6.133% +ST_OP_SHIFT 839522 0.632% 839522 0.632% +ST_OP_FMEM 566427 0.427% 566427 0.427% +ST_OP_FCVT 0 0.000% 0 0.000% +ST_OP_FADD 0 0.000% 0 0.000% +ST_OP_FMUL 0 0.000% 0 0.000% +ST_OP_FMA 0 0.000% 0 0.000% +ST_OP_FDIV 0 0.000% 0 0.000% +ST_OP_FCMP 0 0.000% 0 0.000% +ST_OP_FCMOV 0 0.000% 0 0.000% +ST_OP_GATHER 0 0.000% 0 0.000% +ST_OP_SCATTER 0 0.000% 0 0.000% +ST_OP_PIPELINED_FAST 19490 0.015% 19490 0.015% +ST_OP_PIPELINED_MEDIUM 0 0.000% 0 0.000% +ST_OP_PIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_MEDIUM 3664 0.003% 3664 0.003% +ST_OP_NOTPIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_VERY_SLOW 0 0.000% 0 0.000% + 132806100 100.000% 132806100 100.000% + 5.89 2.66 5.89 2.66 + +ST_NOT_CF 112570634 84.763% 112570634 84.763% +ST_CF_BR 1452144 1.093% 1452144 1.093% +ST_CF_CBR 13786408 10.381% 13786408 10.381% +ST_CF_CALL 2078431 1.565% 2078431 1.565% +ST_CF_IBR 626914 0.472% 626914 0.472% +ST_CF_ICALL 106568 0.080% 106568 0.080% +ST_CF_ICO 0 0.000% 0 0.000% +ST_CF_RET 2184983 1.645% 2184983 1.645% +ST_CF_SYS 18 0.000% 18 0.000% + 132806100 100.000% 132806100 100.000% + 0.40 1.08 0.40 1.08 + +ST_BAR_NONE 132806082 100.000% 132806082 100.000% +ST_BAR_FETCH 18 0.000% 18 0.000% +ST_BAR_ISSUE 0 0.000% 0 0.000% +ST_BAR_BOTH 0 0.000% 0 0.000% + 132806100 100.000% 132806100 100.000% + 0.00 0.00 0.00 0.00 + +ST_NOT_MEM 85873329 64.661% 85873329 64.661% +ST_MEM_LD 29555012 22.254% 29555012 22.254% +ST_MEM_ST 17377759 13.085% 17377759 13.085% +ST_MEM_PF 0 0.000% 0 0.000% +ST_MEM_WH 0 0.000% 0 0.000% +ST_MEM_EVICT 0 0.000% 0 0.000% + 132806100 100.000% 132806100 100.000% + 0.48 0.60 0.48 0.60 + +ST_NOT_MEM_OFFPATH 0 -nan% 0 -nan% +ST_MEM_LD_OFFPATH 0 -nan% 0 -nan% +ST_MEM_ST_OFFPATH 0 -nan% 0 -nan% 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--- /dev/null +++ b/labs/LAB5/runs/sgcc_base-sms0/l2l1pref.stat.0.out @@ -0,0 +1,140 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 80868545 Instructions: 100000000 IPC: 1.23657 + +L2WAY_FILL_L1 0 0 + +L2WAY_WAY_HIT 0 -nan% 0 -nan% +L2WAY_WAY_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_PREF_REQ 0 0 + +L2WAY_PREF_HIT_DATA_IN_CACHE 0 -nan% 0 -nan% +L2WAY_PREF_HIT_DATA_REQ 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_TRAIN_HIT 0 -nan% 0 -nan% +L2WAY_TRAIN_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L1_HIT_REQ_TYPE_IFETCH 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DFETCH 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DSTORE 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_IPRF 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DPRF 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_WB 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2_ACCESS_INTERVAL__0 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__1 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__2 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__3 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__4 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__5 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__6 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__7 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__8 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_L1INSERT_PORT_FULL 0 -nan% 0 -nan% +L2WAY_L1INSERT_PORT_READY 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2MARKV_NEXT_ADDR_HIT 0 -nan% 0 -nan% +L2MARKV_NEXT_ADDR_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2MARKV_LAST_ADDR_HIT 0 -nan% 0 -nan% +L2MARKV_LAST_ADDR_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +MARKV_L2_TIME_DIFF__0 0 -nan% 0 -nan% +MARKV_L2_TIME_DIFF__1 0 -nan% 0 -nan% +MARKV_L2_TIME_DIFF__2 0 -nan% 0 -nan% +MARKV_L2_TIME_DIFF__3 0 -nan% 0 -nan% +MARKV_L2_TIME_DIFF__4 0 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-nan% 0 -nan% +L2HIT_IP_HIT_COUNT__8 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__9 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + + + diff --git a/labs/LAB5/runs/sgcc_base-sms0/memory.stat.0.out b/labs/LAB5/runs/sgcc_base-sms0/memory.stat.0.out new file mode 100644 index 00000000..3815e76b --- /dev/null +++ b/labs/LAB5/runs/sgcc_base-sms0/memory.stat.0.out @@ -0,0 +1,3416 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 80868545 Instructions: 100000000 IPC: 1.23657 + +ICACHE_MISS 1872365 5.180% 1872365 5.180% +ICACHE_HIT 34276744 94.820% 34276744 94.820% + 36149109 100.000% 36149109 100.000% + 0.95 0.92 0.95 0.92 + +ICACHE_MISS_ONPATH 1872365 100.000% 1872365 100.000% +ICACHE_MISS_OFFPATH 0 0.000% 0 0.000% + 1872365 100.000% 1872365 100.000% + 0.00 0.00 0.00 0.00 + +ICACHE_HIT_ONPATH 34276744 100.000% 34276744 100.000% +ICACHE_HIT_OFFPATH 0 0.000% 0 0.000% + 34276744 100.000% 34276744 100.000% + 0.00 0.00 0.00 0.00 + +ICACHE_HIT_ONPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +ICACHE_HIT_ONPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ICACHE_HIT_OFFPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +ICACHE_HIT_OFFPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DCACHE_MISS 1350634 2.878% 1350634 2.878% +DCACHE_ST_BUFFER_HIT 100391 0.214% 100391 0.214% +DCACHE_HIT 45481699 96.908% 45481699 96.908% + 46932724 100.000% 46932724 100.000% + 1.94 1.91 1.94 1.91 + +DCACHE_MISS_COMPULSORY 45292 0.0335 45292 0.0335 + +DCACHE_MISS_CAPACITY 1300148 0.9626 1300148 0.9626 + +DCACHE_MISS_CONFLICT 5194 0.0038 5194 0.0038 + +DCACHE_MISS_ONPATH 1350634 100.000% 1350634 100.000% +DCACHE_MISS_OFFPATH 0 0.000% 0 0.000% + 1350634 100.000% 1350634 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_ST_BUFFER_HIT_ONPATH 100391 100.000% 100391 100.000% +DCACHE_ST_BUFFER_HIT_OFFPATH 0 0.000% 0 0.000% + 100391 100.000% 100391 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_HIT_ONPATH 45481699 100.000% 45481699 100.000% +DCACHE_HIT_OFFPATH 0 0.000% 0 0.000% + 45481699 100.000% 45481699 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_HIT_ONPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +DCACHE_HIT_ONPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DCACHE_HIT_OFFPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +DCACHE_HIT_OFFPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DCACHE_MISS_LD 642356 47.560% 642356 47.560% +DCACHE_MISS_ST 708278 52.440% 708278 52.440% + 1350634 100.000% 1350634 100.000% + 0.52 0.51 0.52 0.51 + +DCACHE_MISS_LD_ONPATH 642356 100.000% 642356 100.000% +DCACHE_MISS_LD_OFFPATH 0 0.000% 0 0.000% + 642356 100.000% 642356 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_MISS_ST_ONPATH 708278 100.000% 708278 100.000% +DCACHE_MISS_ST_OFFPATH 0 0.000% 0 0.000% + 708278 100.000% 708278 100.000% + 0.00 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3244421 109.8686 3244421 109.8686 + +CORE_MEM_LATENCY_AVE_PREF_NOT_USED 404195 155.4596 404195 155.4596 + +DRAM_LATENCY 0 0 + +TOTAL_DRAM_LATENCY 0 0 + +DRAM_CLOSED_PAGE_POLICY_CMD 0 0 + +DRAM_ACTIVATE_STALLING 0 0 + +DRAM_PRECHARGE_STALLING 0 0 + +DRAM_PRECHARGE_STALLING_WAIT_CYCLES 0 0 + +L1_STAY_DEMAND 80787088074 23088621.9131 80787088074 23088621.9131 + +L1_STAY_PREF_USED 649899135016 22008098.0364 649899135016 22008098.0364 + +L1_STAY_PREF_NOT_USED 54293193433 20881997.4742 54293193433 20881997.4742 + +TOTAL_DATA_MISS_LATENCY 781992 781992 + +TOTAL_DATA_MISS_COUNT 5394 5394 + +CORE_PREF_L1_NOT_USED_LATENCY200 2329 89.577% 2329 89.577% +CORE_PREF_L1_NOT_USED_LATENCY400 90 3.462% 90 3.462% +CORE_PREF_L1_NOT_USED_LATENCY600 85 3.269% 85 3.269% +CORE_PREF_L1_NOT_USED_LATENCY800 28 1.077% 28 1.077% +CORE_PREF_L1_NOT_USED_LATENCY1000 22 0.846% 22 0.846% +CORE_PREF_L1_NOT_USED_LATENCY1200 17 0.654% 17 0.654% +CORE_PREF_L1_NOT_USED_LATENCY1400 16 0.615% 16 0.615% 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100.000% + 1.00 1.00 1.00 1.00 + + + diff --git a/labs/LAB5/runs/sgcc_base-sms0/power.stat.0.out b/labs/LAB5/runs/sgcc_base-sms0/power.stat.0.out new file mode 100644 index 00000000..9a4cab3a --- /dev/null +++ b/labs/LAB5/runs/sgcc_base-sms0/power.stat.0.out @@ -0,0 +1,184 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 80868545 Instructions: 100000000 IPC: 1.23657 + +POWER_STATS_BEGIN 0 0 + +POWER_TIME 25271420312500 25271420312500 + +POWER_CYCLE 80868545 80868545 + +POWER_ITLB_ACCESS 36149109 36149109 + +POWER_DTLB_ACCESS 17377725 17377725 + +POWER_ICACHE_ACCESS 36149109 36149109 + +POWER_ICACHE_MISS 1872365 1872365 + +POWER_BTB_READ 36149109 36149109 + +POWER_BTB_WRITE 673690 673690 + +POWER_ROB_READ 132805988 132805988 + +POWER_ROB_WRITE 132805988 132805988 + +POWER_RENAME_READ 265611976 265611976 + +POWER_RENAME_WRITE 132805988 132805988 + +POWER_FP_RENAME_READ 0 0 + +POWER_FP_RENAME_WRITE 0 0 + +POWER_FUNCTION_CALL 2184997 2184997 + +POWER_INST_WINDOW_READ 132805988 132805988 + +POWER_INST_WINDOW_WRITE 132805988 132805988 + +POWER_INT_REGFILE_READ 143061590 143061590 + +POWER_INT_REGFILE_WRITE 103779614 103779614 + +POWER_IALU_ACCESS 132611950 132611950 + +POWER_CDB_IALU_ACCESS 132611950 132611950 + +POWER_MUL_ACCESS 194038 194038 + +POWER_CDB_MUL_ACCESS 194038 194038 + +POWER_FP_INST_WINDOW_WRITE 0 0 + +POWER_FP_INST_WINDOW_READ 0 0 + +POWER_FP_REGFILE_READ 0 0 + +POWER_FP_REGFILE_WRITE 0 0 + +POWER_FPU_ACCESS 0 0 + +POWER_CDB_FPU_ACCESS 0 0 + +POWER_DCACHE_READ_ACCESS 29555040 29555040 + +POWER_DCACHE_WRITE_ACCESS 17377727 17377727 + +POWER_DCACHE_READ_MISS 742787 742787 + +POWER_DCACHE_WRITE_MISS 708281 708281 + +POWER_MLC_READ_ACCESS 0 0 + +POWER_MLC_WRITE_ACCESS 0 0 + +POWER_MLC_READ_MISS 0 0 + +POWER_MLC_WRITE_MISS 0 0 + +POWER_LLC_READ_ACCESS 2496555 2496555 + +POWER_LLC_WRITE_ACCESS 270689 270689 + +POWER_LLC_READ_MISS 52011 52011 + +POWER_LLC_WRITE_MISS 2 2 + +POWER_MEMORY_ACCESS 0 0 + +POWER_MEMORY_READ_ACCESS 0 0 + +POWER_MEMORY_WRITE_ACCESS 0 0 + +POWER_INST_WINDOW_WAKEUP_ACCESS 132805988 132805988 + +POWER_FP_INST_WINDOW_WAKEUP_ACCESS 0 0 + +POWER_L1DIREC_READ_ACCESS 0 0 + +POWER_L1DIREC_WRITE_ACCESS 0 0 + +POWER_L1DIREC_READ_MISS 0 0 + +POWER_L1DIREC_WRITE_MISS 0 0 + +POWER_L2DIREC_READ_ACCESS 0 0 + +POWER_L2DIREC_WRITE_ACCESS 0 0 + +POWER_L2DIREC_READ_MISS 0 0 + +POWER_L2DIREC_WRITE_MISS 0 0 + +POWER_MEMORY_CTRL_ACCESS 82307 82307 + +POWER_MEMORY_CTRL_READ 52011 52011 + +POWER_MEMORY_CTRL_WRITE 30296 30296 + +POWER_OP 132805988 132805988 + +POWER_INT_OP 130305110 130305110 + +POWER_FP_OP 589581 589581 + +POWER_LD_OP 29555000 29555000 + +POWER_ST_OP 17377725 17377725 + +POWER_BRANCH_MISPREDICT 673690 673690 + +POWER_COMMITTED_OP 132805988 132805988 + +POWER_COMMITTED_INT_OP 130305110 130305110 + +POWER_COMMITTED_FP_OP 2500878 2500878 + +POWER_BRANCH_OP 20235456 20235456 + +POWER_DRAM_PRECHARGE 11566 11566 + +POWER_DRAM_ACTIVATE 25054 25054 + +POWER_DRAM_READ 52009 52009 + +POWER_DRAM_WRITE 30289 30289 + +POWER_STATS_END 0 0 + +ENERGY 0.000000 0.000000 + +ENERGY_CORE 0.000000 0.000000 + +ENERGY_UNCORE 0.000000 0.000000 + +ENERGY_MEMORY 0.000000 0.000000 + +ENERGY_OTHER 0.000000 0.000000 + +ENERGY_CORE_STATIC 0.000000 0.000000 + +ENERGY_CORE_DYNAMIC 0.000000 0.000000 + +ENERGY_UNCORE_STATIC 0.000000 0.000000 + +ENERGY_UNCORE_DYNAMIC 0.000000 0.000000 + +ENERGY_MEMORY_STATIC 0.000000 0.000000 + +ENERGY_MEMORY_DYNAMIC 0.000000 0.000000 + +ENERGY_OTHER_STATIC 0.000000 0.000000 + +ENERGY_OTHER_DYNAMIC 0.000000 0.000000 + +TIME 0.000000 0.000000 + +ENERGY_STATS_END 0 0 + + + diff --git a/labs/LAB5/runs/sgcc_base-sms0/pref.stat.0.out b/labs/LAB5/runs/sgcc_base-sms0/pref.stat.0.out new file mode 100644 index 00000000..0147c761 --- /dev/null +++ b/labs/LAB5/runs/sgcc_base-sms0/pref.stat.0.out @@ -0,0 +1,208 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 80868545 Instructions: 100000000 IPC: 1.23657 + +PREF_DL0REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UMLC_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UL1REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_DL0REQ_QUEUE_FULL 0 0 + +PREF_UMLC_REQ_QUEUE_FULL 0 0 + +PREF_UL1REQ_QUEUE_FULL 0 0 + +PREF_DC_HIT_NOSEND 0 0 + +PREF_WBQDC_HIT_NOSEND 0 0 + +PREF_MLCQ_STALL 0 0 + +PREF_L1Q_STALL 0 0 + +PREF_UMLC_REQ_SEND_QUEUE_STALL 0 0 + +PREF_UL1REQ_SEND_QUEUE_STALL 6736 6736 + +PREF_UMLC_REQ_QUEUE_SENTREQ 0 0 + +PREF_UL1REQ_QUEUE_SENTREQ 53396 53396 + +PREF_NEWREQ_MATCHED 205 205 + +PREF_UMLC_REQ_QUEUE_MATCHED_REQ 0 0 + +PREF_UL1REQ_QUEUE_MATCHED_REQ 1361 1361 + +PREF_DL0REQ_QUEUE_MATCHED_REQ 0 0 + +L1_PREF_HIT 184956 184956 + +L1_PREF_UNIQUE_HIT 40366 40366 + +L1_PREF_LATE 290 290 + +L1_LATE_PREF_CYCLES 46537 46537 + +L1_LATE_PREF_CYCLES_DIST_0 185 63.793% 185 63.793% +L1_LATE_PREF_CYCLES_DIST_100 21 7.241% 21 7.241% +L1_LATE_PREF_CYCLES_DIST_200 18 6.207% 18 6.207% +L1_LATE_PREF_CYCLES_DIST_300 14 4.828% 14 4.828% +L1_LATE_PREF_CYCLES_DIST_400 20 6.897% 20 6.897% +L1_LATE_PREF_CYCLES_DIST_500 11 3.793% 11 3.793% +L1_LATE_PREF_CYCLES_DIST_600 10 3.448% 10 3.448% +L1_LATE_PREF_CYCLES_DIST_700 6 2.069% 6 2.069% +L1_LATE_PREF_CYCLES_DIST_800 4 1.379% 4 1.379% +L1_LATE_PREF_CYCLES_DIST_900 1 0.345% 1 0.345% +L1_LATE_PREF_CYCLES_DIST_1000 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1100 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1200 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1300 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1400 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1500 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1600 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1700 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1800 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1900 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_2000 0 0.000% 0 0.000% + 290 100.000% 290 100.000% + 1.30 1.86 1.30 1.86 + +MLC_PREF_HIT 0 0 + +MLC_PREF_UNIQUE_HIT 0 0 + +MLC_PREF_LATE 0 0 + +PREF_HYBRID_SEL_0 0 -nan% 0 -nan% +PREF_HYBRID_SEL_1 0 -nan% 0 -nan% +PREF_HYBRID_SEL_2 0 -nan% 0 -nan% +PREF_HYBRID_SEL_3 0 -nan% 0 -nan% +PREF_HYBRID_SEL_4 0 -nan% 0 -nan% +PREF_HYBRID_SEL_5 0 -nan% 0 -nan% +PREF_HYBRID_SEL_6 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_DISTANCE_1 0 0.000% 0 0.000% +PREF_DISTANCE_2 0 0.000% 0 0.000% +PREF_DISTANCE_3 1 25.000% 1 25.000% +PREF_DISTANCE_4 3 75.000% 3 75.000% +PREF_DISTANCE_5 0 0.000% 0 0.000% +PREF_DISTANCE_6 0 0.000% 0 0.000% +PREF_DISTANCE_7 0 0.000% 0 0.000% +PREF_DISTANCE_8 0 0.000% 0 0.000% +PREF_DISTANCE_9 0 0.000% 0 0.000% +PREF_DISTANCE_10 0 0.000% 0 0.000% + 4 100.000% 4 100.000% + 2.75 0.50 2.75 0.50 + +PREF_REPL_MRU 0 -nan% 0 -nan% +PREF_REPL_MID 0 -nan% 0 -nan% +PREF_REPL_LOWQTR 0 -nan% 0 -nan% +PREF_REPL_LRU 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_REPL_MOVEDOWN 0 -nan% 0 -nan% +PREF_REPL_MOVEUP 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_COV_1 0 -nan% 0 -nan% +PREF_COV_2 0 -nan% 0 -nan% +PREF_COV_3 0 -nan% 0 -nan% +PREF_COV_4 0 -nan% 0 -nan% +PREF_COV_5 0 -nan% 0 -nan% +PREF_COV_6 0 -nan% 0 -nan% +PREF_COV_7 0 -nan% 0 -nan% +PREF_COV_8 0 -nan% 0 -nan% +PREF_COV_9 0 -nan% 0 -nan% +PREF_COV_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_POL_1 0 0.000% 0 0.000% +PREF_POL_2 0 0.000% 0 0.000% +PREF_POL_3 0 0.000% 0 0.000% +PREF_POL_4 0 0.000% 0 0.000% +PREF_POL_5 0 0.000% 0 0.000% +PREF_POL_6 0 0.000% 0 0.000% +PREF_POL_7 0 0.000% 0 0.000% +PREF_POL_8 0 0.000% 0 0.000% +PREF_POL_9 0 0.000% 0 0.000% +PREF_POL_10 4 100.000% 4 100.000% + 4 100.000% 4 100.000% + 9.00 10.39 9.00 10.39 + +PREF_ACC_1 2 50.000% 2 50.000% +PREF_ACC_2 2 50.000% 2 50.000% +PREF_ACC_3 0 0.000% 0 0.000% +PREF_ACC_4 0 0.000% 0 0.000% +PREF_ACC_5 0 0.000% 0 0.000% +PREF_ACC_6 0 0.000% 0 0.000% +PREF_ACC_7 0 0.000% 0 0.000% +PREF_ACC_8 0 0.000% 0 0.000% +PREF_ACC_9 0 0.000% 0 0.000% +PREF_ACC_10 0 0.000% 0 0.000% + 4 100.000% 4 100.000% + 0.50 0.41 0.50 0.41 + +PREF_TIMELY_1 0 0.000% 0 0.000% +PREF_TIMELY_2 0 0.000% 0 0.000% +PREF_TIMELY_3 0 0.000% 0 0.000% +PREF_TIMELY_4 0 0.000% 0 0.000% +PREF_TIMELY_5 0 0.000% 0 0.000% +PREF_TIMELY_6 0 0.000% 0 0.000% +PREF_TIMELY_7 0 0.000% 0 0.000% +PREF_TIMELY_8 0 0.000% 0 0.000% +PREF_TIMELY_9 0 0.000% 0 0.000% +PREF_TIMELY_10 4 100.000% 4 100.000% + 4 100.000% 4 100.000% + 9.00 10.39 9.00 10.39 + +PREF_UNUSED_EVICT 2600 2600 + +PREF_REGION_SENT 0 0 + +PREF_REGION_USEFUL 0 0 + +PREF_REGION_EVICT 0 0 + +PREF_PFPOL 0 0 + +PREF_PHASE_NEWPHASE_DET 0 0 + +PREF_PHASE_NEWPHASE_NOTVALID 0 0 + +PREF_PHASE_SENTPREF 0 0 + +PREF_PHASE_OVERWRITE_PAGE 0 0 + +PREF_UPDATE_COUNT 4 4 + +PREF_ACC1_HT_HP 0 0.000% 0 0.000% +PREF_ACC1_HT_LP 3 75.000% 3 75.000% +PREF_ACC1_LT_HP 0 0.000% 0 0.000% +PREF_ACC1_LT_LP 1 25.000% 1 25.000% +PREF_ACC2_HT_HP 0 0.000% 0 0.000% +PREF_ACC2_HT_LP 0 0.000% 0 0.000% +PREF_ACC2_LT_HP 0 0.000% 0 0.000% +PREF_ACC2_LT_LP 0 0.000% 0 0.000% +PREF_ACC3_HT_HP 0 0.000% 0 0.000% +PREF_ACC3_HT_LP 0 0.000% 0 0.000% +PREF_ACC3_LT_HP 0 0.000% 0 0.000% +PREF_ACC3_LT_LP 0 0.000% 0 0.000% +PREF_ACC4_HT_HP 0 0.000% 0 0.000% +PREF_ACC4_HT_LP 0 0.000% 0 0.000% +PREF_ACC4_LT_HP 0 0.000% 0 0.000% +PREF_ACC4_LT_LP 0 0.000% 0 0.000% + 4 100.000% 4 100.000% + 1.50 1.00 1.50 1.00 + + + diff --git a/labs/LAB5/runs/sgcc_base-sms0/ramulator.stat.out b/labs/LAB5/runs/sgcc_base-sms0/ramulator.stat.out new file mode 100644 index 00000000..263b78df --- /dev/null +++ b/labs/LAB5/runs/sgcc_base-sms0/ramulator.stat.out @@ -0,0 +1,150 @@ + ramulator.active_cycles_0 2760696 # Total active cycles for level _0 + ramulator.busy_cycles_0 2760696 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0 + ramulator.serving_requests_0 3364547 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.average_serving_requests_0 0.110947 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.active_cycles_0_0 2760696 # Total active cycles for level _0_0 + ramulator.busy_cycles_0_0 4047156 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0 + ramulator.serving_requests_0_0 3364547 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.average_serving_requests_0_0 0.110947 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.active_cycles_0_0_0 731872 # Total active cycles for level _0_0_0 + ramulator.busy_cycles_0_0_0 731872 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0 + ramulator.serving_requests_0_0_0 795706 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 +ramulator.average_serving_requests_0_0_0 0.026239 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 + ramulator.active_cycles_0_0_0_0 146326 # Total active cycles for level _0_0_0_0 + ramulator.busy_cycles_0_0_0_0 146326 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_0 + ramulator.serving_requests_0_0_0_0 157958 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 +ramulator.average_serving_requests_0_0_0_0 0.005209 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 + ramulator.active_cycles_0_0_0_1 262866 # Total active cycles for level _0_0_0_1 + ramulator.busy_cycles_0_0_0_1 262866 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_1 + ramulator.serving_requests_0_0_0_1 274635 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 +ramulator.average_serving_requests_0_0_0_1 0.009056 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 + ramulator.active_cycles_0_0_0_2 188083 # Total active cycles for level _0_0_0_2 + ramulator.busy_cycles_0_0_0_2 188083 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_2 + ramulator.serving_requests_0_0_0_2 198544 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 +ramulator.average_serving_requests_0_0_0_2 0.006547 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 + ramulator.active_cycles_0_0_0_3 153366 # Total active cycles for level _0_0_0_3 + ramulator.busy_cycles_0_0_0_3 153366 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_3 + ramulator.serving_requests_0_0_0_3 164569 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 +ramulator.average_serving_requests_0_0_0_3 0.005427 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 + ramulator.active_cycles_0_0_1 796929 # Total active cycles for level _0_0_1 + ramulator.busy_cycles_0_0_1 796929 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1 + ramulator.serving_requests_0_0_1 880143 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 +ramulator.average_serving_requests_0_0_1 0.029023 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 + ramulator.active_cycles_0_0_1_0 204177 # Total active cycles for level _0_0_1_0 + ramulator.busy_cycles_0_0_1_0 204177 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_0 + ramulator.serving_requests_0_0_1_0 217615 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 +ramulator.average_serving_requests_0_0_1_0 0.007176 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 + ramulator.active_cycles_0_0_1_1 161328 # Total active cycles for level _0_0_1_1 + ramulator.busy_cycles_0_0_1_1 161328 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_1 + ramulator.serving_requests_0_0_1_1 174710 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 +ramulator.average_serving_requests_0_0_1_1 0.005761 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 + ramulator.active_cycles_0_0_1_2 282219 # Total active cycles for level _0_0_1_2 + ramulator.busy_cycles_0_0_1_2 282219 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_2 + ramulator.serving_requests_0_0_1_2 294104 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 +ramulator.average_serving_requests_0_0_1_2 0.009698 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 + ramulator.active_cycles_0_0_1_3 181319 # Total active cycles for level _0_0_1_3 + ramulator.busy_cycles_0_0_1_3 181319 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_3 + ramulator.serving_requests_0_0_1_3 193714 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 +ramulator.average_serving_requests_0_0_1_3 0.006388 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 + ramulator.active_cycles_0_0_2 743304 # Total active cycles for level _0_0_2 + ramulator.busy_cycles_0_0_2 743304 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2 + ramulator.serving_requests_0_0_2 799879 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 +ramulator.average_serving_requests_0_0_2 0.026376 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 + ramulator.active_cycles_0_0_2_0 133367 # Total active cycles for level _0_0_2_0 + ramulator.busy_cycles_0_0_2_0 133367 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_0 + ramulator.serving_requests_0_0_2_0 143805 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 +ramulator.average_serving_requests_0_0_2_0 0.004742 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 + ramulator.active_cycles_0_0_2_1 301238 # Total active cycles for level _0_0_2_1 + ramulator.busy_cycles_0_0_2_1 301238 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_1 + ramulator.serving_requests_0_0_2_1 312685 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 +ramulator.average_serving_requests_0_0_2_1 0.010311 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 + ramulator.active_cycles_0_0_2_2 133575 # Total active cycles for level _0_0_2_2 + ramulator.busy_cycles_0_0_2_2 133575 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_2 + ramulator.serving_requests_0_0_2_2 145360 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 +ramulator.average_serving_requests_0_0_2_2 0.004793 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 + ramulator.active_cycles_0_0_2_3 189961 # Total active cycles for level _0_0_2_3 + ramulator.busy_cycles_0_0_2_3 189961 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_3 + ramulator.serving_requests_0_0_2_3 198029 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 +ramulator.average_serving_requests_0_0_2_3 0.006530 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 + ramulator.active_cycles_0_0_3 817764 # Total active cycles for level _0_0_3 + ramulator.busy_cycles_0_0_3 817764 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3 + ramulator.serving_requests_0_0_3 888819 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 +ramulator.average_serving_requests_0_0_3 0.029309 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 + ramulator.active_cycles_0_0_3_0 159648 # Total active cycles for level _0_0_3_0 + ramulator.busy_cycles_0_0_3_0 159648 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_0 + ramulator.serving_requests_0_0_3_0 168526 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 +ramulator.average_serving_requests_0_0_3_0 0.005557 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 + ramulator.active_cycles_0_0_3_1 268339 # Total active cycles for level _0_0_3_1 + ramulator.busy_cycles_0_0_3_1 268339 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_1 + ramulator.serving_requests_0_0_3_1 282895 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 +ramulator.average_serving_requests_0_0_3_1 0.009329 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 + ramulator.active_cycles_0_0_3_2 309570 # Total active cycles for level _0_0_3_2 + ramulator.busy_cycles_0_0_3_2 309570 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_2 + ramulator.serving_requests_0_0_3_2 324535 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 +ramulator.average_serving_requests_0_0_3_2 0.010702 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 + ramulator.active_cycles_0_0_3_3 103135 # Total active cycles for level _0_0_3_3 + ramulator.busy_cycles_0_0_3_3 103135 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_3 + ramulator.serving_requests_0_0_3_3 112863 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 +ramulator.average_serving_requests_0_0_3_3 0.003722 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 + ramulator.read_transaction_bytes_0 3328576 # The total byte of read transaction per channel + ramulator.write_transaction_bytes_0 1938496 # The total byte of write transaction per channel + ramulator.row_hits_channel_0_core 57245 # Number of row hits per channel per core + ramulator.row_misses_channel_0_core 16866 # Number of row misses per channel per core + ramulator.row_conflicts_channel_0_core 8187 # Number of row conflicts per channel per core + ramulator.read_row_hits_channel_0_core 38581 # Number of row hits for read requests per channel per core + [0] 38581.0 # +ramulator.read_row_misses_channel_0_core 9604 # Number of row misses for read requests per channel per core + [0] 9604.0 # +ramulator.read_row_conflicts_channel_0_core 3824 # Number of row conflicts for read requests per channel per core + [0] 3824.0 # + ramulator.write_row_hits_channel_0_core 18664 # Number of row hits for write requests per channel per core + [0] 18664.0 # +ramulator.write_row_misses_channel_0_core 7262 # Number of row misses for write requests per channel per core + [0] 7262.0 # +ramulator.write_row_conflicts_channel_0_core 4363 # Number of row conflicts for write requests per channel per core + [0] 4363.0 # + ramulator.useless_activates_0_core 1 # Number of useless activations. E.g, ACT -> PRE w/o RD or WR + ramulator.read_latency_avg_0 45.696410 # The average memory latency cycles (in memory time domain) per request for all read requests in this channel + ramulator.read_latency_sum_0 2376716 # The memory latency cycles (in memory time domain) sum for all read requests in this channel + ramulator.req_queue_length_avg_0 11.872353 # Average of read and write queue length per memory cycle per channel. + ramulator.req_queue_length_sum_0 360037608 # Sum of read and write queue length per memory cycle per channel. + ramulator.read_req_queue_length_avg_0 0.071266 # Read queue length average per memory cycle per channel. + ramulator.read_req_queue_length_sum_0 2161201 # Read queue length sum per memory cycle per channel. + ramulator.write_req_queue_length_avg_0 11.801087 # Write queue length average per memory cycle per channel. + ramulator.write_req_queue_length_sum_0 357876407 # Write queue length sum per memory cycle per channel. + ramulator.record_read_hits 0.0 # record read hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_misses 0.0 # record_read_miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_conflicts 0.0 # record read conflict count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_hits 0.0 # record write hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_misses 0.0 # record write miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_conflicts 0.0 # record write conflict for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.dram_capacity 8589934592 # Number of bytes in simulated DRAM + ramulator.dram_cycles 30325716 # Number of DRAM cycles simulated + ramulator.incoming_requests 82307 # Number of incoming requests to DRAM + ramulator.read_requests 52011 # Number of incoming read requests to DRAM per core + [0] 52011.0 # + ramulator.write_requests 30296 # Number of incoming write requests to DRAM per core + [0] 30296.0 # + ramulator.ramulator_active_cycles 2760696 # The total number of cycles that the DRAM part is active (serving R/W) + ramulator.incoming_requests_per_channel 82307.0 # Number of incoming requests to each DRAM channel + [0] 82307.0 # +ramulator.incoming_read_reqs_per_channel 52011.0 # Number of incoming read requests to each DRAM channel + [0] 52011.0 # + ramulator.physical_page_replacement 0 # The number of times that physical page replacement happens. + ramulator.maximum_bandwidth 19200000000 # The theoretical maximum bandwidth (Bps) + ramulator.in_queue_req_num_sum 360037608 # Sum of read/write queue length + ramulator.in_queue_read_req_num_sum 2161201 # Sum of read queue length + ramulator.in_queue_write_req_num_sum 357876407 # Sum of write queue length + ramulator.in_queue_req_num_avg 11.872353 # Average of read/write queue length per memory cycle + ramulator.in_queue_read_req_num_avg 0.071266 # Average of read queue length per memory cycle + ramulator.in_queue_write_req_num_avg 11.801087 # Average of write queue length per memory cycle + ramulator.record_read_requests 0.0 # record read requests for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_requests 0.0 # record write requests for this core when it reaches request limit or to the end + [0] 0.0 # diff --git a/labs/LAB5/runs/sgcc_base-sms0/run.err b/labs/LAB5/runs/sgcc_base-sms0/run.err new file mode 100644 index 00000000..e69de29b diff --git a/labs/LAB5/runs/sgcc_base-sms0/run.out b/labs/LAB5/runs/sgcc_base-sms0/run.out new file mode 100644 index 00000000..eff46955 --- /dev/null +++ b/labs/LAB5/runs/sgcc_base-sms0/run.out @@ -0,0 +1,107 @@ +Scarab gitrev: 7ab9e17 +Scarab started at Sun Jun 11 08:08:38 2023 + +Initialized Ramulator. +** Heartbeat: 1% -- { 1000004 } -- 0.00 KIPS (333.33 KIPS) +** Heartbeat: 2% -- { 2000005 } -- 500.00 KIPS (400.00 KIPS) +** Heartbeat: 3% -- { 3000005 } -- 500.00 KIPS (428.57 KIPS) +** Heartbeat: 4% -- { 4000008 } -- 500.00 KIPS (444.45 KIPS) +** Heartbeat: 5% -- { 5000011 } -- 333.33 KIPS (416.67 KIPS) +** Heartbeat: 6% -- { 6000011 } -- 500.00 KIPS (428.57 KIPS) +** Heartbeat: 7% -- { 7000013 } -- 500.00 KIPS (437.50 KIPS) +** Heartbeat: 8% -- { 8000014 } -- 500.00 KIPS (444.45 KIPS) +** Heartbeat: 9% -- { 9000014 } -- 500.00 KIPS (450.00 KIPS) +** Heartbeat: 10% -- { 10000019 } -- 333.33 KIPS (434.78 KIPS) +** Heartbeat: 11% -- { 11000024 } -- 500.00 KIPS (440.00 KIPS) +** Heartbeat: 12% -- { 12000024 } -- 500.00 KIPS (444.45 KIPS) +** Heartbeat: 13% -- { 13000024 } -- 500.00 KIPS (448.28 KIPS) +** Heartbeat: 14% -- { 14000029 } -- 500.00 KIPS (451.61 KIPS) +** Heartbeat: 15% -- { 15000034 } -- 333.33 KIPS (441.18 KIPS) +** Heartbeat: 16% -- { 16000036 } -- 500.00 KIPS (444.45 KIPS) +** Heartbeat: 17% -- { 17000037 } -- 500.00 KIPS (447.37 KIPS) +** Heartbeat: 18% -- { 18000042 } -- 500.00 KIPS (450.00 KIPS) +** Heartbeat: 19% -- { 19000042 } -- 500.00 KIPS (452.38 KIPS) +** Heartbeat: 20% -- { 20000045 } -- 500.00 KIPS (454.55 KIPS) +** Heartbeat: 21% -- { 21000046 } -- 333.33 KIPS (446.81 KIPS) +** Heartbeat: 22% -- { 22000046 } -- 500.00 KIPS (448.98 KIPS) +** Heartbeat: 23% -- { 23000049 } -- 500.00 KIPS (450.98 KIPS) +** Heartbeat: 24% -- { 24000052 } -- 500.00 KIPS (452.83 KIPS) +** Heartbeat: 25% -- { 25000053 } -- 500.00 KIPS (454.55 KIPS) +** Heartbeat: 26% -- { 26000053 } -- 333.33 KIPS (448.28 KIPS) +** Heartbeat: 27% -- { 27000056 } -- 500.00 KIPS (450.00 KIPS) +** Heartbeat: 28% -- { 28000056 } -- 500.00 KIPS (451.61 KIPS) +** Heartbeat: 29% -- { 29000056 } -- 500.00 KIPS (453.13 KIPS) +** Heartbeat: 30% -- { 30000056 } -- 500.00 KIPS (454.55 KIPS) +** Heartbeat: 31% -- { 31000057 } -- 333.33 KIPS (449.28 KIPS) +** Heartbeat: 32% -- { 32000057 } -- 500.00 KIPS (450.71 KIPS) +** Heartbeat: 33% -- { 33000058 } -- 500.00 KIPS (452.06 KIPS) +** Heartbeat: 34% -- { 34000058 } -- 500.00 KIPS (453.33 KIPS) +** Heartbeat: 35% -- { 35000058 } -- 333.33 KIPS (448.72 KIPS) +** Heartbeat: 36% -- { 36000058 } -- 500.00 KIPS (450.00 KIPS) +** Heartbeat: 37% -- { 37000061 } -- 500.00 KIPS (451.22 KIPS) +** Heartbeat: 38% -- { 38000064 } -- 500.00 KIPS (452.38 KIPS) +** Heartbeat: 39% -- { 39000064 } -- 333.33 KIPS (448.28 KIPS) +** Heartbeat: 40% -- { 40000065 } -- 500.00 KIPS (449.44 KIPS) +** Heartbeat: 41% -- { 41000067 } -- 500.00 KIPS (450.55 KIPS) +** Heartbeat: 42% -- { 42000067 } -- 333.33 KIPS (446.81 KIPS) +** Heartbeat: 43% -- { 43000068 } -- 500.00 KIPS (447.92 KIPS) +** Heartbeat: 44% -- { 44000068 } -- 500.00 KIPS (448.98 KIPS) +** Heartbeat: 45% -- { 45000069 } -- 500.00 KIPS (450.00 KIPS) +** Heartbeat: 46% -- { 46000069 } -- 333.33 KIPS (446.60 KIPS) +** Heartbeat: 47% -- { 47000069 } -- 500.00 KIPS (447.62 KIPS) +** Heartbeat: 48% -- { 48000070 } -- 500.00 KIPS (448.60 KIPS) +** Heartbeat: 49% -- { 49000072 } -- 500.00 KIPS (449.54 KIPS) +** Heartbeat: 50% -- { 50000073 } -- 333.33 KIPS (446.43 KIPS) +** Heartbeat: 51% -- { 51000075 } -- 500.00 KIPS (447.37 KIPS) +** Heartbeat: 52% -- { 52000077 } -- 500.00 KIPS (448.28 KIPS) +** Heartbeat: 53% -- { 53000077 } -- 500.00 KIPS (449.15 KIPS) +** Heartbeat: 54% -- { 54000077 } -- 500.00 KIPS (450.00 KIPS) +** Heartbeat: 55% -- { 55000080 } -- 333.33 KIPS (447.16 KIPS) +** Heartbeat: 56% -- { 56000082 } -- 500.00 KIPS (448.00 KIPS) +** Heartbeat: 57% -- { 57000083 } -- 500.00 KIPS (448.82 KIPS) +** Heartbeat: 58% -- { 58000086 } -- 333.33 KIPS (446.15 KIPS) +** Heartbeat: 59% -- { 59000091 } -- 500.00 KIPS (446.97 KIPS) +** Heartbeat: 60% -- { 60000091 } -- 500.00 KIPS (447.76 KIPS) +** Heartbeat: 61% -- { 61000093 } -- 500.00 KIPS (448.53 KIPS) +** Heartbeat: 62% -- { 62000093 } -- 500.00 KIPS (449.28 KIPS) +** Heartbeat: 63% -- { 63000093 } -- 333.33 KIPS (446.81 KIPS) +** Heartbeat: 64% -- { 64000093 } -- 500.00 KIPS (447.55 KIPS) +** Heartbeat: 65% -- { 65000093 } -- 500.00 KIPS (448.28 KIPS) +** Heartbeat: 66% -- { 66000093 } -- 500.00 KIPS (448.98 KIPS) +** Heartbeat: 67% -- { 67000093 } -- 333.33 KIPS (446.67 KIPS) +** Heartbeat: 68% -- { 68000094 } -- 500.00 KIPS (447.37 KIPS) +** Heartbeat: 69% -- { 69000095 } -- 500.00 KIPS (448.05 KIPS) +** Heartbeat: 70% -- { 70000095 } -- 333.33 KIPS (445.86 KIPS) +** Heartbeat: 71% -- { 71000098 } -- 500.00 KIPS (446.54 KIPS) +** Heartbeat: 72% -- { 72000102 } -- 500.00 KIPS (447.21 KIPS) +** Heartbeat: 73% -- { 73000105 } -- 500.00 KIPS (447.85 KIPS) +** Heartbeat: 74% -- { 74000106 } -- 333.33 KIPS (445.78 KIPS) +** Heartbeat: 75% -- { 75000109 } -- 500.00 KIPS (446.43 KIPS) +** Heartbeat: 76% -- { 76000112 } -- 500.00 KIPS (447.06 KIPS) +** Heartbeat: 77% -- { 77000115 } -- 500.00 KIPS (447.68 KIPS) +** Heartbeat: 78% -- { 78000116 } -- 333.33 KIPS (445.71 KIPS) +** Heartbeat: 79% -- { 79000118 } -- 500.00 KIPS (446.33 KIPS) +** Heartbeat: 80% -- { 80000118 } -- 500.00 KIPS (446.93 KIPS) +** Heartbeat: 81% -- { 81000118 } -- 500.00 KIPS (447.51 KIPS) +** Heartbeat: 82% -- { 82000118 } -- 333.33 KIPS (445.65 KIPS) +** Heartbeat: 83% -- { 83000120 } -- 500.00 KIPS (446.24 KIPS) +** Heartbeat: 84% -- { 84000121 } -- 500.00 KIPS (446.81 KIPS) +** Heartbeat: 85% -- { 85000122 } -- 500.00 KIPS (447.37 KIPS) +** Heartbeat: 86% -- { 86000122 } -- 500.00 KIPS (447.92 KIPS) +** Heartbeat: 87% -- { 87000123 } -- 500.00 KIPS (448.45 KIPS) +** Heartbeat: 88% -- { 88000128 } -- 500.00 KIPS (448.98 KIPS) +** Heartbeat: 89% -- { 89000130 } -- 500.00 KIPS (449.50 KIPS) +** Heartbeat: 90% -- { 90000130 } -- 333.33 KIPS (447.76 KIPS) +** Heartbeat: 91% -- { 91000130 } -- 500.00 KIPS (448.28 KIPS) +** Heartbeat: 92% -- { 92000132 } -- 500.00 KIPS (448.78 KIPS) +** Heartbeat: 93% -- { 93000136 } -- 500.00 KIPS (449.28 KIPS) +** Heartbeat: 94% -- { 94000140 } -- 500.00 KIPS (449.76 KIPS) +** Heartbeat: 95% -- { 95000143 } -- 333.33 KIPS (448.11 KIPS) +** Heartbeat: 96% -- { 96000143 } -- 500.00 KIPS (448.60 KIPS) +** Heartbeat: 97% -- { 97000146 } -- 500.00 KIPS (449.07 KIPS) +** Heartbeat: 98% -- { 98000148 } -- 500.00 KIPS (449.54 KIPS) +** Heartbeat: 99% -- { 99000150 } -- 500.00 KIPS (450.00 KIPS) +** Core 0 Finished: insts:100000000 cycles:80868545 time:25271420312500 -- 1.24 IPC (1.24 IPC) -- N/A KIPS (448.43 KIPS) +done +Scarab finished at Sun Jun 11 08:12:21 2023 + diff --git a/labs/LAB5/runs/sgcc_base-sms0/stream.stat.0.out b/labs/LAB5/runs/sgcc_base-sms0/stream.stat.0.out new file mode 100644 index 00000000..d2df0e67 --- /dev/null +++ b/labs/LAB5/runs/sgcc_base-sms0/stream.stat.0.out @@ -0,0 +1,188 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 80868545 Instructions: 100000000 IPC: 1.23657 + +DCACHE_PREF_HIT 0 0 + +IFETCH_WB_FIRST_SCHEDULE 0 -nan% 0 -nan% +PREFETCH_LAST_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_PREF_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_LOW_OP_SCHEDULE 0 -nan% 0 -nan% +DEMAND_LAST_SCHEDULE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +SEND_MISS_REQ_QUEUE 52011 52011 + +L1_DATA_EVICT 35629 35629 + +STREAM_BUFFER_REQ 0 0 + +PREF_SEND_TO_MEM_REQ 0 -nan% 0 -nan% +PREF_SEND_TO_MEM_REQ_FAIL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +HIT_TRAIN_STREAM 43012 89.002% 43012 89.002% +MISS_TRAIN_STREAM 5315 10.998% 5315 10.998% + 48327 100.000% 48327 100.000% + 0.11 0.30 0.11 0.30 + +STREAM_TRAIN_CREATE 1989 1989 + +MEM_REQ_MISS_HWP_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_SW_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_IFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DSTORE_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DPRF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_WB_Q 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_BY_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_WB 0 -nan% 0 -nan% +PREF_HIT_BY_PREF 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_WB 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_L1_FILL 0 -nan% 0 -nan% +DEMAND_L1_FILL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TOUCH_L1_REPLACE 0 0.000% 0 0.000% +NO_TOUCH_L1_REPLACE 35629 100.000% 35629 100.000% + 35629 100.000% 35629 100.000% + 1.00 1.00 1.00 1.00 + +PREF_REQ_QUE_FULL 0 0 + +STREAM_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +L2HIT_STREAM_PREF_REQ_QUE_FULL 0 0 + +L2HIT_HIT_TRAIN_STREAM 0 -nan% 0 -nan% +L2HIT_MISS_TRAIN_STREAM 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_TRAIN_CREATE 0 0 + +L2HIT_STREAM_BUFFER_REQ 0 0 + +L2HIT_STREAM_PREF_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_STREAM_PREF_DCACHE_INSERT 0 -nan% 0 -nan% +L2HIT_STREAM_L2_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_DCACHE_PORT_FULL 0 0 + +L2HIT_STREAM_PREF_L1_PORT_FULL 0 0 + +L2HIT_TRAIN_HIT_DEMAND 0 -nan% 0 -nan% +L2HIT_TRAIN_MISS_REQ 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_TRAIN_FILTER_MISS 0 -nan% 0 -nan% +L2HIT_TRAIN_FILTER_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_PREF_REQ_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_PREF_REQ_DCACHE_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_L2SEND_Q_FULL 0 -nan% 0 -nan% +L2HIT_L2SEND_Q_ENTER 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_MEM_REQ 0 0 + +REMOVE_REDUNDANT_STREAM_STAT 0 0 + +REPLACE_OLD_STREAM 1973 1973 + +REQ_SEND_QUEUE_STALL 0 0 + +STREAM_ENTER_RA 0 0 + +CORE_STREAM_LENGTH_0 87 11.083% 87 11.083% +CORE_STREAM_LENGTH_10 119 15.159% 119 15.159% +CORE_STREAM_LENGTH_20 90 11.465% 90 11.465% +CORE_STREAM_LENGTH_30 100 12.739% 100 12.739% +CORE_STREAM_LENGTH_40 56 7.134% 56 7.134% +CORE_STREAM_LENGTH_50 32 4.076% 32 4.076% +CORE_STREAM_LENGTH_60 20 2.548% 20 2.548% +CORE_STREAM_LENGTH_70 27 3.439% 27 3.439% +CORE_STREAM_LENGTH_80 66 8.408% 66 8.408% +CORE_STREAM_LENGTH_90 18 2.293% 18 2.293% +CORE_STREAM_LENGTH_100_P 170 21.656% 170 21.656% + 785 100.000% 785 100.000% + 4.69 3.97 4.69 3.97 + +CORE_CUM_STREAM_LENGTH_0 568 0.955% 568 0.955% +CORE_CUM_STREAM_LENGTH_10 1735 2.918% 1735 2.918% +CORE_CUM_STREAM_LENGTH_20 2167 3.645% 2167 3.645% +CORE_CUM_STREAM_LENGTH_30 3436 5.779% 3436 5.779% +CORE_CUM_STREAM_LENGTH_40 2449 4.119% 2449 4.119% +CORE_CUM_STREAM_LENGTH_50 1728 2.906% 1728 2.906% +CORE_CUM_STREAM_LENGTH_60 1270 2.136% 1270 2.136% +CORE_CUM_STREAM_LENGTH_70 2036 3.424% 2036 3.424% +CORE_CUM_STREAM_LENGTH_80 5392 9.069% 5392 9.069% +CORE_CUM_STREAM_LENGTH_90 1729 2.908% 1729 2.908% +CORE_CUM_STREAM_LENGTH_100_P 36948 62.141% 36948 62.141% + 59458 100.000% 59458 100.000% + 8.15 7.00 8.15 7.00 + +CORE_STREAM_TRAIN_HITS_0 199 25.350% 199 25.350% +CORE_STREAM_TRAIN_HITS_10 167 21.274% 167 21.274% +CORE_STREAM_TRAIN_HITS_20 78 9.936% 78 9.936% +CORE_STREAM_TRAIN_HITS_30 38 4.841% 38 4.841% +CORE_STREAM_TRAIN_HITS_40 26 3.312% 26 3.312% +CORE_STREAM_TRAIN_HITS_50 14 1.783% 14 1.783% +CORE_STREAM_TRAIN_HITS_60 93 11.847% 93 11.847% +CORE_STREAM_TRAIN_HITS_70 11 1.401% 11 1.401% +CORE_STREAM_TRAIN_HITS_80 11 1.401% 11 1.401% +CORE_STREAM_TRAIN_HITS_90 10 1.274% 10 1.274% +CORE_STREAM_TRAIN_HITS_100_P 138 17.580% 138 17.580% + 785 100.000% 785 100.000% + 3.57 3.57 3.57 3.57 + +CORE_CUM_STREAM_TRAIN_HITS_0 1271 2.754% 1271 2.754% +CORE_CUM_STREAM_TRAIN_HITS_10 2319 5.025% 2319 5.025% +CORE_CUM_STREAM_TRAIN_HITS_20 1866 4.043% 1866 4.043% +CORE_CUM_STREAM_TRAIN_HITS_30 1305 2.828% 1305 2.828% +CORE_CUM_STREAM_TRAIN_HITS_40 1149 2.490% 1149 2.490% +CORE_CUM_STREAM_TRAIN_HITS_50 769 1.666% 769 1.666% +CORE_CUM_STREAM_TRAIN_HITS_60 6034 13.074% 6034 13.074% +CORE_CUM_STREAM_TRAIN_HITS_70 807 1.749% 807 1.749% +CORE_CUM_STREAM_TRAIN_HITS_80 918 1.989% 918 1.989% +CORE_CUM_STREAM_TRAIN_HITS_90 947 2.052% 947 2.052% +CORE_CUM_STREAM_TRAIN_HITS_100_P 28767 62.331% 28767 62.331% + 46152 100.000% 46152 100.000% + 7.88 6.86 7.88 6.86 + +CORE_STREAM_TRAIN_CREATE 1989 1989 + + + diff --git a/labs/LAB5/runs/sgcc_base-sms1/PARAMS.in b/labs/LAB5/runs/sgcc_base-sms1/PARAMS.in new file mode 100644 index 00000000..2593c2b8 --- /dev/null +++ b/labs/LAB5/runs/sgcc_base-sms1/PARAMS.in @@ -0,0 +1,226 @@ +# File : PARAMS.kaby_lake +# Date : 03/06/19 +# Description : Kaby Lake Configuration +# +# Based on documentation found here: +# https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake + +## Simulation Parameters +--mode full +--model cmp +--sim_limit none + +## Core Parameters + +# Femptoseconds, 3.2GHz, used for energy estimates. +--chip_cycle_time 312500 + + +### Fetch Stage +--fetch_off_path_ops 1 +--fetch_across_cache_lines 1 + +# Will break the packet upon a taken branch. +--fetch_break_on_taken 1 + +# Number of bubble cycles to wait after taken branch. +--fetch_taken_bubble_cycles 0 + + +#### ICache +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 + +### Branch Predictor +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_mech tagescl + + +#### BTB + +# BTB model to use. +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 + +# Allow the BTB to be updated by off path ops. +--btb_off_path_writes 1 + + +#### CRS + +# Enable return stack +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 + +### iBP +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged + # iBTB Model. tc_tagless, tc_tagged, tc_hybrid. +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 + +### Decode Stage +--decode_cycles 5 + + +### Map Stage +--map_cycles 5 + + +### Issue Stage + +# Max number of instructions to be fetched, decoded, renamed, and issued per cycle. +--issue_width 6 + +--rs_fill_width 0 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 + + +### Exec Stage + +### DCache +--dcache_size 32768 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--dcache_assoc 4 +--dcache_line_size 64 + +### Reorder/Retire Stage + +# Max number of instructions to be retired per cycle. +--node_ret_width 6 +--node_table_size 224 + +# Do not keep stores in RSVs on cache misses; TODO: confirm what this knob does +--stores_do_not_block_window 1 + +# TODO: confirm what this knob does +--prefs_do_not_block_window 1 + + +## Uncore + +### Mid-level cache + +# Enable use of a midlevel cache between i/d and L1 +--mlc_present 0 + +### LLC +--l1_size 1048576 +--l1_banks 1 +--l1_cycles 18 +--l1_assoc 8 +--l1_line_size 64 +--l1_interleave_factor 64 + + +### Prefetcher +--pref_framework_on 1 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--pref_shared_queues 0 +--pref_train_on_pref_misses 0 +--pref_oracle_train 0 +--pref_ul1req_queue_overwrite_on_full 1 + +--stream_length 64 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 + +--pref_throttlefb_on=1 +--pref_acc_thresh_1=0.75 +--pref_acc_thresh_2=0.4 +--pref_acc_thresh_3=0.4 +--pref_timely_thresh=0.01 +--pref_polpf_thresh=0.005 +--pref_update_interval=8192 + +--mem_req_buffer_pref_watermark 4 +--promote_to_higher_priority_mem_req_type 1 + +### Memory +--addr_translation random + +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 + +--mem_req_buffer_entries 32 +--mem_l1_fill_queue_entries 32 +--va_page_size_bytes 4096 +--bus_width_in_bytes 8 + +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 + +## Other + + +### Debug +--debug_inst_start 0 +--debug_inst_stop -1 +--debug_cycle_start 0 +--debug_cycle_stop -1 + + +## Stats and Params +--dump_params 1 +--dump_stats 1 +--dump_trace 0 + +#################################### +--set_off_path_confirmed 1 + +--order_beyond_bus 1 + +--mem_ooo_stores 1 +--mem_obey_store_dep 1 diff --git a/labs/LAB5/runs/sgcc_base-sms1/PARAMS.out b/labs/LAB5/runs/sgcc_base-sms1/PARAMS.out new file mode 100644 index 00000000..94d10918 --- /dev/null +++ b/labs/LAB5/runs/sgcc_base-sms1/PARAMS.out @@ -0,0 +1,908 @@ +--mode full +--model cmp +--frontend memtrace +--inst_limit 100000000 +--sim_limit none +--dump_params 1 +--dump_stats 1 +--dump_trace 0 +--mlc_present 0 +--l1_size 1048576 +--l1_assoc 8 +--l1_line_size 64 +--l1_cycles 18 +--l1_banks 1 +--l1_interleave_factor 64 +--va_page_size_bytes 4096 +--addr_translation random +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 +--dcache_size 32768 +--dcache_assoc 4 +--dcache_line_size 64 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--mem_ooo_stores 1 +--mem_obey_store_dep 1 +--mem_req_buffer_entries 32 +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 +--promote_to_higher_priority_mem_req_type 1 +--mem_req_buffer_pref_watermark 4 +--mem_l1_fill_queue_entries 32 +--order_beyond_bus 1 +--set_off_path_confirmed 1 +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--bus_width_in_bytes 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 +--chip_cycle_time 312500 +--issue_width 6 +--rs_fill_width 0 +--node_table_size 224 +--node_ret_width 6 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 +--decode_cycles 5 +--map_cycles 5 +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--fetch_across_cache_lines 1 +--fetch_off_path_ops 0 +--fetch_break_on_taken 1 +--fetch_taken_bubble_cycles 0 +--stores_do_not_block_window 1 +--prefs_do_not_block_window 1 +--cbp_trace_r0 /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir/trace/drmemtrace.sgcc_base.mytest-m64.555062.3859.trace.gz +--memtrace_modules_log /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir/raw +--debug_cycle_start 0 +--debug_cycle_stop -1 +--debug_inst_start 0 +--debug_inst_stop -1 +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--bp_mech tagescl +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 +--btb_off_path_writes 1 +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_length 64 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 +--pref_framework_on 1 +--pref_shared_queues 0 +--pref_ul1req_queue_overwrite_on_full 1 +--pref_train_on_pref_misses 0 +--pref_oracle_train_on 0 +--pref_throttlefb_on 1 +--pref_acc_thresh_1 0.75 +--pref_acc_thresh_2 0.4 +--pref_acc_thresh_3 0.4 +--pref_update_interval 8192 +--pref_timely_thresh 0.01 +--pref_polpf_thresh 0.005 +--pref_sms_on 1 +1 1 1 1 1 1 1 + +--- Cut out everything below to use this file as PARAMS.in --- + +Parameter status at compile time and values supplied on the command line: + +SIM_MODE 0 full +SIM_MODEL 0 cmp +FRONTEND FE_PIN_EXEC_DRIVEN memtrace +INST_LIMIT NULL 100000000 +SIM_LIMIT "none" none +FORWARD_PROGRESS_LIMIT 100000000 +FORWARD_PROGRESS_INTERVAL 10000 +FAST_FORWARD 0 +FAST_FORWARD_UNTIL_ADDR 0 +FAST_FORWARD_TRACE_INS 0 +WARMUP 0 +HEARTBEAT_INTERVAL 1000000 +NUM_HEARTBEATS 0 +FILE_TAG "" +OUTPUT_DIR "." +STATUS_FILE NULL +BINDIR NULL +DUMP_PARAMS TRUE 1 +DUMP_STATS TRUE 1 +DUMP_TRACE FALSE 0 +CLEAR_STATS "never" +STATS_TO_TRACE NULL +STAT_TRACE_FILE "stats.trace" +STAT_TRACE_INTERVAL "i:100000" +PIPEVIEW FALSE +PIPEVIEW_FILE "pipeview" +MEMVIEW FALSE +MEMVIEW_FILE "memview.out" +MEMVIEW_START "never" +INST_HASH_TABLE_SIZE 500021 const +STDOUT_FILE NULL +STDERR_FILE NULL +PIN_EXEC_DRIVEN_FE_SOCKET "./pin_exec_driven_fe_socket.temp" +PRINT_PID FALSE +USE_UNSURE_FREE_LISTS FALSE +OPTIMIZER2_MAX_NUM_SLAVES 64 +OPTIMIZER2_PERFECT_MEMORYLESS FALSE +EXIT_COND 0 +ENABLE_SWPRF FALSE +MLC_PRESENT FALSE 0 +MLC_SIZE (512 * 1024) +MLC_ASSOC 4 +MLC_LINE_SIZE 64 +MLC_CYCLES 12 +PERFECT_MLC FALSE +MLC_READ_PORTS 1 +MLC_WRITE_PORTS 1 +MLC_BANKS 8 +MLC_INTERLEAVE_FACTOR 64 +MLC_CACHE_REPL_POLICY 0 +MLC_WRITE_THROUGH FALSE +PREFETCH_UPDATE_LRU_MLC TRUE +FORCE_L1_MISS FALSE +L1_SIZE (4 * 1024 * 1024) 1048576 +L1_ASSOC 8 8 +L1_LINE_SIZE 64 64 +L1_CYCLES 24 18 +PERFECT_L1 FALSE +PRIVATE_L1 FALSE +L1_READ_PORTS 1 +L1_WRITE_PORTS 1 +L1_BANKS 8 1 +L1_INTERLEAVE_FACTOR 64 64 +L1_CACHE_REPL_POLICY 0 +L1_WRITE_THROUGH FALSE +L1_IGNORE_WB FALSE +L1_USE_CORE_FREQ FALSE +MARK_L1_MISSES TRUE +PREFETCH_UPDATE_LRU_L1 TRUE +MEMORY_RANDOM_ADDR FALSE +VA_PAGE_SIZE_BYTES 4096 4096 +NUM_ADDR_NON_SIGN_EXTEND_BITS 48 +ADDR_TRANSLATION 0 random +CONSTANT_MEMORY_LATENCY FALSE +MEMORY_CYCLES 100 +STALL_MEM_REQS_ONLY FALSE +ICACHE_SIZE (64 * 1024) 32768 +ICACHE_ASSOC 4 4 +ICACHE_LINE_SIZE 64 64 +PERFECT_ICACHE FALSE +ICACHE_READ_PORTS 2 +ICACHE_WRITE_PORTS 1 +ICACHE_BANKS 8 +ICACHE_REPL 0 +DCACHE_SIZE (64 * 1024) 32768 +DCACHE_ASSOC 1 4 +DCACHE_LINE_SIZE 64 64 +DCACHE_CYCLES 2 +PERFECT_DCACHE FALSE +DCACHE_READ_PORTS 8 2 +DCACHE_WRITE_PORTS 1 1 +DCACHE_BANKS 1 1 +DCACHE_REPL 0 +DCACHE_REPL_PREF_THRESH 1 +MEM_OOO_STORES TRUE 1 +MEM_OBEY_STORE_DEP TRUE 1 +PREF_INSERT_LRU FALSE +PREF_INSERT_MIDDLE FALSE +PREF_INSERT_LOWQTR FALSE +PREF_INSERT_DYNACC FALSE +MEM_REQ_BUFFER_ENTRIES 32 32 +PRIVATE_MSHR_ON TRUE +MEM_PRIORITY_IFETCH 0 0 +MEM_PRIORITY_DFETCH 0 1 +MEM_PRIORITY_DSTORE 0 2 +MEM_PRIORITY_IPRF 9 3 +MEM_PRIORITY_DPRF 10 4 +MEM_PRIORITY_WB 0 5 +MEM_PRIORITY_WB_NODIRTY 0 5 +PROMOTE_TO_HIGHER_PRIORITY_MEM_REQ_TYPE FALSE 1 +MEM_REQ_BUFFER_PREF_WATERMARK 0 4 +MEM_REQ_BUFFER_WB_VALVE 2 +MEM_L1_FILL_QUEUE_ENTRIES 32 32 +MEM_BUS_OUT_QUEUE_PARTITION_ENABLE FALSE +MEM_MEM_QUEUE_PARTITION_ENABLE FALSE +MEM_BUS_OUT_QUEUE_AS_FIFO TRUE +OLDEST_FIRST_TO_MEM_QUEUE TRUE +ROUND_ROBIN_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE_TH 0 +L1_CYCLE_TIME 312500 +MLCQ_TO_L1Q_TRANSFER_LATENCY 1 +L1Q_TO_FSB_TRANSFER_LATENCY 1 +PRIORITIZE_PREFETCHES_WITH_UNIQUE FALSE +KICKOUT_PREFETCHES FALSE +KICKOUT_LOOK_FOR_OLDEST_FIRST FALSE +KICKOUT_OLDEST_PREFETCH FALSE +KICKOUT_OLDEST_PREFETCH_WITHIN_BANK FALSE +ORDER_BEYOND_BUS FALSE 1 +ALL_FIFO_QUEUES FALSE +QUEUE_MLC_SIZE 0 +QUEUE_L1_SIZE 0 +QUEUE_BUS_OUT_SIZE 0 +QUEUE_CORE_FILL_SIZE 0 +ALLOW_TYPE_MATCHES FALSE +STREAM_PREFETCH_ON FALSE +DC_PREF_CACHE_ENABLE FALSE +DC_PREF_CACHE_CYCLE 0 +PREF_INSERT_DCACHE_IMM TRUE +DC_PREF_CACHE_SIZE (64 * 1024) +DC_PREF_CACHE_ASSOC 4 +DC_PREF_ONLY_L1HIT FALSE +PREF_CACHE_USE_RDY_CYCLE FALSE +IC_PREF_CACHE_ENABLE FALSE +IC_PREF_CACHE_SIZE (64 * 1024) +IC_PREF_CACHE_ASSOC 4 +L1_PREF_CACHE_ENABLE FALSE +L1_PREF_CACHE_SIZE (1024 * 1024) +L1_PREF_CACHE_ASSOC 8 +SET_OFF_PATH_CONFIRMED FALSE 1 +USE_CONFIRMED_OFF FALSE +PREFCACHE_MOVE_OFFPATH FALSE +CACHE_STAT_ENABLE FALSE +PREF_DCACHE_HIT_FILL_L1 TRUE +PREF_ICACHE_HIT_FILL_L1 TRUE +CRITICAL_ACCESS_PLOT_ENABLE FALSE +CRITICAL_ACCESS_PLOT_FILE "critical_access_plot.dat" +ROUND_ROBIN_TO_L1 FALSE +PREF_I_TOGETHER FALSE +ONE_MORE_CACHE_LINE_ENABLE FALSE +L1_STATIC_PARTITION_ENABLE 0 +L1_STATIC_PARTITION NULL +L1_DYNAMIC_PARTITION_ENABLE FALSE +L1_DYNAMIC_PARTITION_POLICY 0 +PARTITION_UMON_DSS_PREF_ENABLE FALSE +L1_CACHE_HIT_POSITION_COLLECT FALSE +L1_PART_ON FALSE +L1_PART_TRIGGER "c:1000000" +L1_PART_START "t:0" +L1_PART_WARMUP FALSE +L1_PART_SHADOW_WARMUP FALSE +L1_PART_METRIC 0 +L1_PART_SEARCH 0 +L1_PART_USE_STALLING TRUE +L1_PART_FILL_DELAY 0 +L1_SHADOW_TAGS_MODULO 1 +HIER_MSHR_ON FALSE +PERF_PRED_ENABLE FALSE +PERF_PRED_MECH PERF_PRED_CP +PERF_PRED_REQ_LATENCY_MECH PERF_PRED_REQ_LATENCY_MECH_REQ_LATENCY +PERF_PRED_COUNT_ALL FALSE +PERF_PRED_COUNT_INST_MISSES TRUE +PERF_PRED_COUNT_PREFETCHES FALSE +PERF_PRED_COUNT_OFFPATH_REQS FALSE +PERF_PRED_COUNT_BW_REQS TRUE +PERF_PRED_UPDATE_MEM_REQ_TYPE FALSE +PERF_PRED_SLACK_PERIOD_SIZE 32 +PERF_PRED_REQS_FINISH_AT_FILL FALSE +PERF_PRED_MEM_UTIL_VIA_BUS_BW FALSE +PERF_PRED_CHIP_UTIL_VIA_MEM_STALL FALSE +DUMB_MODEL_AVG_REQ_DISTANCE 100 +DUMB_MODEL_RANDOMIZE_DISTANCE FALSE +DUMB_MODEL_AVG_REQ_DISTANCE_PER_CORE NULL +DUMB_MODEL_AVG_ROW_HITS 1 +DUMB_MODEL_AVG_ROW_HITS_PER_CORE NULL +DUMB_MODEL_MLP 1 +DUMB_MODEL_MLP_PER_CORE NULL +RAMULATOR_STANDARD "DDR4" DDR4 +RAMULATOR_SPEED "DDR4_2400R" DDR4_2400R +RAMULATOR_ORG "DDR4_8Gb_x8" DDR4_8Gb_x8 +RAMULATOR_CHANNELS 1 1 +RAMULATOR_RANKS 1 1 +RAMULATOR_BANKGROUPS 4 4 +RAMULATOR_BANKS 4 4 +RAMULATOR_CHIP_WIDTH 8 8 +BUS_WIDTH_IN_BYTES 8 8 +RAMULATOR_ROWS 65536 65536 +RAMULATOR_COLS 1024 1024 +RAMULATOR_SCHEDULING_POLICY "FRFCFS_Cap" FRFCFS_Cap +RAMULATOR_READQ_ENTRIES 32 32 +RAMULATOR_WRITEQ_ENTRIES 32 32 +RAMULATOR_REC_CMD_TRACE "off" FALSE +RAMULATOR_PRINT_CMD_TRACE "off" FALSE +RAMULATOR_USE_REST_OF_ADDR_AS_ROW_ADDR "on" +RAMULATOR_TCK 833333 833333 +RAMULATOR_TCL 16 16 +RAMULATOR_TCCD 6 6 +RAMULATOR_TCCDS 4 4 +RAMULATOR_TCCDL 6 6 +RAMULATOR_TCWL 12 12 +RAMULATOR_TBL 4 4 +RAMULATOR_TWTR 9 9 +RAMULATOR_TWTRS 3 3 +RAMULATOR_TWTRL 9 9 +RAMULATOR_TRP 16 16 +RAMULATOR_TRPpb 16 16 +RAMULATOR_TRPab 16 16 +RAMULATOR_TRCD 16 16 +RAMULATOR_TRCDR 16 16 +RAMULATOR_TRCDW 16 16 +RAMULATOR_TRAS 39 39 +DRAM_TECH_IN_NM 32 32 +DVFS_ON FALSE +DVFS_METRIC DVFS_METRIC_NUM_ELEMS +DVFS_CONFIGS NULL +DVFS_CONFIG_FILE NULL +DVFS_START "t:0" +DVFS_PERIOD "t:312500000000" +DVFS_LOG TRUE +DVFS_INDIVIDUAL_CORES FALSE +DVFS_CHIP_LEVEL FALSE +DVFS_STATIC NULL +DVFS_FORCE_CONFIG NULL +DVFS_REPLAY_CONFIG_TRACE NULL +DVFS_USE_ORACLE FALSE +DVFS_USE_BW_SHARING FALSE +DVFS_USE_DRAM_SHARING FALSE +DVFS_USE_STALL_TIME FALSE +DVFS_DRAM_SHARING_SOLVER_BIN NULL +DVFS_DRAM_SHARING_SOLVER_STRICT TRUE +DVFS_BW_SHARING_BUS_UTIL_THRESH 0.95 +DVFS_BW_SHARING_MAX_REQS 28.0 +DVFS_BW_SHARING_MAX_RW_COST 0.25 +DVFS_BW_SHARING_NO_PREF_STALL TRUE +DVFS_BW_SHARING_CRIT_STATS TRUE +DVFS_COUNT_L1_ACCESS_STALL FALSE +NUM_CORES 1 +CHIP_CYCLE_TIME 312500 312500 +CORE_0_CYCLE_TIME 312500 +CORE_1_CYCLE_TIME 312500 +CORE_2_CYCLE_TIME 312500 +CORE_3_CYCLE_TIME 312500 +CORE_4_CYCLE_TIME 312500 +CORE_5_CYCLE_TIME 312500 +CORE_6_CYCLE_TIME 312500 +CORE_7_CYCLE_TIME 312500 +CORE_8_CYCLE_TIME 312500 +CORE_9_CYCLE_TIME 312500 +CORE_10_CYCLE_TIME 312500 +CORE_11_CYCLE_TIME 312500 +CORE_12_CYCLE_TIME 312500 +CORE_13_CYCLE_TIME 312500 +CORE_14_CYCLE_TIME 312500 +CORE_15_CYCLE_TIME 312500 +CORE_16_CYCLE_TIME 312500 +CORE_17_CYCLE_TIME 312500 +CORE_18_CYCLE_TIME 312500 +CORE_19_CYCLE_TIME 312500 +CORE_20_CYCLE_TIME 312500 +CORE_21_CYCLE_TIME 312500 +CORE_22_CYCLE_TIME 312500 +CORE_23_CYCLE_TIME 312500 +CORE_24_CYCLE_TIME 312500 +CORE_25_CYCLE_TIME 312500 +CORE_26_CYCLE_TIME 312500 +CORE_27_CYCLE_TIME 312500 +CORE_28_CYCLE_TIME 312500 +CORE_29_CYCLE_TIME 312500 +CORE_30_CYCLE_TIME 312500 +CORE_31_CYCLE_TIME 312500 +CORE_32_CYCLE_TIME 312500 +CORE_33_CYCLE_TIME 312500 +CORE_34_CYCLE_TIME 312500 +CORE_35_CYCLE_TIME 312500 +CORE_36_CYCLE_TIME 312500 +CORE_37_CYCLE_TIME 312500 +CORE_38_CYCLE_TIME 312500 +CORE_39_CYCLE_TIME 312500 +CORE_40_CYCLE_TIME 312500 +CORE_41_CYCLE_TIME 312500 +CORE_42_CYCLE_TIME 312500 +CORE_43_CYCLE_TIME 312500 +CORE_44_CYCLE_TIME 312500 +CORE_45_CYCLE_TIME 312500 +CORE_46_CYCLE_TIME 312500 +CORE_47_CYCLE_TIME 312500 +CORE_48_CYCLE_TIME 312500 +CORE_49_CYCLE_TIME 312500 +CORE_50_CYCLE_TIME 312500 +CORE_51_CYCLE_TIME 312500 +CORE_52_CYCLE_TIME 312500 +CORE_53_CYCLE_TIME 312500 +CORE_54_CYCLE_TIME 312500 +CORE_55_CYCLE_TIME 312500 +CORE_56_CYCLE_TIME 312500 +CORE_57_CYCLE_TIME 312500 +CORE_58_CYCLE_TIME 312500 +CORE_59_CYCLE_TIME 312500 +CORE_60_CYCLE_TIME 312500 +CORE_61_CYCLE_TIME 312500 +CORE_62_CYCLE_TIME 312500 +CORE_63_CYCLE_TIME 312500 +ISSUE_WIDTH 4 6 +RS_FILL_WIDTH 8 0 +NODE_TABLE_SIZE 256 224 +NODE_RET_WIDTH 4 6 +NODE_RETIRE_RATE 10 +RS_SIZES "256" 97 +RS_CONNECTIONS "xF" 0 +FU_TYPES "0, 0, 0, 0" 0 0 0 0 0 0 0 0 +DECODE_CYCLES 1 5 +MAP_CYCLES 1 5 +EXTRA_RECOVERY_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after recovery. +EXTRA_REDIRECT_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after redirect. +EXTRA_CALLSYS_CYCLES 20 const +DIE_ON_CALLSYS FALSE +DIE_ON_RET_STALL_THRESH 0 +DIE_ON_RET_STALL_CORE 0 +DIE_ON_MEM_BLOCK_THRESH 0 +DIE_ON_MEM_BLOCK_CORE 0 +FETCH_ACROSS_CACHE_LINES FALSE 1 +FETCH_OFF_PATH_OPS TRUE 0 +FETCH_BREAK_ON_TAKEN FALSE 1 +FETCH_TAKEN_BUBBLE_CYCLES 0 0 +WP_COLLECT_STATS FALSE +SWITCH_IC_FETCH_ON_RECOVERY TRUE +OP_INV_DELAY 1 +OP_NOP_DELAY 1 +OP_CF_DELAY 1 +OP_MOV_DELAY 1 +OP_CMOV_DELAY 1 +OP_LDA_DELAY 1 +OP_IMEM_DELAY 1 +OP_IADD_DELAY 1 +OP_IMUL_DELAY 3 +OP_IDIV_DELAY -20 +OP_ICMP_DELAY 1 +OP_LOGIC_DELAY 1 +OP_SHIFT_DELAY 1 +OP_FMEM_DELAY 1 +OP_FCVT_DELAY 3 +OP_FADD_DELAY 3 +OP_FMUL_DELAY 5 +OP_FMA_DELAY 5 +OP_FDIV_DELAY -20 +OP_FCMP_DELAY 3 +OP_FCMOV_DELAY 1 +OP_GATHER_DELAY 12 +OP_SCATTER_DELAY 18 +OP_PIPELINED_FAST_DELAY 2 +OP_PIPELINED_MEDIUM_DELAY 5 +OP_PIPELINED_SLOW_DELAY 10 +OP_NOTPIPELINED_MEDIUM_DELAY -5 +OP_NOTPIPELINED_SLOW_DELAY -20 +OP_NOTPIPELINED_VERY_SLOW_DELAY -100 +UNIFORM_OP_DELAY 0 +STALL_ON_WAIT_MEM TRUE +STORES_DO_NOT_BLOCK_WINDOW FALSE 1 +PREFS_DO_NOT_BLOCK_WINDOW FALSE 1 +OBEY_REG_DEP TRUE +OLDEST_FIRST_SCHED FALSE +FIND_EMPTIEST_RS FALSE +TRACK_L1_MISS_DEPS FALSE +CBP_TRACE_R0 NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir/trace/drmemtrace.sgcc_base.mytest-m64.555062.3859.trace.gz +CBP_TRACE_R1 NULL +CBP_TRACE_R2 NULL +CBP_TRACE_R3 NULL +CBP_TRACE_R4 NULL +CBP_TRACE_R5 NULL +CBP_TRACE_R6 NULL +CBP_TRACE_R7 NULL +CBP_TRACE_R8 NULL +CBP_TRACE_R9 NULL +CBP_TRACE_R10 NULL +CBP_TRACE_R11 NULL +CBP_TRACE_R12 NULL +CBP_TRACE_R13 NULL +CBP_TRACE_R14 NULL +CBP_TRACE_R15 NULL +CBP_TRACE_R16 NULL +CBP_TRACE_R17 NULL +CBP_TRACE_R18 NULL +CBP_TRACE_R19 NULL +CBP_TRACE_R20 NULL +CBP_TRACE_R21 NULL +CBP_TRACE_R22 NULL +CBP_TRACE_R23 NULL +CBP_TRACE_R24 NULL +CBP_TRACE_R25 NULL +CBP_TRACE_R26 NULL +CBP_TRACE_R27 NULL +CBP_TRACE_R28 NULL +CBP_TRACE_R29 NULL +CBP_TRACE_R30 NULL +CBP_TRACE_R31 NULL +CBP_TRACE_R32 NULL +CBP_TRACE_R33 NULL +CBP_TRACE_R34 NULL +CBP_TRACE_R35 NULL +CBP_TRACE_R36 NULL +CBP_TRACE_R37 NULL +CBP_TRACE_R38 NULL +CBP_TRACE_R39 NULL +CBP_TRACE_R40 NULL +CBP_TRACE_R41 NULL +CBP_TRACE_R42 NULL +CBP_TRACE_R43 NULL +CBP_TRACE_R44 NULL +CBP_TRACE_R45 NULL +CBP_TRACE_R46 NULL +CBP_TRACE_R47 NULL +CBP_TRACE_R48 NULL +CBP_TRACE_R49 NULL +CBP_TRACE_R50 NULL +CBP_TRACE_R51 NULL +CBP_TRACE_R52 NULL +CBP_TRACE_R53 NULL +CBP_TRACE_R54 NULL +CBP_TRACE_R55 NULL +CBP_TRACE_R56 NULL +CBP_TRACE_R57 NULL +CBP_TRACE_R58 NULL +CBP_TRACE_R59 NULL +CBP_TRACE_R60 NULL +CBP_TRACE_R61 NULL +CBP_TRACE_R62 NULL +CBP_TRACE_R63 NULL +MEMTRACE_MODULES_LOG NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.sgcc_base.mytest-m64.555062.6619.dir/raw +DUMB_CORE_ON FALSE +DUMB_CORE 1 +DEBUG_CYCLE_START 0 0 +DEBUG_CYCLE_STOP 0 -1 +DEBUG_TIME_START 0 +DEBUG_TIME_STOP 0 +DEBUG_INST_START 0 0 +DEBUG_INST_STOP 0 -1 +DEBUG_OP_START 0 +DEBUG_OP_STOP 0 +DEBUG_CACHE_LIB FALSE +DEBUG_HASH_LIB FALSE +DEBUG_LIST_LIB FALSE +DEBUG_PORT_LIB FALSE +DEBUG_BUS_LIB FALSE +DEBUG_OP_POOL FALSE +DEBUG_ORACLE FALSE +DEBUG_FRONTEND FALSE +DEBUG_ADDR_TRANS FALSE +DEBUG_BP FALSE +DEBUG_BP_DIR FALSE +DEBUG_BTB FALSE +DEBUG_CRS FALSE +DEBUG_MAP FALSE +DEBUG_MEMORY FALSE +DEBUG_REPLAY FALSE +DEBUG_FREQ FALSE +DEBUG_MODEL FALSE +DEBUG_THREAD FALSE +DEBUG_ICACHE_STAGE FALSE +DEBUG_DECODE_STAGE FALSE +DEBUG_MAP_STAGE FALSE +DEBUG_NODE_STAGE FALSE +DEBUG_EXEC_STAGE FALSE +DEBUG_DCACHE_STAGE FALSE +DEBUG_RETIRED_UOPS FALSE +DEBUG_EXC_INSERTS FALSE +DEBUG_BP_CONF FALSE +DEBUG_ONPATH_CONF FALSE +DEBUG_STREAM FALSE +DEBUG_STREAM_MEM FALSE +DEBUG_WAY FALSE +DEBUG_L2MARKV FALSE +DEBUG_L2L1PREF FALSE +DEBUG_PERF_PRED FALSE +DEBUG_POWER_UTILS FALSE +DEBUG_DVFS FALSE +DEBUG_TRACE_READ FALSE +DEBUG_INST_FIELDS FALSE +DEBUG_OP_FIELDS FALSE +DEBUG_PIN_EXEC_DRIVEN FALSE +DEBUG_CACHE_PART FALSE +DEBUG_OPTIMIZER2 FALSE +DEBUG_PREF FALSE +PERFECT_BP FALSE +PERFECT_BTB FALSE +PERFECT_IBP FALSE +PERFECT_CRS FALSE +PERFECT_CBR_BTB FALSE +PERFECT_NT_BTB FALSE +CFS_PER_CYCLE 3 6 # Number of branches that can be predicted in a single cycle +UPDATE_BP_OFF_PATH FALSE 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +BP_UPDATE_AT_RETIRE FALSE 0 # Update the BP at retire. If false, update at the end of exec. +BP_MECH 0 tagescl +LATE_BP_MECH NUM_BP +LATE_BP_LATENCY 5 +HIST_LENGTH 16 +PHT_CTR_BITS 2 const +BHT_ENTRIES (4 * 1024) +BHT_ASSOC 4 +HYBRIDS_INDEX_LENGTH 16 +HYBRIDG_HIST_LENGTH 16 +HYBRIDP_HIST_LENGTH 16 +FILTER_INDEX_LENGTH 16 +USE_FILTER FALSE +INF_HYBRIDGP FALSE +BP_HASH_TOS FALSE +IBTB_HASH_TOS FALSE +BTB_MECH 0 generic +BTB_ENTRIES (4 * 1024) 4096 +BTB_ASSOC 4 4 +BTB_OFF_PATH_WRITES TRUE 1 +ENABLE_CRS TRUE 1 +CRS_ENTRIES 32 32 +CRS_REALISTIC 0 1 +ENABLE_IBP TRUE 1 # Enable the indirect branch predictor +USE_PAT_HIST TRUE +IBTB_MECH 1 tc_tagged +IBTB_HIST_LENGTH 16 +IBTB_OFF_PATH_WRITES TRUE 1 # Allow off path ops to update the ibtb. +TARGETS_IN_HIST 4 +TC_ENTRIES (4 * 1024) 4096 +TC_ASSOC 4 4 +NUM_CORR_BRANCHES 3 +SEL_HIST_BP_ENTRIES 8192 +SEL_HIST_LENGTH 16 +SEL_HIST_DYN_CNT_TH 16 +SEL_HIST_MISPRED_TH 4 +ENABLE_BP_CONF FALSE +CONF_MECH 0 +PERF_BP_CONF_PRED FALSE +BPC_BITS 16 +BPC_MECH 1 +BPC_CTR_RESET TRUE +BPC_CIT_BITS 8 +BPC_CIT_TH 50 +BPC_CTR_BITS 3 +OPC_COUNT_ZEROS FALSE +OPC_COUNT_THRESH 10 +INF_LOOP FALSE +INF_LOOP_BUCKETS 811 +LOOP_ENTRIES (4 * 1024) +LOOP_ASSOC 4 +LOOP_COUNT_MAX 127 +LOOP_REPEAT_MAX 15 +KNOB_PRINT_BRINFO FALSE +BR_MISPRED_FILE NULL +CONF_PERCEPTRON_TH 0 +CONF_PERCEPTRON_CTR_BITS 8 +CONF_PERCEPTRON_ENTRIES 127 +CONF_PERCEPTRON_THRESH_OVRD 0 +CONF_HIST_LENGTH 32 +PERCEPTRON_CONF_USE_CONF FALSE +PERCEPTRON_CONF_TRAIN_HIS FALSE +PERCEPTRON_CONF_TRAIN_CONF FALSE +PERCEPTRON_CONF_TRAIN_OFFSET_CONF FALSE +PERCEPTRON_TRAIN_MISP_FACTOR 1 +PERCEPTRON_TRAIN_CORR_FACTOR 1 +PERCEPTRON_CONF_HIS_BOTH FALSE +PERCEPTRON_CONF_HIS_BOTH_LENGTH 4 +ENABLE_ICACHE_PACKET_BREAKING TRUE +NUM_LOAD_STORE_PER_PACKET 0 +PACKET_BREAK_ON_FUS FALSE +PACKET_BREAK_FU_TYPES "G,G,G,G,G,G,G,G,G,G,G,G" +POWER_INTF_ON FALSE +POWER_INTF_ENABLE_SCALING FALSE +POWER_INTF_EXEC "power/power_intf.py" +POWER_INTF_REF_CHIP_TECH_NM 22 +POWER_INTF_REF_CHIP_FREQ (3.2e9) +POWER_INTF_REF_MEMORY_FREQ (0.8e9) +POWER_OTHER (0.0) +PREF_STREAM_ON FALSE 1 +PREF_STREAM_PER_CORE_ENABLE FALSE 1 +STREAM_BUFFER_N 16 +STREAM_PREFETCH_N 2 4 +STREAM_START_DIS 5 1 +STREAM_LENGTH 16 64 +STREAM_FULL_N 1 +STREAM_TRAIN_LENGTH 16 +STREAM_TRAIN_NUM 1 4 +PREF_ACC_USE_CACHE FALSE +STREAM_STALL_ON_QUEUE_FULL FALSE +PREF_SCHEDULE_NUM 4 +TRAIN_FILTER_SIZE 32 +PREF_REQ_Q_SIZE 64 +STREAM_CREATE_ON_DC_MISS FALSE 0 +STREAM_CREATE_ON_L1_MISS TRUE 1 +STREAM_TRAIN_ON_WRONGPATH TRUE +STREAM_CREATE_ON_WRONGPATH TRUE +STREAM_PREF_INTO_DCACHE FALSE +REMOVE_REDUNDANT_STREAM FALSE +L2HIT_STREAM_SCHEDULE_NUM 4 +PREF_REQ_QUEUE_FILTER_ON FALSE +HW_PREF_HIT_TRAIN_STREAM FALSE +L2HIT_STREAM_BUFFER_N 32 +L2HIT_STREAM_PREFETCH_N 2 +L2HIT_STREAM_START_DIS 2 +L2HIT_STREAM_LENGTH 8 +L2HIT_PREF_REQ_Q_SIZE 128 +L2HIT_L2ACCESS_REQ_Q_SIZE 64 +PREF_STREAM_ACCPERSTREAM FALSE +PREF_ACC_DISTANCE_10 128 +PREF_FRAMEWORK_ON FALSE 1 +PREF_TRACE_ON FALSE +PREF_DL0REQ_QUEUE_SIZE 32 +PREF_UMLC_REQ_QUEUE_SIZE 64 +PREF_UL1REQ_QUEUE_SIZE 128 +PREF_SHARED_QUEUES TRUE 0 +PREF_DL0_MISS_ON TRUE +PREF_DL0_HIT_ON TRUE +PREF_DL0REQ_QUEUE_FILTER_ON TRUE +PREF_UMLC_REQ_QUEUE_FILTER_ON TRUE +PREF_UL1REQ_QUEUE_FILTER_ON TRUE +PREF_DL0REQ_ADD_FILTER_ON TRUE +PREF_UMLC_REQ_ADD_FILTER_ON TRUE +PREF_UL1REQ_ADD_FILTER_ON TRUE +PREF_DL0REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UMLC_REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UL1REQ_QUEUE_OVERWRITE_ON_FULL FALSE 1 +PREF_DL0SCHEDULE_NUM 4 +PREF_UMLC_SCHEDULE_NUM 4 +PREF_UL1SCHEDULE_NUM 4 +PREF_L1Q_DEMAND_RESERVE 0 +PREF_REPORT_PREF_MATCH_AS_MISS FALSE +PREF_REPORT_PREF_MATCH_AS_HIT TRUE +PREF_UPDATE_ON_WRONGPATH TRUE +PREF_TRAIN_ON_PREF_MISSES FALSE 0 +PREF_ORACLE_TRAIN_ON FALSE 0 +PREF_REQ_DROP FALSE +PREF_THROTTLE_ON FALSE +PREF_THROTTLEFB_ON FALSE 1 +PREF_ACC_THRESH_1 0.90 0.75 +PREF_ACC_THRESH_2 0.70 0.4 +PREF_ACC_THRESH_3 0.60 0.4 +PREF_ACC_THRESH_4 0.40 +PREF_UPDATE_INTERVAL 0 8192 +PREF_ANALYZE_LOAD FALSE +PREF_POL_THRESH_1 0.25 +PREF_POL_THRESH_2 0.10 +PREF_POLBV_ON FALSE +PREF_POLBV_SIZE 1024 +PREF_TIMELY_THRESH 0.05 0.01 +PREF_POLPF_THRESH 0.01 0.005 +PREF_DEGFB_USEONLYACC FALSE +PREF_DEGFB_USEONLYPOL FALSE +PREF_DEGFB_USEONLYLATE FALSE +PREF_TIMELY_THRESH_2 0.005 +PREF_DEGFB_STATPHASEFILE FALSE +PREF_MAX_DEGFB 4 +PREF_DHAL FALSE +PREF_DHAL_SENTTHRESH 16 +PREF_DHAL_USETHRESH_MAX 12 +PREF_DHAL_USETHRESH_MIN2 8 +PREF_DHAL_USETHRESH_MIN1 4 +PREF_DHAL_MAXDEG 64 +PREF_HFILTER_ON FALSE +PREF_HFILTER_INDEX_BITS 12 +PREF_HFILTER_USE_PC FALSE +PREF_HFILTER_PRED_USELESS_THRES 2 +PREF_HFILTER_RESET_ENABLE FALSE +PREF_HFILTER_RESET_INTERVAL 100000 +L2L1PREF_ON FALSE +L2WAY_PREF FALSE +L2MARKV_PREF_ON FALSE +L2NEXT_PREF_ON FALSE +L2HIT_STREAM_PREF_ON FALSE +L2L1_DC_HIT_TRAIN FALSE +L1_HIT_DUMP_FILE_ON FALSE +L1_HIT_DUMP_WO_TXT FALSE +L1_HIT_DUMPFILE "l1hit_dump.out" +IDEAL_L2_L1_PREFETCHER FALSE +IDEAL_L2_ICACHE_PREFETCHER FALSE +L1WAY_PREF_SEND_QUEUE 4 +L1PREF_REQ_QUEUE_SIZE 1024 +L1PREF_IMMEDIATE FALSE +L1WAY_PREF_TIMER_DIS 1000 +L1MARKV_PREF_SEND_QUEUE 4 +L1PREF_MARKV_REQ_QUEUE_SIZE 1024 +MARKV_L2ACCESS_REQ_Q_SIZE 64 +L1MARKV_PREF_IMMEDIATE FALSE +L1MARKV_PREF_TIMER_DIS 1 +L2L1_HIT_TRAIN TRUE +L1MARKV_REQ_TH 1 +L2L1_IMMEDIATE_PREF_CACHE FALSE +L2L1_FILL_PREF_CACHE FALSE +L2L1_L2_HIT_STAT FALSE +PREF_GHB_ON FALSE +DEBUG_PREF_GHB FALSE +PREF_GHB_BUFFER_N 1024 +PREF_GHB_INDEX_N 128 +PREF_GHB_CZONE_BITS 12 +PREF_GHB_DEGREE 16 +PREF_GHB_MAX_DEGREE 32 +PREF_STRIDE_ON FALSE +DEBUG_PREF_STRIDE FALSE +PREF_STRIDE_TABLE_N 1024 +PREF_STRIDE_REGION_BITS 16 +PREF_STRIDE_DEGREE 4 +PREF_STRIDE_DISTANCE 16 +PREF_STRIDE_STARTDISTANCE 1 +PREF_STRIDE_SINGLE_THRESH 6 +PREF_STRIDE_MULTI_THRESH 6 +PREF_STRIDE_SINGLE_STRIDE_MODE FALSE +PREF_STRIDEPC_ON FALSE +DEBUG_PREF_STRIDEPC FALSE +PREF_STRIDEPC_TABLE_N 1024 +PREF_STRIDEPC_DEGREE 4 +PREF_STRIDEPC_DISTANCE 16 +PREF_STRIDEPC_USELOADADDR FALSE +PREF_STRIDEPC_TRAINNUM 2 +PREF_STRIDEPC_STARTDIS 4 +PREF_PHASE_ON FALSE +PREF_PHASE_STUDY FALSE +DEBUG_PREF_PHASE FALSE +PREF_PHASE_PRIME_HASH 16381 +PREF_PHASE_INFOSIZE 16384 +PREF_PHASE_LOG2REGIONSIZE 12 +PREF_PHASE_REGIONENTRIES 64 +PREF_PHASE_TRACKEDREGIONS 32 +PREF_PHASE_INTERVAL 100000 +PREF_PHASE_TABLE_SIZE 64 +PREF_PHASE_MAXDIFF_THRESH 64 +PREF_PHASE_MIN_MISSES 64 +PREF_PHASE_MISSPER 0.4 +PREF_2DC_ON FALSE +DEBUG_PREF_2DC FALSE +PREF_2DC_CACHE_SIZE (1 * 1024) +PREF_2DC_CACHE_ASSOC 4 +PREF_2DC_CACHE_LINE_SIZE 1 +PREF_2DC_DEGREE 16 +PREF_2DC_ZONE_SHIFT 10 +PREF_2DC_TAG_SIZE 16 +PREF_2DC_NUM_REGIONS 64 +PREF_2DC_REGION_HASH 61 +PREF_MARKOV_ON FALSE +DEBUG_PREF_MARKOV FALSE +PREF_MARKOV_NUM_ENTRIES 65536 +PREF_MARKOV_NUM_NEXT_STATES 8 +PREF_MARKOV_SEND_ON_PREF_HIT TRUE +PREF_MARKOV_UPDATE_ON_PREF_HIT TRUE +PREF_MARKOV_TABLE_UPDATE_POLICY 0 +PREF_MARKOV_SEND_THRESHOLD 0 +PREF_SMS_ON FALSE 1 +PREF_SMS_AT_SIZE 64 +PREF_SMS_FT_SIZE 64 +PREF_SMS_PHT_SIZE 16384 +PREF_SMS_PRF_SIZE 1024 +PREF_SMS_REGION_SIZE 2048 diff --git a/labs/LAB5/runs/sgcc_base-sms1/bp.stat.0.out b/labs/LAB5/runs/sgcc_base-sms1/bp.stat.0.out new file mode 100644 index 00000000..139d4160 --- /dev/null +++ b/labs/LAB5/runs/sgcc_base-sms1/bp.stat.0.out @@ -0,0 +1,752 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 80868545 Instructions: 100000000 IPC: 1.23657 + +BTB_ON_PATH_MISS 639615 3.161% 639615 3.161% +BTB_ON_PATH_HIT 19595833 96.839% 19595833 96.839% + 20235448 100.000% 20235448 100.000% + 0.97 0.95 0.97 0.95 + +BTB_OFF_PATH_MISS 0 -nan% 0 -nan% +BTB_OFF_PATH_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BTB_ON_PATH_WRITE 639615 100.000% 639615 100.000% +BTB_OFF_PATH_WRITE 0 0.000% 0 0.000% + 639615 100.000% 639615 100.000% + 0.00 0.00 0.00 0.00 + +BP_ON_PATH_CORRECT 19561758 96.671% 19561758 96.671% +BP_ON_PATH_MISPREDICT 13468 0.067% 13468 0.067% +BP_ON_PATH_MISFETCH 660222 3.263% 660222 3.263% + 20235448 100.000% 20235448 100.000% + 0.07 0.35 0.07 0.35 + +BP_OFF_PATH_CORRECT 0 -nan% 0 -nan% +BP_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% +BP_OFF_PATH_MISFETCH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +LATE_BP_ON_PATH_CORRECT 20235448 100.000% 20235448 100.000% +LATE_BP_ON_PATH_MISPREDICT 0 0.000% 0 0.000% +LATE_BP_ON_PATH_MISFETCH 0 0.000% 0 0.000% + 20235448 100.000% 20235448 100.000% + 0.00 0.00 0.00 0.00 + +LATE_BP_OFF_PATH_CORRECT 0 -nan% 0 -nan% +LATE_BP_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% +LATE_BP_OFF_PATH_MISFETCH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_PVN 0 -nan% 0 -nan% +BP_ON_PATH_CONF_PVN_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_PVP 0 -nan% 0 -nan% +BP_ON_PATH_CONF_PVP_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_SPEC 0 -nan% 0 -nan% +BP_ON_PATH_CONF_SPEC_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CRS_MISS_ON_PATH 139253 6.373% 139253 6.373% +CRS_HIT_ON_PATH 2045730 93.627% 2045730 93.627% + 2184983 100.000% 2184983 100.000% + 0.94 0.91 0.94 0.91 + +CRS_MISS_OFF_PATH 0 -nan% 0 -nan% +CRS_HIT_OFF_PATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CRS_CLOBBER 21001 21001 + +TARG_ON_PATH_MISS 95701 13.047% 95701 13.047% +TARG_ON_PATH_HIT 637781 86.953% 637781 86.953% + 733482 100.000% 733482 100.000% + 0.87 0.82 0.87 0.82 + +TARG_OFF_PATH_MISS 0 -nan% 0 -nan% +TARG_OFF_PATH_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_ON_PATH_WRITE 733482 100.000% 733482 100.000% +TARG_OFF_PATH_WRITE 0 0.000% 0 0.000% + 733482 100.000% 733482 100.000% + 0.00 0.00 0.00 0.00 + +TARG_HYBRID_CORRECT_TAGLESS 0 -nan% 0 -nan% +TARG_HYBRID_CORRECT_TAGGED 0 -nan% 0 -nan% +TARG_HYBRID_MISPRED_TAGLESS 0 -nan% 0 -nan% +TARG_HYBRID_MISPRED_TAGGED 0 -nan% 0 -nan% +TARG_HYBRID_NO_PRED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_VP_INDIRECT_MISPRED 0 -nan% 0 -nan% +TARG_VP_INDIRECT_NOPRED 0 -nan% 0 -nan% +TARG_VP_INDIRECT_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CBR_ON_PATH_CORRECT 13772940 99.902% 13772940 99.902% +CBR_ON_PATH_MISPREDICT 13468 0.098% 13468 0.098% + 13786408 100.000% 13786408 100.000% + 0.00 0.03 0.00 0.03 + +CBR_ON_PATH_CORRECT_PER1000INST 13772940 137.7294 13772940 137.7294 + +CBR_ON_PATH_MISPREDICT_PER1000INST 13468 0.1347 13468 0.1347 + +CBR_OFF_PATH_CORRECT 0 -nan% 0 -nan% +CBR_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PRED_TO_UPDATE_CYCLES_0 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_1 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_2 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_3 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_4 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_5 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_6 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_7 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_8 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_9 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_10 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_11 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_12 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_13 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_14 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_15 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_16 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_17 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_18 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_19 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_20 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_21 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_22 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_23 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_24 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_25 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_26 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_27 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_28 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_29 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_30 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_CORRECTED 0 -nan% 0 -nan% +BP_NOT_CORRECTED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_CORRECTED 0 -nan% 0 -nan% +TARG_NOT_CORRECTED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_MISP_PENALTY 6714504 6714504 + +BP_ON_PATH_CONF_MISPRED 0 -nan% 0 -nan% +BP_ON_PATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_OFF_PATH_CONF_MISPRED 0 -nan% 0 -nan% +BP_OFF_PATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_PRED_MIS_CONF_MISPRED 0 -nan% 0 -nan% +BP_ON_PATH_PRED_MIS_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_PRED_COR_CONF_MISPRED 0 -nan% 0 -nan% +BP_ON_PATH_PRED_COR_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_OFF_PATH_PRED_MIS_CONF_MISPRED 0 -nan% 0 -nan% +BP_OFF_PATH_PRED_MIS_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_OFF_PATH_PRED_COR_CONF_MISPRED 0 -nan% 0 -nan% +BP_OFF_PATH_PRED_COR_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ONPATH_CONF_MISPRED 0 -nan% 0 -nan% +ONPATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ONPATH_ON_PATH_CONF_MISPRED 0 -nan% 0 -nan% +ONPATH_ON_PATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ONPATH_OFF_PATH_CONF_MISPRED 0 -nan% 0 -nan% +ONPATH_OFF_PATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PRED_ONPATH_CONF_MISPRED 0 -nan% 0 -nan% +PRED_ONPATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PRED_OFFPATH_CONF_MISPRED 0 -nan% 0 -nan% +PRED_OFFPATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +LONG_OVWT_MIS 0 -nan% 0 -nan% +LONG_OVWT_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_0_7_MIS 0 -nan% 0 -nan% +OPC_LENGTH_0_7_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_8_15_MIS 0 -nan% 0 -nan% +OPC_LENGTH_8_15_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_16_23_MIS 0 -nan% 0 -nan% +OPC_LENGTH_16_23_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_24_31_MIS 0 -nan% 0 -nan% +OPC_LENGTH_24_31_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_32_39_MIS 0 -nan% 0 -nan% +OPC_LENGTH_32_39_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_40_47_MIS 0 -nan% 0 -nan% +OPC_LENGTH_40_47_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_48_55_MIS 0 -nan% 0 -nan% +OPC_LENGTH_48_55_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_56_63_MIS 0 -nan% 0 -nan% +OPC_LENGTH_56_63_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_64_71_MIS 0 -nan% 0 -nan% +OPC_LENGTH_64_71_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_72_79_MIS 0 -nan% 0 -nan% +OPC_LENGTH_72_79_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_80_MIS 0 -nan% 0 -nan% +OPC_LENGTH_80_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ALL_ONES_MIS 0 -nan% 0 -nan% +ALL_ONES_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan 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+CYCLES_UNDER_NONCRITICAL_MEM_REQ 0 0 + +CHIP_UTILIZATION_UNDER_MEM_REQ 0 -nan 0 -nan + +CHIP_UTILIZATION_UNDER_NO_MEM_REQ 0 -nan 0 -nan + +CHIP_UTILIZATION_UNDER_CRITICAL_MEM_REQ 0 -nan 0 -nan + +CHIP_UTILIZATION_UNDER_NONCRITICAL_MEM_REQ 0 -nan 0 -nan + +CYCLES_NOT_WAITING_FOR_OFF_CHIP 0 0.0000 0 0.0000 + +FUS_BUSY_NOT_WAITING_FOR_OFF_CHIP 0 -nan 0 -nan + +CYCLES_WAITING_FOR_OFF_CHIP 0 0.0000 0 0.0000 + +FUS_BUSY_WAITING_FOR_OFF_CHIP 0 -nan 0 -nan + +TOTAL_OFF_CHIP_DELAYS_LEFT 0 0 + +WRONG_IO_SCHED 0 0 + +DVFS_CONFIG_SWITCH 0 0 + + + diff --git a/labs/LAB5/runs/sgcc_base-sms1/fetch.stat.0.out b/labs/LAB5/runs/sgcc_base-sms1/fetch.stat.0.out new file mode 100644 index 00000000..619eb54f --- /dev/null +++ b/labs/LAB5/runs/sgcc_base-sms1/fetch.stat.0.out @@ -0,0 +1,248 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 80868545 Instructions: 100000000 IPC: 1.23657 + +ICACHE_CYCLE 80868545 80868545 + +TCACHE_CYCLE 0 0 + +ICACHE_CYCLE_ONPATH 66000389 81.614% 66000389 81.614% +ICACHE_CYCLE_OFFPATH 14868156 18.386% 14868156 18.386% + 80868545 100.000% 80868545 100.000% + 0.18 0.36 0.18 0.36 + +FETCH_ON_PATH 28608817 100.000% 28608817 100.000% +FETCH_OFF_PATH 0 0.000% 0 0.000% + 28608817 100.000% 28608817 100.000% + 0.00 0.00 0.00 0.00 + +FETCHED_OPS_ON_PATH 0 -nan% 0 -nan% +FETCHED_OPS_OFF_PATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +INST_LOST_WAIT_FOR_MISP_RECOVERY 0 0.000% 0 0.000% +INST_LOST_WAIT_FOR_TIMER 0 0.000% 0 0.000% +INST_LOST_WAIT_FOR_EMPTY_ROB 1404 0.000% 1404 0.000% +INST_LOST_WAIT_FOR_REDIRECT 24231354 6.049% 24231354 6.049% +INST_LOST_FETCH 132806100 33.153% 132806100 33.153% +INST_LOST_OFF_PATH 0 0.000% 0 0.000% +INST_LOST_FULL_WINDOW 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_OTHER 857394 0.214% 857394 0.214% +INST_LOST_ROB_STALL_WAIT_FOR_RECOVERY 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_REDIRECT 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_GAP_FILL 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_L1_MISS 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_MEMORY 126 0.000% 126 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_DC_MISS 700314 0.175% 700314 0.175% +INST_LOST_ROB_BLOCK_ISSUE_FULL 0 0.000% 0 0.000% +INST_LOST_ROB_BLOCK_ISSUE_GAP_TOO_LARGE 0 0.000% 0 0.000% +INST_LOST_BREAK_DONT 0 0.000% 0 0.000% +INST_LOST_BREAK_ISSUE_WIDTH 0 0.000% 0 0.000% +INST_LOST_BREAK_CF 0 0.000% 0 0.000% +INST_LOST_BREAK_BTB_MISS 1623485 0.405% 1623485 0.405% +INST_LOST_BREAK_ICACHE_MISS 213712628 53.349% 213712628 53.349% +INST_LOST_BREAK_LINE_END 0 0.000% 0 0.000% +INST_LOST_BREAK_STALL 0 0.000% 0 0.000% +INST_LOST_BREAK_BARRIER 36 0.000% 36 0.000% +INST_LOST_BREAK_OFFPATH 18473 0.005% 18473 0.005% +INST_LOST_BREAK_ALIGNMENT 0 0.000% 0 0.000% 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4.075% 5411217 4.075% +ST_OP_IMEM 46366344 34.913% 46366344 34.913% +ST_OP_IADD 27020418 20.346% 27020418 20.346% +ST_OP_IMUL 183565 0.138% 183565 0.138% +ST_OP_IDIV 10473 0.008% 10473 0.008% +ST_OP_ICMP 9950552 7.493% 9950552 7.493% +ST_OP_LOGIC 8145181 6.133% 8145181 6.133% +ST_OP_SHIFT 839522 0.632% 839522 0.632% +ST_OP_FMEM 566427 0.427% 566427 0.427% +ST_OP_FCVT 0 0.000% 0 0.000% +ST_OP_FADD 0 0.000% 0 0.000% +ST_OP_FMUL 0 0.000% 0 0.000% +ST_OP_FMA 0 0.000% 0 0.000% +ST_OP_FDIV 0 0.000% 0 0.000% +ST_OP_FCMP 0 0.000% 0 0.000% +ST_OP_FCMOV 0 0.000% 0 0.000% +ST_OP_GATHER 0 0.000% 0 0.000% +ST_OP_SCATTER 0 0.000% 0 0.000% +ST_OP_PIPELINED_FAST 19490 0.015% 19490 0.015% +ST_OP_PIPELINED_MEDIUM 0 0.000% 0 0.000% +ST_OP_PIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_MEDIUM 3664 0.003% 3664 0.003% +ST_OP_NOTPIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_VERY_SLOW 0 0.000% 0 0.000% + 132806100 100.000% 132806100 100.000% + 5.89 2.66 5.89 2.66 + +ST_NOT_CF 112570634 84.763% 112570634 84.763% +ST_CF_BR 1452144 1.093% 1452144 1.093% +ST_CF_CBR 13786408 10.381% 13786408 10.381% +ST_CF_CALL 2078431 1.565% 2078431 1.565% +ST_CF_IBR 626914 0.472% 626914 0.472% +ST_CF_ICALL 106568 0.080% 106568 0.080% +ST_CF_ICO 0 0.000% 0 0.000% +ST_CF_RET 2184983 1.645% 2184983 1.645% +ST_CF_SYS 18 0.000% 18 0.000% + 132806100 100.000% 132806100 100.000% + 0.40 1.08 0.40 1.08 + +ST_BAR_NONE 132806082 100.000% 132806082 100.000% +ST_BAR_FETCH 18 0.000% 18 0.000% +ST_BAR_ISSUE 0 0.000% 0 0.000% +ST_BAR_BOTH 0 0.000% 0 0.000% + 132806100 100.000% 132806100 100.000% + 0.00 0.00 0.00 0.00 + +ST_NOT_MEM 85873329 64.661% 85873329 64.661% +ST_MEM_LD 29555012 22.254% 29555012 22.254% +ST_MEM_ST 17377759 13.085% 17377759 13.085% +ST_MEM_PF 0 0.000% 0 0.000% +ST_MEM_WH 0 0.000% 0 0.000% +ST_MEM_EVICT 0 0.000% 0 0.000% + 132806100 100.000% 132806100 100.000% + 0.48 0.60 0.48 0.60 + +ST_NOT_MEM_OFFPATH 0 -nan% 0 -nan% +ST_MEM_LD_OFFPATH 0 -nan% 0 -nan% +ST_MEM_ST_OFFPATH 0 -nan% 0 -nan% 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--- /dev/null +++ b/labs/LAB5/runs/sgcc_base-sms1/l2l1pref.stat.0.out @@ -0,0 +1,140 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 80868545 Instructions: 100000000 IPC: 1.23657 + +L2WAY_FILL_L1 0 0 + +L2WAY_WAY_HIT 0 -nan% 0 -nan% +L2WAY_WAY_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_PREF_REQ 0 0 + +L2WAY_PREF_HIT_DATA_IN_CACHE 0 -nan% 0 -nan% +L2WAY_PREF_HIT_DATA_REQ 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_TRAIN_HIT 0 -nan% 0 -nan% +L2WAY_TRAIN_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L1_HIT_REQ_TYPE_IFETCH 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DFETCH 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DSTORE 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_IPRF 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DPRF 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_WB 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2_ACCESS_INTERVAL__0 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__1 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__2 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__3 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__4 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__5 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__6 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__7 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__8 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_L1INSERT_PORT_FULL 0 -nan% 0 -nan% +L2WAY_L1INSERT_PORT_READY 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2MARKV_NEXT_ADDR_HIT 0 -nan% 0 -nan% +L2MARKV_NEXT_ADDR_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2MARKV_LAST_ADDR_HIT 0 -nan% 0 -nan% +L2MARKV_LAST_ADDR_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +MARKV_L2_TIME_DIFF__0 0 -nan% 0 -nan% +MARKV_L2_TIME_DIFF__1 0 -nan% 0 -nan% +MARKV_L2_TIME_DIFF__2 0 -nan% 0 -nan% +MARKV_L2_TIME_DIFF__3 0 -nan% 0 -nan% +MARKV_L2_TIME_DIFF__4 0 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-nan% 0 -nan% +L2HIT_IP_HIT_COUNT__8 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__9 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + + + diff --git a/labs/LAB5/runs/sgcc_base-sms1/memory.stat.0.out b/labs/LAB5/runs/sgcc_base-sms1/memory.stat.0.out new file mode 100644 index 00000000..3815e76b --- /dev/null +++ b/labs/LAB5/runs/sgcc_base-sms1/memory.stat.0.out @@ -0,0 +1,3416 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 80868545 Instructions: 100000000 IPC: 1.23657 + +ICACHE_MISS 1872365 5.180% 1872365 5.180% +ICACHE_HIT 34276744 94.820% 34276744 94.820% + 36149109 100.000% 36149109 100.000% + 0.95 0.92 0.95 0.92 + +ICACHE_MISS_ONPATH 1872365 100.000% 1872365 100.000% +ICACHE_MISS_OFFPATH 0 0.000% 0 0.000% + 1872365 100.000% 1872365 100.000% + 0.00 0.00 0.00 0.00 + +ICACHE_HIT_ONPATH 34276744 100.000% 34276744 100.000% +ICACHE_HIT_OFFPATH 0 0.000% 0 0.000% + 34276744 100.000% 34276744 100.000% + 0.00 0.00 0.00 0.00 + +ICACHE_HIT_ONPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +ICACHE_HIT_ONPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ICACHE_HIT_OFFPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +ICACHE_HIT_OFFPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DCACHE_MISS 1350634 2.878% 1350634 2.878% +DCACHE_ST_BUFFER_HIT 100391 0.214% 100391 0.214% +DCACHE_HIT 45481699 96.908% 45481699 96.908% + 46932724 100.000% 46932724 100.000% + 1.94 1.91 1.94 1.91 + +DCACHE_MISS_COMPULSORY 45292 0.0335 45292 0.0335 + +DCACHE_MISS_CAPACITY 1300148 0.9626 1300148 0.9626 + +DCACHE_MISS_CONFLICT 5194 0.0038 5194 0.0038 + +DCACHE_MISS_ONPATH 1350634 100.000% 1350634 100.000% +DCACHE_MISS_OFFPATH 0 0.000% 0 0.000% + 1350634 100.000% 1350634 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_ST_BUFFER_HIT_ONPATH 100391 100.000% 100391 100.000% +DCACHE_ST_BUFFER_HIT_OFFPATH 0 0.000% 0 0.000% + 100391 100.000% 100391 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_HIT_ONPATH 45481699 100.000% 45481699 100.000% +DCACHE_HIT_OFFPATH 0 0.000% 0 0.000% + 45481699 100.000% 45481699 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_HIT_ONPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +DCACHE_HIT_ONPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DCACHE_HIT_OFFPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +DCACHE_HIT_OFFPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DCACHE_MISS_LD 642356 47.560% 642356 47.560% +DCACHE_MISS_ST 708278 52.440% 708278 52.440% + 1350634 100.000% 1350634 100.000% + 0.52 0.51 0.52 0.51 + +DCACHE_MISS_LD_ONPATH 642356 100.000% 642356 100.000% +DCACHE_MISS_LD_OFFPATH 0 0.000% 0 0.000% + 642356 100.000% 642356 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_MISS_ST_ONPATH 708278 100.000% 708278 100.000% +DCACHE_MISS_ST_OFFPATH 0 0.000% 0 0.000% + 708278 100.000% 708278 100.000% + 0.00 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3244421 109.8686 3244421 109.8686 + +CORE_MEM_LATENCY_AVE_PREF_NOT_USED 404195 155.4596 404195 155.4596 + +DRAM_LATENCY 0 0 + +TOTAL_DRAM_LATENCY 0 0 + +DRAM_CLOSED_PAGE_POLICY_CMD 0 0 + +DRAM_ACTIVATE_STALLING 0 0 + +DRAM_PRECHARGE_STALLING 0 0 + +DRAM_PRECHARGE_STALLING_WAIT_CYCLES 0 0 + +L1_STAY_DEMAND 80787088074 23088621.9131 80787088074 23088621.9131 + +L1_STAY_PREF_USED 649899135016 22008098.0364 649899135016 22008098.0364 + +L1_STAY_PREF_NOT_USED 54293193433 20881997.4742 54293193433 20881997.4742 + +TOTAL_DATA_MISS_LATENCY 781992 781992 + +TOTAL_DATA_MISS_COUNT 5394 5394 + +CORE_PREF_L1_NOT_USED_LATENCY200 2329 89.577% 2329 89.577% +CORE_PREF_L1_NOT_USED_LATENCY400 90 3.462% 90 3.462% +CORE_PREF_L1_NOT_USED_LATENCY600 85 3.269% 85 3.269% +CORE_PREF_L1_NOT_USED_LATENCY800 28 1.077% 28 1.077% +CORE_PREF_L1_NOT_USED_LATENCY1000 22 0.846% 22 0.846% +CORE_PREF_L1_NOT_USED_LATENCY1200 17 0.654% 17 0.654% +CORE_PREF_L1_NOT_USED_LATENCY1400 16 0.615% 16 0.615% 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100.000% + 1.00 1.00 1.00 1.00 + + + diff --git a/labs/LAB5/runs/sgcc_base-sms1/power.stat.0.out b/labs/LAB5/runs/sgcc_base-sms1/power.stat.0.out new file mode 100644 index 00000000..9a4cab3a --- /dev/null +++ b/labs/LAB5/runs/sgcc_base-sms1/power.stat.0.out @@ -0,0 +1,184 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 80868545 Instructions: 100000000 IPC: 1.23657 + +POWER_STATS_BEGIN 0 0 + +POWER_TIME 25271420312500 25271420312500 + +POWER_CYCLE 80868545 80868545 + +POWER_ITLB_ACCESS 36149109 36149109 + +POWER_DTLB_ACCESS 17377725 17377725 + +POWER_ICACHE_ACCESS 36149109 36149109 + +POWER_ICACHE_MISS 1872365 1872365 + +POWER_BTB_READ 36149109 36149109 + +POWER_BTB_WRITE 673690 673690 + +POWER_ROB_READ 132805988 132805988 + +POWER_ROB_WRITE 132805988 132805988 + +POWER_RENAME_READ 265611976 265611976 + +POWER_RENAME_WRITE 132805988 132805988 + +POWER_FP_RENAME_READ 0 0 + +POWER_FP_RENAME_WRITE 0 0 + +POWER_FUNCTION_CALL 2184997 2184997 + +POWER_INST_WINDOW_READ 132805988 132805988 + +POWER_INST_WINDOW_WRITE 132805988 132805988 + +POWER_INT_REGFILE_READ 143061590 143061590 + +POWER_INT_REGFILE_WRITE 103779614 103779614 + +POWER_IALU_ACCESS 132611950 132611950 + +POWER_CDB_IALU_ACCESS 132611950 132611950 + +POWER_MUL_ACCESS 194038 194038 + +POWER_CDB_MUL_ACCESS 194038 194038 + +POWER_FP_INST_WINDOW_WRITE 0 0 + +POWER_FP_INST_WINDOW_READ 0 0 + +POWER_FP_REGFILE_READ 0 0 + +POWER_FP_REGFILE_WRITE 0 0 + +POWER_FPU_ACCESS 0 0 + +POWER_CDB_FPU_ACCESS 0 0 + +POWER_DCACHE_READ_ACCESS 29555040 29555040 + +POWER_DCACHE_WRITE_ACCESS 17377727 17377727 + +POWER_DCACHE_READ_MISS 742787 742787 + +POWER_DCACHE_WRITE_MISS 708281 708281 + +POWER_MLC_READ_ACCESS 0 0 + +POWER_MLC_WRITE_ACCESS 0 0 + +POWER_MLC_READ_MISS 0 0 + +POWER_MLC_WRITE_MISS 0 0 + +POWER_LLC_READ_ACCESS 2496555 2496555 + +POWER_LLC_WRITE_ACCESS 270689 270689 + +POWER_LLC_READ_MISS 52011 52011 + +POWER_LLC_WRITE_MISS 2 2 + +POWER_MEMORY_ACCESS 0 0 + +POWER_MEMORY_READ_ACCESS 0 0 + +POWER_MEMORY_WRITE_ACCESS 0 0 + +POWER_INST_WINDOW_WAKEUP_ACCESS 132805988 132805988 + +POWER_FP_INST_WINDOW_WAKEUP_ACCESS 0 0 + +POWER_L1DIREC_READ_ACCESS 0 0 + +POWER_L1DIREC_WRITE_ACCESS 0 0 + +POWER_L1DIREC_READ_MISS 0 0 + +POWER_L1DIREC_WRITE_MISS 0 0 + +POWER_L2DIREC_READ_ACCESS 0 0 + +POWER_L2DIREC_WRITE_ACCESS 0 0 + +POWER_L2DIREC_READ_MISS 0 0 + +POWER_L2DIREC_WRITE_MISS 0 0 + +POWER_MEMORY_CTRL_ACCESS 82307 82307 + +POWER_MEMORY_CTRL_READ 52011 52011 + +POWER_MEMORY_CTRL_WRITE 30296 30296 + +POWER_OP 132805988 132805988 + +POWER_INT_OP 130305110 130305110 + +POWER_FP_OP 589581 589581 + +POWER_LD_OP 29555000 29555000 + +POWER_ST_OP 17377725 17377725 + +POWER_BRANCH_MISPREDICT 673690 673690 + +POWER_COMMITTED_OP 132805988 132805988 + +POWER_COMMITTED_INT_OP 130305110 130305110 + +POWER_COMMITTED_FP_OP 2500878 2500878 + +POWER_BRANCH_OP 20235456 20235456 + +POWER_DRAM_PRECHARGE 11566 11566 + +POWER_DRAM_ACTIVATE 25054 25054 + +POWER_DRAM_READ 52009 52009 + +POWER_DRAM_WRITE 30289 30289 + +POWER_STATS_END 0 0 + +ENERGY 0.000000 0.000000 + +ENERGY_CORE 0.000000 0.000000 + +ENERGY_UNCORE 0.000000 0.000000 + +ENERGY_MEMORY 0.000000 0.000000 + +ENERGY_OTHER 0.000000 0.000000 + +ENERGY_CORE_STATIC 0.000000 0.000000 + +ENERGY_CORE_DYNAMIC 0.000000 0.000000 + +ENERGY_UNCORE_STATIC 0.000000 0.000000 + +ENERGY_UNCORE_DYNAMIC 0.000000 0.000000 + +ENERGY_MEMORY_STATIC 0.000000 0.000000 + +ENERGY_MEMORY_DYNAMIC 0.000000 0.000000 + +ENERGY_OTHER_STATIC 0.000000 0.000000 + +ENERGY_OTHER_DYNAMIC 0.000000 0.000000 + +TIME 0.000000 0.000000 + +ENERGY_STATS_END 0 0 + + + diff --git a/labs/LAB5/runs/sgcc_base-sms1/pref.stat.0.out b/labs/LAB5/runs/sgcc_base-sms1/pref.stat.0.out new file mode 100644 index 00000000..0147c761 --- /dev/null +++ b/labs/LAB5/runs/sgcc_base-sms1/pref.stat.0.out @@ -0,0 +1,208 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 80868545 Instructions: 100000000 IPC: 1.23657 + +PREF_DL0REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UMLC_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UL1REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_DL0REQ_QUEUE_FULL 0 0 + +PREF_UMLC_REQ_QUEUE_FULL 0 0 + +PREF_UL1REQ_QUEUE_FULL 0 0 + +PREF_DC_HIT_NOSEND 0 0 + +PREF_WBQDC_HIT_NOSEND 0 0 + +PREF_MLCQ_STALL 0 0 + +PREF_L1Q_STALL 0 0 + +PREF_UMLC_REQ_SEND_QUEUE_STALL 0 0 + +PREF_UL1REQ_SEND_QUEUE_STALL 6736 6736 + +PREF_UMLC_REQ_QUEUE_SENTREQ 0 0 + +PREF_UL1REQ_QUEUE_SENTREQ 53396 53396 + +PREF_NEWREQ_MATCHED 205 205 + +PREF_UMLC_REQ_QUEUE_MATCHED_REQ 0 0 + +PREF_UL1REQ_QUEUE_MATCHED_REQ 1361 1361 + +PREF_DL0REQ_QUEUE_MATCHED_REQ 0 0 + +L1_PREF_HIT 184956 184956 + +L1_PREF_UNIQUE_HIT 40366 40366 + +L1_PREF_LATE 290 290 + +L1_LATE_PREF_CYCLES 46537 46537 + +L1_LATE_PREF_CYCLES_DIST_0 185 63.793% 185 63.793% +L1_LATE_PREF_CYCLES_DIST_100 21 7.241% 21 7.241% +L1_LATE_PREF_CYCLES_DIST_200 18 6.207% 18 6.207% +L1_LATE_PREF_CYCLES_DIST_300 14 4.828% 14 4.828% +L1_LATE_PREF_CYCLES_DIST_400 20 6.897% 20 6.897% +L1_LATE_PREF_CYCLES_DIST_500 11 3.793% 11 3.793% +L1_LATE_PREF_CYCLES_DIST_600 10 3.448% 10 3.448% +L1_LATE_PREF_CYCLES_DIST_700 6 2.069% 6 2.069% +L1_LATE_PREF_CYCLES_DIST_800 4 1.379% 4 1.379% +L1_LATE_PREF_CYCLES_DIST_900 1 0.345% 1 0.345% +L1_LATE_PREF_CYCLES_DIST_1000 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1100 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1200 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1300 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1400 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1500 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1600 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1700 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1800 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1900 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_2000 0 0.000% 0 0.000% + 290 100.000% 290 100.000% + 1.30 1.86 1.30 1.86 + +MLC_PREF_HIT 0 0 + +MLC_PREF_UNIQUE_HIT 0 0 + +MLC_PREF_LATE 0 0 + +PREF_HYBRID_SEL_0 0 -nan% 0 -nan% +PREF_HYBRID_SEL_1 0 -nan% 0 -nan% +PREF_HYBRID_SEL_2 0 -nan% 0 -nan% +PREF_HYBRID_SEL_3 0 -nan% 0 -nan% +PREF_HYBRID_SEL_4 0 -nan% 0 -nan% +PREF_HYBRID_SEL_5 0 -nan% 0 -nan% +PREF_HYBRID_SEL_6 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_DISTANCE_1 0 0.000% 0 0.000% +PREF_DISTANCE_2 0 0.000% 0 0.000% +PREF_DISTANCE_3 1 25.000% 1 25.000% +PREF_DISTANCE_4 3 75.000% 3 75.000% +PREF_DISTANCE_5 0 0.000% 0 0.000% +PREF_DISTANCE_6 0 0.000% 0 0.000% +PREF_DISTANCE_7 0 0.000% 0 0.000% +PREF_DISTANCE_8 0 0.000% 0 0.000% +PREF_DISTANCE_9 0 0.000% 0 0.000% +PREF_DISTANCE_10 0 0.000% 0 0.000% + 4 100.000% 4 100.000% + 2.75 0.50 2.75 0.50 + +PREF_REPL_MRU 0 -nan% 0 -nan% +PREF_REPL_MID 0 -nan% 0 -nan% +PREF_REPL_LOWQTR 0 -nan% 0 -nan% +PREF_REPL_LRU 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_REPL_MOVEDOWN 0 -nan% 0 -nan% +PREF_REPL_MOVEUP 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_COV_1 0 -nan% 0 -nan% +PREF_COV_2 0 -nan% 0 -nan% +PREF_COV_3 0 -nan% 0 -nan% +PREF_COV_4 0 -nan% 0 -nan% +PREF_COV_5 0 -nan% 0 -nan% +PREF_COV_6 0 -nan% 0 -nan% +PREF_COV_7 0 -nan% 0 -nan% +PREF_COV_8 0 -nan% 0 -nan% +PREF_COV_9 0 -nan% 0 -nan% +PREF_COV_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_POL_1 0 0.000% 0 0.000% +PREF_POL_2 0 0.000% 0 0.000% +PREF_POL_3 0 0.000% 0 0.000% +PREF_POL_4 0 0.000% 0 0.000% +PREF_POL_5 0 0.000% 0 0.000% +PREF_POL_6 0 0.000% 0 0.000% +PREF_POL_7 0 0.000% 0 0.000% +PREF_POL_8 0 0.000% 0 0.000% +PREF_POL_9 0 0.000% 0 0.000% +PREF_POL_10 4 100.000% 4 100.000% + 4 100.000% 4 100.000% + 9.00 10.39 9.00 10.39 + +PREF_ACC_1 2 50.000% 2 50.000% +PREF_ACC_2 2 50.000% 2 50.000% +PREF_ACC_3 0 0.000% 0 0.000% +PREF_ACC_4 0 0.000% 0 0.000% +PREF_ACC_5 0 0.000% 0 0.000% +PREF_ACC_6 0 0.000% 0 0.000% +PREF_ACC_7 0 0.000% 0 0.000% +PREF_ACC_8 0 0.000% 0 0.000% +PREF_ACC_9 0 0.000% 0 0.000% +PREF_ACC_10 0 0.000% 0 0.000% + 4 100.000% 4 100.000% + 0.50 0.41 0.50 0.41 + +PREF_TIMELY_1 0 0.000% 0 0.000% +PREF_TIMELY_2 0 0.000% 0 0.000% +PREF_TIMELY_3 0 0.000% 0 0.000% +PREF_TIMELY_4 0 0.000% 0 0.000% +PREF_TIMELY_5 0 0.000% 0 0.000% +PREF_TIMELY_6 0 0.000% 0 0.000% +PREF_TIMELY_7 0 0.000% 0 0.000% +PREF_TIMELY_8 0 0.000% 0 0.000% +PREF_TIMELY_9 0 0.000% 0 0.000% +PREF_TIMELY_10 4 100.000% 4 100.000% + 4 100.000% 4 100.000% + 9.00 10.39 9.00 10.39 + +PREF_UNUSED_EVICT 2600 2600 + +PREF_REGION_SENT 0 0 + +PREF_REGION_USEFUL 0 0 + +PREF_REGION_EVICT 0 0 + +PREF_PFPOL 0 0 + +PREF_PHASE_NEWPHASE_DET 0 0 + +PREF_PHASE_NEWPHASE_NOTVALID 0 0 + +PREF_PHASE_SENTPREF 0 0 + +PREF_PHASE_OVERWRITE_PAGE 0 0 + +PREF_UPDATE_COUNT 4 4 + +PREF_ACC1_HT_HP 0 0.000% 0 0.000% +PREF_ACC1_HT_LP 3 75.000% 3 75.000% +PREF_ACC1_LT_HP 0 0.000% 0 0.000% +PREF_ACC1_LT_LP 1 25.000% 1 25.000% +PREF_ACC2_HT_HP 0 0.000% 0 0.000% +PREF_ACC2_HT_LP 0 0.000% 0 0.000% +PREF_ACC2_LT_HP 0 0.000% 0 0.000% +PREF_ACC2_LT_LP 0 0.000% 0 0.000% +PREF_ACC3_HT_HP 0 0.000% 0 0.000% +PREF_ACC3_HT_LP 0 0.000% 0 0.000% +PREF_ACC3_LT_HP 0 0.000% 0 0.000% +PREF_ACC3_LT_LP 0 0.000% 0 0.000% +PREF_ACC4_HT_HP 0 0.000% 0 0.000% +PREF_ACC4_HT_LP 0 0.000% 0 0.000% +PREF_ACC4_LT_HP 0 0.000% 0 0.000% +PREF_ACC4_LT_LP 0 0.000% 0 0.000% + 4 100.000% 4 100.000% + 1.50 1.00 1.50 1.00 + + + diff --git a/labs/LAB5/runs/sgcc_base-sms1/ramulator.stat.out b/labs/LAB5/runs/sgcc_base-sms1/ramulator.stat.out new file mode 100644 index 00000000..263b78df --- /dev/null +++ b/labs/LAB5/runs/sgcc_base-sms1/ramulator.stat.out @@ -0,0 +1,150 @@ + ramulator.active_cycles_0 2760696 # Total active cycles for level _0 + ramulator.busy_cycles_0 2760696 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0 + ramulator.serving_requests_0 3364547 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.average_serving_requests_0 0.110947 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.active_cycles_0_0 2760696 # Total active cycles for level _0_0 + ramulator.busy_cycles_0_0 4047156 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0 + ramulator.serving_requests_0_0 3364547 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.average_serving_requests_0_0 0.110947 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.active_cycles_0_0_0 731872 # Total active cycles for level _0_0_0 + ramulator.busy_cycles_0_0_0 731872 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0 + ramulator.serving_requests_0_0_0 795706 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 +ramulator.average_serving_requests_0_0_0 0.026239 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 + ramulator.active_cycles_0_0_0_0 146326 # Total active cycles for level _0_0_0_0 + ramulator.busy_cycles_0_0_0_0 146326 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_0 + ramulator.serving_requests_0_0_0_0 157958 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 +ramulator.average_serving_requests_0_0_0_0 0.005209 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 + ramulator.active_cycles_0_0_0_1 262866 # Total active cycles for level _0_0_0_1 + ramulator.busy_cycles_0_0_0_1 262866 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_1 + ramulator.serving_requests_0_0_0_1 274635 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 +ramulator.average_serving_requests_0_0_0_1 0.009056 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 + ramulator.active_cycles_0_0_0_2 188083 # Total active cycles for level _0_0_0_2 + ramulator.busy_cycles_0_0_0_2 188083 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_2 + ramulator.serving_requests_0_0_0_2 198544 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 +ramulator.average_serving_requests_0_0_0_2 0.006547 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 + ramulator.active_cycles_0_0_0_3 153366 # Total active cycles for level _0_0_0_3 + ramulator.busy_cycles_0_0_0_3 153366 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_3 + ramulator.serving_requests_0_0_0_3 164569 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 +ramulator.average_serving_requests_0_0_0_3 0.005427 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 + ramulator.active_cycles_0_0_1 796929 # Total active cycles for level _0_0_1 + ramulator.busy_cycles_0_0_1 796929 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1 + ramulator.serving_requests_0_0_1 880143 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 +ramulator.average_serving_requests_0_0_1 0.029023 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 + ramulator.active_cycles_0_0_1_0 204177 # Total active cycles for level _0_0_1_0 + ramulator.busy_cycles_0_0_1_0 204177 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_0 + ramulator.serving_requests_0_0_1_0 217615 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 +ramulator.average_serving_requests_0_0_1_0 0.007176 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 + ramulator.active_cycles_0_0_1_1 161328 # Total active cycles for level _0_0_1_1 + ramulator.busy_cycles_0_0_1_1 161328 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_1 + ramulator.serving_requests_0_0_1_1 174710 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 +ramulator.average_serving_requests_0_0_1_1 0.005761 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 + ramulator.active_cycles_0_0_1_2 282219 # Total active cycles for level _0_0_1_2 + ramulator.busy_cycles_0_0_1_2 282219 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_2 + ramulator.serving_requests_0_0_1_2 294104 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 +ramulator.average_serving_requests_0_0_1_2 0.009698 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 + ramulator.active_cycles_0_0_1_3 181319 # Total active cycles for level _0_0_1_3 + ramulator.busy_cycles_0_0_1_3 181319 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_3 + ramulator.serving_requests_0_0_1_3 193714 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 +ramulator.average_serving_requests_0_0_1_3 0.006388 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 + ramulator.active_cycles_0_0_2 743304 # Total active cycles for level _0_0_2 + ramulator.busy_cycles_0_0_2 743304 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2 + ramulator.serving_requests_0_0_2 799879 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 +ramulator.average_serving_requests_0_0_2 0.026376 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 + ramulator.active_cycles_0_0_2_0 133367 # Total active cycles for level _0_0_2_0 + ramulator.busy_cycles_0_0_2_0 133367 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_0 + ramulator.serving_requests_0_0_2_0 143805 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 +ramulator.average_serving_requests_0_0_2_0 0.004742 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 + ramulator.active_cycles_0_0_2_1 301238 # Total active cycles for level _0_0_2_1 + ramulator.busy_cycles_0_0_2_1 301238 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_1 + ramulator.serving_requests_0_0_2_1 312685 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 +ramulator.average_serving_requests_0_0_2_1 0.010311 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 + ramulator.active_cycles_0_0_2_2 133575 # Total active cycles for level _0_0_2_2 + ramulator.busy_cycles_0_0_2_2 133575 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_2 + ramulator.serving_requests_0_0_2_2 145360 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 +ramulator.average_serving_requests_0_0_2_2 0.004793 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 + ramulator.active_cycles_0_0_2_3 189961 # Total active cycles for level _0_0_2_3 + ramulator.busy_cycles_0_0_2_3 189961 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_3 + ramulator.serving_requests_0_0_2_3 198029 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 +ramulator.average_serving_requests_0_0_2_3 0.006530 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 + ramulator.active_cycles_0_0_3 817764 # Total active cycles for level _0_0_3 + ramulator.busy_cycles_0_0_3 817764 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3 + ramulator.serving_requests_0_0_3 888819 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 +ramulator.average_serving_requests_0_0_3 0.029309 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 + ramulator.active_cycles_0_0_3_0 159648 # Total active cycles for level _0_0_3_0 + ramulator.busy_cycles_0_0_3_0 159648 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_0 + ramulator.serving_requests_0_0_3_0 168526 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 +ramulator.average_serving_requests_0_0_3_0 0.005557 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 + ramulator.active_cycles_0_0_3_1 268339 # Total active cycles for level _0_0_3_1 + ramulator.busy_cycles_0_0_3_1 268339 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_1 + ramulator.serving_requests_0_0_3_1 282895 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 +ramulator.average_serving_requests_0_0_3_1 0.009329 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 + ramulator.active_cycles_0_0_3_2 309570 # Total active cycles for level _0_0_3_2 + ramulator.busy_cycles_0_0_3_2 309570 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_2 + ramulator.serving_requests_0_0_3_2 324535 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 +ramulator.average_serving_requests_0_0_3_2 0.010702 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 + ramulator.active_cycles_0_0_3_3 103135 # Total active cycles for level _0_0_3_3 + ramulator.busy_cycles_0_0_3_3 103135 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_3 + ramulator.serving_requests_0_0_3_3 112863 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 +ramulator.average_serving_requests_0_0_3_3 0.003722 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 + ramulator.read_transaction_bytes_0 3328576 # The total byte of read transaction per channel + ramulator.write_transaction_bytes_0 1938496 # The total byte of write transaction per channel + ramulator.row_hits_channel_0_core 57245 # Number of row hits per channel per core + ramulator.row_misses_channel_0_core 16866 # Number of row misses per channel per core + ramulator.row_conflicts_channel_0_core 8187 # Number of row conflicts per channel per core + ramulator.read_row_hits_channel_0_core 38581 # Number of row hits for read requests per channel per core + [0] 38581.0 # +ramulator.read_row_misses_channel_0_core 9604 # Number of row misses for read requests per channel per core + [0] 9604.0 # +ramulator.read_row_conflicts_channel_0_core 3824 # Number of row conflicts for read requests per channel per core + [0] 3824.0 # + ramulator.write_row_hits_channel_0_core 18664 # Number of row hits for write requests per channel per core + [0] 18664.0 # +ramulator.write_row_misses_channel_0_core 7262 # Number of row misses for write requests per channel per core + [0] 7262.0 # +ramulator.write_row_conflicts_channel_0_core 4363 # Number of row conflicts for write requests per channel per core + [0] 4363.0 # + ramulator.useless_activates_0_core 1 # Number of useless activations. E.g, ACT -> PRE w/o RD or WR + ramulator.read_latency_avg_0 45.696410 # The average memory latency cycles (in memory time domain) per request for all read requests in this channel + ramulator.read_latency_sum_0 2376716 # The memory latency cycles (in memory time domain) sum for all read requests in this channel + ramulator.req_queue_length_avg_0 11.872353 # Average of read and write queue length per memory cycle per channel. + ramulator.req_queue_length_sum_0 360037608 # Sum of read and write queue length per memory cycle per channel. + ramulator.read_req_queue_length_avg_0 0.071266 # Read queue length average per memory cycle per channel. + ramulator.read_req_queue_length_sum_0 2161201 # Read queue length sum per memory cycle per channel. + ramulator.write_req_queue_length_avg_0 11.801087 # Write queue length average per memory cycle per channel. + ramulator.write_req_queue_length_sum_0 357876407 # Write queue length sum per memory cycle per channel. + ramulator.record_read_hits 0.0 # record read hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_misses 0.0 # record_read_miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_conflicts 0.0 # record read conflict count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_hits 0.0 # record write hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_misses 0.0 # record write miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_conflicts 0.0 # record write conflict for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.dram_capacity 8589934592 # Number of bytes in simulated DRAM + ramulator.dram_cycles 30325716 # Number of DRAM cycles simulated + ramulator.incoming_requests 82307 # Number of incoming requests to DRAM + ramulator.read_requests 52011 # Number of incoming read requests to DRAM per core + [0] 52011.0 # + ramulator.write_requests 30296 # Number of incoming write requests to DRAM per core + [0] 30296.0 # + ramulator.ramulator_active_cycles 2760696 # The total number of cycles that the DRAM part is active (serving R/W) + ramulator.incoming_requests_per_channel 82307.0 # Number of incoming requests to each DRAM channel + [0] 82307.0 # +ramulator.incoming_read_reqs_per_channel 52011.0 # Number of incoming read requests to each DRAM channel + [0] 52011.0 # + ramulator.physical_page_replacement 0 # The number of times that physical page replacement happens. + ramulator.maximum_bandwidth 19200000000 # The theoretical maximum bandwidth (Bps) + ramulator.in_queue_req_num_sum 360037608 # Sum of read/write queue length + ramulator.in_queue_read_req_num_sum 2161201 # Sum of read queue length + ramulator.in_queue_write_req_num_sum 357876407 # Sum of write queue length + ramulator.in_queue_req_num_avg 11.872353 # Average of read/write queue length per memory cycle + ramulator.in_queue_read_req_num_avg 0.071266 # Average of read queue length per memory cycle + ramulator.in_queue_write_req_num_avg 11.801087 # Average of write queue length per memory cycle + ramulator.record_read_requests 0.0 # record read requests for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_requests 0.0 # record write requests for this core when it reaches request limit or to the end + [0] 0.0 # diff --git a/labs/LAB5/runs/sgcc_base-sms1/run.err b/labs/LAB5/runs/sgcc_base-sms1/run.err new file mode 100644 index 00000000..e69de29b diff --git a/labs/LAB5/runs/sgcc_base-sms1/run.out b/labs/LAB5/runs/sgcc_base-sms1/run.out new file mode 100644 index 00000000..8af022d4 --- /dev/null +++ b/labs/LAB5/runs/sgcc_base-sms1/run.out @@ -0,0 +1,107 @@ +Scarab gitrev: 7ab9e17 +Scarab started at Sun Jun 11 08:08:38 2023 + +Initialized Ramulator. +** Heartbeat: 1% -- { 1000004 } -- 0.00 KIPS (333.33 KIPS) +** Heartbeat: 2% -- { 2000005 } -- 500.00 KIPS (400.00 KIPS) +** Heartbeat: 3% -- { 3000005 } -- 500.00 KIPS (428.57 KIPS) +** Heartbeat: 4% -- { 4000008 } -- 333.33 KIPS (400.00 KIPS) +** Heartbeat: 5% -- { 5000011 } -- 500.00 KIPS (416.67 KIPS) +** Heartbeat: 6% -- { 6000011 } -- 500.00 KIPS (428.57 KIPS) +** Heartbeat: 7% -- { 7000013 } -- 333.33 KIPS (411.77 KIPS) +** Heartbeat: 8% -- { 8000014 } -- 500.00 KIPS (421.05 KIPS) +** Heartbeat: 9% -- { 9000014 } -- 500.00 KIPS (428.57 KIPS) +** Heartbeat: 10% -- { 10000019 } -- 333.33 KIPS (416.67 KIPS) +** Heartbeat: 11% -- { 11000024 } -- 500.00 KIPS (423.08 KIPS) +** Heartbeat: 12% -- { 12000024 } -- 500.00 KIPS (428.57 KIPS) +** Heartbeat: 13% -- { 13000024 } -- 333.33 KIPS (419.36 KIPS) +** Heartbeat: 14% -- { 14000029 } -- 500.00 KIPS (424.24 KIPS) +** Heartbeat: 15% -- { 15000034 } -- 500.00 KIPS (428.57 KIPS) +** Heartbeat: 16% -- { 16000036 } -- 500.00 KIPS (432.43 KIPS) +** Heartbeat: 17% -- { 17000037 } -- 333.33 KIPS (425.00 KIPS) +** Heartbeat: 18% -- { 18000042 } -- 500.00 KIPS (428.57 KIPS) +** Heartbeat: 19% -- { 19000042 } -- 500.00 KIPS (431.82 KIPS) +** Heartbeat: 20% -- { 20000045 } -- 333.33 KIPS (425.53 KIPS) +** Heartbeat: 21% -- { 21000046 } -- 500.00 KIPS (428.57 KIPS) +** Heartbeat: 22% -- { 22000046 } -- 333.33 KIPS (423.08 KIPS) +** Heartbeat: 23% -- { 23000049 } -- 500.00 KIPS (425.93 KIPS) +** Heartbeat: 24% -- { 24000052 } -- 500.00 KIPS (428.57 KIPS) +** Heartbeat: 25% -- { 25000053 } -- 333.33 KIPS (423.73 KIPS) +** Heartbeat: 26% -- { 26000053 } -- 500.00 KIPS (426.23 KIPS) +** Heartbeat: 27% -- { 27000056 } -- 500.00 KIPS (428.57 KIPS) +** Heartbeat: 28% -- { 28000056 } -- 333.33 KIPS (424.24 KIPS) +** Heartbeat: 29% -- { 29000056 } -- 500.00 KIPS (426.47 KIPS) +** Heartbeat: 30% -- { 30000056 } -- 333.33 KIPS (422.54 KIPS) +** Heartbeat: 31% -- { 31000057 } -- 500.00 KIPS (424.66 KIPS) +** Heartbeat: 32% -- { 32000057 } -- 500.00 KIPS (426.67 KIPS) +** Heartbeat: 33% -- { 33000058 } -- 333.33 KIPS (423.08 KIPS) +** Heartbeat: 34% -- { 34000058 } -- 500.00 KIPS (425.00 KIPS) +** Heartbeat: 35% -- { 35000058 } -- 500.00 KIPS (426.83 KIPS) +** Heartbeat: 36% -- { 36000058 } -- 333.33 KIPS (423.53 KIPS) +** Heartbeat: 37% -- { 37000061 } -- 500.00 KIPS (425.29 KIPS) +** Heartbeat: 38% -- { 38000064 } -- 333.33 KIPS (422.22 KIPS) +** Heartbeat: 39% -- { 39000064 } -- 500.00 KIPS (423.91 KIPS) +** Heartbeat: 40% -- { 40000065 } -- 500.00 KIPS (425.53 KIPS) +** Heartbeat: 41% -- { 41000067 } -- 333.33 KIPS (422.68 KIPS) +** Heartbeat: 42% -- { 42000067 } -- 500.00 KIPS (424.24 KIPS) +** Heartbeat: 43% -- { 43000068 } -- 500.00 KIPS (425.74 KIPS) +** Heartbeat: 44% -- { 44000068 } -- 333.33 KIPS (423.08 KIPS) +** Heartbeat: 45% -- { 45000069 } -- 500.00 KIPS (424.53 KIPS) +** Heartbeat: 46% -- { 46000069 } -- 333.33 KIPS (422.02 KIPS) +** Heartbeat: 47% -- { 47000069 } -- 500.00 KIPS (423.42 KIPS) +** Heartbeat: 48% -- { 48000070 } -- 500.00 KIPS (424.78 KIPS) +** Heartbeat: 49% -- { 49000072 } -- 333.33 KIPS (422.41 KIPS) +** Heartbeat: 50% -- { 50000073 } -- 500.00 KIPS (423.73 KIPS) +** Heartbeat: 51% -- { 51000075 } -- 500.00 KIPS (425.00 KIPS) +** Heartbeat: 52% -- { 52000077 } -- 333.33 KIPS (422.76 KIPS) +** Heartbeat: 53% -- { 53000077 } -- 500.00 KIPS (424.00 KIPS) +** Heartbeat: 54% -- { 54000077 } -- 500.00 KIPS (425.20 KIPS) +** Heartbeat: 55% -- { 55000080 } -- 333.33 KIPS (423.08 KIPS) +** Heartbeat: 56% -- { 56000082 } -- 500.00 KIPS (424.24 KIPS) +** Heartbeat: 57% -- { 57000083 } -- 500.00 KIPS (425.37 KIPS) +** Heartbeat: 58% -- { 58000086 } -- 333.33 KIPS (423.36 KIPS) +** Heartbeat: 59% -- { 59000091 } -- 500.00 KIPS (424.46 KIPS) +** Heartbeat: 60% -- { 60000091 } -- 500.00 KIPS (425.53 KIPS) +** Heartbeat: 61% -- { 61000093 } -- 333.33 KIPS (423.61 KIPS) +** Heartbeat: 62% -- { 62000093 } -- 500.00 KIPS (424.66 KIPS) +** Heartbeat: 63% -- { 63000093 } -- 500.00 KIPS (425.68 KIPS) +** Heartbeat: 64% -- { 64000093 } -- 333.33 KIPS (423.84 KIPS) +** Heartbeat: 65% -- { 65000093 } -- 500.00 KIPS (424.84 KIPS) +** Heartbeat: 66% -- { 66000093 } -- 333.33 KIPS (423.08 KIPS) +** Heartbeat: 67% -- { 67000093 } -- 500.00 KIPS (424.05 KIPS) +** Heartbeat: 68% -- { 68000094 } -- 500.00 KIPS (425.00 KIPS) +** Heartbeat: 69% -- { 69000095 } -- 333.33 KIPS (423.31 KIPS) +** Heartbeat: 70% -- { 70000095 } -- 500.00 KIPS (424.24 KIPS) +** Heartbeat: 71% -- { 71000098 } -- 500.00 KIPS (425.15 KIPS) +** Heartbeat: 72% -- { 72000102 } -- 333.33 KIPS (423.53 KIPS) +** Heartbeat: 73% -- { 73000105 } -- 500.00 KIPS (424.42 KIPS) +** Heartbeat: 74% -- { 74000106 } -- 333.33 KIPS (422.86 KIPS) +** Heartbeat: 75% -- { 75000109 } -- 500.00 KIPS (423.73 KIPS) +** Heartbeat: 76% -- { 76000112 } -- 500.00 KIPS (424.58 KIPS) +** Heartbeat: 77% -- { 77000115 } -- 333.33 KIPS (423.08 KIPS) +** Heartbeat: 78% -- { 78000116 } -- 500.00 KIPS (423.91 KIPS) +** Heartbeat: 79% -- { 79000118 } -- 500.00 KIPS (424.73 KIPS) +** Heartbeat: 80% -- { 80000118 } -- 333.33 KIPS (423.28 KIPS) +** Heartbeat: 81% -- { 81000118 } -- 500.00 KIPS (424.08 KIPS) +** Heartbeat: 82% -- { 82000118 } -- 500.00 KIPS (424.87 KIPS) +** Heartbeat: 83% -- { 83000120 } -- 500.00 KIPS (425.64 KIPS) +** Heartbeat: 84% -- { 84000121 } -- 333.33 KIPS (424.24 KIPS) +** Heartbeat: 85% -- { 85000122 } -- 500.00 KIPS (425.00 KIPS) +** Heartbeat: 86% -- { 86000122 } -- 500.00 KIPS (425.74 KIPS) +** Heartbeat: 87% -- { 87000123 } -- 500.00 KIPS (426.47 KIPS) +** Heartbeat: 88% -- { 88000128 } -- 500.00 KIPS (427.19 KIPS) +** Heartbeat: 89% -- { 89000130 } -- 333.33 KIPS (425.84 KIPS) +** Heartbeat: 90% -- { 90000130 } -- 500.00 KIPS (426.54 KIPS) +** Heartbeat: 91% -- { 91000130 } -- 500.00 KIPS (427.23 KIPS) +** Heartbeat: 92% -- { 92000132 } -- 500.00 KIPS (427.91 KIPS) +** Heartbeat: 93% -- { 93000136 } -- 500.00 KIPS (428.57 KIPS) +** Heartbeat: 94% -- { 94000140 } -- 333.33 KIPS (427.27 KIPS) +** Heartbeat: 95% -- { 95000143 } -- 500.00 KIPS (427.93 KIPS) +** Heartbeat: 96% -- { 96000143 } -- 500.00 KIPS (428.57 KIPS) +** Heartbeat: 97% -- { 97000146 } -- 500.00 KIPS (429.20 KIPS) +** Heartbeat: 98% -- { 98000148 } -- 333.33 KIPS (427.95 KIPS) +** Heartbeat: 99% -- { 99000150 } -- 500.00 KIPS (428.57 KIPS) +** Core 0 Finished: insts:100000000 cycles:80868545 time:25271420312500 -- 1.24 IPC (1.24 IPC) -- N/A KIPS (429.18 KIPS) +done +Scarab finished at Sun Jun 11 08:12:31 2023 + diff --git a/labs/LAB5/runs/sgcc_base-sms1/stream.stat.0.out b/labs/LAB5/runs/sgcc_base-sms1/stream.stat.0.out new file mode 100644 index 00000000..d2df0e67 --- /dev/null +++ b/labs/LAB5/runs/sgcc_base-sms1/stream.stat.0.out @@ -0,0 +1,188 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 80868545 Instructions: 100000000 IPC: 1.23657 + +DCACHE_PREF_HIT 0 0 + +IFETCH_WB_FIRST_SCHEDULE 0 -nan% 0 -nan% +PREFETCH_LAST_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_PREF_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_LOW_OP_SCHEDULE 0 -nan% 0 -nan% +DEMAND_LAST_SCHEDULE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +SEND_MISS_REQ_QUEUE 52011 52011 + +L1_DATA_EVICT 35629 35629 + +STREAM_BUFFER_REQ 0 0 + +PREF_SEND_TO_MEM_REQ 0 -nan% 0 -nan% +PREF_SEND_TO_MEM_REQ_FAIL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +HIT_TRAIN_STREAM 43012 89.002% 43012 89.002% +MISS_TRAIN_STREAM 5315 10.998% 5315 10.998% + 48327 100.000% 48327 100.000% + 0.11 0.30 0.11 0.30 + +STREAM_TRAIN_CREATE 1989 1989 + +MEM_REQ_MISS_HWP_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_SW_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_IFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DSTORE_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DPRF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_WB_Q 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_BY_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_WB 0 -nan% 0 -nan% +PREF_HIT_BY_PREF 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_WB 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_L1_FILL 0 -nan% 0 -nan% +DEMAND_L1_FILL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TOUCH_L1_REPLACE 0 0.000% 0 0.000% +NO_TOUCH_L1_REPLACE 35629 100.000% 35629 100.000% + 35629 100.000% 35629 100.000% + 1.00 1.00 1.00 1.00 + +PREF_REQ_QUE_FULL 0 0 + +STREAM_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +L2HIT_STREAM_PREF_REQ_QUE_FULL 0 0 + +L2HIT_HIT_TRAIN_STREAM 0 -nan% 0 -nan% +L2HIT_MISS_TRAIN_STREAM 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_TRAIN_CREATE 0 0 + +L2HIT_STREAM_BUFFER_REQ 0 0 + +L2HIT_STREAM_PREF_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_STREAM_PREF_DCACHE_INSERT 0 -nan% 0 -nan% +L2HIT_STREAM_L2_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_DCACHE_PORT_FULL 0 0 + +L2HIT_STREAM_PREF_L1_PORT_FULL 0 0 + +L2HIT_TRAIN_HIT_DEMAND 0 -nan% 0 -nan% +L2HIT_TRAIN_MISS_REQ 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_TRAIN_FILTER_MISS 0 -nan% 0 -nan% +L2HIT_TRAIN_FILTER_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_PREF_REQ_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_PREF_REQ_DCACHE_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_L2SEND_Q_FULL 0 -nan% 0 -nan% +L2HIT_L2SEND_Q_ENTER 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_MEM_REQ 0 0 + +REMOVE_REDUNDANT_STREAM_STAT 0 0 + +REPLACE_OLD_STREAM 1973 1973 + +REQ_SEND_QUEUE_STALL 0 0 + +STREAM_ENTER_RA 0 0 + +CORE_STREAM_LENGTH_0 87 11.083% 87 11.083% +CORE_STREAM_LENGTH_10 119 15.159% 119 15.159% +CORE_STREAM_LENGTH_20 90 11.465% 90 11.465% +CORE_STREAM_LENGTH_30 100 12.739% 100 12.739% +CORE_STREAM_LENGTH_40 56 7.134% 56 7.134% +CORE_STREAM_LENGTH_50 32 4.076% 32 4.076% +CORE_STREAM_LENGTH_60 20 2.548% 20 2.548% +CORE_STREAM_LENGTH_70 27 3.439% 27 3.439% +CORE_STREAM_LENGTH_80 66 8.408% 66 8.408% +CORE_STREAM_LENGTH_90 18 2.293% 18 2.293% +CORE_STREAM_LENGTH_100_P 170 21.656% 170 21.656% + 785 100.000% 785 100.000% + 4.69 3.97 4.69 3.97 + +CORE_CUM_STREAM_LENGTH_0 568 0.955% 568 0.955% +CORE_CUM_STREAM_LENGTH_10 1735 2.918% 1735 2.918% +CORE_CUM_STREAM_LENGTH_20 2167 3.645% 2167 3.645% +CORE_CUM_STREAM_LENGTH_30 3436 5.779% 3436 5.779% +CORE_CUM_STREAM_LENGTH_40 2449 4.119% 2449 4.119% +CORE_CUM_STREAM_LENGTH_50 1728 2.906% 1728 2.906% +CORE_CUM_STREAM_LENGTH_60 1270 2.136% 1270 2.136% +CORE_CUM_STREAM_LENGTH_70 2036 3.424% 2036 3.424% +CORE_CUM_STREAM_LENGTH_80 5392 9.069% 5392 9.069% +CORE_CUM_STREAM_LENGTH_90 1729 2.908% 1729 2.908% +CORE_CUM_STREAM_LENGTH_100_P 36948 62.141% 36948 62.141% + 59458 100.000% 59458 100.000% + 8.15 7.00 8.15 7.00 + +CORE_STREAM_TRAIN_HITS_0 199 25.350% 199 25.350% +CORE_STREAM_TRAIN_HITS_10 167 21.274% 167 21.274% +CORE_STREAM_TRAIN_HITS_20 78 9.936% 78 9.936% +CORE_STREAM_TRAIN_HITS_30 38 4.841% 38 4.841% +CORE_STREAM_TRAIN_HITS_40 26 3.312% 26 3.312% +CORE_STREAM_TRAIN_HITS_50 14 1.783% 14 1.783% +CORE_STREAM_TRAIN_HITS_60 93 11.847% 93 11.847% +CORE_STREAM_TRAIN_HITS_70 11 1.401% 11 1.401% +CORE_STREAM_TRAIN_HITS_80 11 1.401% 11 1.401% +CORE_STREAM_TRAIN_HITS_90 10 1.274% 10 1.274% +CORE_STREAM_TRAIN_HITS_100_P 138 17.580% 138 17.580% + 785 100.000% 785 100.000% + 3.57 3.57 3.57 3.57 + +CORE_CUM_STREAM_TRAIN_HITS_0 1271 2.754% 1271 2.754% +CORE_CUM_STREAM_TRAIN_HITS_10 2319 5.025% 2319 5.025% +CORE_CUM_STREAM_TRAIN_HITS_20 1866 4.043% 1866 4.043% +CORE_CUM_STREAM_TRAIN_HITS_30 1305 2.828% 1305 2.828% +CORE_CUM_STREAM_TRAIN_HITS_40 1149 2.490% 1149 2.490% +CORE_CUM_STREAM_TRAIN_HITS_50 769 1.666% 769 1.666% +CORE_CUM_STREAM_TRAIN_HITS_60 6034 13.074% 6034 13.074% +CORE_CUM_STREAM_TRAIN_HITS_70 807 1.749% 807 1.749% +CORE_CUM_STREAM_TRAIN_HITS_80 918 1.989% 918 1.989% +CORE_CUM_STREAM_TRAIN_HITS_90 947 2.052% 947 2.052% +CORE_CUM_STREAM_TRAIN_HITS_100_P 28767 62.331% 28767 62.331% + 46152 100.000% 46152 100.000% + 7.88 6.86 7.88 6.86 + +CORE_STREAM_TRAIN_CREATE 1989 1989 + + + diff --git a/labs/LAB5/runs/specrand_i-sms0/PARAMS.in b/labs/LAB5/runs/specrand_i-sms0/PARAMS.in new file mode 100644 index 00000000..2593c2b8 --- /dev/null +++ b/labs/LAB5/runs/specrand_i-sms0/PARAMS.in @@ -0,0 +1,226 @@ +# File : PARAMS.kaby_lake +# Date : 03/06/19 +# Description : Kaby Lake Configuration +# +# Based on documentation found here: +# https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake + +## Simulation Parameters +--mode full +--model cmp +--sim_limit none + +## Core Parameters + +# Femptoseconds, 3.2GHz, used for energy estimates. +--chip_cycle_time 312500 + + +### Fetch Stage +--fetch_off_path_ops 1 +--fetch_across_cache_lines 1 + +# Will break the packet upon a taken branch. +--fetch_break_on_taken 1 + +# Number of bubble cycles to wait after taken branch. +--fetch_taken_bubble_cycles 0 + + +#### ICache +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 + +### Branch Predictor +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_mech tagescl + + +#### BTB + +# BTB model to use. +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 + +# Allow the BTB to be updated by off path ops. +--btb_off_path_writes 1 + + +#### CRS + +# Enable return stack +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 + +### iBP +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged + # iBTB Model. tc_tagless, tc_tagged, tc_hybrid. +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 + +### Decode Stage +--decode_cycles 5 + + +### Map Stage +--map_cycles 5 + + +### Issue Stage + +# Max number of instructions to be fetched, decoded, renamed, and issued per cycle. +--issue_width 6 + +--rs_fill_width 0 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 + + +### Exec Stage + +### DCache +--dcache_size 32768 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--dcache_assoc 4 +--dcache_line_size 64 + +### Reorder/Retire Stage + +# Max number of instructions to be retired per cycle. +--node_ret_width 6 +--node_table_size 224 + +# Do not keep stores in RSVs on cache misses; TODO: confirm what this knob does +--stores_do_not_block_window 1 + +# TODO: confirm what this knob does +--prefs_do_not_block_window 1 + + +## Uncore + +### Mid-level cache + +# Enable use of a midlevel cache between i/d and L1 +--mlc_present 0 + +### LLC +--l1_size 1048576 +--l1_banks 1 +--l1_cycles 18 +--l1_assoc 8 +--l1_line_size 64 +--l1_interleave_factor 64 + + +### Prefetcher +--pref_framework_on 1 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--pref_shared_queues 0 +--pref_train_on_pref_misses 0 +--pref_oracle_train 0 +--pref_ul1req_queue_overwrite_on_full 1 + +--stream_length 64 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 + +--pref_throttlefb_on=1 +--pref_acc_thresh_1=0.75 +--pref_acc_thresh_2=0.4 +--pref_acc_thresh_3=0.4 +--pref_timely_thresh=0.01 +--pref_polpf_thresh=0.005 +--pref_update_interval=8192 + +--mem_req_buffer_pref_watermark 4 +--promote_to_higher_priority_mem_req_type 1 + +### Memory +--addr_translation random + +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 + +--mem_req_buffer_entries 32 +--mem_l1_fill_queue_entries 32 +--va_page_size_bytes 4096 +--bus_width_in_bytes 8 + +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 + +## Other + + +### Debug +--debug_inst_start 0 +--debug_inst_stop -1 +--debug_cycle_start 0 +--debug_cycle_stop -1 + + +## Stats and Params +--dump_params 1 +--dump_stats 1 +--dump_trace 0 + +#################################### +--set_off_path_confirmed 1 + +--order_beyond_bus 1 + +--mem_ooo_stores 1 +--mem_obey_store_dep 1 diff --git a/labs/LAB5/runs/specrand_i-sms0/PARAMS.out b/labs/LAB5/runs/specrand_i-sms0/PARAMS.out new file mode 100644 index 00000000..31ab3e07 --- /dev/null +++ b/labs/LAB5/runs/specrand_i-sms0/PARAMS.out @@ -0,0 +1,908 @@ +--mode full +--model cmp +--frontend memtrace +--inst_limit 100000000 +--sim_limit none +--dump_params 1 +--dump_stats 1 +--dump_trace 0 +--mlc_present 0 +--l1_size 1048576 +--l1_assoc 8 +--l1_line_size 64 +--l1_cycles 18 +--l1_banks 1 +--l1_interleave_factor 64 +--va_page_size_bytes 4096 +--addr_translation random +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 +--dcache_size 32768 +--dcache_assoc 4 +--dcache_line_size 64 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--mem_ooo_stores 1 +--mem_obey_store_dep 1 +--mem_req_buffer_entries 32 +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 +--promote_to_higher_priority_mem_req_type 1 +--mem_req_buffer_pref_watermark 4 +--mem_l1_fill_queue_entries 32 +--order_beyond_bus 1 +--set_off_path_confirmed 1 +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--bus_width_in_bytes 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 +--chip_cycle_time 312500 +--issue_width 6 +--rs_fill_width 0 +--node_table_size 224 +--node_ret_width 6 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 +--decode_cycles 5 +--map_cycles 5 +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--fetch_across_cache_lines 1 +--fetch_off_path_ops 0 +--fetch_break_on_taken 1 +--fetch_taken_bubble_cycles 0 +--stores_do_not_block_window 1 +--prefs_do_not_block_window 1 +--cbp_trace_r0 /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir/trace/drmemtrace.specrand_i.553922.2837.trace.gz +--memtrace_modules_log /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir/raw +--debug_cycle_start 0 +--debug_cycle_stop -1 +--debug_inst_start 0 +--debug_inst_stop -1 +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--bp_mech tagescl +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 +--btb_off_path_writes 1 +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_length 64 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 +--pref_framework_on 1 +--pref_shared_queues 0 +--pref_ul1req_queue_overwrite_on_full 1 +--pref_train_on_pref_misses 0 +--pref_oracle_train_on 0 +--pref_throttlefb_on 1 +--pref_acc_thresh_1 0.75 +--pref_acc_thresh_2 0.4 +--pref_acc_thresh_3 0.4 +--pref_update_interval 8192 +--pref_timely_thresh 0.01 +--pref_polpf_thresh 0.005 +--pref_sms_on 0 +1 1 1 1 1 1 1 + +--- Cut out everything below to use this file as PARAMS.in --- + +Parameter status at compile time and values supplied on the command line: + +SIM_MODE 0 full +SIM_MODEL 0 cmp +FRONTEND FE_PIN_EXEC_DRIVEN memtrace +INST_LIMIT NULL 100000000 +SIM_LIMIT "none" none +FORWARD_PROGRESS_LIMIT 100000000 +FORWARD_PROGRESS_INTERVAL 10000 +FAST_FORWARD 0 +FAST_FORWARD_UNTIL_ADDR 0 +FAST_FORWARD_TRACE_INS 0 +WARMUP 0 +HEARTBEAT_INTERVAL 1000000 +NUM_HEARTBEATS 0 +FILE_TAG "" +OUTPUT_DIR "." +STATUS_FILE NULL +BINDIR NULL +DUMP_PARAMS TRUE 1 +DUMP_STATS TRUE 1 +DUMP_TRACE FALSE 0 +CLEAR_STATS "never" +STATS_TO_TRACE NULL +STAT_TRACE_FILE "stats.trace" +STAT_TRACE_INTERVAL "i:100000" +PIPEVIEW FALSE +PIPEVIEW_FILE "pipeview" +MEMVIEW FALSE +MEMVIEW_FILE "memview.out" +MEMVIEW_START "never" +INST_HASH_TABLE_SIZE 500021 const +STDOUT_FILE NULL +STDERR_FILE NULL +PIN_EXEC_DRIVEN_FE_SOCKET "./pin_exec_driven_fe_socket.temp" +PRINT_PID FALSE +USE_UNSURE_FREE_LISTS FALSE +OPTIMIZER2_MAX_NUM_SLAVES 64 +OPTIMIZER2_PERFECT_MEMORYLESS FALSE +EXIT_COND 0 +ENABLE_SWPRF FALSE +MLC_PRESENT FALSE 0 +MLC_SIZE (512 * 1024) +MLC_ASSOC 4 +MLC_LINE_SIZE 64 +MLC_CYCLES 12 +PERFECT_MLC FALSE +MLC_READ_PORTS 1 +MLC_WRITE_PORTS 1 +MLC_BANKS 8 +MLC_INTERLEAVE_FACTOR 64 +MLC_CACHE_REPL_POLICY 0 +MLC_WRITE_THROUGH FALSE +PREFETCH_UPDATE_LRU_MLC TRUE +FORCE_L1_MISS FALSE +L1_SIZE (4 * 1024 * 1024) 1048576 +L1_ASSOC 8 8 +L1_LINE_SIZE 64 64 +L1_CYCLES 24 18 +PERFECT_L1 FALSE +PRIVATE_L1 FALSE +L1_READ_PORTS 1 +L1_WRITE_PORTS 1 +L1_BANKS 8 1 +L1_INTERLEAVE_FACTOR 64 64 +L1_CACHE_REPL_POLICY 0 +L1_WRITE_THROUGH FALSE +L1_IGNORE_WB FALSE +L1_USE_CORE_FREQ FALSE +MARK_L1_MISSES TRUE +PREFETCH_UPDATE_LRU_L1 TRUE +MEMORY_RANDOM_ADDR FALSE +VA_PAGE_SIZE_BYTES 4096 4096 +NUM_ADDR_NON_SIGN_EXTEND_BITS 48 +ADDR_TRANSLATION 0 random +CONSTANT_MEMORY_LATENCY FALSE +MEMORY_CYCLES 100 +STALL_MEM_REQS_ONLY FALSE +ICACHE_SIZE (64 * 1024) 32768 +ICACHE_ASSOC 4 4 +ICACHE_LINE_SIZE 64 64 +PERFECT_ICACHE FALSE +ICACHE_READ_PORTS 2 +ICACHE_WRITE_PORTS 1 +ICACHE_BANKS 8 +ICACHE_REPL 0 +DCACHE_SIZE (64 * 1024) 32768 +DCACHE_ASSOC 1 4 +DCACHE_LINE_SIZE 64 64 +DCACHE_CYCLES 2 +PERFECT_DCACHE FALSE +DCACHE_READ_PORTS 8 2 +DCACHE_WRITE_PORTS 1 1 +DCACHE_BANKS 1 1 +DCACHE_REPL 0 +DCACHE_REPL_PREF_THRESH 1 +MEM_OOO_STORES TRUE 1 +MEM_OBEY_STORE_DEP TRUE 1 +PREF_INSERT_LRU FALSE +PREF_INSERT_MIDDLE FALSE +PREF_INSERT_LOWQTR FALSE +PREF_INSERT_DYNACC FALSE +MEM_REQ_BUFFER_ENTRIES 32 32 +PRIVATE_MSHR_ON TRUE +MEM_PRIORITY_IFETCH 0 0 +MEM_PRIORITY_DFETCH 0 1 +MEM_PRIORITY_DSTORE 0 2 +MEM_PRIORITY_IPRF 9 3 +MEM_PRIORITY_DPRF 10 4 +MEM_PRIORITY_WB 0 5 +MEM_PRIORITY_WB_NODIRTY 0 5 +PROMOTE_TO_HIGHER_PRIORITY_MEM_REQ_TYPE FALSE 1 +MEM_REQ_BUFFER_PREF_WATERMARK 0 4 +MEM_REQ_BUFFER_WB_VALVE 2 +MEM_L1_FILL_QUEUE_ENTRIES 32 32 +MEM_BUS_OUT_QUEUE_PARTITION_ENABLE FALSE +MEM_MEM_QUEUE_PARTITION_ENABLE FALSE +MEM_BUS_OUT_QUEUE_AS_FIFO TRUE +OLDEST_FIRST_TO_MEM_QUEUE TRUE +ROUND_ROBIN_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE_TH 0 +L1_CYCLE_TIME 312500 +MLCQ_TO_L1Q_TRANSFER_LATENCY 1 +L1Q_TO_FSB_TRANSFER_LATENCY 1 +PRIORITIZE_PREFETCHES_WITH_UNIQUE FALSE +KICKOUT_PREFETCHES FALSE +KICKOUT_LOOK_FOR_OLDEST_FIRST FALSE +KICKOUT_OLDEST_PREFETCH FALSE +KICKOUT_OLDEST_PREFETCH_WITHIN_BANK FALSE +ORDER_BEYOND_BUS FALSE 1 +ALL_FIFO_QUEUES FALSE +QUEUE_MLC_SIZE 0 +QUEUE_L1_SIZE 0 +QUEUE_BUS_OUT_SIZE 0 +QUEUE_CORE_FILL_SIZE 0 +ALLOW_TYPE_MATCHES FALSE +STREAM_PREFETCH_ON FALSE +DC_PREF_CACHE_ENABLE FALSE +DC_PREF_CACHE_CYCLE 0 +PREF_INSERT_DCACHE_IMM TRUE +DC_PREF_CACHE_SIZE (64 * 1024) +DC_PREF_CACHE_ASSOC 4 +DC_PREF_ONLY_L1HIT FALSE +PREF_CACHE_USE_RDY_CYCLE FALSE +IC_PREF_CACHE_ENABLE FALSE +IC_PREF_CACHE_SIZE (64 * 1024) +IC_PREF_CACHE_ASSOC 4 +L1_PREF_CACHE_ENABLE FALSE +L1_PREF_CACHE_SIZE (1024 * 1024) +L1_PREF_CACHE_ASSOC 8 +SET_OFF_PATH_CONFIRMED FALSE 1 +USE_CONFIRMED_OFF FALSE +PREFCACHE_MOVE_OFFPATH FALSE +CACHE_STAT_ENABLE FALSE +PREF_DCACHE_HIT_FILL_L1 TRUE +PREF_ICACHE_HIT_FILL_L1 TRUE +CRITICAL_ACCESS_PLOT_ENABLE FALSE +CRITICAL_ACCESS_PLOT_FILE "critical_access_plot.dat" +ROUND_ROBIN_TO_L1 FALSE +PREF_I_TOGETHER FALSE +ONE_MORE_CACHE_LINE_ENABLE FALSE +L1_STATIC_PARTITION_ENABLE 0 +L1_STATIC_PARTITION NULL +L1_DYNAMIC_PARTITION_ENABLE FALSE +L1_DYNAMIC_PARTITION_POLICY 0 +PARTITION_UMON_DSS_PREF_ENABLE FALSE +L1_CACHE_HIT_POSITION_COLLECT FALSE +L1_PART_ON FALSE +L1_PART_TRIGGER "c:1000000" +L1_PART_START "t:0" +L1_PART_WARMUP FALSE +L1_PART_SHADOW_WARMUP FALSE +L1_PART_METRIC 0 +L1_PART_SEARCH 0 +L1_PART_USE_STALLING TRUE +L1_PART_FILL_DELAY 0 +L1_SHADOW_TAGS_MODULO 1 +HIER_MSHR_ON FALSE +PERF_PRED_ENABLE FALSE +PERF_PRED_MECH PERF_PRED_CP +PERF_PRED_REQ_LATENCY_MECH PERF_PRED_REQ_LATENCY_MECH_REQ_LATENCY +PERF_PRED_COUNT_ALL FALSE +PERF_PRED_COUNT_INST_MISSES TRUE +PERF_PRED_COUNT_PREFETCHES FALSE +PERF_PRED_COUNT_OFFPATH_REQS FALSE +PERF_PRED_COUNT_BW_REQS TRUE +PERF_PRED_UPDATE_MEM_REQ_TYPE FALSE +PERF_PRED_SLACK_PERIOD_SIZE 32 +PERF_PRED_REQS_FINISH_AT_FILL FALSE +PERF_PRED_MEM_UTIL_VIA_BUS_BW FALSE +PERF_PRED_CHIP_UTIL_VIA_MEM_STALL FALSE +DUMB_MODEL_AVG_REQ_DISTANCE 100 +DUMB_MODEL_RANDOMIZE_DISTANCE FALSE +DUMB_MODEL_AVG_REQ_DISTANCE_PER_CORE NULL +DUMB_MODEL_AVG_ROW_HITS 1 +DUMB_MODEL_AVG_ROW_HITS_PER_CORE NULL +DUMB_MODEL_MLP 1 +DUMB_MODEL_MLP_PER_CORE NULL +RAMULATOR_STANDARD "DDR4" DDR4 +RAMULATOR_SPEED "DDR4_2400R" DDR4_2400R +RAMULATOR_ORG "DDR4_8Gb_x8" DDR4_8Gb_x8 +RAMULATOR_CHANNELS 1 1 +RAMULATOR_RANKS 1 1 +RAMULATOR_BANKGROUPS 4 4 +RAMULATOR_BANKS 4 4 +RAMULATOR_CHIP_WIDTH 8 8 +BUS_WIDTH_IN_BYTES 8 8 +RAMULATOR_ROWS 65536 65536 +RAMULATOR_COLS 1024 1024 +RAMULATOR_SCHEDULING_POLICY "FRFCFS_Cap" FRFCFS_Cap +RAMULATOR_READQ_ENTRIES 32 32 +RAMULATOR_WRITEQ_ENTRIES 32 32 +RAMULATOR_REC_CMD_TRACE "off" FALSE +RAMULATOR_PRINT_CMD_TRACE "off" FALSE +RAMULATOR_USE_REST_OF_ADDR_AS_ROW_ADDR "on" +RAMULATOR_TCK 833333 833333 +RAMULATOR_TCL 16 16 +RAMULATOR_TCCD 6 6 +RAMULATOR_TCCDS 4 4 +RAMULATOR_TCCDL 6 6 +RAMULATOR_TCWL 12 12 +RAMULATOR_TBL 4 4 +RAMULATOR_TWTR 9 9 +RAMULATOR_TWTRS 3 3 +RAMULATOR_TWTRL 9 9 +RAMULATOR_TRP 16 16 +RAMULATOR_TRPpb 16 16 +RAMULATOR_TRPab 16 16 +RAMULATOR_TRCD 16 16 +RAMULATOR_TRCDR 16 16 +RAMULATOR_TRCDW 16 16 +RAMULATOR_TRAS 39 39 +DRAM_TECH_IN_NM 32 32 +DVFS_ON FALSE +DVFS_METRIC DVFS_METRIC_NUM_ELEMS +DVFS_CONFIGS NULL +DVFS_CONFIG_FILE NULL +DVFS_START "t:0" +DVFS_PERIOD "t:312500000000" +DVFS_LOG TRUE +DVFS_INDIVIDUAL_CORES FALSE +DVFS_CHIP_LEVEL FALSE +DVFS_STATIC NULL +DVFS_FORCE_CONFIG NULL +DVFS_REPLAY_CONFIG_TRACE NULL +DVFS_USE_ORACLE FALSE +DVFS_USE_BW_SHARING FALSE +DVFS_USE_DRAM_SHARING FALSE +DVFS_USE_STALL_TIME FALSE +DVFS_DRAM_SHARING_SOLVER_BIN NULL +DVFS_DRAM_SHARING_SOLVER_STRICT TRUE +DVFS_BW_SHARING_BUS_UTIL_THRESH 0.95 +DVFS_BW_SHARING_MAX_REQS 28.0 +DVFS_BW_SHARING_MAX_RW_COST 0.25 +DVFS_BW_SHARING_NO_PREF_STALL TRUE +DVFS_BW_SHARING_CRIT_STATS TRUE +DVFS_COUNT_L1_ACCESS_STALL FALSE +NUM_CORES 1 +CHIP_CYCLE_TIME 312500 312500 +CORE_0_CYCLE_TIME 312500 +CORE_1_CYCLE_TIME 312500 +CORE_2_CYCLE_TIME 312500 +CORE_3_CYCLE_TIME 312500 +CORE_4_CYCLE_TIME 312500 +CORE_5_CYCLE_TIME 312500 +CORE_6_CYCLE_TIME 312500 +CORE_7_CYCLE_TIME 312500 +CORE_8_CYCLE_TIME 312500 +CORE_9_CYCLE_TIME 312500 +CORE_10_CYCLE_TIME 312500 +CORE_11_CYCLE_TIME 312500 +CORE_12_CYCLE_TIME 312500 +CORE_13_CYCLE_TIME 312500 +CORE_14_CYCLE_TIME 312500 +CORE_15_CYCLE_TIME 312500 +CORE_16_CYCLE_TIME 312500 +CORE_17_CYCLE_TIME 312500 +CORE_18_CYCLE_TIME 312500 +CORE_19_CYCLE_TIME 312500 +CORE_20_CYCLE_TIME 312500 +CORE_21_CYCLE_TIME 312500 +CORE_22_CYCLE_TIME 312500 +CORE_23_CYCLE_TIME 312500 +CORE_24_CYCLE_TIME 312500 +CORE_25_CYCLE_TIME 312500 +CORE_26_CYCLE_TIME 312500 +CORE_27_CYCLE_TIME 312500 +CORE_28_CYCLE_TIME 312500 +CORE_29_CYCLE_TIME 312500 +CORE_30_CYCLE_TIME 312500 +CORE_31_CYCLE_TIME 312500 +CORE_32_CYCLE_TIME 312500 +CORE_33_CYCLE_TIME 312500 +CORE_34_CYCLE_TIME 312500 +CORE_35_CYCLE_TIME 312500 +CORE_36_CYCLE_TIME 312500 +CORE_37_CYCLE_TIME 312500 +CORE_38_CYCLE_TIME 312500 +CORE_39_CYCLE_TIME 312500 +CORE_40_CYCLE_TIME 312500 +CORE_41_CYCLE_TIME 312500 +CORE_42_CYCLE_TIME 312500 +CORE_43_CYCLE_TIME 312500 +CORE_44_CYCLE_TIME 312500 +CORE_45_CYCLE_TIME 312500 +CORE_46_CYCLE_TIME 312500 +CORE_47_CYCLE_TIME 312500 +CORE_48_CYCLE_TIME 312500 +CORE_49_CYCLE_TIME 312500 +CORE_50_CYCLE_TIME 312500 +CORE_51_CYCLE_TIME 312500 +CORE_52_CYCLE_TIME 312500 +CORE_53_CYCLE_TIME 312500 +CORE_54_CYCLE_TIME 312500 +CORE_55_CYCLE_TIME 312500 +CORE_56_CYCLE_TIME 312500 +CORE_57_CYCLE_TIME 312500 +CORE_58_CYCLE_TIME 312500 +CORE_59_CYCLE_TIME 312500 +CORE_60_CYCLE_TIME 312500 +CORE_61_CYCLE_TIME 312500 +CORE_62_CYCLE_TIME 312500 +CORE_63_CYCLE_TIME 312500 +ISSUE_WIDTH 4 6 +RS_FILL_WIDTH 8 0 +NODE_TABLE_SIZE 256 224 +NODE_RET_WIDTH 4 6 +NODE_RETIRE_RATE 10 +RS_SIZES "256" 97 +RS_CONNECTIONS "xF" 0 +FU_TYPES "0, 0, 0, 0" 0 0 0 0 0 0 0 0 +DECODE_CYCLES 1 5 +MAP_CYCLES 1 5 +EXTRA_RECOVERY_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after recovery. +EXTRA_REDIRECT_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after redirect. +EXTRA_CALLSYS_CYCLES 20 const +DIE_ON_CALLSYS FALSE +DIE_ON_RET_STALL_THRESH 0 +DIE_ON_RET_STALL_CORE 0 +DIE_ON_MEM_BLOCK_THRESH 0 +DIE_ON_MEM_BLOCK_CORE 0 +FETCH_ACROSS_CACHE_LINES FALSE 1 +FETCH_OFF_PATH_OPS TRUE 0 +FETCH_BREAK_ON_TAKEN FALSE 1 +FETCH_TAKEN_BUBBLE_CYCLES 0 0 +WP_COLLECT_STATS FALSE +SWITCH_IC_FETCH_ON_RECOVERY TRUE +OP_INV_DELAY 1 +OP_NOP_DELAY 1 +OP_CF_DELAY 1 +OP_MOV_DELAY 1 +OP_CMOV_DELAY 1 +OP_LDA_DELAY 1 +OP_IMEM_DELAY 1 +OP_IADD_DELAY 1 +OP_IMUL_DELAY 3 +OP_IDIV_DELAY -20 +OP_ICMP_DELAY 1 +OP_LOGIC_DELAY 1 +OP_SHIFT_DELAY 1 +OP_FMEM_DELAY 1 +OP_FCVT_DELAY 3 +OP_FADD_DELAY 3 +OP_FMUL_DELAY 5 +OP_FMA_DELAY 5 +OP_FDIV_DELAY -20 +OP_FCMP_DELAY 3 +OP_FCMOV_DELAY 1 +OP_GATHER_DELAY 12 +OP_SCATTER_DELAY 18 +OP_PIPELINED_FAST_DELAY 2 +OP_PIPELINED_MEDIUM_DELAY 5 +OP_PIPELINED_SLOW_DELAY 10 +OP_NOTPIPELINED_MEDIUM_DELAY -5 +OP_NOTPIPELINED_SLOW_DELAY -20 +OP_NOTPIPELINED_VERY_SLOW_DELAY -100 +UNIFORM_OP_DELAY 0 +STALL_ON_WAIT_MEM TRUE +STORES_DO_NOT_BLOCK_WINDOW FALSE 1 +PREFS_DO_NOT_BLOCK_WINDOW FALSE 1 +OBEY_REG_DEP TRUE +OLDEST_FIRST_SCHED FALSE +FIND_EMPTIEST_RS FALSE +TRACK_L1_MISS_DEPS FALSE +CBP_TRACE_R0 NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir/trace/drmemtrace.specrand_i.553922.2837.trace.gz +CBP_TRACE_R1 NULL +CBP_TRACE_R2 NULL +CBP_TRACE_R3 NULL +CBP_TRACE_R4 NULL +CBP_TRACE_R5 NULL +CBP_TRACE_R6 NULL +CBP_TRACE_R7 NULL +CBP_TRACE_R8 NULL +CBP_TRACE_R9 NULL +CBP_TRACE_R10 NULL +CBP_TRACE_R11 NULL +CBP_TRACE_R12 NULL +CBP_TRACE_R13 NULL +CBP_TRACE_R14 NULL +CBP_TRACE_R15 NULL +CBP_TRACE_R16 NULL +CBP_TRACE_R17 NULL +CBP_TRACE_R18 NULL +CBP_TRACE_R19 NULL +CBP_TRACE_R20 NULL +CBP_TRACE_R21 NULL +CBP_TRACE_R22 NULL +CBP_TRACE_R23 NULL +CBP_TRACE_R24 NULL +CBP_TRACE_R25 NULL +CBP_TRACE_R26 NULL +CBP_TRACE_R27 NULL +CBP_TRACE_R28 NULL +CBP_TRACE_R29 NULL +CBP_TRACE_R30 NULL +CBP_TRACE_R31 NULL +CBP_TRACE_R32 NULL +CBP_TRACE_R33 NULL +CBP_TRACE_R34 NULL +CBP_TRACE_R35 NULL +CBP_TRACE_R36 NULL +CBP_TRACE_R37 NULL +CBP_TRACE_R38 NULL +CBP_TRACE_R39 NULL +CBP_TRACE_R40 NULL +CBP_TRACE_R41 NULL +CBP_TRACE_R42 NULL +CBP_TRACE_R43 NULL +CBP_TRACE_R44 NULL +CBP_TRACE_R45 NULL +CBP_TRACE_R46 NULL +CBP_TRACE_R47 NULL +CBP_TRACE_R48 NULL +CBP_TRACE_R49 NULL +CBP_TRACE_R50 NULL +CBP_TRACE_R51 NULL +CBP_TRACE_R52 NULL +CBP_TRACE_R53 NULL +CBP_TRACE_R54 NULL +CBP_TRACE_R55 NULL +CBP_TRACE_R56 NULL +CBP_TRACE_R57 NULL +CBP_TRACE_R58 NULL +CBP_TRACE_R59 NULL +CBP_TRACE_R60 NULL +CBP_TRACE_R61 NULL +CBP_TRACE_R62 NULL +CBP_TRACE_R63 NULL +MEMTRACE_MODULES_LOG NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir/raw +DUMB_CORE_ON FALSE +DUMB_CORE 1 +DEBUG_CYCLE_START 0 0 +DEBUG_CYCLE_STOP 0 -1 +DEBUG_TIME_START 0 +DEBUG_TIME_STOP 0 +DEBUG_INST_START 0 0 +DEBUG_INST_STOP 0 -1 +DEBUG_OP_START 0 +DEBUG_OP_STOP 0 +DEBUG_CACHE_LIB FALSE +DEBUG_HASH_LIB FALSE +DEBUG_LIST_LIB FALSE +DEBUG_PORT_LIB FALSE +DEBUG_BUS_LIB FALSE +DEBUG_OP_POOL FALSE +DEBUG_ORACLE FALSE +DEBUG_FRONTEND FALSE +DEBUG_ADDR_TRANS FALSE +DEBUG_BP FALSE +DEBUG_BP_DIR FALSE +DEBUG_BTB FALSE +DEBUG_CRS FALSE +DEBUG_MAP FALSE +DEBUG_MEMORY FALSE +DEBUG_REPLAY FALSE +DEBUG_FREQ FALSE +DEBUG_MODEL FALSE +DEBUG_THREAD FALSE +DEBUG_ICACHE_STAGE FALSE +DEBUG_DECODE_STAGE FALSE +DEBUG_MAP_STAGE FALSE +DEBUG_NODE_STAGE FALSE +DEBUG_EXEC_STAGE FALSE +DEBUG_DCACHE_STAGE FALSE +DEBUG_RETIRED_UOPS FALSE +DEBUG_EXC_INSERTS FALSE +DEBUG_BP_CONF FALSE +DEBUG_ONPATH_CONF FALSE +DEBUG_STREAM FALSE +DEBUG_STREAM_MEM FALSE +DEBUG_WAY FALSE +DEBUG_L2MARKV FALSE +DEBUG_L2L1PREF FALSE +DEBUG_PERF_PRED FALSE +DEBUG_POWER_UTILS FALSE +DEBUG_DVFS FALSE +DEBUG_TRACE_READ FALSE +DEBUG_INST_FIELDS FALSE +DEBUG_OP_FIELDS FALSE +DEBUG_PIN_EXEC_DRIVEN FALSE +DEBUG_CACHE_PART FALSE +DEBUG_OPTIMIZER2 FALSE +DEBUG_PREF FALSE +PERFECT_BP FALSE +PERFECT_BTB FALSE +PERFECT_IBP FALSE +PERFECT_CRS FALSE +PERFECT_CBR_BTB FALSE +PERFECT_NT_BTB FALSE +CFS_PER_CYCLE 3 6 # Number of branches that can be predicted in a single cycle +UPDATE_BP_OFF_PATH FALSE 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +BP_UPDATE_AT_RETIRE FALSE 0 # Update the BP at retire. If false, update at the end of exec. +BP_MECH 0 tagescl +LATE_BP_MECH NUM_BP +LATE_BP_LATENCY 5 +HIST_LENGTH 16 +PHT_CTR_BITS 2 const +BHT_ENTRIES (4 * 1024) +BHT_ASSOC 4 +HYBRIDS_INDEX_LENGTH 16 +HYBRIDG_HIST_LENGTH 16 +HYBRIDP_HIST_LENGTH 16 +FILTER_INDEX_LENGTH 16 +USE_FILTER FALSE +INF_HYBRIDGP FALSE +BP_HASH_TOS FALSE +IBTB_HASH_TOS FALSE +BTB_MECH 0 generic +BTB_ENTRIES (4 * 1024) 4096 +BTB_ASSOC 4 4 +BTB_OFF_PATH_WRITES TRUE 1 +ENABLE_CRS TRUE 1 +CRS_ENTRIES 32 32 +CRS_REALISTIC 0 1 +ENABLE_IBP TRUE 1 # Enable the indirect branch predictor +USE_PAT_HIST TRUE +IBTB_MECH 1 tc_tagged +IBTB_HIST_LENGTH 16 +IBTB_OFF_PATH_WRITES TRUE 1 # Allow off path ops to update the ibtb. +TARGETS_IN_HIST 4 +TC_ENTRIES (4 * 1024) 4096 +TC_ASSOC 4 4 +NUM_CORR_BRANCHES 3 +SEL_HIST_BP_ENTRIES 8192 +SEL_HIST_LENGTH 16 +SEL_HIST_DYN_CNT_TH 16 +SEL_HIST_MISPRED_TH 4 +ENABLE_BP_CONF FALSE +CONF_MECH 0 +PERF_BP_CONF_PRED FALSE +BPC_BITS 16 +BPC_MECH 1 +BPC_CTR_RESET TRUE +BPC_CIT_BITS 8 +BPC_CIT_TH 50 +BPC_CTR_BITS 3 +OPC_COUNT_ZEROS FALSE +OPC_COUNT_THRESH 10 +INF_LOOP FALSE +INF_LOOP_BUCKETS 811 +LOOP_ENTRIES (4 * 1024) +LOOP_ASSOC 4 +LOOP_COUNT_MAX 127 +LOOP_REPEAT_MAX 15 +KNOB_PRINT_BRINFO FALSE +BR_MISPRED_FILE NULL +CONF_PERCEPTRON_TH 0 +CONF_PERCEPTRON_CTR_BITS 8 +CONF_PERCEPTRON_ENTRIES 127 +CONF_PERCEPTRON_THRESH_OVRD 0 +CONF_HIST_LENGTH 32 +PERCEPTRON_CONF_USE_CONF FALSE +PERCEPTRON_CONF_TRAIN_HIS FALSE +PERCEPTRON_CONF_TRAIN_CONF FALSE +PERCEPTRON_CONF_TRAIN_OFFSET_CONF FALSE +PERCEPTRON_TRAIN_MISP_FACTOR 1 +PERCEPTRON_TRAIN_CORR_FACTOR 1 +PERCEPTRON_CONF_HIS_BOTH FALSE +PERCEPTRON_CONF_HIS_BOTH_LENGTH 4 +ENABLE_ICACHE_PACKET_BREAKING TRUE +NUM_LOAD_STORE_PER_PACKET 0 +PACKET_BREAK_ON_FUS FALSE +PACKET_BREAK_FU_TYPES "G,G,G,G,G,G,G,G,G,G,G,G" +POWER_INTF_ON FALSE +POWER_INTF_ENABLE_SCALING FALSE +POWER_INTF_EXEC "power/power_intf.py" +POWER_INTF_REF_CHIP_TECH_NM 22 +POWER_INTF_REF_CHIP_FREQ (3.2e9) +POWER_INTF_REF_MEMORY_FREQ (0.8e9) +POWER_OTHER (0.0) +PREF_STREAM_ON FALSE 1 +PREF_STREAM_PER_CORE_ENABLE FALSE 1 +STREAM_BUFFER_N 16 +STREAM_PREFETCH_N 2 4 +STREAM_START_DIS 5 1 +STREAM_LENGTH 16 64 +STREAM_FULL_N 1 +STREAM_TRAIN_LENGTH 16 +STREAM_TRAIN_NUM 1 4 +PREF_ACC_USE_CACHE FALSE +STREAM_STALL_ON_QUEUE_FULL FALSE +PREF_SCHEDULE_NUM 4 +TRAIN_FILTER_SIZE 32 +PREF_REQ_Q_SIZE 64 +STREAM_CREATE_ON_DC_MISS FALSE 0 +STREAM_CREATE_ON_L1_MISS TRUE 1 +STREAM_TRAIN_ON_WRONGPATH TRUE +STREAM_CREATE_ON_WRONGPATH TRUE +STREAM_PREF_INTO_DCACHE FALSE +REMOVE_REDUNDANT_STREAM FALSE +L2HIT_STREAM_SCHEDULE_NUM 4 +PREF_REQ_QUEUE_FILTER_ON FALSE +HW_PREF_HIT_TRAIN_STREAM FALSE +L2HIT_STREAM_BUFFER_N 32 +L2HIT_STREAM_PREFETCH_N 2 +L2HIT_STREAM_START_DIS 2 +L2HIT_STREAM_LENGTH 8 +L2HIT_PREF_REQ_Q_SIZE 128 +L2HIT_L2ACCESS_REQ_Q_SIZE 64 +PREF_STREAM_ACCPERSTREAM FALSE +PREF_ACC_DISTANCE_10 128 +PREF_FRAMEWORK_ON FALSE 1 +PREF_TRACE_ON FALSE +PREF_DL0REQ_QUEUE_SIZE 32 +PREF_UMLC_REQ_QUEUE_SIZE 64 +PREF_UL1REQ_QUEUE_SIZE 128 +PREF_SHARED_QUEUES TRUE 0 +PREF_DL0_MISS_ON TRUE +PREF_DL0_HIT_ON TRUE +PREF_DL0REQ_QUEUE_FILTER_ON TRUE +PREF_UMLC_REQ_QUEUE_FILTER_ON TRUE +PREF_UL1REQ_QUEUE_FILTER_ON TRUE +PREF_DL0REQ_ADD_FILTER_ON TRUE +PREF_UMLC_REQ_ADD_FILTER_ON TRUE +PREF_UL1REQ_ADD_FILTER_ON TRUE +PREF_DL0REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UMLC_REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UL1REQ_QUEUE_OVERWRITE_ON_FULL FALSE 1 +PREF_DL0SCHEDULE_NUM 4 +PREF_UMLC_SCHEDULE_NUM 4 +PREF_UL1SCHEDULE_NUM 4 +PREF_L1Q_DEMAND_RESERVE 0 +PREF_REPORT_PREF_MATCH_AS_MISS FALSE +PREF_REPORT_PREF_MATCH_AS_HIT TRUE +PREF_UPDATE_ON_WRONGPATH TRUE +PREF_TRAIN_ON_PREF_MISSES FALSE 0 +PREF_ORACLE_TRAIN_ON FALSE 0 +PREF_REQ_DROP FALSE +PREF_THROTTLE_ON FALSE +PREF_THROTTLEFB_ON FALSE 1 +PREF_ACC_THRESH_1 0.90 0.75 +PREF_ACC_THRESH_2 0.70 0.4 +PREF_ACC_THRESH_3 0.60 0.4 +PREF_ACC_THRESH_4 0.40 +PREF_UPDATE_INTERVAL 0 8192 +PREF_ANALYZE_LOAD FALSE +PREF_POL_THRESH_1 0.25 +PREF_POL_THRESH_2 0.10 +PREF_POLBV_ON FALSE +PREF_POLBV_SIZE 1024 +PREF_TIMELY_THRESH 0.05 0.01 +PREF_POLPF_THRESH 0.01 0.005 +PREF_DEGFB_USEONLYACC FALSE +PREF_DEGFB_USEONLYPOL FALSE +PREF_DEGFB_USEONLYLATE FALSE +PREF_TIMELY_THRESH_2 0.005 +PREF_DEGFB_STATPHASEFILE FALSE +PREF_MAX_DEGFB 4 +PREF_DHAL FALSE +PREF_DHAL_SENTTHRESH 16 +PREF_DHAL_USETHRESH_MAX 12 +PREF_DHAL_USETHRESH_MIN2 8 +PREF_DHAL_USETHRESH_MIN1 4 +PREF_DHAL_MAXDEG 64 +PREF_HFILTER_ON FALSE +PREF_HFILTER_INDEX_BITS 12 +PREF_HFILTER_USE_PC FALSE +PREF_HFILTER_PRED_USELESS_THRES 2 +PREF_HFILTER_RESET_ENABLE FALSE +PREF_HFILTER_RESET_INTERVAL 100000 +L2L1PREF_ON FALSE +L2WAY_PREF FALSE +L2MARKV_PREF_ON FALSE +L2NEXT_PREF_ON FALSE +L2HIT_STREAM_PREF_ON FALSE +L2L1_DC_HIT_TRAIN FALSE +L1_HIT_DUMP_FILE_ON FALSE +L1_HIT_DUMP_WO_TXT FALSE +L1_HIT_DUMPFILE "l1hit_dump.out" +IDEAL_L2_L1_PREFETCHER FALSE +IDEAL_L2_ICACHE_PREFETCHER FALSE +L1WAY_PREF_SEND_QUEUE 4 +L1PREF_REQ_QUEUE_SIZE 1024 +L1PREF_IMMEDIATE FALSE +L1WAY_PREF_TIMER_DIS 1000 +L1MARKV_PREF_SEND_QUEUE 4 +L1PREF_MARKV_REQ_QUEUE_SIZE 1024 +MARKV_L2ACCESS_REQ_Q_SIZE 64 +L1MARKV_PREF_IMMEDIATE FALSE +L1MARKV_PREF_TIMER_DIS 1 +L2L1_HIT_TRAIN TRUE +L1MARKV_REQ_TH 1 +L2L1_IMMEDIATE_PREF_CACHE FALSE +L2L1_FILL_PREF_CACHE FALSE +L2L1_L2_HIT_STAT FALSE +PREF_GHB_ON FALSE +DEBUG_PREF_GHB FALSE +PREF_GHB_BUFFER_N 1024 +PREF_GHB_INDEX_N 128 +PREF_GHB_CZONE_BITS 12 +PREF_GHB_DEGREE 16 +PREF_GHB_MAX_DEGREE 32 +PREF_STRIDE_ON FALSE +DEBUG_PREF_STRIDE FALSE +PREF_STRIDE_TABLE_N 1024 +PREF_STRIDE_REGION_BITS 16 +PREF_STRIDE_DEGREE 4 +PREF_STRIDE_DISTANCE 16 +PREF_STRIDE_STARTDISTANCE 1 +PREF_STRIDE_SINGLE_THRESH 6 +PREF_STRIDE_MULTI_THRESH 6 +PREF_STRIDE_SINGLE_STRIDE_MODE FALSE +PREF_STRIDEPC_ON FALSE +DEBUG_PREF_STRIDEPC FALSE +PREF_STRIDEPC_TABLE_N 1024 +PREF_STRIDEPC_DEGREE 4 +PREF_STRIDEPC_DISTANCE 16 +PREF_STRIDEPC_USELOADADDR FALSE +PREF_STRIDEPC_TRAINNUM 2 +PREF_STRIDEPC_STARTDIS 4 +PREF_PHASE_ON FALSE +PREF_PHASE_STUDY FALSE +DEBUG_PREF_PHASE FALSE +PREF_PHASE_PRIME_HASH 16381 +PREF_PHASE_INFOSIZE 16384 +PREF_PHASE_LOG2REGIONSIZE 12 +PREF_PHASE_REGIONENTRIES 64 +PREF_PHASE_TRACKEDREGIONS 32 +PREF_PHASE_INTERVAL 100000 +PREF_PHASE_TABLE_SIZE 64 +PREF_PHASE_MAXDIFF_THRESH 64 +PREF_PHASE_MIN_MISSES 64 +PREF_PHASE_MISSPER 0.4 +PREF_2DC_ON FALSE +DEBUG_PREF_2DC FALSE +PREF_2DC_CACHE_SIZE (1 * 1024) +PREF_2DC_CACHE_ASSOC 4 +PREF_2DC_CACHE_LINE_SIZE 1 +PREF_2DC_DEGREE 16 +PREF_2DC_ZONE_SHIFT 10 +PREF_2DC_TAG_SIZE 16 +PREF_2DC_NUM_REGIONS 64 +PREF_2DC_REGION_HASH 61 +PREF_MARKOV_ON FALSE +DEBUG_PREF_MARKOV FALSE +PREF_MARKOV_NUM_ENTRIES 65536 +PREF_MARKOV_NUM_NEXT_STATES 8 +PREF_MARKOV_SEND_ON_PREF_HIT TRUE +PREF_MARKOV_UPDATE_ON_PREF_HIT TRUE +PREF_MARKOV_TABLE_UPDATE_POLICY 0 +PREF_MARKOV_SEND_THRESHOLD 0 +PREF_SMS_ON FALSE 0 +PREF_SMS_AT_SIZE 64 +PREF_SMS_FT_SIZE 64 +PREF_SMS_PHT_SIZE 16384 +PREF_SMS_PRF_SIZE 1024 +PREF_SMS_REGION_SIZE 2048 diff --git a/labs/LAB5/runs/specrand_i-sms0/bp.stat.0.out b/labs/LAB5/runs/specrand_i-sms0/bp.stat.0.out new file mode 100644 index 00000000..caa9a70e --- /dev/null +++ b/labs/LAB5/runs/specrand_i-sms0/bp.stat.0.out @@ -0,0 +1,752 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 37600340 Instructions: 100000004 IPC: 2.65955 + +BTB_ON_PATH_MISS 529 0.003% 529 0.003% +BTB_ON_PATH_HIT 20919436 99.997% 20919436 99.997% + 20919965 100.000% 20919965 100.000% + 1.00 1.00 1.00 1.00 + +BTB_OFF_PATH_MISS 0 -nan% 0 -nan% +BTB_OFF_PATH_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BTB_ON_PATH_WRITE 529 100.000% 529 100.000% +BTB_OFF_PATH_WRITE 0 0.000% 0 0.000% + 529 100.000% 529 100.000% + 0.00 0.00 0.00 0.00 + +BP_ON_PATH_CORRECT 20394052 97.486% 20394052 97.486% +BP_ON_PATH_MISPREDICT 38936 0.186% 38936 0.186% +BP_ON_PATH_MISFETCH 486977 2.328% 486977 2.328% + 20919965 100.000% 20919965 100.000% + 0.05 0.30 0.05 0.30 + +BP_OFF_PATH_CORRECT 0 -nan% 0 -nan% +BP_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% +BP_OFF_PATH_MISFETCH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +LATE_BP_ON_PATH_CORRECT 20919965 100.000% 20919965 100.000% +LATE_BP_ON_PATH_MISPREDICT 0 0.000% 0 0.000% +LATE_BP_ON_PATH_MISFETCH 0 0.000% 0 0.000% + 20919965 100.000% 20919965 100.000% + 0.00 0.00 0.00 0.00 + +LATE_BP_OFF_PATH_CORRECT 0 -nan% 0 -nan% +LATE_BP_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% +LATE_BP_OFF_PATH_MISFETCH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_PVN 0 -nan% 0 -nan% +BP_ON_PATH_CONF_PVN_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_PVP 0 -nan% 0 -nan% +BP_ON_PATH_CONF_PVP_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_SPEC 0 -nan% 0 -nan% +BP_ON_PATH_CONF_SPEC_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CRS_MISS_ON_PATH 85185 4.432% 85185 4.432% +CRS_HIT_ON_PATH 1836733 95.568% 1836733 95.568% + 1921918 100.000% 1921918 100.000% + 0.96 0.94 0.96 0.94 + +CRS_MISS_OFF_PATH 0 -nan% 0 -nan% +CRS_HIT_OFF_PATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CRS_CLOBBER 0 0 + +TARG_ON_PATH_MISS 921 0.116% 921 0.116% +TARG_ON_PATH_HIT 791502 99.884% 791502 99.884% + 792423 100.000% 792423 100.000% + 1.00 1.00 1.00 1.00 + +TARG_OFF_PATH_MISS 0 -nan% 0 -nan% +TARG_OFF_PATH_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_ON_PATH_WRITE 792423 100.000% 792423 100.000% +TARG_OFF_PATH_WRITE 0 0.000% 0 0.000% + 792423 100.000% 792423 100.000% + 0.00 0.00 0.00 0.00 + +TARG_HYBRID_CORRECT_TAGLESS 0 -nan% 0 -nan% +TARG_HYBRID_CORRECT_TAGGED 0 -nan% 0 -nan% +TARG_HYBRID_MISPRED_TAGLESS 0 -nan% 0 -nan% +TARG_HYBRID_MISPRED_TAGGED 0 -nan% 0 -nan% +TARG_HYBRID_NO_PRED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_VP_INDIRECT_MISPRED 0 -nan% 0 -nan% +TARG_VP_INDIRECT_NOPRED 0 -nan% 0 -nan% +TARG_VP_INDIRECT_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CBR_ON_PATH_CORRECT 15130259 99.743% 15130259 99.743% +CBR_ON_PATH_MISPREDICT 38936 0.257% 38936 0.257% + 15169195 100.000% 15169195 100.000% + 0.00 0.05 0.00 0.05 + +CBR_ON_PATH_CORRECT_PER1000INST 15130259 151.3026 15130259 151.3026 + +CBR_ON_PATH_MISPREDICT_PER1000INST 38936 0.3894 38936 0.3894 + +CBR_OFF_PATH_CORRECT 0 -nan% 0 -nan% +CBR_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PRED_TO_UPDATE_CYCLES_0 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_1 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_2 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_3 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_4 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_5 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_6 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_7 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_8 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_9 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_10 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_11 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_12 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_13 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_14 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_15 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_16 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_17 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_18 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_19 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_20 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_21 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_22 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_23 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_24 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_25 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_26 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_27 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_28 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_29 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_30 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_CORRECTED 0 -nan% 0 -nan% +BP_NOT_CORRECTED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_CORRECTED 0 -nan% 0 -nan% +TARG_NOT_CORRECTED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_MISP_PENALTY 3512142 3512142 + +BP_ON_PATH_CONF_MISPRED 0 -nan% 0 -nan% +BP_ON_PATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_OFF_PATH_CONF_MISPRED 0 -nan% 0 -nan% +BP_OFF_PATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_PRED_MIS_CONF_MISPRED 0 -nan% 0 -nan% +BP_ON_PATH_PRED_MIS_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_PRED_COR_CONF_MISPRED 0 -nan% 0 -nan% +BP_ON_PATH_PRED_COR_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_OFF_PATH_PRED_MIS_CONF_MISPRED 0 -nan% 0 -nan% +BP_OFF_PATH_PRED_MIS_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_OFF_PATH_PRED_COR_CONF_MISPRED 0 -nan% 0 -nan% +BP_OFF_PATH_PRED_COR_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ONPATH_CONF_MISPRED 0 -nan% 0 -nan% +ONPATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ONPATH_ON_PATH_CONF_MISPRED 0 -nan% 0 -nan% +ONPATH_ON_PATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ONPATH_OFF_PATH_CONF_MISPRED 0 -nan% 0 -nan% +ONPATH_OFF_PATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PRED_ONPATH_CONF_MISPRED 0 -nan% 0 -nan% +PRED_ONPATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PRED_OFFPATH_CONF_MISPRED 0 -nan% 0 -nan% +PRED_OFFPATH_CONF_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +LONG_OVWT_MIS 0 -nan% 0 -nan% +LONG_OVWT_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_0_7_MIS 0 -nan% 0 -nan% +OPC_LENGTH_0_7_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_8_15_MIS 0 -nan% 0 -nan% +OPC_LENGTH_8_15_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_16_23_MIS 0 -nan% 0 -nan% +OPC_LENGTH_16_23_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_24_31_MIS 0 -nan% 0 -nan% +OPC_LENGTH_24_31_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_32_39_MIS 0 -nan% 0 -nan% +OPC_LENGTH_32_39_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_40_47_MIS 0 -nan% 0 -nan% +OPC_LENGTH_40_47_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_48_55_MIS 0 -nan% 0 -nan% +OPC_LENGTH_48_55_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_56_63_MIS 0 -nan% 0 -nan% +OPC_LENGTH_56_63_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_64_71_MIS 0 -nan% 0 -nan% +OPC_LENGTH_64_71_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_72_79_MIS 0 -nan% 0 -nan% +OPC_LENGTH_72_79_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +OPC_LENGTH_80_MIS 0 -nan% 0 -nan% +OPC_LENGTH_80_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ALL_ONES_MIS 0 -nan% 0 -nan% +ALL_ONES_COR 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan 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-nan 0 -nan + +CYCLES_WAITING_FOR_OFF_CHIP 0 0.0000 0 0.0000 + +FUS_BUSY_WAITING_FOR_OFF_CHIP 0 -nan 0 -nan + +TOTAL_OFF_CHIP_DELAYS_LEFT 0 0 + +WRONG_IO_SCHED 0 0 + +DVFS_CONFIG_SWITCH 0 0 + + + diff --git a/labs/LAB5/runs/specrand_i-sms0/fetch.stat.0.out b/labs/LAB5/runs/specrand_i-sms0/fetch.stat.0.out new file mode 100644 index 00000000..33342bb8 --- /dev/null +++ b/labs/LAB5/runs/specrand_i-sms0/fetch.stat.0.out @@ -0,0 +1,248 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 37600340 Instructions: 100000004 IPC: 2.65955 + +ICACHE_CYCLE 37600340 37600340 + +TCACHE_CYCLE 0 0 + +ICACHE_CYCLE_ONPATH 27777217 73.875% 27777217 73.875% +ICACHE_CYCLE_OFFPATH 9823123 26.125% 9823123 26.125% + 37600340 100.000% 37600340 100.000% + 0.26 0.40 0.26 0.40 + +FETCH_ON_PATH 24860691 100.000% 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b/labs/LAB5/runs/specrand_i-sms0/inst.stat.0.out @@ -0,0 +1,103 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 37600340 Instructions: 100000004 IPC: 2.65955 + +ST_OP_INV 0 0.000% 0 0.000% +ST_OP_NOP 2435080 2.046% 2435080 2.046% +ST_OP_CF 20948368 17.603% 20948368 17.603% +ST_OP_MOV 12802380 10.758% 12802380 10.758% +ST_OP_CMOV 175550 0.148% 175550 0.148% +ST_OP_LDA 4521657 3.800% 4521657 3.800% +ST_OP_IMEM 31644662 26.592% 31644662 26.592% +ST_OP_IADD 20142062 16.926% 20142062 16.926% +ST_OP_IMUL 616477 0.518% 616477 0.518% +ST_OP_IDIV 28403 0.024% 28403 0.024% +ST_OP_ICMP 9277559 7.796% 9277559 7.796% +ST_OP_LOGIC 12076608 10.148% 12076608 10.148% +ST_OP_SHIFT 2546917 2.140% 2546917 2.140% +ST_OP_FMEM 864571 0.727% 864571 0.727% +ST_OP_FCVT 292192 0.246% 292192 0.246% +ST_OP_FADD 8189 0.007% 8189 0.007% +ST_OP_FMUL 292192 0.246% 292192 0.246% +ST_OP_FMA 0 0.000% 0 0.000% +ST_OP_FDIV 0 0.000% 0 0.000% +ST_OP_FCMP 56802 0.048% 56802 0.048% +ST_OP_FCMOV 0 0.000% 0 0.000% +ST_OP_GATHER 0 0.000% 0 0.000% +ST_OP_SCATTER 0 0.000% 0 0.000% +ST_OP_PIPELINED_FAST 109769 0.092% 109769 0.092% +ST_OP_PIPELINED_MEDIUM 0 0.000% 0 0.000% +ST_OP_PIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_MEDIUM 162362 0.136% 162362 0.136% +ST_OP_NOTPIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_VERY_SLOW 0 0.000% 0 0.000% + 119001800 100.000% 119001800 100.000% + 6.10 3.28 6.10 3.28 + +ST_NOT_CF 98053432 82.397% 98053432 82.397% +ST_CF_BR 1297461 1.090% 1297461 1.090% +ST_CF_CBR 15169195 12.747% 15169195 12.747% +ST_CF_CALL 1738968 1.461% 1738968 1.461% +ST_CF_IBR 609473 0.512% 609473 0.512% +ST_CF_ICALL 182950 0.154% 182950 0.154% +ST_CF_ICO 0 0.000% 0 0.000% +ST_CF_RET 1921918 1.615% 1921918 1.615% +ST_CF_SYS 28403 0.024% 28403 0.024% + 119001800 100.000% 119001800 100.000% + 0.45 1.10 0.45 1.10 + +ST_BAR_NONE 118973397 99.976% 118973397 99.976% +ST_BAR_FETCH 28403 0.024% 28403 0.024% +ST_BAR_ISSUE 0 0.000% 0 0.000% +ST_BAR_BOTH 0 0.000% 0 0.000% + 119001800 100.000% 119001800 100.000% + 0.00 0.02 0.00 0.02 + +ST_NOT_MEM 86492567 72.682% 86492567 72.682% +ST_MEM_LD 19982216 16.792% 19982216 16.792% +ST_MEM_ST 12527017 10.527% 12527017 10.527% +ST_MEM_PF 0 0.000% 0 0.000% +ST_MEM_WH 0 0.000% 0 0.000% +ST_MEM_EVICT 0 0.000% 0 0.000% + 119001800 100.000% 119001800 100.000% + 0.38 0.58 0.38 0.58 + +ST_NOT_MEM_OFFPATH 0 -nan% 0 -nan% +ST_MEM_LD_OFFPATH 0 -nan% 0 -nan% +ST_MEM_ST_OFFPATH 0 -nan% 0 -nan% +ST_MEM_PF_OFFPATH 0 -nan% 0 -nan% +ST_MEM_WH_OFFPATH 0 -nan% 0 -nan% +ST_MEM_EVIC_OFFPATHT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ST_OP_ONPATH 119001800 119001800 + +ST_OP_OFFPATH 0 0 + +ST_FAKE_OP_OFFPATH 0 -nan% 0 -nan% +ST_NOT_FAKE_OP_OFFPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ST_FAKE_REASON_NOT_FAKE 0 -nan% 0 -nan% +ST_FAKE_REASON_REDIRECT_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_RETURN_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_NONRET_CF_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_NOT_TAKEN_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_WRONG_PATH_STORE_TO_NEW_REGION 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ST_INST_ONPATH 100000090 100000090 + +ST_INST_OFFPATH 0 0 + +STATIC_PIN_NOP 0 0 + +DYNAMIC_PIN_REP_GREATER_256 0 0 + + + diff --git a/labs/LAB5/runs/specrand_i-sms0/l2l1pref.stat.0.out b/labs/LAB5/runs/specrand_i-sms0/l2l1pref.stat.0.out new file mode 100644 index 00000000..2309bfc6 --- /dev/null +++ b/labs/LAB5/runs/specrand_i-sms0/l2l1pref.stat.0.out @@ -0,0 +1,140 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 37600340 Instructions: 100000004 IPC: 2.65955 + +L2WAY_FILL_L1 0 0 + +L2WAY_WAY_HIT 0 -nan% 0 -nan% +L2WAY_WAY_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_PREF_REQ 0 0 + +L2WAY_PREF_HIT_DATA_IN_CACHE 0 -nan% 0 -nan% +L2WAY_PREF_HIT_DATA_REQ 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_TRAIN_HIT 0 -nan% 0 -nan% +L2WAY_TRAIN_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L1_HIT_REQ_TYPE_IFETCH 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DFETCH 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DSTORE 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_IPRF 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DPRF 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_WB 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2_ACCESS_INTERVAL__0 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__1 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__2 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__3 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__4 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__5 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__6 0 -nan% 0 -nan% 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+ -nan -nan -nan -nan + +L2HIT_SAME_IP_DELTA__0 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__1 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__2 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__3 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__4 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__5 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__6 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__7 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__8 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_IP_HIT_COUNT__1 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__2 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__3 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__4 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__5 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__6 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__7 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__8 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__9 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + + + diff --git a/labs/LAB5/runs/specrand_i-sms0/memory.stat.0.out b/labs/LAB5/runs/specrand_i-sms0/memory.stat.0.out new file mode 100644 index 00000000..b8de60b4 --- /dev/null +++ b/labs/LAB5/runs/specrand_i-sms0/memory.stat.0.out @@ -0,0 +1,3416 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 37600340 Instructions: 100000004 IPC: 2.65955 + +ICACHE_MISS 162959 0.499% 162959 0.499% +ICACHE_HIT 32501548 99.501% 32501548 99.501% + 32664507 100.000% 32664507 100.000% + 1.00 0.99 1.00 0.99 + +ICACHE_MISS_ONPATH 162959 100.000% 162959 100.000% +ICACHE_MISS_OFFPATH 0 0.000% 0 0.000% + 162959 100.000% 162959 100.000% + 0.00 0.00 0.00 0.00 + +ICACHE_HIT_ONPATH 32501548 100.000% 32501548 100.000% +ICACHE_HIT_OFFPATH 0 0.000% 0 0.000% + 32501548 100.000% 32501548 100.000% + 0.00 0.00 0.00 0.00 + +ICACHE_HIT_ONPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +ICACHE_HIT_ONPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ICACHE_HIT_OFFPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +ICACHE_HIT_OFFPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DCACHE_MISS 504 0.002% 504 0.002% +DCACHE_ST_BUFFER_HIT 0 0.000% 0 0.000% +DCACHE_HIT 32508709 99.998% 32508709 99.998% + 32509213 100.000% 32509213 100.000% + 2.00 2.00 2.00 2.00 + +DCACHE_MISS_COMPULSORY 157 0.3115 157 0.3115 + +DCACHE_MISS_CAPACITY 0 0.0000 0 0.0000 + +DCACHE_MISS_CONFLICT 347 0.6885 347 0.6885 + +DCACHE_MISS_ONPATH 504 100.000% 504 100.000% +DCACHE_MISS_OFFPATH 0 0.000% 0 0.000% + 504 100.000% 504 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_ST_BUFFER_HIT_ONPATH 0 -nan% 0 -nan% +DCACHE_ST_BUFFER_HIT_OFFPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DCACHE_HIT_ONPATH 32508709 100.000% 32508709 100.000% +DCACHE_HIT_OFFPATH 0 0.000% 0 0.000% + 32508709 100.000% 32508709 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_HIT_ONPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +DCACHE_HIT_ONPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DCACHE_HIT_OFFPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +DCACHE_HIT_OFFPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DCACHE_MISS_LD 460 91.270% 460 91.270% +DCACHE_MISS_ST 44 8.730% 44 8.730% + 504 100.000% 504 100.000% + 0.09 0.27 0.09 0.27 + +DCACHE_MISS_LD_ONPATH 460 100.000% 460 100.000% +DCACHE_MISS_LD_OFFPATH 0 0.000% 0 0.000% + 460 100.000% 460 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_MISS_ST_ONPATH 44 100.000% 44 100.000% +DCACHE_MISS_ST_OFFPATH 0 0.000% 0 0.000% + 44 100.000% 44 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_MISS_WAITMEM 0 0 + +MEM_REQ_ROW_BUFFER_HITS 0 -nan% 0 -nan% +MEM_REQ_ROW_BUFFER_MISSES 0 -nan% 0 -nan% +MEM_REQ_ROW_BUFFER_CONFLICTS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +SHADOW_ROW_BUFFER_HITS 0 0 + +SHADOW_ROW_HIT_STALL_TIME 0 0 + +CHANNEL0_BUS_BUSY_CYCLES 0 -nan% 0 -nan% +CHANNEL1_BUS_BUSY_CYCLES 0 -nan% 0 -nan% +CHANNEL2_BUS_BUSY_CYCLES 0 -nan% 0 -nan% +CHANNEL3_BUS_BUSY_CYCLES 0 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-nan 0 -nan + +DRAM_NUM_REQS_22_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_22_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_22_WB_NODIRTY 0 -nan 0 -nan + +DRAM_NUM_REQS_23_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_23_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_23_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_23_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_23_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_23_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_23_WB_NODIRTY 0 -nan 0 -nan + +DRAM_NUM_REQS_24_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_24_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_24_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_24_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_24_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_24_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_24_WB_NODIRTY 0 -nan 0 -nan + +DRAM_NUM_REQS_25_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_25_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_25_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_25_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_25_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_25_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_25_WB_NODIRTY 0 -nan 0 -nan + +DRAM_NUM_REQS_26_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_26_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_26_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_26_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_26_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_26_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_26_WB_NODIRTY 0 -nan 0 -nan + +DRAM_NUM_REQS_27_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_27_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_27_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_27_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_27_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_27_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_27_WB_NODIRTY 0 -nan 0 -nan + +DRAM_NUM_REQS_28_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_28_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_28_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_28_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_28_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_28_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_28_WB_NODIRTY 0 -nan 0 -nan + +DRAM_NUM_REQS_29_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_29_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_29_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_29_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_29_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_29_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_29_WB_NODIRTY 0 -nan 0 -nan + +DRAM_NUM_REQS_30_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_30_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_30_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_30_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_30_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_30_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_30_WB_NODIRTY 0 -nan 0 -nan + +DRAM_NUM_REQS_31_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_31_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_31_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_31_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_31_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_31_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_31_WB_NODIRTY 0 -nan 0 -nan + +DRAM_NUM_REQS_32_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_32_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_32_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_32_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_32_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_32_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_32_WB_NODIRTY 0 -nan 0 -nan + +DRAM_BOTTLENECK_BUS_0 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_10 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_20 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_30 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_40 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_50 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_60 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_70 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_80 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_90 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_100 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DRAM_BOTTLENECK_BANKS_0 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_10 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_20 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_30 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_40 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_50 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_60 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_70 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_80 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_90 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_100 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DRAM_BOTTLENECK_FAW_0 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_10 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_20 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_30 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_40 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_50 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_60 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_70 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_80 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_90 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_100 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DRAM_ROW_HIT_GEN_AFTER_ROW_OPEN_STALLING 0 0 + +KNOWN_BAD_ADDRESS 0 0.000% 0 0.000% +GOOD_ADDRESS 326816 100.000% 326816 100.000% + 326816 100.000% 326816 100.000% + 1.00 1.00 1.00 1.00 + + + diff --git a/labs/LAB5/runs/specrand_i-sms0/power.stat.0.out b/labs/LAB5/runs/specrand_i-sms0/power.stat.0.out new file mode 100644 index 00000000..9bfdba7f --- /dev/null +++ b/labs/LAB5/runs/specrand_i-sms0/power.stat.0.out @@ -0,0 +1,184 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 37600340 Instructions: 100000004 IPC: 2.65955 + +POWER_STATS_BEGIN 0 0 + +POWER_TIME 11750106250000 11750106250000 + +POWER_CYCLE 37600340 37600340 + +POWER_ITLB_ACCESS 32664507 32664507 + +POWER_DTLB_ACCESS 12527008 12527008 + +POWER_ICACHE_ACCESS 32664507 32664507 + +POWER_ICACHE_MISS 162959 162959 + +POWER_BTB_READ 32664507 32664507 + +POWER_BTB_WRITE 525913 525913 + +POWER_ROB_READ 119001726 119001726 + +POWER_ROB_WRITE 119001726 119001726 + +POWER_RENAME_READ 238003452 238003452 + +POWER_RENAME_WRITE 119001726 119001726 + +POWER_FP_RENAME_READ 0 0 + +POWER_FP_RENAME_WRITE 0 0 + +POWER_FUNCTION_CALL 1921916 1921916 + +POWER_INST_WINDOW_READ 119001726 119001726 + +POWER_INST_WINDOW_WRITE 119001726 119001726 + +POWER_INT_REGFILE_READ 132918899 132918899 + +POWER_INT_REGFILE_WRITE 103094988 103094988 + +POWER_IALU_ACCESS 118356847 118356847 + +POWER_CDB_IALU_ACCESS 118356847 118356847 + +POWER_MUL_ACCESS 644879 644879 + +POWER_CDB_MUL_ACCESS 644879 644879 + +POWER_FP_INST_WINDOW_WRITE 0 0 + +POWER_FP_INST_WINDOW_READ 0 0 + +POWER_FP_REGFILE_READ 0 0 + +POWER_FP_REGFILE_WRITE 0 0 + +POWER_FPU_ACCESS 0 0 + +POWER_CDB_FPU_ACCESS 0 0 + +POWER_DCACHE_READ_ACCESS 19982206 19982206 + +POWER_DCACHE_WRITE_ACCESS 12527007 12527007 + +POWER_DCACHE_READ_MISS 460 460 + +POWER_DCACHE_WRITE_MISS 44 44 + +POWER_MLC_READ_ACCESS 0 0 + +POWER_MLC_WRITE_ACCESS 0 0 + +POWER_MLC_READ_MISS 0 0 + +POWER_MLC_WRITE_MISS 0 0 + +POWER_LLC_READ_ACCESS 163235 163235 + +POWER_LLC_WRITE_ACCESS 0 0 + +POWER_LLC_READ_MISS 430 430 + +POWER_LLC_WRITE_MISS 0 0 + +POWER_MEMORY_ACCESS 0 0 + +POWER_MEMORY_READ_ACCESS 0 0 + +POWER_MEMORY_WRITE_ACCESS 0 0 + +POWER_INST_WINDOW_WAKEUP_ACCESS 119001726 119001726 + +POWER_FP_INST_WINDOW_WAKEUP_ACCESS 0 0 + +POWER_L1DIREC_READ_ACCESS 0 0 + +POWER_L1DIREC_WRITE_ACCESS 0 0 + +POWER_L1DIREC_READ_MISS 0 0 + +POWER_L1DIREC_WRITE_MISS 0 0 + +POWER_L2DIREC_READ_ACCESS 0 0 + +POWER_L2DIREC_WRITE_ACCESS 0 0 + +POWER_L2DIREC_READ_MISS 0 0 + +POWER_L2DIREC_WRITE_MISS 0 0 + +POWER_MEMORY_CTRL_ACCESS 430 430 + +POWER_MEMORY_CTRL_READ 430 430 + +POWER_MEMORY_CTRL_WRITE 0 0 + +POWER_OP 119001726 119001726 + +POWER_INT_OP 114780570 114780570 + +POWER_FP_OP 1786077 1786077 + +POWER_LD_OP 19982208 19982208 + +POWER_ST_OP 12527008 12527008 + +POWER_BRANCH_MISPREDICT 525913 525913 + +POWER_COMMITTED_OP 119001726 119001726 + +POWER_COMMITTED_INT_OP 114780570 114780570 + +POWER_COMMITTED_FP_OP 4221156 4221156 + +POWER_BRANCH_OP 20948352 20948352 + +POWER_DRAM_PRECHARGE 76 76 + +POWER_DRAM_ACTIVATE 103 103 + +POWER_DRAM_READ 430 430 + +POWER_DRAM_WRITE 0 0 + +POWER_STATS_END 0 0 + +ENERGY 0.000000 0.000000 + +ENERGY_CORE 0.000000 0.000000 + +ENERGY_UNCORE 0.000000 0.000000 + +ENERGY_MEMORY 0.000000 0.000000 + +ENERGY_OTHER 0.000000 0.000000 + +ENERGY_CORE_STATIC 0.000000 0.000000 + +ENERGY_CORE_DYNAMIC 0.000000 0.000000 + +ENERGY_UNCORE_STATIC 0.000000 0.000000 + +ENERGY_UNCORE_DYNAMIC 0.000000 0.000000 + +ENERGY_MEMORY_STATIC 0.000000 0.000000 + +ENERGY_MEMORY_DYNAMIC 0.000000 0.000000 + +ENERGY_OTHER_STATIC 0.000000 0.000000 + +ENERGY_OTHER_DYNAMIC 0.000000 0.000000 + +TIME 0.000000 0.000000 + +ENERGY_STATS_END 0 0 + + + diff --git a/labs/LAB5/runs/specrand_i-sms0/pref.stat.0.out b/labs/LAB5/runs/specrand_i-sms0/pref.stat.0.out new file mode 100644 index 00000000..5847d386 --- /dev/null +++ b/labs/LAB5/runs/specrand_i-sms0/pref.stat.0.out @@ -0,0 +1,208 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 37600340 Instructions: 100000004 IPC: 2.65955 + +PREF_DL0REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UMLC_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UL1REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_DL0REQ_QUEUE_FULL 0 0 + +PREF_UMLC_REQ_QUEUE_FULL 0 0 + +PREF_UL1REQ_QUEUE_FULL 0 0 + +PREF_DC_HIT_NOSEND 0 0 + +PREF_WBQDC_HIT_NOSEND 0 0 + +PREF_MLCQ_STALL 0 0 + +PREF_L1Q_STALL 0 0 + +PREF_UMLC_REQ_SEND_QUEUE_STALL 0 0 + +PREF_UL1REQ_SEND_QUEUE_STALL 0 0 + +PREF_UMLC_REQ_QUEUE_SENTREQ 0 0 + +PREF_UL1REQ_QUEUE_SENTREQ 118 118 + +PREF_NEWREQ_MATCHED 0 0 + +PREF_UMLC_REQ_QUEUE_MATCHED_REQ 0 0 + +PREF_UL1REQ_QUEUE_MATCHED_REQ 8 8 + +PREF_DL0REQ_QUEUE_MATCHED_REQ 0 0 + +L1_PREF_HIT 68 68 + +L1_PREF_UNIQUE_HIT 68 68 + +L1_PREF_LATE 1 1 + +L1_LATE_PREF_CYCLES 55 55 + +L1_LATE_PREF_CYCLES_DIST_0 1 100.000% 1 100.000% +L1_LATE_PREF_CYCLES_DIST_100 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_200 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_300 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_400 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_500 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_600 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_700 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_800 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_900 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1000 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1100 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1200 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1300 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1400 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1500 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1600 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1700 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1800 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1900 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_2000 0 0.000% 0 0.000% + 1 100.000% 1 100.000% + 0.00 -nan 0.00 -nan + +MLC_PREF_HIT 0 0 + +MLC_PREF_UNIQUE_HIT 0 0 + +MLC_PREF_LATE 0 0 + +PREF_HYBRID_SEL_0 0 -nan% 0 -nan% +PREF_HYBRID_SEL_1 0 -nan% 0 -nan% +PREF_HYBRID_SEL_2 0 -nan% 0 -nan% +PREF_HYBRID_SEL_3 0 -nan% 0 -nan% +PREF_HYBRID_SEL_4 0 -nan% 0 -nan% +PREF_HYBRID_SEL_5 0 -nan% 0 -nan% +PREF_HYBRID_SEL_6 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_DISTANCE_1 0 -nan% 0 -nan% +PREF_DISTANCE_2 0 -nan% 0 -nan% +PREF_DISTANCE_3 0 -nan% 0 -nan% +PREF_DISTANCE_4 0 -nan% 0 -nan% +PREF_DISTANCE_5 0 -nan% 0 -nan% +PREF_DISTANCE_6 0 -nan% 0 -nan% +PREF_DISTANCE_7 0 -nan% 0 -nan% +PREF_DISTANCE_8 0 -nan% 0 -nan% +PREF_DISTANCE_9 0 -nan% 0 -nan% +PREF_DISTANCE_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_REPL_MRU 0 -nan% 0 -nan% +PREF_REPL_MID 0 -nan% 0 -nan% +PREF_REPL_LOWQTR 0 -nan% 0 -nan% +PREF_REPL_LRU 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_REPL_MOVEDOWN 0 -nan% 0 -nan% +PREF_REPL_MOVEUP 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_COV_1 0 -nan% 0 -nan% +PREF_COV_2 0 -nan% 0 -nan% +PREF_COV_3 0 -nan% 0 -nan% +PREF_COV_4 0 -nan% 0 -nan% +PREF_COV_5 0 -nan% 0 -nan% +PREF_COV_6 0 -nan% 0 -nan% +PREF_COV_7 0 -nan% 0 -nan% +PREF_COV_8 0 -nan% 0 -nan% +PREF_COV_9 0 -nan% 0 -nan% +PREF_COV_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_POL_1 0 -nan% 0 -nan% +PREF_POL_2 0 -nan% 0 -nan% +PREF_POL_3 0 -nan% 0 -nan% +PREF_POL_4 0 -nan% 0 -nan% +PREF_POL_5 0 -nan% 0 -nan% +PREF_POL_6 0 -nan% 0 -nan% +PREF_POL_7 0 -nan% 0 -nan% +PREF_POL_8 0 -nan% 0 -nan% +PREF_POL_9 0 -nan% 0 -nan% +PREF_POL_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_ACC_1 0 -nan% 0 -nan% +PREF_ACC_2 0 -nan% 0 -nan% +PREF_ACC_3 0 -nan% 0 -nan% +PREF_ACC_4 0 -nan% 0 -nan% +PREF_ACC_5 0 -nan% 0 -nan% +PREF_ACC_6 0 -nan% 0 -nan% +PREF_ACC_7 0 -nan% 0 -nan% +PREF_ACC_8 0 -nan% 0 -nan% +PREF_ACC_9 0 -nan% 0 -nan% +PREF_ACC_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_TIMELY_1 0 -nan% 0 -nan% +PREF_TIMELY_2 0 -nan% 0 -nan% +PREF_TIMELY_3 0 -nan% 0 -nan% +PREF_TIMELY_4 0 -nan% 0 -nan% +PREF_TIMELY_5 0 -nan% 0 -nan% +PREF_TIMELY_6 0 -nan% 0 -nan% +PREF_TIMELY_7 0 -nan% 0 -nan% +PREF_TIMELY_8 0 -nan% 0 -nan% +PREF_TIMELY_9 0 -nan% 0 -nan% +PREF_TIMELY_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_UNUSED_EVICT 0 0 + +PREF_REGION_SENT 0 0 + +PREF_REGION_USEFUL 0 0 + +PREF_REGION_EVICT 0 0 + +PREF_PFPOL 0 0 + +PREF_PHASE_NEWPHASE_DET 0 0 + +PREF_PHASE_NEWPHASE_NOTVALID 0 0 + +PREF_PHASE_SENTPREF 0 0 + +PREF_PHASE_OVERWRITE_PAGE 0 0 + +PREF_UPDATE_COUNT 0 0 + +PREF_ACC1_HT_HP 0 -nan% 0 -nan% +PREF_ACC1_HT_LP 0 -nan% 0 -nan% +PREF_ACC1_LT_HP 0 -nan% 0 -nan% +PREF_ACC1_LT_LP 0 -nan% 0 -nan% +PREF_ACC2_HT_HP 0 -nan% 0 -nan% +PREF_ACC2_HT_LP 0 -nan% 0 -nan% +PREF_ACC2_LT_HP 0 -nan% 0 -nan% +PREF_ACC2_LT_LP 0 -nan% 0 -nan% +PREF_ACC3_HT_HP 0 -nan% 0 -nan% +PREF_ACC3_HT_LP 0 -nan% 0 -nan% +PREF_ACC3_LT_HP 0 -nan% 0 -nan% +PREF_ACC3_LT_LP 0 -nan% 0 -nan% +PREF_ACC4_HT_HP 0 -nan% 0 -nan% +PREF_ACC4_HT_LP 0 -nan% 0 -nan% +PREF_ACC4_LT_HP 0 -nan% 0 -nan% +PREF_ACC4_LT_LP 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + + + diff --git a/labs/LAB5/runs/specrand_i-sms0/ramulator.stat.out b/labs/LAB5/runs/specrand_i-sms0/ramulator.stat.out new file mode 100644 index 00000000..446806b1 --- /dev/null +++ b/labs/LAB5/runs/specrand_i-sms0/ramulator.stat.out @@ -0,0 +1,150 @@ + ramulator.active_cycles_0 9073 # Total active cycles for level _0 + ramulator.busy_cycles_0 9073 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0 + ramulator.serving_requests_0 11370 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.average_serving_requests_0 0.000806 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.active_cycles_0_0 9073 # Total active cycles for level _0_0 + ramulator.busy_cycles_0_0 641593 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0 + ramulator.serving_requests_0_0 11370 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.average_serving_requests_0_0 0.000806 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.active_cycles_0_0_0 3111 # Total active cycles for level _0_0_0 + ramulator.busy_cycles_0_0_0 3111 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0 + ramulator.serving_requests_0_0_0 3515 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 +ramulator.average_serving_requests_0_0_0 0.000249 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 + ramulator.active_cycles_0_0_0_0 805 # Total active cycles for level _0_0_0_0 + ramulator.busy_cycles_0_0_0_0 805 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_0 + ramulator.serving_requests_0_0_0_0 976 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 +ramulator.average_serving_requests_0_0_0_0 0.000069 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 + ramulator.active_cycles_0_0_0_1 344 # Total active cycles for level _0_0_0_1 + ramulator.busy_cycles_0_0_0_1 344 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_1 + ramulator.serving_requests_0_0_0_1 344 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 +ramulator.average_serving_requests_0_0_0_1 0.000024 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 + ramulator.active_cycles_0_0_0_2 352 # Total active cycles for level _0_0_0_2 + ramulator.busy_cycles_0_0_0_2 352 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_2 + ramulator.serving_requests_0_0_0_2 352 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 +ramulator.average_serving_requests_0_0_0_2 0.000025 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 + ramulator.active_cycles_0_0_0_3 1773 # Total active cycles for level _0_0_0_3 + ramulator.busy_cycles_0_0_0_3 1773 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_3 + ramulator.serving_requests_0_0_0_3 1843 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 +ramulator.average_serving_requests_0_0_0_3 0.000131 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 + ramulator.active_cycles_0_0_1 1000 # Total active cycles for level _0_0_1 + ramulator.busy_cycles_0_0_1 1000 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1 + ramulator.serving_requests_0_0_1 1000 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 +ramulator.average_serving_requests_0_0_1 0.000071 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 + ramulator.active_cycles_0_0_1_0 0 # Total active cycles for level _0_0_1_0 + ramulator.busy_cycles_0_0_1_0 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_0 + ramulator.serving_requests_0_0_1_0 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 +ramulator.average_serving_requests_0_0_1_0 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 + ramulator.active_cycles_0_0_1_1 328 # Total active cycles for level _0_0_1_1 + ramulator.busy_cycles_0_0_1_1 328 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_1 + ramulator.serving_requests_0_0_1_1 328 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 +ramulator.average_serving_requests_0_0_1_1 0.000023 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 + ramulator.active_cycles_0_0_1_2 672 # Total active cycles for level _0_0_1_2 + ramulator.busy_cycles_0_0_1_2 672 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_2 + ramulator.serving_requests_0_0_1_2 672 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 +ramulator.average_serving_requests_0_0_1_2 0.000048 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 + ramulator.active_cycles_0_0_1_3 0 # Total active cycles for level _0_0_1_3 + ramulator.busy_cycles_0_0_1_3 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_3 + ramulator.serving_requests_0_0_1_3 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 +ramulator.average_serving_requests_0_0_1_3 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 + ramulator.active_cycles_0_0_2 3812 # Total active cycles for level _0_0_2 + ramulator.busy_cycles_0_0_2 3812 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2 + ramulator.serving_requests_0_0_2 4736 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 +ramulator.average_serving_requests_0_0_2 0.000336 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 + ramulator.active_cycles_0_0_2_0 524 # Total active cycles for level _0_0_2_0 + ramulator.busy_cycles_0_0_2_0 524 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_0 + ramulator.serving_requests_0_0_2_0 652 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 +ramulator.average_serving_requests_0_0_2_0 0.000046 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 + ramulator.active_cycles_0_0_2_1 423 # Total active cycles for level _0_0_2_1 + ramulator.busy_cycles_0_0_2_1 423 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_1 + ramulator.serving_requests_0_0_2_1 428 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 +ramulator.average_serving_requests_0_0_2_1 0.000030 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 + ramulator.active_cycles_0_0_2_2 1893 # Total active cycles for level _0_0_2_2 + ramulator.busy_cycles_0_0_2_2 1893 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_2 + ramulator.serving_requests_0_0_2_2 2512 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 +ramulator.average_serving_requests_0_0_2_2 0.000178 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 + ramulator.active_cycles_0_0_2_3 1144 # Total active cycles for level _0_0_2_3 + ramulator.busy_cycles_0_0_2_3 1144 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_3 + ramulator.serving_requests_0_0_2_3 1144 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 +ramulator.average_serving_requests_0_0_2_3 0.000081 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 + ramulator.active_cycles_0_0_3 1848 # Total active cycles for level _0_0_3 + ramulator.busy_cycles_0_0_3 1848 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3 + ramulator.serving_requests_0_0_3 2119 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 +ramulator.average_serving_requests_0_0_3 0.000150 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 + ramulator.active_cycles_0_0_3_0 452 # Total active cycles for level _0_0_3_0 + ramulator.busy_cycles_0_0_3_0 452 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_0 + ramulator.serving_requests_0_0_3_0 452 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 +ramulator.average_serving_requests_0_0_3_0 0.000032 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 + ramulator.active_cycles_0_0_3_1 603 # Total active cycles for level _0_0_3_1 + ramulator.busy_cycles_0_0_3_1 603 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_1 + ramulator.serving_requests_0_0_3_1 695 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 +ramulator.average_serving_requests_0_0_3_1 0.000049 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 + ramulator.active_cycles_0_0_3_2 360 # Total active cycles for level _0_0_3_2 + ramulator.busy_cycles_0_0_3_2 360 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_2 + ramulator.serving_requests_0_0_3_2 360 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 +ramulator.average_serving_requests_0_0_3_2 0.000026 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 + ramulator.active_cycles_0_0_3_3 516 # Total active cycles for level _0_0_3_3 + ramulator.busy_cycles_0_0_3_3 516 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_3 + ramulator.serving_requests_0_0_3_3 612 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 +ramulator.average_serving_requests_0_0_3_3 0.000043 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 + ramulator.read_transaction_bytes_0 27520 # The total byte of read transaction per channel + ramulator.write_transaction_bytes_0 0 # The total byte of write transaction per channel + ramulator.row_hits_channel_0_core 327 # Number of row hits per channel per core + ramulator.row_misses_channel_0_core 34 # Number of row misses per channel per core + ramulator.row_conflicts_channel_0_core 69 # Number of row conflicts per channel per core + ramulator.read_row_hits_channel_0_core 327 # Number of row hits for read requests per channel per core + [0] 327.0 # +ramulator.read_row_misses_channel_0_core 34 # Number of row misses for read requests per channel per core + [0] 34.0 # +ramulator.read_row_conflicts_channel_0_core 69 # Number of row conflicts for read requests per channel per core + [0] 69.0 # + ramulator.write_row_hits_channel_0_core 0 # Number of row hits for write requests per channel per core + [0] 0.0 # +ramulator.write_row_misses_channel_0_core 0 # Number of row misses for write requests per channel per core + [0] 0.0 # +ramulator.write_row_conflicts_channel_0_core 0 # Number of row conflicts for write requests per channel per core + [0] 0.0 # + ramulator.useless_activates_0_core 0 # Number of useless activations. E.g, ACT -> PRE w/o RD or WR + ramulator.read_latency_avg_0 32.641860 # The average memory latency cycles (in memory time domain) per request for all read requests in this channel + ramulator.read_latency_sum_0 14036 # The memory latency cycles (in memory time domain) sum for all read requests in this channel + ramulator.req_queue_length_avg_0 0.000878 # Average of read and write queue length per memory cycle per channel. + ramulator.req_queue_length_sum_0 12379 # Sum of read and write queue length per memory cycle per channel. + ramulator.read_req_queue_length_avg_0 0.000878 # Read queue length average per memory cycle per channel. + ramulator.read_req_queue_length_sum_0 12379 # Read queue length sum per memory cycle per channel. + ramulator.write_req_queue_length_avg_0 0.000000 # Write queue length average per memory cycle per channel. + ramulator.write_req_queue_length_sum_0 0 # Write queue length sum per memory cycle per channel. + ramulator.record_read_hits 0.0 # record read hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_misses 0.0 # record_read_miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_conflicts 0.0 # record read conflict count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_hits 0.0 # record write hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_misses 0.0 # record write miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_conflicts 0.0 # record write conflict for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.dram_capacity 8589934592 # Number of bytes in simulated DRAM + ramulator.dram_cycles 14100133 # Number of DRAM cycles simulated + ramulator.incoming_requests 430 # Number of incoming requests to DRAM + ramulator.read_requests 430 # Number of incoming read requests to DRAM per core + [0] 430.0 # + ramulator.write_requests 0 # Number of incoming write requests to DRAM per core + [0] 0.0 # + ramulator.ramulator_active_cycles 9073 # The total number of cycles that the DRAM part is active (serving R/W) + ramulator.incoming_requests_per_channel 430.0 # Number of incoming requests to each DRAM channel + [0] 430.0 # +ramulator.incoming_read_reqs_per_channel 430.0 # Number of incoming read requests to each DRAM channel + [0] 430.0 # + ramulator.physical_page_replacement 0 # The number of times that physical page replacement happens. + ramulator.maximum_bandwidth 19200000000 # The theoretical maximum bandwidth (Bps) + ramulator.in_queue_req_num_sum 12379 # Sum of read/write queue length + ramulator.in_queue_read_req_num_sum 12379 # Sum of read queue length + ramulator.in_queue_write_req_num_sum 0 # Sum of write queue length + ramulator.in_queue_req_num_avg 0.000878 # Average of read/write queue length per memory cycle + ramulator.in_queue_read_req_num_avg 0.000878 # Average of read queue length per memory cycle + ramulator.in_queue_write_req_num_avg 0.000000 # Average of write queue length per memory cycle + ramulator.record_read_requests 0.0 # record read requests for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_requests 0.0 # record write requests for this core when it reaches request limit or to the end + [0] 0.0 # diff --git a/labs/LAB5/runs/specrand_i-sms0/run.err b/labs/LAB5/runs/specrand_i-sms0/run.err new file mode 100644 index 00000000..e69de29b diff --git a/labs/LAB5/runs/specrand_i-sms0/run.out b/labs/LAB5/runs/specrand_i-sms0/run.out new file mode 100644 index 00000000..88de4023 --- /dev/null +++ b/labs/LAB5/runs/specrand_i-sms0/run.out @@ -0,0 +1,107 @@ +Scarab gitrev: 7ab9e17 +Scarab started at Sun Jun 11 08:08:38 2023 + +Initialized Ramulator. +** Heartbeat: 1% -- { 1000001 } -- 0.00 KIPS (500.00 KIPS) +** Heartbeat: 2% -- { 2000004 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 3% -- { 3000007 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 4% -- { 4000007 } -- 1000.00 KIPS (571.43 KIPS) +** Heartbeat: 5% -- { 5000009 } -- 500.00 KIPS (555.56 KIPS) +** Heartbeat: 6% -- { 6000012 } -- 500.00 KIPS (545.46 KIPS) +** Heartbeat: 7% -- { 7000015 } -- 1000.00 KIPS (583.33 KIPS) +** Heartbeat: 8% -- { 8000015 } -- 500.00 KIPS (571.43 KIPS) +** Heartbeat: 9% -- { 9000015 } -- 500.00 KIPS (562.50 KIPS) +** Heartbeat: 10% -- { 10000017 } -- 500.00 KIPS (555.56 KIPS) +** Heartbeat: 11% -- { 11000020 } -- 1000.00 KIPS (578.95 KIPS) +** Heartbeat: 12% -- { 12000022 } -- 500.00 KIPS (571.43 KIPS) +** Heartbeat: 13% -- { 13000026 } -- 500.00 KIPS (565.22 KIPS) +** Heartbeat: 14% -- { 14000027 } -- 1000.00 KIPS (583.33 KIPS) +** Heartbeat: 15% -- { 15000027 } -- 500.00 KIPS (576.92 KIPS) +** Heartbeat: 16% -- { 16000031 } -- 500.00 KIPS (571.43 KIPS) +** Heartbeat: 17% -- { 17000035 } -- 500.00 KIPS (566.67 KIPS) +** Heartbeat: 18% -- { 18000035 } -- 1000.00 KIPS (580.65 KIPS) +** Heartbeat: 19% -- { 19000038 } -- 500.00 KIPS (575.76 KIPS) +** Heartbeat: 20% -- { 20000040 } -- 500.00 KIPS (571.43 KIPS) +** Heartbeat: 21% -- { 21000042 } -- 1000.00 KIPS (583.33 KIPS) +** Heartbeat: 22% -- { 22000044 } -- 500.00 KIPS (578.95 KIPS) +** Heartbeat: 23% -- { 23000045 } -- 500.00 KIPS (575.00 KIPS) +** Heartbeat: 24% -- { 24000047 } -- 500.00 KIPS (571.43 KIPS) +** Heartbeat: 25% -- { 25000048 } -- 1000.00 KIPS (581.40 KIPS) +** Heartbeat: 26% -- { 26000049 } -- 500.00 KIPS (577.78 KIPS) +** Heartbeat: 27% -- { 27000052 } -- 500.00 KIPS (574.47 KIPS) +** Heartbeat: 28% -- { 28000054 } -- 1000.00 KIPS (583.33 KIPS) +** Heartbeat: 29% -- { 29000057 } -- 500.00 KIPS (580.00 KIPS) +** Heartbeat: 30% -- { 30000061 } -- 500.00 KIPS (576.92 KIPS) +** Heartbeat: 31% -- { 31000062 } -- 1000.00 KIPS (584.91 KIPS) +** Heartbeat: 32% -- { 32000063 } -- 500.00 KIPS (581.82 KIPS) +** Heartbeat: 33% -- { 33000066 } -- 500.00 KIPS (578.95 KIPS) +** Heartbeat: 34% -- { 34000068 } -- 500.00 KIPS (576.27 KIPS) +** Heartbeat: 35% -- { 35000069 } -- 1000.00 KIPS (583.33 KIPS) +** Heartbeat: 36% -- { 36000070 } -- 500.00 KIPS (580.65 KIPS) +** Heartbeat: 37% -- { 37000074 } -- 500.00 KIPS (578.13 KIPS) +** Heartbeat: 38% -- { 38000075 } -- 1000.00 KIPS (584.62 KIPS) +** Heartbeat: 39% -- { 39000079 } -- 500.00 KIPS (582.09 KIPS) +** Heartbeat: 40% -- { 40000081 } -- 500.00 KIPS (579.71 KIPS) +** Heartbeat: 41% -- { 41000081 } -- 500.00 KIPS (577.47 KIPS) +** Heartbeat: 42% -- { 42000082 } -- 1000.00 KIPS (583.33 KIPS) +** Heartbeat: 43% -- { 43000085 } -- 500.00 KIPS (581.08 KIPS) +** Heartbeat: 44% -- { 44000089 } -- 500.00 KIPS (578.95 KIPS) +** Heartbeat: 45% -- { 45000091 } -- 1000.00 KIPS (584.42 KIPS) +** Heartbeat: 46% -- { 46000096 } -- 500.00 KIPS (582.28 KIPS) +** Heartbeat: 47% -- { 47000098 } -- 500.00 KIPS (580.25 KIPS) +** Heartbeat: 48% -- { 48000098 } -- 500.00 KIPS (578.31 KIPS) +** Heartbeat: 49% -- { 49000103 } -- 1000.00 KIPS (583.33 KIPS) +** Heartbeat: 50% -- { 50000107 } -- 500.00 KIPS (581.40 KIPS) +** Heartbeat: 51% -- { 51000111 } -- 500.00 KIPS (579.55 KIPS) +** Heartbeat: 52% -- { 52000116 } -- 1000.00 KIPS (584.27 KIPS) +** Heartbeat: 53% -- { 53000116 } -- 500.00 KIPS (582.42 KIPS) +** Heartbeat: 54% -- { 54000118 } -- 500.00 KIPS (580.65 KIPS) +** Heartbeat: 55% -- { 55000122 } -- 1000.00 KIPS (585.11 KIPS) +** Heartbeat: 56% -- { 56000123 } -- 500.00 KIPS (583.33 KIPS) +** Heartbeat: 57% -- { 57000125 } -- 500.00 KIPS (581.63 KIPS) +** Heartbeat: 58% -- { 58000125 } -- 500.00 KIPS (580.00 KIPS) +** Heartbeat: 59% -- { 59000130 } -- 1000.00 KIPS (584.16 KIPS) +** Heartbeat: 60% -- { 60000130 } -- 500.00 KIPS (582.53 KIPS) +** Heartbeat: 61% -- { 61000131 } -- 500.00 KIPS (580.95 KIPS) +** Heartbeat: 62% -- { 62000133 } -- 1000.00 KIPS (584.91 KIPS) +** Heartbeat: 63% -- { 63000136 } -- 500.00 KIPS (583.33 KIPS) +** Heartbeat: 64% -- { 64000140 } -- 500.00 KIPS (581.82 KIPS) +** Heartbeat: 65% -- { 65000142 } -- 500.00 KIPS (580.36 KIPS) +** Heartbeat: 66% -- { 66000142 } -- 1000.00 KIPS (584.07 KIPS) +** Heartbeat: 67% -- { 67000146 } -- 500.00 KIPS (582.61 KIPS) +** Heartbeat: 68% -- { 68000149 } -- 500.00 KIPS (581.20 KIPS) +** Heartbeat: 69% -- { 69000153 } -- 500.00 KIPS (579.83 KIPS) +** Heartbeat: 70% -- { 70000157 } -- 1000.00 KIPS (583.33 KIPS) +** Heartbeat: 71% -- { 71000157 } -- 500.00 KIPS (581.97 KIPS) +** Heartbeat: 72% -- { 72000157 } -- 500.00 KIPS (580.65 KIPS) +** Heartbeat: 73% -- { 73000159 } -- 500.00 KIPS (579.37 KIPS) +** Heartbeat: 74% -- { 74000162 } -- 1000.00 KIPS (582.68 KIPS) +** Heartbeat: 75% -- { 75000163 } -- 500.00 KIPS (581.40 KIPS) +** Heartbeat: 76% -- { 76000165 } -- 500.00 KIPS (580.15 KIPS) +** Heartbeat: 77% -- { 77000165 } -- 500.00 KIPS (578.95 KIPS) +** Heartbeat: 78% -- { 78000168 } -- 1000.00 KIPS (582.09 KIPS) +** Heartbeat: 79% -- { 79000172 } -- 500.00 KIPS (580.88 KIPS) +** Heartbeat: 80% -- { 80000174 } -- 500.00 KIPS (579.71 KIPS) +** Heartbeat: 81% -- { 81000174 } -- 500.00 KIPS (578.57 KIPS) +** Heartbeat: 82% -- { 82000176 } -- 1000.00 KIPS (581.56 KIPS) +** Heartbeat: 83% -- { 83000176 } -- 500.00 KIPS (580.42 KIPS) +** Heartbeat: 84% -- { 84000176 } -- 500.00 KIPS (579.31 KIPS) +** Heartbeat: 85% -- { 85000176 } -- 500.00 KIPS (578.23 KIPS) +** Heartbeat: 86% -- { 86000177 } -- 1000.00 KIPS (581.08 KIPS) +** Heartbeat: 87% -- { 87000182 } -- 500.00 KIPS (580.00 KIPS) +** Heartbeat: 88% -- { 88000187 } -- 500.00 KIPS (578.95 KIPS) +** Heartbeat: 89% -- { 89000189 } -- 500.00 KIPS (577.92 KIPS) +** Heartbeat: 90% -- { 90000189 } -- 1000.00 KIPS (580.65 KIPS) +** Heartbeat: 91% -- { 91000191 } -- 500.00 KIPS (579.62 KIPS) +** Heartbeat: 92% -- { 92000194 } -- 500.00 KIPS (578.62 KIPS) +** Heartbeat: 93% -- { 93000195 } -- 500.00 KIPS (577.64 KIPS) +** Heartbeat: 94% -- { 94000195 } -- 1000.00 KIPS (580.25 KIPS) +** Heartbeat: 95% -- { 95000199 } -- 500.00 KIPS (579.27 KIPS) +** Heartbeat: 96% -- { 96000202 } -- 500.00 KIPS (578.31 KIPS) +** Heartbeat: 97% -- { 97000205 } -- 1000.00 KIPS (580.84 KIPS) +** Heartbeat: 98% -- { 98000207 } -- 500.00 KIPS (579.88 KIPS) +** Heartbeat: 99% -- { 99000207 } -- 500.00 KIPS (578.95 KIPS) +** Core 0 Finished: insts:100000004 cycles:37600340 time:11750106250000 -- 2.66 IPC (2.66 IPC) -- N/A KIPS (578.03 KIPS) +done +Scarab finished at Sun Jun 11 08:11:31 2023 + diff --git a/labs/LAB5/runs/specrand_i-sms0/stream.stat.0.out b/labs/LAB5/runs/specrand_i-sms0/stream.stat.0.out new file mode 100644 index 00000000..7558b0ec --- /dev/null +++ b/labs/LAB5/runs/specrand_i-sms0/stream.stat.0.out @@ -0,0 +1,188 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 37600340 Instructions: 100000004 IPC: 2.65955 + +DCACHE_PREF_HIT 0 0 + +IFETCH_WB_FIRST_SCHEDULE 0 -nan% 0 -nan% +PREFETCH_LAST_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_PREF_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_LOW_OP_SCHEDULE 0 -nan% 0 -nan% +DEMAND_LAST_SCHEDULE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +SEND_MISS_REQ_QUEUE 430 430 + +L1_DATA_EVICT 0 0 + +STREAM_BUFFER_REQ 0 0 + +PREF_SEND_TO_MEM_REQ 0 -nan% 0 -nan% +PREF_SEND_TO_MEM_REQ_FAIL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +HIT_TRAIN_STREAM 83 52.866% 83 52.866% +MISS_TRAIN_STREAM 74 47.134% 74 47.134% + 157 100.000% 157 100.000% + 0.47 0.49 0.47 0.49 + +STREAM_TRAIN_CREATE 31 31 + +MEM_REQ_MISS_HWP_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_SW_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_IFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DSTORE_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DPRF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_WB_Q 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_BY_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_WB 0 -nan% 0 -nan% +PREF_HIT_BY_PREF 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_WB 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_L1_FILL 0 -nan% 0 -nan% +DEMAND_L1_FILL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TOUCH_L1_REPLACE 0 -nan% 0 -nan% +NO_TOUCH_L1_REPLACE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_REQ_QUE_FULL 0 0 + +STREAM_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +L2HIT_STREAM_PREF_REQ_QUE_FULL 0 0 + +L2HIT_HIT_TRAIN_STREAM 0 -nan% 0 -nan% +L2HIT_MISS_TRAIN_STREAM 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_TRAIN_CREATE 0 0 + +L2HIT_STREAM_BUFFER_REQ 0 0 + +L2HIT_STREAM_PREF_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_STREAM_PREF_DCACHE_INSERT 0 -nan% 0 -nan% +L2HIT_STREAM_L2_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_DCACHE_PORT_FULL 0 0 + +L2HIT_STREAM_PREF_L1_PORT_FULL 0 0 + +L2HIT_TRAIN_HIT_DEMAND 0 -nan% 0 -nan% +L2HIT_TRAIN_MISS_REQ 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_TRAIN_FILTER_MISS 0 -nan% 0 -nan% +L2HIT_TRAIN_FILTER_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_PREF_REQ_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_PREF_REQ_DCACHE_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_L2SEND_Q_FULL 0 -nan% 0 -nan% +L2HIT_L2SEND_Q_ENTER 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_MEM_REQ 0 0 + +REMOVE_REDUNDANT_STREAM_STAT 0 0 + +REPLACE_OLD_STREAM 15 15 + +REQ_SEND_QUEUE_STALL 0 0 + +STREAM_ENTER_RA 0 0 + +CORE_STREAM_LENGTH_0 3 37.500% 3 37.500% +CORE_STREAM_LENGTH_10 3 37.500% 3 37.500% +CORE_STREAM_LENGTH_20 0 0.000% 0 0.000% +CORE_STREAM_LENGTH_30 0 0.000% 0 0.000% +CORE_STREAM_LENGTH_40 1 12.500% 1 12.500% +CORE_STREAM_LENGTH_50 0 0.000% 0 0.000% +CORE_STREAM_LENGTH_60 1 12.500% 1 12.500% +CORE_STREAM_LENGTH_70 0 0.000% 0 0.000% +CORE_STREAM_LENGTH_80 0 0.000% 0 0.000% +CORE_STREAM_LENGTH_90 0 0.000% 0 0.000% +CORE_STREAM_LENGTH_100_P 0 0.000% 0 0.000% + 8 100.000% 8 100.000% + 1.62 1.93 1.62 1.93 + +CORE_CUM_STREAM_LENGTH_0 17 10.241% 17 10.241% +CORE_CUM_STREAM_LENGTH_10 41 24.699% 41 24.699% +CORE_CUM_STREAM_LENGTH_20 0 0.000% 0 0.000% +CORE_CUM_STREAM_LENGTH_30 0 0.000% 0 0.000% +CORE_CUM_STREAM_LENGTH_40 48 28.916% 48 28.916% +CORE_CUM_STREAM_LENGTH_50 0 0.000% 0 0.000% +CORE_CUM_STREAM_LENGTH_60 60 36.145% 60 36.145% +CORE_CUM_STREAM_LENGTH_70 0 0.000% 0 0.000% +CORE_CUM_STREAM_LENGTH_80 0 0.000% 0 0.000% +CORE_CUM_STREAM_LENGTH_90 0 0.000% 0 0.000% +CORE_CUM_STREAM_LENGTH_100_P 0 0.000% 0 0.000% + 166 100.000% 166 100.000% + 3.57 1.96 3.57 1.96 + +CORE_STREAM_TRAIN_HITS_0 6 75.000% 6 75.000% +CORE_STREAM_TRAIN_HITS_10 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_20 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_30 1 12.500% 1 12.500% +CORE_STREAM_TRAIN_HITS_40 1 12.500% 1 12.500% +CORE_STREAM_TRAIN_HITS_50 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_60 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_70 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_80 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_90 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_100_P 0 0.000% 0 0.000% + 8 100.000% 8 100.000% + 0.88 1.43 0.88 1.43 + +CORE_CUM_STREAM_TRAIN_HITS_0 39 33.913% 39 33.913% +CORE_CUM_STREAM_TRAIN_HITS_10 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_20 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_30 32 27.826% 32 27.826% +CORE_CUM_STREAM_TRAIN_HITS_40 44 38.261% 44 38.261% +CORE_CUM_STREAM_TRAIN_HITS_50 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_60 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_70 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_80 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_90 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_100_P 0 0.000% 0 0.000% + 115 100.000% 115 100.000% + 2.37 1.07 2.37 1.07 + +CORE_STREAM_TRAIN_CREATE 31 31 + + + diff --git a/labs/LAB5/runs/specrand_i-sms1/PARAMS.in b/labs/LAB5/runs/specrand_i-sms1/PARAMS.in new file mode 100644 index 00000000..2593c2b8 --- /dev/null +++ b/labs/LAB5/runs/specrand_i-sms1/PARAMS.in @@ -0,0 +1,226 @@ +# File : PARAMS.kaby_lake +# Date : 03/06/19 +# Description : Kaby Lake Configuration +# +# Based on documentation found here: +# https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake + +## Simulation Parameters +--mode full +--model cmp +--sim_limit none + +## Core Parameters + +# Femptoseconds, 3.2GHz, used for energy estimates. +--chip_cycle_time 312500 + + +### Fetch Stage +--fetch_off_path_ops 1 +--fetch_across_cache_lines 1 + +# Will break the packet upon a taken branch. +--fetch_break_on_taken 1 + +# Number of bubble cycles to wait after taken branch. +--fetch_taken_bubble_cycles 0 + + +#### ICache +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 + +### Branch Predictor +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_mech tagescl + + +#### BTB + +# BTB model to use. +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 + +# Allow the BTB to be updated by off path ops. +--btb_off_path_writes 1 + + +#### CRS + +# Enable return stack +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 + +### iBP +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged + # iBTB Model. tc_tagless, tc_tagged, tc_hybrid. +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 + +### Decode Stage +--decode_cycles 5 + + +### Map Stage +--map_cycles 5 + + +### Issue Stage + +# Max number of instructions to be fetched, decoded, renamed, and issued per cycle. +--issue_width 6 + +--rs_fill_width 0 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 + + +### Exec Stage + +### DCache +--dcache_size 32768 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--dcache_assoc 4 +--dcache_line_size 64 + +### Reorder/Retire Stage + +# Max number of instructions to be retired per cycle. +--node_ret_width 6 +--node_table_size 224 + +# Do not keep stores in RSVs on cache misses; TODO: confirm what this knob does +--stores_do_not_block_window 1 + +# TODO: confirm what this knob does +--prefs_do_not_block_window 1 + + +## Uncore + +### Mid-level cache + +# Enable use of a midlevel cache between i/d and L1 +--mlc_present 0 + +### LLC +--l1_size 1048576 +--l1_banks 1 +--l1_cycles 18 +--l1_assoc 8 +--l1_line_size 64 +--l1_interleave_factor 64 + + +### Prefetcher +--pref_framework_on 1 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--pref_shared_queues 0 +--pref_train_on_pref_misses 0 +--pref_oracle_train 0 +--pref_ul1req_queue_overwrite_on_full 1 + +--stream_length 64 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 + +--pref_throttlefb_on=1 +--pref_acc_thresh_1=0.75 +--pref_acc_thresh_2=0.4 +--pref_acc_thresh_3=0.4 +--pref_timely_thresh=0.01 +--pref_polpf_thresh=0.005 +--pref_update_interval=8192 + +--mem_req_buffer_pref_watermark 4 +--promote_to_higher_priority_mem_req_type 1 + +### Memory +--addr_translation random + +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 + +--mem_req_buffer_entries 32 +--mem_l1_fill_queue_entries 32 +--va_page_size_bytes 4096 +--bus_width_in_bytes 8 + +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 + +## Other + + +### Debug +--debug_inst_start 0 +--debug_inst_stop -1 +--debug_cycle_start 0 +--debug_cycle_stop -1 + + +## Stats and Params +--dump_params 1 +--dump_stats 1 +--dump_trace 0 + +#################################### +--set_off_path_confirmed 1 + +--order_beyond_bus 1 + +--mem_ooo_stores 1 +--mem_obey_store_dep 1 diff --git a/labs/LAB5/runs/specrand_i-sms1/PARAMS.out b/labs/LAB5/runs/specrand_i-sms1/PARAMS.out new file mode 100644 index 00000000..0a8f0a6f --- /dev/null +++ b/labs/LAB5/runs/specrand_i-sms1/PARAMS.out @@ -0,0 +1,908 @@ +--mode full +--model cmp +--frontend memtrace +--inst_limit 100000000 +--sim_limit none +--dump_params 1 +--dump_stats 1 +--dump_trace 0 +--mlc_present 0 +--l1_size 1048576 +--l1_assoc 8 +--l1_line_size 64 +--l1_cycles 18 +--l1_banks 1 +--l1_interleave_factor 64 +--va_page_size_bytes 4096 +--addr_translation random +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 +--dcache_size 32768 +--dcache_assoc 4 +--dcache_line_size 64 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--mem_ooo_stores 1 +--mem_obey_store_dep 1 +--mem_req_buffer_entries 32 +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 +--promote_to_higher_priority_mem_req_type 1 +--mem_req_buffer_pref_watermark 4 +--mem_l1_fill_queue_entries 32 +--order_beyond_bus 1 +--set_off_path_confirmed 1 +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--bus_width_in_bytes 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 +--chip_cycle_time 312500 +--issue_width 6 +--rs_fill_width 0 +--node_table_size 224 +--node_ret_width 6 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 +--decode_cycles 5 +--map_cycles 5 +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--fetch_across_cache_lines 1 +--fetch_off_path_ops 0 +--fetch_break_on_taken 1 +--fetch_taken_bubble_cycles 0 +--stores_do_not_block_window 1 +--prefs_do_not_block_window 1 +--cbp_trace_r0 /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir/trace/drmemtrace.specrand_i.553922.2837.trace.gz +--memtrace_modules_log /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir/raw +--debug_cycle_start 0 +--debug_cycle_stop -1 +--debug_inst_start 0 +--debug_inst_stop -1 +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--bp_mech tagescl +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 +--btb_off_path_writes 1 +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_length 64 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 +--pref_framework_on 1 +--pref_shared_queues 0 +--pref_ul1req_queue_overwrite_on_full 1 +--pref_train_on_pref_misses 0 +--pref_oracle_train_on 0 +--pref_throttlefb_on 1 +--pref_acc_thresh_1 0.75 +--pref_acc_thresh_2 0.4 +--pref_acc_thresh_3 0.4 +--pref_update_interval 8192 +--pref_timely_thresh 0.01 +--pref_polpf_thresh 0.005 +--pref_sms_on 1 +1 1 1 1 1 1 1 + +--- Cut out everything below to use this file as PARAMS.in --- + +Parameter status at compile time and values supplied on the command line: + +SIM_MODE 0 full +SIM_MODEL 0 cmp +FRONTEND FE_PIN_EXEC_DRIVEN memtrace +INST_LIMIT NULL 100000000 +SIM_LIMIT "none" none +FORWARD_PROGRESS_LIMIT 100000000 +FORWARD_PROGRESS_INTERVAL 10000 +FAST_FORWARD 0 +FAST_FORWARD_UNTIL_ADDR 0 +FAST_FORWARD_TRACE_INS 0 +WARMUP 0 +HEARTBEAT_INTERVAL 1000000 +NUM_HEARTBEATS 0 +FILE_TAG "" +OUTPUT_DIR "." +STATUS_FILE NULL +BINDIR NULL +DUMP_PARAMS TRUE 1 +DUMP_STATS TRUE 1 +DUMP_TRACE FALSE 0 +CLEAR_STATS "never" +STATS_TO_TRACE NULL +STAT_TRACE_FILE "stats.trace" +STAT_TRACE_INTERVAL "i:100000" +PIPEVIEW FALSE +PIPEVIEW_FILE "pipeview" +MEMVIEW FALSE +MEMVIEW_FILE "memview.out" +MEMVIEW_START "never" +INST_HASH_TABLE_SIZE 500021 const +STDOUT_FILE NULL +STDERR_FILE NULL +PIN_EXEC_DRIVEN_FE_SOCKET "./pin_exec_driven_fe_socket.temp" +PRINT_PID FALSE +USE_UNSURE_FREE_LISTS FALSE +OPTIMIZER2_MAX_NUM_SLAVES 64 +OPTIMIZER2_PERFECT_MEMORYLESS FALSE +EXIT_COND 0 +ENABLE_SWPRF FALSE +MLC_PRESENT FALSE 0 +MLC_SIZE (512 * 1024) +MLC_ASSOC 4 +MLC_LINE_SIZE 64 +MLC_CYCLES 12 +PERFECT_MLC FALSE +MLC_READ_PORTS 1 +MLC_WRITE_PORTS 1 +MLC_BANKS 8 +MLC_INTERLEAVE_FACTOR 64 +MLC_CACHE_REPL_POLICY 0 +MLC_WRITE_THROUGH FALSE +PREFETCH_UPDATE_LRU_MLC TRUE +FORCE_L1_MISS FALSE +L1_SIZE (4 * 1024 * 1024) 1048576 +L1_ASSOC 8 8 +L1_LINE_SIZE 64 64 +L1_CYCLES 24 18 +PERFECT_L1 FALSE +PRIVATE_L1 FALSE +L1_READ_PORTS 1 +L1_WRITE_PORTS 1 +L1_BANKS 8 1 +L1_INTERLEAVE_FACTOR 64 64 +L1_CACHE_REPL_POLICY 0 +L1_WRITE_THROUGH FALSE +L1_IGNORE_WB FALSE +L1_USE_CORE_FREQ FALSE +MARK_L1_MISSES TRUE +PREFETCH_UPDATE_LRU_L1 TRUE +MEMORY_RANDOM_ADDR FALSE +VA_PAGE_SIZE_BYTES 4096 4096 +NUM_ADDR_NON_SIGN_EXTEND_BITS 48 +ADDR_TRANSLATION 0 random +CONSTANT_MEMORY_LATENCY FALSE +MEMORY_CYCLES 100 +STALL_MEM_REQS_ONLY FALSE +ICACHE_SIZE (64 * 1024) 32768 +ICACHE_ASSOC 4 4 +ICACHE_LINE_SIZE 64 64 +PERFECT_ICACHE FALSE +ICACHE_READ_PORTS 2 +ICACHE_WRITE_PORTS 1 +ICACHE_BANKS 8 +ICACHE_REPL 0 +DCACHE_SIZE (64 * 1024) 32768 +DCACHE_ASSOC 1 4 +DCACHE_LINE_SIZE 64 64 +DCACHE_CYCLES 2 +PERFECT_DCACHE FALSE +DCACHE_READ_PORTS 8 2 +DCACHE_WRITE_PORTS 1 1 +DCACHE_BANKS 1 1 +DCACHE_REPL 0 +DCACHE_REPL_PREF_THRESH 1 +MEM_OOO_STORES TRUE 1 +MEM_OBEY_STORE_DEP TRUE 1 +PREF_INSERT_LRU FALSE +PREF_INSERT_MIDDLE FALSE +PREF_INSERT_LOWQTR FALSE +PREF_INSERT_DYNACC FALSE +MEM_REQ_BUFFER_ENTRIES 32 32 +PRIVATE_MSHR_ON TRUE +MEM_PRIORITY_IFETCH 0 0 +MEM_PRIORITY_DFETCH 0 1 +MEM_PRIORITY_DSTORE 0 2 +MEM_PRIORITY_IPRF 9 3 +MEM_PRIORITY_DPRF 10 4 +MEM_PRIORITY_WB 0 5 +MEM_PRIORITY_WB_NODIRTY 0 5 +PROMOTE_TO_HIGHER_PRIORITY_MEM_REQ_TYPE FALSE 1 +MEM_REQ_BUFFER_PREF_WATERMARK 0 4 +MEM_REQ_BUFFER_WB_VALVE 2 +MEM_L1_FILL_QUEUE_ENTRIES 32 32 +MEM_BUS_OUT_QUEUE_PARTITION_ENABLE FALSE +MEM_MEM_QUEUE_PARTITION_ENABLE FALSE +MEM_BUS_OUT_QUEUE_AS_FIFO TRUE +OLDEST_FIRST_TO_MEM_QUEUE TRUE +ROUND_ROBIN_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE_TH 0 +L1_CYCLE_TIME 312500 +MLCQ_TO_L1Q_TRANSFER_LATENCY 1 +L1Q_TO_FSB_TRANSFER_LATENCY 1 +PRIORITIZE_PREFETCHES_WITH_UNIQUE FALSE +KICKOUT_PREFETCHES FALSE +KICKOUT_LOOK_FOR_OLDEST_FIRST FALSE +KICKOUT_OLDEST_PREFETCH FALSE +KICKOUT_OLDEST_PREFETCH_WITHIN_BANK FALSE +ORDER_BEYOND_BUS FALSE 1 +ALL_FIFO_QUEUES FALSE +QUEUE_MLC_SIZE 0 +QUEUE_L1_SIZE 0 +QUEUE_BUS_OUT_SIZE 0 +QUEUE_CORE_FILL_SIZE 0 +ALLOW_TYPE_MATCHES FALSE +STREAM_PREFETCH_ON FALSE +DC_PREF_CACHE_ENABLE FALSE +DC_PREF_CACHE_CYCLE 0 +PREF_INSERT_DCACHE_IMM TRUE +DC_PREF_CACHE_SIZE (64 * 1024) +DC_PREF_CACHE_ASSOC 4 +DC_PREF_ONLY_L1HIT FALSE +PREF_CACHE_USE_RDY_CYCLE FALSE +IC_PREF_CACHE_ENABLE FALSE +IC_PREF_CACHE_SIZE (64 * 1024) +IC_PREF_CACHE_ASSOC 4 +L1_PREF_CACHE_ENABLE FALSE +L1_PREF_CACHE_SIZE (1024 * 1024) +L1_PREF_CACHE_ASSOC 8 +SET_OFF_PATH_CONFIRMED FALSE 1 +USE_CONFIRMED_OFF FALSE +PREFCACHE_MOVE_OFFPATH FALSE +CACHE_STAT_ENABLE FALSE +PREF_DCACHE_HIT_FILL_L1 TRUE +PREF_ICACHE_HIT_FILL_L1 TRUE +CRITICAL_ACCESS_PLOT_ENABLE FALSE +CRITICAL_ACCESS_PLOT_FILE "critical_access_plot.dat" +ROUND_ROBIN_TO_L1 FALSE +PREF_I_TOGETHER FALSE +ONE_MORE_CACHE_LINE_ENABLE FALSE +L1_STATIC_PARTITION_ENABLE 0 +L1_STATIC_PARTITION NULL +L1_DYNAMIC_PARTITION_ENABLE FALSE +L1_DYNAMIC_PARTITION_POLICY 0 +PARTITION_UMON_DSS_PREF_ENABLE FALSE +L1_CACHE_HIT_POSITION_COLLECT FALSE +L1_PART_ON FALSE +L1_PART_TRIGGER "c:1000000" +L1_PART_START "t:0" +L1_PART_WARMUP FALSE +L1_PART_SHADOW_WARMUP FALSE +L1_PART_METRIC 0 +L1_PART_SEARCH 0 +L1_PART_USE_STALLING TRUE +L1_PART_FILL_DELAY 0 +L1_SHADOW_TAGS_MODULO 1 +HIER_MSHR_ON FALSE +PERF_PRED_ENABLE FALSE +PERF_PRED_MECH PERF_PRED_CP +PERF_PRED_REQ_LATENCY_MECH PERF_PRED_REQ_LATENCY_MECH_REQ_LATENCY +PERF_PRED_COUNT_ALL FALSE +PERF_PRED_COUNT_INST_MISSES TRUE +PERF_PRED_COUNT_PREFETCHES FALSE +PERF_PRED_COUNT_OFFPATH_REQS FALSE +PERF_PRED_COUNT_BW_REQS TRUE +PERF_PRED_UPDATE_MEM_REQ_TYPE FALSE +PERF_PRED_SLACK_PERIOD_SIZE 32 +PERF_PRED_REQS_FINISH_AT_FILL FALSE +PERF_PRED_MEM_UTIL_VIA_BUS_BW FALSE +PERF_PRED_CHIP_UTIL_VIA_MEM_STALL FALSE +DUMB_MODEL_AVG_REQ_DISTANCE 100 +DUMB_MODEL_RANDOMIZE_DISTANCE FALSE +DUMB_MODEL_AVG_REQ_DISTANCE_PER_CORE NULL +DUMB_MODEL_AVG_ROW_HITS 1 +DUMB_MODEL_AVG_ROW_HITS_PER_CORE NULL +DUMB_MODEL_MLP 1 +DUMB_MODEL_MLP_PER_CORE NULL +RAMULATOR_STANDARD "DDR4" DDR4 +RAMULATOR_SPEED "DDR4_2400R" DDR4_2400R +RAMULATOR_ORG "DDR4_8Gb_x8" DDR4_8Gb_x8 +RAMULATOR_CHANNELS 1 1 +RAMULATOR_RANKS 1 1 +RAMULATOR_BANKGROUPS 4 4 +RAMULATOR_BANKS 4 4 +RAMULATOR_CHIP_WIDTH 8 8 +BUS_WIDTH_IN_BYTES 8 8 +RAMULATOR_ROWS 65536 65536 +RAMULATOR_COLS 1024 1024 +RAMULATOR_SCHEDULING_POLICY "FRFCFS_Cap" FRFCFS_Cap +RAMULATOR_READQ_ENTRIES 32 32 +RAMULATOR_WRITEQ_ENTRIES 32 32 +RAMULATOR_REC_CMD_TRACE "off" FALSE +RAMULATOR_PRINT_CMD_TRACE "off" FALSE +RAMULATOR_USE_REST_OF_ADDR_AS_ROW_ADDR "on" +RAMULATOR_TCK 833333 833333 +RAMULATOR_TCL 16 16 +RAMULATOR_TCCD 6 6 +RAMULATOR_TCCDS 4 4 +RAMULATOR_TCCDL 6 6 +RAMULATOR_TCWL 12 12 +RAMULATOR_TBL 4 4 +RAMULATOR_TWTR 9 9 +RAMULATOR_TWTRS 3 3 +RAMULATOR_TWTRL 9 9 +RAMULATOR_TRP 16 16 +RAMULATOR_TRPpb 16 16 +RAMULATOR_TRPab 16 16 +RAMULATOR_TRCD 16 16 +RAMULATOR_TRCDR 16 16 +RAMULATOR_TRCDW 16 16 +RAMULATOR_TRAS 39 39 +DRAM_TECH_IN_NM 32 32 +DVFS_ON FALSE +DVFS_METRIC DVFS_METRIC_NUM_ELEMS +DVFS_CONFIGS NULL +DVFS_CONFIG_FILE NULL +DVFS_START "t:0" +DVFS_PERIOD "t:312500000000" +DVFS_LOG TRUE +DVFS_INDIVIDUAL_CORES FALSE +DVFS_CHIP_LEVEL FALSE +DVFS_STATIC NULL +DVFS_FORCE_CONFIG NULL +DVFS_REPLAY_CONFIG_TRACE NULL +DVFS_USE_ORACLE FALSE +DVFS_USE_BW_SHARING FALSE +DVFS_USE_DRAM_SHARING FALSE +DVFS_USE_STALL_TIME FALSE +DVFS_DRAM_SHARING_SOLVER_BIN NULL +DVFS_DRAM_SHARING_SOLVER_STRICT TRUE +DVFS_BW_SHARING_BUS_UTIL_THRESH 0.95 +DVFS_BW_SHARING_MAX_REQS 28.0 +DVFS_BW_SHARING_MAX_RW_COST 0.25 +DVFS_BW_SHARING_NO_PREF_STALL TRUE +DVFS_BW_SHARING_CRIT_STATS TRUE +DVFS_COUNT_L1_ACCESS_STALL FALSE +NUM_CORES 1 +CHIP_CYCLE_TIME 312500 312500 +CORE_0_CYCLE_TIME 312500 +CORE_1_CYCLE_TIME 312500 +CORE_2_CYCLE_TIME 312500 +CORE_3_CYCLE_TIME 312500 +CORE_4_CYCLE_TIME 312500 +CORE_5_CYCLE_TIME 312500 +CORE_6_CYCLE_TIME 312500 +CORE_7_CYCLE_TIME 312500 +CORE_8_CYCLE_TIME 312500 +CORE_9_CYCLE_TIME 312500 +CORE_10_CYCLE_TIME 312500 +CORE_11_CYCLE_TIME 312500 +CORE_12_CYCLE_TIME 312500 +CORE_13_CYCLE_TIME 312500 +CORE_14_CYCLE_TIME 312500 +CORE_15_CYCLE_TIME 312500 +CORE_16_CYCLE_TIME 312500 +CORE_17_CYCLE_TIME 312500 +CORE_18_CYCLE_TIME 312500 +CORE_19_CYCLE_TIME 312500 +CORE_20_CYCLE_TIME 312500 +CORE_21_CYCLE_TIME 312500 +CORE_22_CYCLE_TIME 312500 +CORE_23_CYCLE_TIME 312500 +CORE_24_CYCLE_TIME 312500 +CORE_25_CYCLE_TIME 312500 +CORE_26_CYCLE_TIME 312500 +CORE_27_CYCLE_TIME 312500 +CORE_28_CYCLE_TIME 312500 +CORE_29_CYCLE_TIME 312500 +CORE_30_CYCLE_TIME 312500 +CORE_31_CYCLE_TIME 312500 +CORE_32_CYCLE_TIME 312500 +CORE_33_CYCLE_TIME 312500 +CORE_34_CYCLE_TIME 312500 +CORE_35_CYCLE_TIME 312500 +CORE_36_CYCLE_TIME 312500 +CORE_37_CYCLE_TIME 312500 +CORE_38_CYCLE_TIME 312500 +CORE_39_CYCLE_TIME 312500 +CORE_40_CYCLE_TIME 312500 +CORE_41_CYCLE_TIME 312500 +CORE_42_CYCLE_TIME 312500 +CORE_43_CYCLE_TIME 312500 +CORE_44_CYCLE_TIME 312500 +CORE_45_CYCLE_TIME 312500 +CORE_46_CYCLE_TIME 312500 +CORE_47_CYCLE_TIME 312500 +CORE_48_CYCLE_TIME 312500 +CORE_49_CYCLE_TIME 312500 +CORE_50_CYCLE_TIME 312500 +CORE_51_CYCLE_TIME 312500 +CORE_52_CYCLE_TIME 312500 +CORE_53_CYCLE_TIME 312500 +CORE_54_CYCLE_TIME 312500 +CORE_55_CYCLE_TIME 312500 +CORE_56_CYCLE_TIME 312500 +CORE_57_CYCLE_TIME 312500 +CORE_58_CYCLE_TIME 312500 +CORE_59_CYCLE_TIME 312500 +CORE_60_CYCLE_TIME 312500 +CORE_61_CYCLE_TIME 312500 +CORE_62_CYCLE_TIME 312500 +CORE_63_CYCLE_TIME 312500 +ISSUE_WIDTH 4 6 +RS_FILL_WIDTH 8 0 +NODE_TABLE_SIZE 256 224 +NODE_RET_WIDTH 4 6 +NODE_RETIRE_RATE 10 +RS_SIZES "256" 97 +RS_CONNECTIONS "xF" 0 +FU_TYPES "0, 0, 0, 0" 0 0 0 0 0 0 0 0 +DECODE_CYCLES 1 5 +MAP_CYCLES 1 5 +EXTRA_RECOVERY_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after recovery. +EXTRA_REDIRECT_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after redirect. +EXTRA_CALLSYS_CYCLES 20 const +DIE_ON_CALLSYS FALSE +DIE_ON_RET_STALL_THRESH 0 +DIE_ON_RET_STALL_CORE 0 +DIE_ON_MEM_BLOCK_THRESH 0 +DIE_ON_MEM_BLOCK_CORE 0 +FETCH_ACROSS_CACHE_LINES FALSE 1 +FETCH_OFF_PATH_OPS TRUE 0 +FETCH_BREAK_ON_TAKEN FALSE 1 +FETCH_TAKEN_BUBBLE_CYCLES 0 0 +WP_COLLECT_STATS FALSE +SWITCH_IC_FETCH_ON_RECOVERY TRUE +OP_INV_DELAY 1 +OP_NOP_DELAY 1 +OP_CF_DELAY 1 +OP_MOV_DELAY 1 +OP_CMOV_DELAY 1 +OP_LDA_DELAY 1 +OP_IMEM_DELAY 1 +OP_IADD_DELAY 1 +OP_IMUL_DELAY 3 +OP_IDIV_DELAY -20 +OP_ICMP_DELAY 1 +OP_LOGIC_DELAY 1 +OP_SHIFT_DELAY 1 +OP_FMEM_DELAY 1 +OP_FCVT_DELAY 3 +OP_FADD_DELAY 3 +OP_FMUL_DELAY 5 +OP_FMA_DELAY 5 +OP_FDIV_DELAY -20 +OP_FCMP_DELAY 3 +OP_FCMOV_DELAY 1 +OP_GATHER_DELAY 12 +OP_SCATTER_DELAY 18 +OP_PIPELINED_FAST_DELAY 2 +OP_PIPELINED_MEDIUM_DELAY 5 +OP_PIPELINED_SLOW_DELAY 10 +OP_NOTPIPELINED_MEDIUM_DELAY -5 +OP_NOTPIPELINED_SLOW_DELAY -20 +OP_NOTPIPELINED_VERY_SLOW_DELAY -100 +UNIFORM_OP_DELAY 0 +STALL_ON_WAIT_MEM TRUE +STORES_DO_NOT_BLOCK_WINDOW FALSE 1 +PREFS_DO_NOT_BLOCK_WINDOW FALSE 1 +OBEY_REG_DEP TRUE +OLDEST_FIRST_SCHED FALSE +FIND_EMPTIEST_RS FALSE +TRACK_L1_MISS_DEPS FALSE +CBP_TRACE_R0 NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir/trace/drmemtrace.specrand_i.553922.2837.trace.gz +CBP_TRACE_R1 NULL +CBP_TRACE_R2 NULL +CBP_TRACE_R3 NULL +CBP_TRACE_R4 NULL +CBP_TRACE_R5 NULL +CBP_TRACE_R6 NULL +CBP_TRACE_R7 NULL +CBP_TRACE_R8 NULL +CBP_TRACE_R9 NULL +CBP_TRACE_R10 NULL +CBP_TRACE_R11 NULL +CBP_TRACE_R12 NULL +CBP_TRACE_R13 NULL +CBP_TRACE_R14 NULL +CBP_TRACE_R15 NULL +CBP_TRACE_R16 NULL +CBP_TRACE_R17 NULL +CBP_TRACE_R18 NULL +CBP_TRACE_R19 NULL +CBP_TRACE_R20 NULL +CBP_TRACE_R21 NULL +CBP_TRACE_R22 NULL +CBP_TRACE_R23 NULL +CBP_TRACE_R24 NULL +CBP_TRACE_R25 NULL +CBP_TRACE_R26 NULL +CBP_TRACE_R27 NULL +CBP_TRACE_R28 NULL +CBP_TRACE_R29 NULL +CBP_TRACE_R30 NULL +CBP_TRACE_R31 NULL +CBP_TRACE_R32 NULL +CBP_TRACE_R33 NULL +CBP_TRACE_R34 NULL +CBP_TRACE_R35 NULL +CBP_TRACE_R36 NULL +CBP_TRACE_R37 NULL +CBP_TRACE_R38 NULL +CBP_TRACE_R39 NULL +CBP_TRACE_R40 NULL +CBP_TRACE_R41 NULL +CBP_TRACE_R42 NULL +CBP_TRACE_R43 NULL +CBP_TRACE_R44 NULL +CBP_TRACE_R45 NULL +CBP_TRACE_R46 NULL +CBP_TRACE_R47 NULL +CBP_TRACE_R48 NULL +CBP_TRACE_R49 NULL +CBP_TRACE_R50 NULL +CBP_TRACE_R51 NULL +CBP_TRACE_R52 NULL +CBP_TRACE_R53 NULL +CBP_TRACE_R54 NULL +CBP_TRACE_R55 NULL +CBP_TRACE_R56 NULL +CBP_TRACE_R57 NULL +CBP_TRACE_R58 NULL +CBP_TRACE_R59 NULL +CBP_TRACE_R60 NULL +CBP_TRACE_R61 NULL +CBP_TRACE_R62 NULL +CBP_TRACE_R63 NULL +MEMTRACE_MODULES_LOG NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.specrand_i.553922.3230.dir/raw +DUMB_CORE_ON FALSE +DUMB_CORE 1 +DEBUG_CYCLE_START 0 0 +DEBUG_CYCLE_STOP 0 -1 +DEBUG_TIME_START 0 +DEBUG_TIME_STOP 0 +DEBUG_INST_START 0 0 +DEBUG_INST_STOP 0 -1 +DEBUG_OP_START 0 +DEBUG_OP_STOP 0 +DEBUG_CACHE_LIB FALSE +DEBUG_HASH_LIB FALSE +DEBUG_LIST_LIB FALSE +DEBUG_PORT_LIB FALSE +DEBUG_BUS_LIB FALSE +DEBUG_OP_POOL FALSE +DEBUG_ORACLE FALSE +DEBUG_FRONTEND FALSE +DEBUG_ADDR_TRANS FALSE +DEBUG_BP FALSE +DEBUG_BP_DIR FALSE +DEBUG_BTB FALSE +DEBUG_CRS FALSE +DEBUG_MAP FALSE +DEBUG_MEMORY FALSE +DEBUG_REPLAY FALSE +DEBUG_FREQ FALSE +DEBUG_MODEL FALSE +DEBUG_THREAD FALSE +DEBUG_ICACHE_STAGE FALSE +DEBUG_DECODE_STAGE FALSE +DEBUG_MAP_STAGE FALSE +DEBUG_NODE_STAGE FALSE +DEBUG_EXEC_STAGE FALSE +DEBUG_DCACHE_STAGE FALSE +DEBUG_RETIRED_UOPS FALSE +DEBUG_EXC_INSERTS FALSE +DEBUG_BP_CONF FALSE +DEBUG_ONPATH_CONF FALSE +DEBUG_STREAM FALSE +DEBUG_STREAM_MEM FALSE +DEBUG_WAY FALSE +DEBUG_L2MARKV FALSE +DEBUG_L2L1PREF FALSE +DEBUG_PERF_PRED FALSE +DEBUG_POWER_UTILS FALSE +DEBUG_DVFS FALSE +DEBUG_TRACE_READ FALSE +DEBUG_INST_FIELDS FALSE +DEBUG_OP_FIELDS FALSE +DEBUG_PIN_EXEC_DRIVEN FALSE +DEBUG_CACHE_PART FALSE +DEBUG_OPTIMIZER2 FALSE +DEBUG_PREF FALSE +PERFECT_BP FALSE +PERFECT_BTB FALSE +PERFECT_IBP FALSE +PERFECT_CRS FALSE +PERFECT_CBR_BTB FALSE +PERFECT_NT_BTB FALSE +CFS_PER_CYCLE 3 6 # Number of branches that can be predicted in a single cycle +UPDATE_BP_OFF_PATH FALSE 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +BP_UPDATE_AT_RETIRE FALSE 0 # Update the BP at retire. If false, update at the end of exec. +BP_MECH 0 tagescl +LATE_BP_MECH NUM_BP +LATE_BP_LATENCY 5 +HIST_LENGTH 16 +PHT_CTR_BITS 2 const +BHT_ENTRIES (4 * 1024) +BHT_ASSOC 4 +HYBRIDS_INDEX_LENGTH 16 +HYBRIDG_HIST_LENGTH 16 +HYBRIDP_HIST_LENGTH 16 +FILTER_INDEX_LENGTH 16 +USE_FILTER FALSE +INF_HYBRIDGP FALSE +BP_HASH_TOS FALSE +IBTB_HASH_TOS FALSE +BTB_MECH 0 generic +BTB_ENTRIES (4 * 1024) 4096 +BTB_ASSOC 4 4 +BTB_OFF_PATH_WRITES TRUE 1 +ENABLE_CRS TRUE 1 +CRS_ENTRIES 32 32 +CRS_REALISTIC 0 1 +ENABLE_IBP TRUE 1 # Enable the indirect branch predictor +USE_PAT_HIST TRUE +IBTB_MECH 1 tc_tagged +IBTB_HIST_LENGTH 16 +IBTB_OFF_PATH_WRITES TRUE 1 # Allow off path ops to update the ibtb. +TARGETS_IN_HIST 4 +TC_ENTRIES (4 * 1024) 4096 +TC_ASSOC 4 4 +NUM_CORR_BRANCHES 3 +SEL_HIST_BP_ENTRIES 8192 +SEL_HIST_LENGTH 16 +SEL_HIST_DYN_CNT_TH 16 +SEL_HIST_MISPRED_TH 4 +ENABLE_BP_CONF FALSE +CONF_MECH 0 +PERF_BP_CONF_PRED FALSE +BPC_BITS 16 +BPC_MECH 1 +BPC_CTR_RESET TRUE +BPC_CIT_BITS 8 +BPC_CIT_TH 50 +BPC_CTR_BITS 3 +OPC_COUNT_ZEROS FALSE +OPC_COUNT_THRESH 10 +INF_LOOP FALSE +INF_LOOP_BUCKETS 811 +LOOP_ENTRIES (4 * 1024) +LOOP_ASSOC 4 +LOOP_COUNT_MAX 127 +LOOP_REPEAT_MAX 15 +KNOB_PRINT_BRINFO FALSE +BR_MISPRED_FILE NULL +CONF_PERCEPTRON_TH 0 +CONF_PERCEPTRON_CTR_BITS 8 +CONF_PERCEPTRON_ENTRIES 127 +CONF_PERCEPTRON_THRESH_OVRD 0 +CONF_HIST_LENGTH 32 +PERCEPTRON_CONF_USE_CONF FALSE +PERCEPTRON_CONF_TRAIN_HIS FALSE +PERCEPTRON_CONF_TRAIN_CONF FALSE +PERCEPTRON_CONF_TRAIN_OFFSET_CONF FALSE +PERCEPTRON_TRAIN_MISP_FACTOR 1 +PERCEPTRON_TRAIN_CORR_FACTOR 1 +PERCEPTRON_CONF_HIS_BOTH FALSE +PERCEPTRON_CONF_HIS_BOTH_LENGTH 4 +ENABLE_ICACHE_PACKET_BREAKING TRUE +NUM_LOAD_STORE_PER_PACKET 0 +PACKET_BREAK_ON_FUS FALSE +PACKET_BREAK_FU_TYPES "G,G,G,G,G,G,G,G,G,G,G,G" +POWER_INTF_ON FALSE +POWER_INTF_ENABLE_SCALING FALSE +POWER_INTF_EXEC "power/power_intf.py" +POWER_INTF_REF_CHIP_TECH_NM 22 +POWER_INTF_REF_CHIP_FREQ (3.2e9) +POWER_INTF_REF_MEMORY_FREQ (0.8e9) +POWER_OTHER (0.0) +PREF_STREAM_ON FALSE 1 +PREF_STREAM_PER_CORE_ENABLE FALSE 1 +STREAM_BUFFER_N 16 +STREAM_PREFETCH_N 2 4 +STREAM_START_DIS 5 1 +STREAM_LENGTH 16 64 +STREAM_FULL_N 1 +STREAM_TRAIN_LENGTH 16 +STREAM_TRAIN_NUM 1 4 +PREF_ACC_USE_CACHE FALSE +STREAM_STALL_ON_QUEUE_FULL FALSE +PREF_SCHEDULE_NUM 4 +TRAIN_FILTER_SIZE 32 +PREF_REQ_Q_SIZE 64 +STREAM_CREATE_ON_DC_MISS FALSE 0 +STREAM_CREATE_ON_L1_MISS TRUE 1 +STREAM_TRAIN_ON_WRONGPATH TRUE +STREAM_CREATE_ON_WRONGPATH TRUE +STREAM_PREF_INTO_DCACHE FALSE +REMOVE_REDUNDANT_STREAM FALSE +L2HIT_STREAM_SCHEDULE_NUM 4 +PREF_REQ_QUEUE_FILTER_ON FALSE +HW_PREF_HIT_TRAIN_STREAM FALSE +L2HIT_STREAM_BUFFER_N 32 +L2HIT_STREAM_PREFETCH_N 2 +L2HIT_STREAM_START_DIS 2 +L2HIT_STREAM_LENGTH 8 +L2HIT_PREF_REQ_Q_SIZE 128 +L2HIT_L2ACCESS_REQ_Q_SIZE 64 +PREF_STREAM_ACCPERSTREAM FALSE +PREF_ACC_DISTANCE_10 128 +PREF_FRAMEWORK_ON FALSE 1 +PREF_TRACE_ON FALSE +PREF_DL0REQ_QUEUE_SIZE 32 +PREF_UMLC_REQ_QUEUE_SIZE 64 +PREF_UL1REQ_QUEUE_SIZE 128 +PREF_SHARED_QUEUES TRUE 0 +PREF_DL0_MISS_ON TRUE +PREF_DL0_HIT_ON TRUE +PREF_DL0REQ_QUEUE_FILTER_ON TRUE +PREF_UMLC_REQ_QUEUE_FILTER_ON TRUE +PREF_UL1REQ_QUEUE_FILTER_ON TRUE +PREF_DL0REQ_ADD_FILTER_ON TRUE +PREF_UMLC_REQ_ADD_FILTER_ON TRUE +PREF_UL1REQ_ADD_FILTER_ON TRUE +PREF_DL0REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UMLC_REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UL1REQ_QUEUE_OVERWRITE_ON_FULL FALSE 1 +PREF_DL0SCHEDULE_NUM 4 +PREF_UMLC_SCHEDULE_NUM 4 +PREF_UL1SCHEDULE_NUM 4 +PREF_L1Q_DEMAND_RESERVE 0 +PREF_REPORT_PREF_MATCH_AS_MISS FALSE +PREF_REPORT_PREF_MATCH_AS_HIT TRUE +PREF_UPDATE_ON_WRONGPATH TRUE +PREF_TRAIN_ON_PREF_MISSES FALSE 0 +PREF_ORACLE_TRAIN_ON FALSE 0 +PREF_REQ_DROP FALSE +PREF_THROTTLE_ON FALSE +PREF_THROTTLEFB_ON FALSE 1 +PREF_ACC_THRESH_1 0.90 0.75 +PREF_ACC_THRESH_2 0.70 0.4 +PREF_ACC_THRESH_3 0.60 0.4 +PREF_ACC_THRESH_4 0.40 +PREF_UPDATE_INTERVAL 0 8192 +PREF_ANALYZE_LOAD FALSE +PREF_POL_THRESH_1 0.25 +PREF_POL_THRESH_2 0.10 +PREF_POLBV_ON FALSE +PREF_POLBV_SIZE 1024 +PREF_TIMELY_THRESH 0.05 0.01 +PREF_POLPF_THRESH 0.01 0.005 +PREF_DEGFB_USEONLYACC FALSE +PREF_DEGFB_USEONLYPOL FALSE +PREF_DEGFB_USEONLYLATE FALSE +PREF_TIMELY_THRESH_2 0.005 +PREF_DEGFB_STATPHASEFILE FALSE +PREF_MAX_DEGFB 4 +PREF_DHAL FALSE +PREF_DHAL_SENTTHRESH 16 +PREF_DHAL_USETHRESH_MAX 12 +PREF_DHAL_USETHRESH_MIN2 8 +PREF_DHAL_USETHRESH_MIN1 4 +PREF_DHAL_MAXDEG 64 +PREF_HFILTER_ON FALSE +PREF_HFILTER_INDEX_BITS 12 +PREF_HFILTER_USE_PC FALSE +PREF_HFILTER_PRED_USELESS_THRES 2 +PREF_HFILTER_RESET_ENABLE FALSE +PREF_HFILTER_RESET_INTERVAL 100000 +L2L1PREF_ON FALSE +L2WAY_PREF FALSE +L2MARKV_PREF_ON FALSE +L2NEXT_PREF_ON FALSE +L2HIT_STREAM_PREF_ON FALSE +L2L1_DC_HIT_TRAIN FALSE +L1_HIT_DUMP_FILE_ON FALSE +L1_HIT_DUMP_WO_TXT FALSE +L1_HIT_DUMPFILE "l1hit_dump.out" +IDEAL_L2_L1_PREFETCHER FALSE +IDEAL_L2_ICACHE_PREFETCHER FALSE +L1WAY_PREF_SEND_QUEUE 4 +L1PREF_REQ_QUEUE_SIZE 1024 +L1PREF_IMMEDIATE FALSE +L1WAY_PREF_TIMER_DIS 1000 +L1MARKV_PREF_SEND_QUEUE 4 +L1PREF_MARKV_REQ_QUEUE_SIZE 1024 +MARKV_L2ACCESS_REQ_Q_SIZE 64 +L1MARKV_PREF_IMMEDIATE FALSE +L1MARKV_PREF_TIMER_DIS 1 +L2L1_HIT_TRAIN TRUE +L1MARKV_REQ_TH 1 +L2L1_IMMEDIATE_PREF_CACHE FALSE +L2L1_FILL_PREF_CACHE FALSE +L2L1_L2_HIT_STAT FALSE +PREF_GHB_ON FALSE +DEBUG_PREF_GHB FALSE +PREF_GHB_BUFFER_N 1024 +PREF_GHB_INDEX_N 128 +PREF_GHB_CZONE_BITS 12 +PREF_GHB_DEGREE 16 +PREF_GHB_MAX_DEGREE 32 +PREF_STRIDE_ON FALSE +DEBUG_PREF_STRIDE FALSE +PREF_STRIDE_TABLE_N 1024 +PREF_STRIDE_REGION_BITS 16 +PREF_STRIDE_DEGREE 4 +PREF_STRIDE_DISTANCE 16 +PREF_STRIDE_STARTDISTANCE 1 +PREF_STRIDE_SINGLE_THRESH 6 +PREF_STRIDE_MULTI_THRESH 6 +PREF_STRIDE_SINGLE_STRIDE_MODE FALSE +PREF_STRIDEPC_ON FALSE +DEBUG_PREF_STRIDEPC FALSE +PREF_STRIDEPC_TABLE_N 1024 +PREF_STRIDEPC_DEGREE 4 +PREF_STRIDEPC_DISTANCE 16 +PREF_STRIDEPC_USELOADADDR FALSE +PREF_STRIDEPC_TRAINNUM 2 +PREF_STRIDEPC_STARTDIS 4 +PREF_PHASE_ON FALSE +PREF_PHASE_STUDY FALSE +DEBUG_PREF_PHASE FALSE +PREF_PHASE_PRIME_HASH 16381 +PREF_PHASE_INFOSIZE 16384 +PREF_PHASE_LOG2REGIONSIZE 12 +PREF_PHASE_REGIONENTRIES 64 +PREF_PHASE_TRACKEDREGIONS 32 +PREF_PHASE_INTERVAL 100000 +PREF_PHASE_TABLE_SIZE 64 +PREF_PHASE_MAXDIFF_THRESH 64 +PREF_PHASE_MIN_MISSES 64 +PREF_PHASE_MISSPER 0.4 +PREF_2DC_ON FALSE +DEBUG_PREF_2DC FALSE +PREF_2DC_CACHE_SIZE (1 * 1024) +PREF_2DC_CACHE_ASSOC 4 +PREF_2DC_CACHE_LINE_SIZE 1 +PREF_2DC_DEGREE 16 +PREF_2DC_ZONE_SHIFT 10 +PREF_2DC_TAG_SIZE 16 +PREF_2DC_NUM_REGIONS 64 +PREF_2DC_REGION_HASH 61 +PREF_MARKOV_ON FALSE +DEBUG_PREF_MARKOV FALSE +PREF_MARKOV_NUM_ENTRIES 65536 +PREF_MARKOV_NUM_NEXT_STATES 8 +PREF_MARKOV_SEND_ON_PREF_HIT TRUE +PREF_MARKOV_UPDATE_ON_PREF_HIT TRUE +PREF_MARKOV_TABLE_UPDATE_POLICY 0 +PREF_MARKOV_SEND_THRESHOLD 0 +PREF_SMS_ON FALSE 1 +PREF_SMS_AT_SIZE 64 +PREF_SMS_FT_SIZE 64 +PREF_SMS_PHT_SIZE 16384 +PREF_SMS_PRF_SIZE 1024 +PREF_SMS_REGION_SIZE 2048 diff --git a/labs/LAB5/runs/specrand_i-sms1/bp.stat.0.out b/labs/LAB5/runs/specrand_i-sms1/bp.stat.0.out new file mode 100644 index 00000000..caa9a70e --- /dev/null +++ b/labs/LAB5/runs/specrand_i-sms1/bp.stat.0.out @@ -0,0 +1,752 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 37600340 Instructions: 100000004 IPC: 2.65955 + +BTB_ON_PATH_MISS 529 0.003% 529 0.003% +BTB_ON_PATH_HIT 20919436 99.997% 20919436 99.997% + 20919965 100.000% 20919965 100.000% + 1.00 1.00 1.00 1.00 + +BTB_OFF_PATH_MISS 0 -nan% 0 -nan% +BTB_OFF_PATH_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BTB_ON_PATH_WRITE 529 100.000% 529 100.000% +BTB_OFF_PATH_WRITE 0 0.000% 0 0.000% + 529 100.000% 529 100.000% + 0.00 0.00 0.00 0.00 + +BP_ON_PATH_CORRECT 20394052 97.486% 20394052 97.486% +BP_ON_PATH_MISPREDICT 38936 0.186% 38936 0.186% +BP_ON_PATH_MISFETCH 486977 2.328% 486977 2.328% + 20919965 100.000% 20919965 100.000% + 0.05 0.30 0.05 0.30 + +BP_OFF_PATH_CORRECT 0 -nan% 0 -nan% +BP_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% +BP_OFF_PATH_MISFETCH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +LATE_BP_ON_PATH_CORRECT 20919965 100.000% 20919965 100.000% +LATE_BP_ON_PATH_MISPREDICT 0 0.000% 0 0.000% +LATE_BP_ON_PATH_MISFETCH 0 0.000% 0 0.000% + 20919965 100.000% 20919965 100.000% + 0.00 0.00 0.00 0.00 + +LATE_BP_OFF_PATH_CORRECT 0 -nan% 0 -nan% +LATE_BP_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% +LATE_BP_OFF_PATH_MISFETCH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_PVN 0 -nan% 0 -nan% +BP_ON_PATH_CONF_PVN_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_PVP 0 -nan% 0 -nan% +BP_ON_PATH_CONF_PVP_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BP_ON_PATH_CONF_SPEC 0 -nan% 0 -nan% +BP_ON_PATH_CONF_SPEC_BOT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CRS_MISS_ON_PATH 85185 4.432% 85185 4.432% +CRS_HIT_ON_PATH 1836733 95.568% 1836733 95.568% + 1921918 100.000% 1921918 100.000% + 0.96 0.94 0.96 0.94 + +CRS_MISS_OFF_PATH 0 -nan% 0 -nan% +CRS_HIT_OFF_PATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CRS_CLOBBER 0 0 + +TARG_ON_PATH_MISS 921 0.116% 921 0.116% +TARG_ON_PATH_HIT 791502 99.884% 791502 99.884% + 792423 100.000% 792423 100.000% + 1.00 1.00 1.00 1.00 + +TARG_OFF_PATH_MISS 0 -nan% 0 -nan% +TARG_OFF_PATH_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_ON_PATH_WRITE 792423 100.000% 792423 100.000% +TARG_OFF_PATH_WRITE 0 0.000% 0 0.000% + 792423 100.000% 792423 100.000% + 0.00 0.00 0.00 0.00 + +TARG_HYBRID_CORRECT_TAGLESS 0 -nan% 0 -nan% +TARG_HYBRID_CORRECT_TAGGED 0 -nan% 0 -nan% +TARG_HYBRID_MISPRED_TAGLESS 0 -nan% 0 -nan% +TARG_HYBRID_MISPRED_TAGGED 0 -nan% 0 -nan% +TARG_HYBRID_NO_PRED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TARG_VP_INDIRECT_MISPRED 0 -nan% 0 -nan% +TARG_VP_INDIRECT_NOPRED 0 -nan% 0 -nan% +TARG_VP_INDIRECT_CORRECT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CBR_ON_PATH_CORRECT 15130259 99.743% 15130259 99.743% +CBR_ON_PATH_MISPREDICT 38936 0.257% 38936 0.257% + 15169195 100.000% 15169195 100.000% + 0.00 0.05 0.00 0.05 + +CBR_ON_PATH_CORRECT_PER1000INST 15130259 151.3026 15130259 151.3026 + +CBR_ON_PATH_MISPREDICT_PER1000INST 38936 0.3894 38936 0.3894 + +CBR_OFF_PATH_CORRECT 0 -nan% 0 -nan% +CBR_OFF_PATH_MISPREDICT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PRED_TO_UPDATE_CYCLES_0 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_1 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_2 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_3 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_4 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_5 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_6 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_7 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_8 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_9 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_10 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_11 0 -nan% 0 -nan% +PRED_TO_UPDATE_CYCLES_12 0 -nan% 0 -nan% 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b/labs/LAB5/runs/specrand_i-sms1/inst.stat.0.out @@ -0,0 +1,103 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 37600340 Instructions: 100000004 IPC: 2.65955 + +ST_OP_INV 0 0.000% 0 0.000% +ST_OP_NOP 2435080 2.046% 2435080 2.046% +ST_OP_CF 20948368 17.603% 20948368 17.603% +ST_OP_MOV 12802380 10.758% 12802380 10.758% +ST_OP_CMOV 175550 0.148% 175550 0.148% +ST_OP_LDA 4521657 3.800% 4521657 3.800% +ST_OP_IMEM 31644662 26.592% 31644662 26.592% +ST_OP_IADD 20142062 16.926% 20142062 16.926% +ST_OP_IMUL 616477 0.518% 616477 0.518% +ST_OP_IDIV 28403 0.024% 28403 0.024% +ST_OP_ICMP 9277559 7.796% 9277559 7.796% +ST_OP_LOGIC 12076608 10.148% 12076608 10.148% +ST_OP_SHIFT 2546917 2.140% 2546917 2.140% +ST_OP_FMEM 864571 0.727% 864571 0.727% +ST_OP_FCVT 292192 0.246% 292192 0.246% +ST_OP_FADD 8189 0.007% 8189 0.007% +ST_OP_FMUL 292192 0.246% 292192 0.246% +ST_OP_FMA 0 0.000% 0 0.000% +ST_OP_FDIV 0 0.000% 0 0.000% +ST_OP_FCMP 56802 0.048% 56802 0.048% +ST_OP_FCMOV 0 0.000% 0 0.000% +ST_OP_GATHER 0 0.000% 0 0.000% +ST_OP_SCATTER 0 0.000% 0 0.000% +ST_OP_PIPELINED_FAST 109769 0.092% 109769 0.092% +ST_OP_PIPELINED_MEDIUM 0 0.000% 0 0.000% +ST_OP_PIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_MEDIUM 162362 0.136% 162362 0.136% +ST_OP_NOTPIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_VERY_SLOW 0 0.000% 0 0.000% + 119001800 100.000% 119001800 100.000% + 6.10 3.28 6.10 3.28 + +ST_NOT_CF 98053432 82.397% 98053432 82.397% +ST_CF_BR 1297461 1.090% 1297461 1.090% +ST_CF_CBR 15169195 12.747% 15169195 12.747% +ST_CF_CALL 1738968 1.461% 1738968 1.461% +ST_CF_IBR 609473 0.512% 609473 0.512% +ST_CF_ICALL 182950 0.154% 182950 0.154% +ST_CF_ICO 0 0.000% 0 0.000% +ST_CF_RET 1921918 1.615% 1921918 1.615% +ST_CF_SYS 28403 0.024% 28403 0.024% + 119001800 100.000% 119001800 100.000% + 0.45 1.10 0.45 1.10 + +ST_BAR_NONE 118973397 99.976% 118973397 99.976% +ST_BAR_FETCH 28403 0.024% 28403 0.024% +ST_BAR_ISSUE 0 0.000% 0 0.000% +ST_BAR_BOTH 0 0.000% 0 0.000% + 119001800 100.000% 119001800 100.000% + 0.00 0.02 0.00 0.02 + +ST_NOT_MEM 86492567 72.682% 86492567 72.682% +ST_MEM_LD 19982216 16.792% 19982216 16.792% +ST_MEM_ST 12527017 10.527% 12527017 10.527% +ST_MEM_PF 0 0.000% 0 0.000% +ST_MEM_WH 0 0.000% 0 0.000% +ST_MEM_EVICT 0 0.000% 0 0.000% + 119001800 100.000% 119001800 100.000% + 0.38 0.58 0.38 0.58 + +ST_NOT_MEM_OFFPATH 0 -nan% 0 -nan% +ST_MEM_LD_OFFPATH 0 -nan% 0 -nan% +ST_MEM_ST_OFFPATH 0 -nan% 0 -nan% +ST_MEM_PF_OFFPATH 0 -nan% 0 -nan% +ST_MEM_WH_OFFPATH 0 -nan% 0 -nan% +ST_MEM_EVIC_OFFPATHT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ST_OP_ONPATH 119001800 119001800 + +ST_OP_OFFPATH 0 0 + +ST_FAKE_OP_OFFPATH 0 -nan% 0 -nan% +ST_NOT_FAKE_OP_OFFPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ST_FAKE_REASON_NOT_FAKE 0 -nan% 0 -nan% +ST_FAKE_REASON_REDIRECT_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_RETURN_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_NONRET_CF_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_NOT_TAKEN_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_WRONG_PATH_STORE_TO_NEW_REGION 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ST_INST_ONPATH 100000090 100000090 + +ST_INST_OFFPATH 0 0 + +STATIC_PIN_NOP 0 0 + +DYNAMIC_PIN_REP_GREATER_256 0 0 + + + diff --git a/labs/LAB5/runs/specrand_i-sms1/l2l1pref.stat.0.out b/labs/LAB5/runs/specrand_i-sms1/l2l1pref.stat.0.out new file mode 100644 index 00000000..2309bfc6 --- /dev/null +++ b/labs/LAB5/runs/specrand_i-sms1/l2l1pref.stat.0.out @@ -0,0 +1,140 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 37600340 Instructions: 100000004 IPC: 2.65955 + +L2WAY_FILL_L1 0 0 + +L2WAY_WAY_HIT 0 -nan% 0 -nan% +L2WAY_WAY_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_PREF_REQ 0 0 + +L2WAY_PREF_HIT_DATA_IN_CACHE 0 -nan% 0 -nan% +L2WAY_PREF_HIT_DATA_REQ 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_TRAIN_HIT 0 -nan% 0 -nan% +L2WAY_TRAIN_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L1_HIT_REQ_TYPE_IFETCH 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DFETCH 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DSTORE 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_IPRF 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DPRF 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_WB 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2_ACCESS_INTERVAL__0 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__1 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__2 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__3 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__4 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__5 0 -nan% 0 -nan% +L2_ACCESS_INTERVAL__6 0 -nan% 0 -nan% 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+ -nan -nan -nan -nan + +L2HIT_SAME_IP_DELTA__0 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__1 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__2 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__3 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__4 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__5 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__6 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__7 0 -nan% 0 -nan% +L2HIT_SAME_IP_DELTA__8 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_IP_HIT_COUNT__1 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__2 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__3 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__4 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__5 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__6 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__7 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__8 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__9 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + + + diff --git a/labs/LAB5/runs/specrand_i-sms1/memory.stat.0.out b/labs/LAB5/runs/specrand_i-sms1/memory.stat.0.out new file mode 100644 index 00000000..b8de60b4 --- /dev/null +++ b/labs/LAB5/runs/specrand_i-sms1/memory.stat.0.out @@ -0,0 +1,3416 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 37600340 Instructions: 100000004 IPC: 2.65955 + +ICACHE_MISS 162959 0.499% 162959 0.499% +ICACHE_HIT 32501548 99.501% 32501548 99.501% + 32664507 100.000% 32664507 100.000% + 1.00 0.99 1.00 0.99 + +ICACHE_MISS_ONPATH 162959 100.000% 162959 100.000% +ICACHE_MISS_OFFPATH 0 0.000% 0 0.000% + 162959 100.000% 162959 100.000% + 0.00 0.00 0.00 0.00 + +ICACHE_HIT_ONPATH 32501548 100.000% 32501548 100.000% +ICACHE_HIT_OFFPATH 0 0.000% 0 0.000% + 32501548 100.000% 32501548 100.000% + 0.00 0.00 0.00 0.00 + +ICACHE_HIT_ONPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +ICACHE_HIT_ONPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ICACHE_HIT_OFFPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +ICACHE_HIT_OFFPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DCACHE_MISS 504 0.002% 504 0.002% +DCACHE_ST_BUFFER_HIT 0 0.000% 0 0.000% +DCACHE_HIT 32508709 99.998% 32508709 99.998% + 32509213 100.000% 32509213 100.000% + 2.00 2.00 2.00 2.00 + +DCACHE_MISS_COMPULSORY 157 0.3115 157 0.3115 + +DCACHE_MISS_CAPACITY 0 0.0000 0 0.0000 + +DCACHE_MISS_CONFLICT 347 0.6885 347 0.6885 + +DCACHE_MISS_ONPATH 504 100.000% 504 100.000% +DCACHE_MISS_OFFPATH 0 0.000% 0 0.000% + 504 100.000% 504 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_ST_BUFFER_HIT_ONPATH 0 -nan% 0 -nan% +DCACHE_ST_BUFFER_HIT_OFFPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DCACHE_HIT_ONPATH 32508709 100.000% 32508709 100.000% +DCACHE_HIT_OFFPATH 0 0.000% 0 0.000% + 32508709 100.000% 32508709 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_HIT_ONPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +DCACHE_HIT_ONPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DCACHE_HIT_OFFPATH_SAT_BY_OFFPATH 0 -nan% 0 -nan% +DCACHE_HIT_OFFPATH_SAT_BY_ONPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DCACHE_MISS_LD 460 91.270% 460 91.270% +DCACHE_MISS_ST 44 8.730% 44 8.730% + 504 100.000% 504 100.000% + 0.09 0.27 0.09 0.27 + +DCACHE_MISS_LD_ONPATH 460 100.000% 460 100.000% +DCACHE_MISS_LD_OFFPATH 0 0.000% 0 0.000% + 460 100.000% 460 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_MISS_ST_ONPATH 44 100.000% 44 100.000% +DCACHE_MISS_ST_OFFPATH 0 0.000% 0 0.000% + 44 100.000% 44 100.000% + 0.00 0.00 0.00 0.00 + +DCACHE_MISS_WAITMEM 0 0 + +MEM_REQ_ROW_BUFFER_HITS 0 -nan% 0 -nan% +MEM_REQ_ROW_BUFFER_MISSES 0 -nan% 0 -nan% +MEM_REQ_ROW_BUFFER_CONFLICTS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +SHADOW_ROW_BUFFER_HITS 0 0 + +SHADOW_ROW_HIT_STALL_TIME 0 0 + +CHANNEL0_BUS_BUSY_CYCLES 0 -nan% 0 -nan% +CHANNEL1_BUS_BUSY_CYCLES 0 -nan% 0 -nan% +CHANNEL2_BUS_BUSY_CYCLES 0 -nan% 0 -nan% +CHANNEL3_BUS_BUSY_CYCLES 0 -nan% 0 -nan% +CHANNEL4_BUS_BUSY_CYCLES 0 -nan% 0 -nan% +CHANNEL5_BUS_BUSY_CYCLES 0 -nan% 0 -nan% +CHANNEL6_BUS_BUSY_CYCLES 0 -nan% 0 -nan% +CHANNEL7_BUS_BUSY_CYCLES 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CHANNEL_IDLE_DESPITE_READY_CMD 0 0 + +MEM_NUM_TOTAL_BUS_CYCLES 0 0 + +MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan + +CORE_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan + +CHANNEL0_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan% +CHANNEL1_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan% +CHANNEL2_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan% +CHANNEL3_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan% +CHANNEL4_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan% +CHANNEL5_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan% +CHANNEL6_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan% +CHANNEL7_MEM_NUM_TOTAL_BUS_CYCLES 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CHANNEL0_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan + +CHANNEL1_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan + +CHANNEL2_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan + +CHANNEL3_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan + +CHANNEL4_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan + +CHANNEL5_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan + +CHANNEL6_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan + +CHANNEL7_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE 0 -nan 0 -nan + +BUS_DEMAND_ACCESS 321 321 + +BUS_PREF_ACCESS 109 109 + +BUS_ACCESS 0 0 + +L1_DEMAND_ACCESS 326236 326236 + +L1_PREF_ACCESS 291 291 + +L1_ACCESS 163292 163292 + +MLC_DEMAND_ACCESS 0 0 + +MLC_PREF_ACCESS 0 0 + +MLC_ACCESS 0 0 + +L1_HIT 162796 99.803% 162796 99.803% +L1_MISS 321 0.197% 321 0.197% + 163117 100.000% 163117 100.000% + 0.00 0.04 0.00 0.04 + +L1_HIT_ALL 162805 99.737% 162805 99.737% +L1_MISS_ALL 430 0.263% 430 0.263% + 163235 100.000% 163235 100.000% + 0.00 0.05 0.00 0.05 + +L1_DEMAND_MISS 321 74.651% 321 74.651% +L1_PREF_REQ_MISS 109 25.349% 109 25.349% +L1_WB_MISS 0 0.000% 0 0.000% + 430 100.000% 430 100.000% + 0.25 0.38 0.25 0.38 + +L1_DEMAND_HIT 162796 99.994% 162796 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-nan 0 -nan + +DRAM_NUM_REQS_29_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_29_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_29_WB_NODIRTY 0 -nan 0 -nan + +DRAM_NUM_REQS_30_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_30_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_30_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_30_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_30_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_30_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_30_WB_NODIRTY 0 -nan 0 -nan + +DRAM_NUM_REQS_31_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_31_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_31_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_31_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_31_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_31_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_31_WB_NODIRTY 0 -nan 0 -nan + +DRAM_NUM_REQS_32_IFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_32_DFETCH 0 -nan 0 -nan + +DRAM_NUM_REQS_32_DSTORE 0 -nan 0 -nan + +DRAM_NUM_REQS_32_IPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_32_DPRF 0 -nan 0 -nan + +DRAM_NUM_REQS_32_WB 0 -nan 0 -nan + +DRAM_NUM_REQS_32_WB_NODIRTY 0 -nan 0 -nan + +DRAM_BOTTLENECK_BUS_0 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_10 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_20 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_30 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_40 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_50 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_60 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_70 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_80 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_90 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_100 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DRAM_BOTTLENECK_BANKS_0 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_10 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_20 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_30 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_40 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_50 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_60 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_70 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_80 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_90 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_100 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DRAM_BOTTLENECK_FAW_0 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_10 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_20 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_30 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_40 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_50 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_60 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_70 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_80 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_90 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_100 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DRAM_ROW_HIT_GEN_AFTER_ROW_OPEN_STALLING 0 0 + +KNOWN_BAD_ADDRESS 0 0.000% 0 0.000% +GOOD_ADDRESS 326816 100.000% 326816 100.000% + 326816 100.000% 326816 100.000% + 1.00 1.00 1.00 1.00 + + + diff --git a/labs/LAB5/runs/specrand_i-sms1/power.stat.0.out b/labs/LAB5/runs/specrand_i-sms1/power.stat.0.out new file mode 100644 index 00000000..9bfdba7f --- /dev/null +++ b/labs/LAB5/runs/specrand_i-sms1/power.stat.0.out @@ -0,0 +1,184 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 37600340 Instructions: 100000004 IPC: 2.65955 + +POWER_STATS_BEGIN 0 0 + +POWER_TIME 11750106250000 11750106250000 + +POWER_CYCLE 37600340 37600340 + +POWER_ITLB_ACCESS 32664507 32664507 + +POWER_DTLB_ACCESS 12527008 12527008 + +POWER_ICACHE_ACCESS 32664507 32664507 + +POWER_ICACHE_MISS 162959 162959 + +POWER_BTB_READ 32664507 32664507 + +POWER_BTB_WRITE 525913 525913 + +POWER_ROB_READ 119001726 119001726 + +POWER_ROB_WRITE 119001726 119001726 + +POWER_RENAME_READ 238003452 238003452 + +POWER_RENAME_WRITE 119001726 119001726 + +POWER_FP_RENAME_READ 0 0 + +POWER_FP_RENAME_WRITE 0 0 + +POWER_FUNCTION_CALL 1921916 1921916 + +POWER_INST_WINDOW_READ 119001726 119001726 + +POWER_INST_WINDOW_WRITE 119001726 119001726 + +POWER_INT_REGFILE_READ 132918899 132918899 + +POWER_INT_REGFILE_WRITE 103094988 103094988 + +POWER_IALU_ACCESS 118356847 118356847 + +POWER_CDB_IALU_ACCESS 118356847 118356847 + +POWER_MUL_ACCESS 644879 644879 + +POWER_CDB_MUL_ACCESS 644879 644879 + +POWER_FP_INST_WINDOW_WRITE 0 0 + +POWER_FP_INST_WINDOW_READ 0 0 + +POWER_FP_REGFILE_READ 0 0 + +POWER_FP_REGFILE_WRITE 0 0 + +POWER_FPU_ACCESS 0 0 + +POWER_CDB_FPU_ACCESS 0 0 + +POWER_DCACHE_READ_ACCESS 19982206 19982206 + +POWER_DCACHE_WRITE_ACCESS 12527007 12527007 + +POWER_DCACHE_READ_MISS 460 460 + +POWER_DCACHE_WRITE_MISS 44 44 + +POWER_MLC_READ_ACCESS 0 0 + +POWER_MLC_WRITE_ACCESS 0 0 + +POWER_MLC_READ_MISS 0 0 + +POWER_MLC_WRITE_MISS 0 0 + +POWER_LLC_READ_ACCESS 163235 163235 + +POWER_LLC_WRITE_ACCESS 0 0 + +POWER_LLC_READ_MISS 430 430 + +POWER_LLC_WRITE_MISS 0 0 + +POWER_MEMORY_ACCESS 0 0 + +POWER_MEMORY_READ_ACCESS 0 0 + +POWER_MEMORY_WRITE_ACCESS 0 0 + +POWER_INST_WINDOW_WAKEUP_ACCESS 119001726 119001726 + +POWER_FP_INST_WINDOW_WAKEUP_ACCESS 0 0 + +POWER_L1DIREC_READ_ACCESS 0 0 + +POWER_L1DIREC_WRITE_ACCESS 0 0 + +POWER_L1DIREC_READ_MISS 0 0 + +POWER_L1DIREC_WRITE_MISS 0 0 + +POWER_L2DIREC_READ_ACCESS 0 0 + +POWER_L2DIREC_WRITE_ACCESS 0 0 + +POWER_L2DIREC_READ_MISS 0 0 + +POWER_L2DIREC_WRITE_MISS 0 0 + +POWER_MEMORY_CTRL_ACCESS 430 430 + +POWER_MEMORY_CTRL_READ 430 430 + +POWER_MEMORY_CTRL_WRITE 0 0 + +POWER_OP 119001726 119001726 + +POWER_INT_OP 114780570 114780570 + +POWER_FP_OP 1786077 1786077 + +POWER_LD_OP 19982208 19982208 + +POWER_ST_OP 12527008 12527008 + +POWER_BRANCH_MISPREDICT 525913 525913 + +POWER_COMMITTED_OP 119001726 119001726 + +POWER_COMMITTED_INT_OP 114780570 114780570 + +POWER_COMMITTED_FP_OP 4221156 4221156 + +POWER_BRANCH_OP 20948352 20948352 + +POWER_DRAM_PRECHARGE 76 76 + +POWER_DRAM_ACTIVATE 103 103 + +POWER_DRAM_READ 430 430 + +POWER_DRAM_WRITE 0 0 + +POWER_STATS_END 0 0 + +ENERGY 0.000000 0.000000 + +ENERGY_CORE 0.000000 0.000000 + +ENERGY_UNCORE 0.000000 0.000000 + +ENERGY_MEMORY 0.000000 0.000000 + +ENERGY_OTHER 0.000000 0.000000 + +ENERGY_CORE_STATIC 0.000000 0.000000 + +ENERGY_CORE_DYNAMIC 0.000000 0.000000 + +ENERGY_UNCORE_STATIC 0.000000 0.000000 + +ENERGY_UNCORE_DYNAMIC 0.000000 0.000000 + +ENERGY_MEMORY_STATIC 0.000000 0.000000 + +ENERGY_MEMORY_DYNAMIC 0.000000 0.000000 + +ENERGY_OTHER_STATIC 0.000000 0.000000 + +ENERGY_OTHER_DYNAMIC 0.000000 0.000000 + +TIME 0.000000 0.000000 + +ENERGY_STATS_END 0 0 + + + diff --git a/labs/LAB5/runs/specrand_i-sms1/pref.stat.0.out b/labs/LAB5/runs/specrand_i-sms1/pref.stat.0.out new file mode 100644 index 00000000..5847d386 --- /dev/null +++ b/labs/LAB5/runs/specrand_i-sms1/pref.stat.0.out @@ -0,0 +1,208 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 37600340 Instructions: 100000004 IPC: 2.65955 + +PREF_DL0REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UMLC_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UL1REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_DL0REQ_QUEUE_FULL 0 0 + +PREF_UMLC_REQ_QUEUE_FULL 0 0 + +PREF_UL1REQ_QUEUE_FULL 0 0 + +PREF_DC_HIT_NOSEND 0 0 + +PREF_WBQDC_HIT_NOSEND 0 0 + +PREF_MLCQ_STALL 0 0 + +PREF_L1Q_STALL 0 0 + +PREF_UMLC_REQ_SEND_QUEUE_STALL 0 0 + +PREF_UL1REQ_SEND_QUEUE_STALL 0 0 + +PREF_UMLC_REQ_QUEUE_SENTREQ 0 0 + +PREF_UL1REQ_QUEUE_SENTREQ 118 118 + +PREF_NEWREQ_MATCHED 0 0 + +PREF_UMLC_REQ_QUEUE_MATCHED_REQ 0 0 + +PREF_UL1REQ_QUEUE_MATCHED_REQ 8 8 + +PREF_DL0REQ_QUEUE_MATCHED_REQ 0 0 + +L1_PREF_HIT 68 68 + +L1_PREF_UNIQUE_HIT 68 68 + +L1_PREF_LATE 1 1 + +L1_LATE_PREF_CYCLES 55 55 + +L1_LATE_PREF_CYCLES_DIST_0 1 100.000% 1 100.000% +L1_LATE_PREF_CYCLES_DIST_100 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_200 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_300 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_400 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_500 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_600 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_700 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_800 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_900 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1000 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1100 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1200 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1300 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1400 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1500 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1600 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1700 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1800 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1900 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_2000 0 0.000% 0 0.000% + 1 100.000% 1 100.000% + 0.00 -nan 0.00 -nan + +MLC_PREF_HIT 0 0 + +MLC_PREF_UNIQUE_HIT 0 0 + +MLC_PREF_LATE 0 0 + +PREF_HYBRID_SEL_0 0 -nan% 0 -nan% +PREF_HYBRID_SEL_1 0 -nan% 0 -nan% +PREF_HYBRID_SEL_2 0 -nan% 0 -nan% +PREF_HYBRID_SEL_3 0 -nan% 0 -nan% +PREF_HYBRID_SEL_4 0 -nan% 0 -nan% +PREF_HYBRID_SEL_5 0 -nan% 0 -nan% +PREF_HYBRID_SEL_6 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_DISTANCE_1 0 -nan% 0 -nan% +PREF_DISTANCE_2 0 -nan% 0 -nan% +PREF_DISTANCE_3 0 -nan% 0 -nan% +PREF_DISTANCE_4 0 -nan% 0 -nan% +PREF_DISTANCE_5 0 -nan% 0 -nan% +PREF_DISTANCE_6 0 -nan% 0 -nan% +PREF_DISTANCE_7 0 -nan% 0 -nan% +PREF_DISTANCE_8 0 -nan% 0 -nan% +PREF_DISTANCE_9 0 -nan% 0 -nan% +PREF_DISTANCE_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_REPL_MRU 0 -nan% 0 -nan% +PREF_REPL_MID 0 -nan% 0 -nan% +PREF_REPL_LOWQTR 0 -nan% 0 -nan% +PREF_REPL_LRU 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_REPL_MOVEDOWN 0 -nan% 0 -nan% +PREF_REPL_MOVEUP 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_COV_1 0 -nan% 0 -nan% +PREF_COV_2 0 -nan% 0 -nan% +PREF_COV_3 0 -nan% 0 -nan% +PREF_COV_4 0 -nan% 0 -nan% +PREF_COV_5 0 -nan% 0 -nan% +PREF_COV_6 0 -nan% 0 -nan% +PREF_COV_7 0 -nan% 0 -nan% +PREF_COV_8 0 -nan% 0 -nan% +PREF_COV_9 0 -nan% 0 -nan% +PREF_COV_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_POL_1 0 -nan% 0 -nan% +PREF_POL_2 0 -nan% 0 -nan% +PREF_POL_3 0 -nan% 0 -nan% +PREF_POL_4 0 -nan% 0 -nan% +PREF_POL_5 0 -nan% 0 -nan% +PREF_POL_6 0 -nan% 0 -nan% +PREF_POL_7 0 -nan% 0 -nan% +PREF_POL_8 0 -nan% 0 -nan% +PREF_POL_9 0 -nan% 0 -nan% +PREF_POL_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_ACC_1 0 -nan% 0 -nan% +PREF_ACC_2 0 -nan% 0 -nan% +PREF_ACC_3 0 -nan% 0 -nan% +PREF_ACC_4 0 -nan% 0 -nan% +PREF_ACC_5 0 -nan% 0 -nan% +PREF_ACC_6 0 -nan% 0 -nan% +PREF_ACC_7 0 -nan% 0 -nan% +PREF_ACC_8 0 -nan% 0 -nan% +PREF_ACC_9 0 -nan% 0 -nan% +PREF_ACC_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_TIMELY_1 0 -nan% 0 -nan% +PREF_TIMELY_2 0 -nan% 0 -nan% +PREF_TIMELY_3 0 -nan% 0 -nan% +PREF_TIMELY_4 0 -nan% 0 -nan% +PREF_TIMELY_5 0 -nan% 0 -nan% +PREF_TIMELY_6 0 -nan% 0 -nan% +PREF_TIMELY_7 0 -nan% 0 -nan% +PREF_TIMELY_8 0 -nan% 0 -nan% +PREF_TIMELY_9 0 -nan% 0 -nan% +PREF_TIMELY_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_UNUSED_EVICT 0 0 + +PREF_REGION_SENT 0 0 + +PREF_REGION_USEFUL 0 0 + +PREF_REGION_EVICT 0 0 + +PREF_PFPOL 0 0 + +PREF_PHASE_NEWPHASE_DET 0 0 + +PREF_PHASE_NEWPHASE_NOTVALID 0 0 + +PREF_PHASE_SENTPREF 0 0 + +PREF_PHASE_OVERWRITE_PAGE 0 0 + +PREF_UPDATE_COUNT 0 0 + +PREF_ACC1_HT_HP 0 -nan% 0 -nan% +PREF_ACC1_HT_LP 0 -nan% 0 -nan% +PREF_ACC1_LT_HP 0 -nan% 0 -nan% +PREF_ACC1_LT_LP 0 -nan% 0 -nan% +PREF_ACC2_HT_HP 0 -nan% 0 -nan% +PREF_ACC2_HT_LP 0 -nan% 0 -nan% +PREF_ACC2_LT_HP 0 -nan% 0 -nan% +PREF_ACC2_LT_LP 0 -nan% 0 -nan% +PREF_ACC3_HT_HP 0 -nan% 0 -nan% +PREF_ACC3_HT_LP 0 -nan% 0 -nan% +PREF_ACC3_LT_HP 0 -nan% 0 -nan% +PREF_ACC3_LT_LP 0 -nan% 0 -nan% +PREF_ACC4_HT_HP 0 -nan% 0 -nan% +PREF_ACC4_HT_LP 0 -nan% 0 -nan% +PREF_ACC4_LT_HP 0 -nan% 0 -nan% +PREF_ACC4_LT_LP 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + + + diff --git a/labs/LAB5/runs/specrand_i-sms1/ramulator.stat.out b/labs/LAB5/runs/specrand_i-sms1/ramulator.stat.out new file mode 100644 index 00000000..446806b1 --- /dev/null +++ b/labs/LAB5/runs/specrand_i-sms1/ramulator.stat.out @@ -0,0 +1,150 @@ + ramulator.active_cycles_0 9073 # Total active cycles for level _0 + ramulator.busy_cycles_0 9073 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0 + ramulator.serving_requests_0 11370 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.average_serving_requests_0 0.000806 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.active_cycles_0_0 9073 # Total active cycles for level _0_0 + ramulator.busy_cycles_0_0 641593 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0 + ramulator.serving_requests_0_0 11370 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.average_serving_requests_0_0 0.000806 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.active_cycles_0_0_0 3111 # Total active cycles for level _0_0_0 + ramulator.busy_cycles_0_0_0 3111 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0 + ramulator.serving_requests_0_0_0 3515 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 +ramulator.average_serving_requests_0_0_0 0.000249 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 + ramulator.active_cycles_0_0_0_0 805 # Total active cycles for level _0_0_0_0 + ramulator.busy_cycles_0_0_0_0 805 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_0 + ramulator.serving_requests_0_0_0_0 976 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 +ramulator.average_serving_requests_0_0_0_0 0.000069 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 + ramulator.active_cycles_0_0_0_1 344 # Total active cycles for level _0_0_0_1 + ramulator.busy_cycles_0_0_0_1 344 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_1 + ramulator.serving_requests_0_0_0_1 344 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 +ramulator.average_serving_requests_0_0_0_1 0.000024 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 + ramulator.active_cycles_0_0_0_2 352 # Total active cycles for level _0_0_0_2 + ramulator.busy_cycles_0_0_0_2 352 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_2 + ramulator.serving_requests_0_0_0_2 352 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 +ramulator.average_serving_requests_0_0_0_2 0.000025 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 + ramulator.active_cycles_0_0_0_3 1773 # Total active cycles for level _0_0_0_3 + ramulator.busy_cycles_0_0_0_3 1773 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_3 + ramulator.serving_requests_0_0_0_3 1843 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 +ramulator.average_serving_requests_0_0_0_3 0.000131 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 + ramulator.active_cycles_0_0_1 1000 # Total active cycles for level _0_0_1 + ramulator.busy_cycles_0_0_1 1000 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1 + ramulator.serving_requests_0_0_1 1000 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 +ramulator.average_serving_requests_0_0_1 0.000071 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 + ramulator.active_cycles_0_0_1_0 0 # Total active cycles for level _0_0_1_0 + ramulator.busy_cycles_0_0_1_0 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_0 + ramulator.serving_requests_0_0_1_0 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 +ramulator.average_serving_requests_0_0_1_0 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 + ramulator.active_cycles_0_0_1_1 328 # Total active cycles for level _0_0_1_1 + ramulator.busy_cycles_0_0_1_1 328 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_1 + ramulator.serving_requests_0_0_1_1 328 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 +ramulator.average_serving_requests_0_0_1_1 0.000023 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 + ramulator.active_cycles_0_0_1_2 672 # Total active cycles for level _0_0_1_2 + ramulator.busy_cycles_0_0_1_2 672 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_2 + ramulator.serving_requests_0_0_1_2 672 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 +ramulator.average_serving_requests_0_0_1_2 0.000048 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 + ramulator.active_cycles_0_0_1_3 0 # Total active cycles for level _0_0_1_3 + ramulator.busy_cycles_0_0_1_3 0 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_3 + ramulator.serving_requests_0_0_1_3 0 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 +ramulator.average_serving_requests_0_0_1_3 0.000000 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 + ramulator.active_cycles_0_0_2 3812 # Total active cycles for level _0_0_2 + ramulator.busy_cycles_0_0_2 3812 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2 + ramulator.serving_requests_0_0_2 4736 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 +ramulator.average_serving_requests_0_0_2 0.000336 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 + ramulator.active_cycles_0_0_2_0 524 # Total active cycles for level _0_0_2_0 + ramulator.busy_cycles_0_0_2_0 524 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_0 + ramulator.serving_requests_0_0_2_0 652 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 +ramulator.average_serving_requests_0_0_2_0 0.000046 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 + ramulator.active_cycles_0_0_2_1 423 # Total active cycles for level _0_0_2_1 + ramulator.busy_cycles_0_0_2_1 423 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_1 + ramulator.serving_requests_0_0_2_1 428 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 +ramulator.average_serving_requests_0_0_2_1 0.000030 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 + ramulator.active_cycles_0_0_2_2 1893 # Total active cycles for level _0_0_2_2 + ramulator.busy_cycles_0_0_2_2 1893 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_2 + ramulator.serving_requests_0_0_2_2 2512 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 +ramulator.average_serving_requests_0_0_2_2 0.000178 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 + ramulator.active_cycles_0_0_2_3 1144 # Total active cycles for level _0_0_2_3 + ramulator.busy_cycles_0_0_2_3 1144 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_3 + ramulator.serving_requests_0_0_2_3 1144 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 +ramulator.average_serving_requests_0_0_2_3 0.000081 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 + ramulator.active_cycles_0_0_3 1848 # Total active cycles for level _0_0_3 + ramulator.busy_cycles_0_0_3 1848 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3 + ramulator.serving_requests_0_0_3 2119 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 +ramulator.average_serving_requests_0_0_3 0.000150 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 + ramulator.active_cycles_0_0_3_0 452 # Total active cycles for level _0_0_3_0 + ramulator.busy_cycles_0_0_3_0 452 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_0 + ramulator.serving_requests_0_0_3_0 452 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 +ramulator.average_serving_requests_0_0_3_0 0.000032 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 + ramulator.active_cycles_0_0_3_1 603 # Total active cycles for level _0_0_3_1 + ramulator.busy_cycles_0_0_3_1 603 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_1 + ramulator.serving_requests_0_0_3_1 695 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 +ramulator.average_serving_requests_0_0_3_1 0.000049 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 + ramulator.active_cycles_0_0_3_2 360 # Total active cycles for level _0_0_3_2 + ramulator.busy_cycles_0_0_3_2 360 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_2 + ramulator.serving_requests_0_0_3_2 360 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 +ramulator.average_serving_requests_0_0_3_2 0.000026 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 + ramulator.active_cycles_0_0_3_3 516 # Total active cycles for level _0_0_3_3 + ramulator.busy_cycles_0_0_3_3 516 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_3 + ramulator.serving_requests_0_0_3_3 612 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 +ramulator.average_serving_requests_0_0_3_3 0.000043 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 + ramulator.read_transaction_bytes_0 27520 # The total byte of read transaction per channel + ramulator.write_transaction_bytes_0 0 # The total byte of write transaction per channel + ramulator.row_hits_channel_0_core 327 # Number of row hits per channel per core + ramulator.row_misses_channel_0_core 34 # Number of row misses per channel per core + ramulator.row_conflicts_channel_0_core 69 # Number of row conflicts per channel per core + ramulator.read_row_hits_channel_0_core 327 # Number of row hits for read requests per channel per core + [0] 327.0 # +ramulator.read_row_misses_channel_0_core 34 # Number of row misses for read requests per channel per core + [0] 34.0 # +ramulator.read_row_conflicts_channel_0_core 69 # Number of row conflicts for read requests per channel per core + [0] 69.0 # + ramulator.write_row_hits_channel_0_core 0 # Number of row hits for write requests per channel per core + [0] 0.0 # +ramulator.write_row_misses_channel_0_core 0 # Number of row misses for write requests per channel per core + [0] 0.0 # +ramulator.write_row_conflicts_channel_0_core 0 # Number of row conflicts for write requests per channel per core + [0] 0.0 # + ramulator.useless_activates_0_core 0 # Number of useless activations. E.g, ACT -> PRE w/o RD or WR + ramulator.read_latency_avg_0 32.641860 # The average memory latency cycles (in memory time domain) per request for all read requests in this channel + ramulator.read_latency_sum_0 14036 # The memory latency cycles (in memory time domain) sum for all read requests in this channel + ramulator.req_queue_length_avg_0 0.000878 # Average of read and write queue length per memory cycle per channel. + ramulator.req_queue_length_sum_0 12379 # Sum of read and write queue length per memory cycle per channel. + ramulator.read_req_queue_length_avg_0 0.000878 # Read queue length average per memory cycle per channel. + ramulator.read_req_queue_length_sum_0 12379 # Read queue length sum per memory cycle per channel. + ramulator.write_req_queue_length_avg_0 0.000000 # Write queue length average per memory cycle per channel. + ramulator.write_req_queue_length_sum_0 0 # Write queue length sum per memory cycle per channel. + ramulator.record_read_hits 0.0 # record read hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_misses 0.0 # record_read_miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_conflicts 0.0 # record read conflict count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_hits 0.0 # record write hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_misses 0.0 # record write miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_conflicts 0.0 # record write conflict for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.dram_capacity 8589934592 # Number of bytes in simulated DRAM + ramulator.dram_cycles 14100133 # Number of DRAM cycles simulated + ramulator.incoming_requests 430 # Number of incoming requests to DRAM + ramulator.read_requests 430 # Number of incoming read requests to DRAM per core + [0] 430.0 # + ramulator.write_requests 0 # Number of incoming write requests to DRAM per core + [0] 0.0 # + ramulator.ramulator_active_cycles 9073 # The total number of cycles that the DRAM part is active (serving R/W) + ramulator.incoming_requests_per_channel 430.0 # Number of incoming requests to each DRAM channel + [0] 430.0 # +ramulator.incoming_read_reqs_per_channel 430.0 # Number of incoming read requests to each DRAM channel + [0] 430.0 # + ramulator.physical_page_replacement 0 # The number of times that physical page replacement happens. + ramulator.maximum_bandwidth 19200000000 # The theoretical maximum bandwidth (Bps) + ramulator.in_queue_req_num_sum 12379 # Sum of read/write queue length + ramulator.in_queue_read_req_num_sum 12379 # Sum of read queue length + ramulator.in_queue_write_req_num_sum 0 # Sum of write queue length + ramulator.in_queue_req_num_avg 0.000878 # Average of read/write queue length per memory cycle + ramulator.in_queue_read_req_num_avg 0.000878 # Average of read queue length per memory cycle + ramulator.in_queue_write_req_num_avg 0.000000 # Average of write queue length per memory cycle + ramulator.record_read_requests 0.0 # record read requests for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_requests 0.0 # record write requests for this core when it reaches request limit or to the end + [0] 0.0 # diff --git a/labs/LAB5/runs/specrand_i-sms1/run.err b/labs/LAB5/runs/specrand_i-sms1/run.err new file mode 100644 index 00000000..e69de29b diff --git a/labs/LAB5/runs/specrand_i-sms1/run.out b/labs/LAB5/runs/specrand_i-sms1/run.out new file mode 100644 index 00000000..453f6d9b --- /dev/null +++ b/labs/LAB5/runs/specrand_i-sms1/run.out @@ -0,0 +1,107 @@ +Scarab gitrev: 7ab9e17 +Scarab started at Sun Jun 11 08:08:38 2023 + +Initialized Ramulator. +** Heartbeat: 1% -- { 1000001 } -- 0.00 KIPS (500.00 KIPS) +** Heartbeat: 2% -- { 2000004 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 3% -- { 3000007 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 4% -- { 4000007 } -- 1000.00 KIPS (571.43 KIPS) +** Heartbeat: 5% -- { 5000009 } -- 500.00 KIPS (555.56 KIPS) +** Heartbeat: 6% -- { 6000012 } -- 500.00 KIPS (545.46 KIPS) +** Heartbeat: 7% -- { 7000015 } -- 500.00 KIPS (538.46 KIPS) +** Heartbeat: 8% -- { 8000015 } -- 1000.00 KIPS (571.43 KIPS) +** Heartbeat: 9% -- { 9000015 } -- 500.00 KIPS (562.50 KIPS) +** Heartbeat: 10% -- { 10000017 } -- 500.00 KIPS (555.56 KIPS) +** Heartbeat: 11% -- { 11000020 } -- 500.00 KIPS (550.00 KIPS) +** Heartbeat: 12% -- { 12000022 } -- 1000.00 KIPS (571.43 KIPS) +** Heartbeat: 13% -- { 13000026 } -- 500.00 KIPS (565.22 KIPS) +** Heartbeat: 14% -- { 14000027 } -- 500.00 KIPS (560.00 KIPS) +** Heartbeat: 15% -- { 15000027 } -- 500.00 KIPS (555.56 KIPS) +** Heartbeat: 16% -- { 16000031 } -- 500.00 KIPS (551.73 KIPS) +** Heartbeat: 17% -- { 17000035 } -- 1000.00 KIPS (566.67 KIPS) +** Heartbeat: 18% -- { 18000035 } -- 500.00 KIPS (562.50 KIPS) +** Heartbeat: 19% -- { 19000038 } -- 500.00 KIPS (558.82 KIPS) +** Heartbeat: 20% -- { 20000040 } -- 500.00 KIPS (555.56 KIPS) +** Heartbeat: 21% -- { 21000042 } -- 1000.00 KIPS (567.57 KIPS) +** Heartbeat: 22% -- { 22000044 } -- 500.00 KIPS (564.10 KIPS) +** Heartbeat: 23% -- { 23000045 } -- 500.00 KIPS (560.98 KIPS) +** Heartbeat: 24% -- { 24000047 } -- 500.00 KIPS (558.14 KIPS) +** Heartbeat: 25% -- { 25000048 } -- 1000.00 KIPS (568.18 KIPS) +** Heartbeat: 26% -- { 26000049 } -- 500.00 KIPS (565.22 KIPS) +** Heartbeat: 27% -- { 27000052 } -- 500.00 KIPS (562.50 KIPS) +** Heartbeat: 28% -- { 28000054 } -- 500.00 KIPS (560.00 KIPS) +** Heartbeat: 29% -- { 29000057 } -- 1000.00 KIPS (568.63 KIPS) +** Heartbeat: 30% -- { 30000061 } -- 500.00 KIPS (566.04 KIPS) +** Heartbeat: 31% -- { 31000062 } -- 500.00 KIPS (563.64 KIPS) +** Heartbeat: 32% -- { 32000063 } -- 500.00 KIPS (561.40 KIPS) +** Heartbeat: 33% -- { 33000066 } -- 1000.00 KIPS (568.97 KIPS) +** Heartbeat: 34% -- { 34000068 } -- 500.00 KIPS (566.67 KIPS) +** Heartbeat: 35% -- { 35000069 } -- 500.00 KIPS (564.52 KIPS) +** Heartbeat: 36% -- { 36000070 } -- 500.00 KIPS (562.50 KIPS) +** Heartbeat: 37% -- { 37000074 } -- 1000.00 KIPS (569.23 KIPS) +** Heartbeat: 38% -- { 38000075 } -- 500.00 KIPS (567.17 KIPS) +** Heartbeat: 39% -- { 39000079 } -- 500.00 KIPS (565.22 KIPS) +** Heartbeat: 40% -- { 40000081 } -- 500.00 KIPS (563.38 KIPS) +** Heartbeat: 41% -- { 41000081 } -- 1000.00 KIPS (569.45 KIPS) +** Heartbeat: 42% -- { 42000082 } -- 500.00 KIPS (567.57 KIPS) +** Heartbeat: 43% -- { 43000085 } -- 500.00 KIPS (565.79 KIPS) +** Heartbeat: 44% -- { 44000089 } -- 500.00 KIPS (564.10 KIPS) +** Heartbeat: 45% -- { 45000091 } -- 1000.00 KIPS (569.62 KIPS) +** Heartbeat: 46% -- { 46000096 } -- 500.00 KIPS (567.90 KIPS) +** Heartbeat: 47% -- { 47000098 } -- 500.00 KIPS (566.27 KIPS) +** Heartbeat: 48% -- { 48000098 } -- 500.00 KIPS (564.71 KIPS) +** Heartbeat: 49% -- { 49000103 } -- 1000.00 KIPS (569.77 KIPS) +** Heartbeat: 50% -- { 50000107 } -- 500.00 KIPS (568.18 KIPS) +** Heartbeat: 51% -- { 51000111 } -- 500.00 KIPS (566.67 KIPS) +** Heartbeat: 52% -- { 52000116 } -- 500.00 KIPS (565.22 KIPS) +** Heartbeat: 53% -- { 53000116 } -- 1000.00 KIPS (569.89 KIPS) +** Heartbeat: 54% -- { 54000118 } -- 500.00 KIPS (568.42 KIPS) +** Heartbeat: 55% -- { 55000122 } -- 500.00 KIPS (567.01 KIPS) +** Heartbeat: 56% -- { 56000123 } -- 500.00 KIPS (565.66 KIPS) +** Heartbeat: 57% -- { 57000125 } -- 1000.00 KIPS (570.00 KIPS) +** Heartbeat: 58% -- { 58000125 } -- 500.00 KIPS (568.63 KIPS) +** Heartbeat: 59% -- { 59000130 } -- 500.00 KIPS (567.31 KIPS) +** Heartbeat: 60% -- { 60000130 } -- 500.00 KIPS (566.04 KIPS) +** Heartbeat: 61% -- { 61000131 } -- 1000.00 KIPS (570.09 KIPS) +** Heartbeat: 62% -- { 62000133 } -- 500.00 KIPS (568.81 KIPS) +** Heartbeat: 63% -- { 63000136 } -- 500.00 KIPS (567.57 KIPS) +** Heartbeat: 64% -- { 64000140 } -- 500.00 KIPS (566.37 KIPS) +** Heartbeat: 65% -- { 65000142 } -- 1000.00 KIPS (570.18 KIPS) +** Heartbeat: 66% -- { 66000142 } -- 500.00 KIPS (568.97 KIPS) +** Heartbeat: 67% -- { 67000146 } -- 500.00 KIPS (567.80 KIPS) +** Heartbeat: 68% -- { 68000149 } -- 500.00 KIPS (566.67 KIPS) +** Heartbeat: 69% -- { 69000153 } -- 500.00 KIPS (565.58 KIPS) +** Heartbeat: 70% -- { 70000157 } -- 1000.00 KIPS (569.11 KIPS) +** Heartbeat: 71% -- { 71000157 } -- 500.00 KIPS (568.00 KIPS) +** Heartbeat: 72% -- { 72000157 } -- 500.00 KIPS (566.93 KIPS) +** Heartbeat: 73% -- { 73000159 } -- 500.00 KIPS (565.89 KIPS) +** Heartbeat: 74% -- { 74000162 } -- 1000.00 KIPS (569.23 KIPS) +** Heartbeat: 75% -- { 75000163 } -- 500.00 KIPS (568.18 KIPS) +** Heartbeat: 76% -- { 76000165 } -- 500.00 KIPS (567.17 KIPS) +** Heartbeat: 77% -- { 77000165 } -- 500.00 KIPS (566.18 KIPS) +** Heartbeat: 78% -- { 78000168 } -- 500.00 KIPS (565.22 KIPS) +** Heartbeat: 79% -- { 79000172 } -- 1000.00 KIPS (568.35 KIPS) +** Heartbeat: 80% -- { 80000174 } -- 500.00 KIPS (567.38 KIPS) +** Heartbeat: 81% -- { 81000174 } -- 500.00 KIPS (566.43 KIPS) +** Heartbeat: 82% -- { 82000176 } -- 500.00 KIPS (565.52 KIPS) +** Heartbeat: 83% -- { 83000176 } -- 500.00 KIPS (564.63 KIPS) +** Heartbeat: 84% -- { 84000176 } -- 1000.00 KIPS (567.57 KIPS) +** Heartbeat: 85% -- { 85000176 } -- 500.00 KIPS (566.67 KIPS) +** Heartbeat: 86% -- { 86000177 } -- 500.00 KIPS (565.79 KIPS) +** Heartbeat: 87% -- { 87000182 } -- 500.00 KIPS (564.94 KIPS) +** Heartbeat: 88% -- { 88000187 } -- 1000.00 KIPS (567.74 KIPS) +** Heartbeat: 89% -- { 89000189 } -- 500.00 KIPS (566.88 KIPS) +** Heartbeat: 90% -- { 90000189 } -- 500.00 KIPS (566.04 KIPS) +** Heartbeat: 91% -- { 91000191 } -- 500.00 KIPS (565.22 KIPS) +** Heartbeat: 92% -- { 92000194 } -- 500.00 KIPS (564.42 KIPS) +** Heartbeat: 93% -- { 93000195 } -- 1000.00 KIPS (567.07 KIPS) +** Heartbeat: 94% -- { 94000195 } -- 500.00 KIPS (566.27 KIPS) +** Heartbeat: 95% -- { 95000199 } -- 500.00 KIPS (565.48 KIPS) +** Heartbeat: 96% -- { 96000202 } -- 500.00 KIPS (564.71 KIPS) +** Heartbeat: 97% -- { 97000205 } -- 500.00 KIPS (563.95 KIPS) +** Heartbeat: 98% -- { 98000207 } -- 1000.00 KIPS (566.48 KIPS) +** Heartbeat: 99% -- { 99000207 } -- 500.00 KIPS (565.72 KIPS) +** Core 0 Finished: insts:100000004 cycles:37600340 time:11750106250000 -- 2.66 IPC (2.66 IPC) -- N/A KIPS (564.97 KIPS) +done +Scarab finished at Sun Jun 11 08:11:35 2023 + diff --git a/labs/LAB5/runs/specrand_i-sms1/stream.stat.0.out b/labs/LAB5/runs/specrand_i-sms1/stream.stat.0.out new file mode 100644 index 00000000..7558b0ec --- /dev/null +++ b/labs/LAB5/runs/specrand_i-sms1/stream.stat.0.out @@ -0,0 +1,188 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 37600340 Instructions: 100000004 IPC: 2.65955 + +DCACHE_PREF_HIT 0 0 + +IFETCH_WB_FIRST_SCHEDULE 0 -nan% 0 -nan% +PREFETCH_LAST_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_PREF_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_LOW_OP_SCHEDULE 0 -nan% 0 -nan% +DEMAND_LAST_SCHEDULE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +SEND_MISS_REQ_QUEUE 430 430 + +L1_DATA_EVICT 0 0 + +STREAM_BUFFER_REQ 0 0 + +PREF_SEND_TO_MEM_REQ 0 -nan% 0 -nan% +PREF_SEND_TO_MEM_REQ_FAIL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +HIT_TRAIN_STREAM 83 52.866% 83 52.866% +MISS_TRAIN_STREAM 74 47.134% 74 47.134% + 157 100.000% 157 100.000% + 0.47 0.49 0.47 0.49 + +STREAM_TRAIN_CREATE 31 31 + +MEM_REQ_MISS_HWP_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_SW_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_IFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DSTORE_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DPRF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_WB_Q 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_BY_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_WB 0 -nan% 0 -nan% +PREF_HIT_BY_PREF 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_WB 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_L1_FILL 0 -nan% 0 -nan% +DEMAND_L1_FILL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TOUCH_L1_REPLACE 0 -nan% 0 -nan% +NO_TOUCH_L1_REPLACE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_REQ_QUE_FULL 0 0 + +STREAM_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +L2HIT_STREAM_PREF_REQ_QUE_FULL 0 0 + +L2HIT_HIT_TRAIN_STREAM 0 -nan% 0 -nan% +L2HIT_MISS_TRAIN_STREAM 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_TRAIN_CREATE 0 0 + +L2HIT_STREAM_BUFFER_REQ 0 0 + +L2HIT_STREAM_PREF_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_STREAM_PREF_DCACHE_INSERT 0 -nan% 0 -nan% +L2HIT_STREAM_L2_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_DCACHE_PORT_FULL 0 0 + +L2HIT_STREAM_PREF_L1_PORT_FULL 0 0 + +L2HIT_TRAIN_HIT_DEMAND 0 -nan% 0 -nan% +L2HIT_TRAIN_MISS_REQ 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_TRAIN_FILTER_MISS 0 -nan% 0 -nan% +L2HIT_TRAIN_FILTER_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_PREF_REQ_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_PREF_REQ_DCACHE_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_L2SEND_Q_FULL 0 -nan% 0 -nan% +L2HIT_L2SEND_Q_ENTER 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_MEM_REQ 0 0 + +REMOVE_REDUNDANT_STREAM_STAT 0 0 + +REPLACE_OLD_STREAM 15 15 + +REQ_SEND_QUEUE_STALL 0 0 + +STREAM_ENTER_RA 0 0 + +CORE_STREAM_LENGTH_0 3 37.500% 3 37.500% +CORE_STREAM_LENGTH_10 3 37.500% 3 37.500% +CORE_STREAM_LENGTH_20 0 0.000% 0 0.000% +CORE_STREAM_LENGTH_30 0 0.000% 0 0.000% +CORE_STREAM_LENGTH_40 1 12.500% 1 12.500% +CORE_STREAM_LENGTH_50 0 0.000% 0 0.000% +CORE_STREAM_LENGTH_60 1 12.500% 1 12.500% +CORE_STREAM_LENGTH_70 0 0.000% 0 0.000% +CORE_STREAM_LENGTH_80 0 0.000% 0 0.000% +CORE_STREAM_LENGTH_90 0 0.000% 0 0.000% +CORE_STREAM_LENGTH_100_P 0 0.000% 0 0.000% + 8 100.000% 8 100.000% + 1.62 1.93 1.62 1.93 + +CORE_CUM_STREAM_LENGTH_0 17 10.241% 17 10.241% +CORE_CUM_STREAM_LENGTH_10 41 24.699% 41 24.699% +CORE_CUM_STREAM_LENGTH_20 0 0.000% 0 0.000% +CORE_CUM_STREAM_LENGTH_30 0 0.000% 0 0.000% +CORE_CUM_STREAM_LENGTH_40 48 28.916% 48 28.916% +CORE_CUM_STREAM_LENGTH_50 0 0.000% 0 0.000% +CORE_CUM_STREAM_LENGTH_60 60 36.145% 60 36.145% +CORE_CUM_STREAM_LENGTH_70 0 0.000% 0 0.000% +CORE_CUM_STREAM_LENGTH_80 0 0.000% 0 0.000% +CORE_CUM_STREAM_LENGTH_90 0 0.000% 0 0.000% +CORE_CUM_STREAM_LENGTH_100_P 0 0.000% 0 0.000% + 166 100.000% 166 100.000% + 3.57 1.96 3.57 1.96 + +CORE_STREAM_TRAIN_HITS_0 6 75.000% 6 75.000% +CORE_STREAM_TRAIN_HITS_10 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_20 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_30 1 12.500% 1 12.500% +CORE_STREAM_TRAIN_HITS_40 1 12.500% 1 12.500% +CORE_STREAM_TRAIN_HITS_50 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_60 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_70 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_80 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_90 0 0.000% 0 0.000% +CORE_STREAM_TRAIN_HITS_100_P 0 0.000% 0 0.000% + 8 100.000% 8 100.000% + 0.88 1.43 0.88 1.43 + +CORE_CUM_STREAM_TRAIN_HITS_0 39 33.913% 39 33.913% +CORE_CUM_STREAM_TRAIN_HITS_10 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_20 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_30 32 27.826% 32 27.826% +CORE_CUM_STREAM_TRAIN_HITS_40 44 38.261% 44 38.261% +CORE_CUM_STREAM_TRAIN_HITS_50 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_60 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_70 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_80 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_90 0 0.000% 0 0.000% +CORE_CUM_STREAM_TRAIN_HITS_100_P 0 0.000% 0 0.000% + 115 100.000% 115 100.000% + 2.37 1.07 2.37 1.07 + +CORE_STREAM_TRAIN_CREATE 31 31 + + + diff --git a/labs/LAB5/runs/x264-sms0/PARAMS.in b/labs/LAB5/runs/x264-sms0/PARAMS.in new file mode 100644 index 00000000..2593c2b8 --- /dev/null +++ b/labs/LAB5/runs/x264-sms0/PARAMS.in @@ -0,0 +1,226 @@ +# File : PARAMS.kaby_lake +# Date : 03/06/19 +# Description : Kaby Lake Configuration +# +# Based on documentation found here: +# https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake + +## Simulation Parameters +--mode full +--model cmp +--sim_limit none + +## Core Parameters + +# Femptoseconds, 3.2GHz, used for energy estimates. +--chip_cycle_time 312500 + + +### Fetch Stage +--fetch_off_path_ops 1 +--fetch_across_cache_lines 1 + +# Will break the packet upon a taken branch. +--fetch_break_on_taken 1 + +# Number of bubble cycles to wait after taken branch. +--fetch_taken_bubble_cycles 0 + + +#### ICache +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 + +### Branch Predictor +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_mech tagescl + + +#### BTB + +# BTB model to use. +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 + +# Allow the BTB to be updated by off path ops. +--btb_off_path_writes 1 + + +#### CRS + +# Enable return stack +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 + +### iBP +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged + # iBTB Model. tc_tagless, tc_tagged, tc_hybrid. +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 + +### Decode Stage +--decode_cycles 5 + + +### Map Stage +--map_cycles 5 + + +### Issue Stage + +# Max number of instructions to be fetched, decoded, renamed, and issued per cycle. +--issue_width 6 + +--rs_fill_width 0 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 + + +### Exec Stage + +### DCache +--dcache_size 32768 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--dcache_assoc 4 +--dcache_line_size 64 + +### Reorder/Retire Stage + +# Max number of instructions to be retired per cycle. +--node_ret_width 6 +--node_table_size 224 + +# Do not keep stores in RSVs on cache misses; TODO: confirm what this knob does +--stores_do_not_block_window 1 + +# TODO: confirm what this knob does +--prefs_do_not_block_window 1 + + +## Uncore + +### Mid-level cache + +# Enable use of a midlevel cache between i/d and L1 +--mlc_present 0 + +### LLC +--l1_size 1048576 +--l1_banks 1 +--l1_cycles 18 +--l1_assoc 8 +--l1_line_size 64 +--l1_interleave_factor 64 + + +### Prefetcher +--pref_framework_on 1 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--pref_shared_queues 0 +--pref_train_on_pref_misses 0 +--pref_oracle_train 0 +--pref_ul1req_queue_overwrite_on_full 1 + +--stream_length 64 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 + +--pref_throttlefb_on=1 +--pref_acc_thresh_1=0.75 +--pref_acc_thresh_2=0.4 +--pref_acc_thresh_3=0.4 +--pref_timely_thresh=0.01 +--pref_polpf_thresh=0.005 +--pref_update_interval=8192 + +--mem_req_buffer_pref_watermark 4 +--promote_to_higher_priority_mem_req_type 1 + +### Memory +--addr_translation random + +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 + +--mem_req_buffer_entries 32 +--mem_l1_fill_queue_entries 32 +--va_page_size_bytes 4096 +--bus_width_in_bytes 8 + +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 + +## Other + + +### Debug +--debug_inst_start 0 +--debug_inst_stop -1 +--debug_cycle_start 0 +--debug_cycle_stop -1 + + +## Stats and Params +--dump_params 1 +--dump_stats 1 +--dump_trace 0 + +#################################### +--set_off_path_confirmed 1 + +--order_beyond_bus 1 + +--mem_ooo_stores 1 +--mem_obey_store_dep 1 diff --git a/labs/LAB5/runs/x264-sms0/PARAMS.out b/labs/LAB5/runs/x264-sms0/PARAMS.out new file mode 100644 index 00000000..b5e1155e --- /dev/null +++ b/labs/LAB5/runs/x264-sms0/PARAMS.out @@ -0,0 +1,908 @@ +--mode full +--model cmp +--frontend memtrace +--inst_limit 100000000 +--sim_limit none +--dump_params 1 +--dump_stats 1 +--dump_trace 0 +--mlc_present 0 +--l1_size 1048576 +--l1_assoc 8 +--l1_line_size 64 +--l1_cycles 18 +--l1_banks 1 +--l1_interleave_factor 64 +--va_page_size_bytes 4096 +--addr_translation random +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 +--dcache_size 32768 +--dcache_assoc 4 +--dcache_line_size 64 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--mem_ooo_stores 1 +--mem_obey_store_dep 1 +--mem_req_buffer_entries 32 +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 +--promote_to_higher_priority_mem_req_type 1 +--mem_req_buffer_pref_watermark 4 +--mem_l1_fill_queue_entries 32 +--order_beyond_bus 1 +--set_off_path_confirmed 1 +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--bus_width_in_bytes 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 +--chip_cycle_time 312500 +--issue_width 6 +--rs_fill_width 0 +--node_table_size 224 +--node_ret_width 6 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 +--decode_cycles 5 +--map_cycles 5 +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--fetch_across_cache_lines 1 +--fetch_off_path_ops 0 +--fetch_break_on_taken 1 +--fetch_taken_bubble_cycles 0 +--stores_do_not_block_window 1 +--prefs_do_not_block_window 1 +--cbp_trace_r0 /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir/trace/drmemtrace.x264.555077.8068.trace.gz +--memtrace_modules_log /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir/raw +--debug_cycle_start 0 +--debug_cycle_stop -1 +--debug_inst_start 0 +--debug_inst_stop -1 +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--bp_mech tagescl +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 +--btb_off_path_writes 1 +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_length 64 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 +--pref_framework_on 1 +--pref_shared_queues 0 +--pref_ul1req_queue_overwrite_on_full 1 +--pref_train_on_pref_misses 0 +--pref_oracle_train_on 0 +--pref_throttlefb_on 1 +--pref_acc_thresh_1 0.75 +--pref_acc_thresh_2 0.4 +--pref_acc_thresh_3 0.4 +--pref_update_interval 8192 +--pref_timely_thresh 0.01 +--pref_polpf_thresh 0.005 +--pref_sms_on 0 +1 1 1 1 1 1 1 + +--- Cut out everything below to use this file as PARAMS.in --- + +Parameter status at compile time and values supplied on the command line: + +SIM_MODE 0 full +SIM_MODEL 0 cmp +FRONTEND FE_PIN_EXEC_DRIVEN memtrace +INST_LIMIT NULL 100000000 +SIM_LIMIT "none" none +FORWARD_PROGRESS_LIMIT 100000000 +FORWARD_PROGRESS_INTERVAL 10000 +FAST_FORWARD 0 +FAST_FORWARD_UNTIL_ADDR 0 +FAST_FORWARD_TRACE_INS 0 +WARMUP 0 +HEARTBEAT_INTERVAL 1000000 +NUM_HEARTBEATS 0 +FILE_TAG "" +OUTPUT_DIR "." +STATUS_FILE NULL +BINDIR NULL +DUMP_PARAMS TRUE 1 +DUMP_STATS TRUE 1 +DUMP_TRACE FALSE 0 +CLEAR_STATS "never" +STATS_TO_TRACE NULL +STAT_TRACE_FILE "stats.trace" +STAT_TRACE_INTERVAL "i:100000" +PIPEVIEW FALSE +PIPEVIEW_FILE "pipeview" +MEMVIEW FALSE +MEMVIEW_FILE "memview.out" +MEMVIEW_START "never" +INST_HASH_TABLE_SIZE 500021 const +STDOUT_FILE NULL +STDERR_FILE NULL +PIN_EXEC_DRIVEN_FE_SOCKET "./pin_exec_driven_fe_socket.temp" +PRINT_PID FALSE +USE_UNSURE_FREE_LISTS FALSE +OPTIMIZER2_MAX_NUM_SLAVES 64 +OPTIMIZER2_PERFECT_MEMORYLESS FALSE +EXIT_COND 0 +ENABLE_SWPRF FALSE +MLC_PRESENT FALSE 0 +MLC_SIZE (512 * 1024) +MLC_ASSOC 4 +MLC_LINE_SIZE 64 +MLC_CYCLES 12 +PERFECT_MLC FALSE +MLC_READ_PORTS 1 +MLC_WRITE_PORTS 1 +MLC_BANKS 8 +MLC_INTERLEAVE_FACTOR 64 +MLC_CACHE_REPL_POLICY 0 +MLC_WRITE_THROUGH FALSE +PREFETCH_UPDATE_LRU_MLC TRUE +FORCE_L1_MISS FALSE +L1_SIZE (4 * 1024 * 1024) 1048576 +L1_ASSOC 8 8 +L1_LINE_SIZE 64 64 +L1_CYCLES 24 18 +PERFECT_L1 FALSE +PRIVATE_L1 FALSE +L1_READ_PORTS 1 +L1_WRITE_PORTS 1 +L1_BANKS 8 1 +L1_INTERLEAVE_FACTOR 64 64 +L1_CACHE_REPL_POLICY 0 +L1_WRITE_THROUGH FALSE +L1_IGNORE_WB FALSE +L1_USE_CORE_FREQ FALSE +MARK_L1_MISSES TRUE +PREFETCH_UPDATE_LRU_L1 TRUE +MEMORY_RANDOM_ADDR FALSE +VA_PAGE_SIZE_BYTES 4096 4096 +NUM_ADDR_NON_SIGN_EXTEND_BITS 48 +ADDR_TRANSLATION 0 random +CONSTANT_MEMORY_LATENCY FALSE +MEMORY_CYCLES 100 +STALL_MEM_REQS_ONLY FALSE +ICACHE_SIZE (64 * 1024) 32768 +ICACHE_ASSOC 4 4 +ICACHE_LINE_SIZE 64 64 +PERFECT_ICACHE FALSE +ICACHE_READ_PORTS 2 +ICACHE_WRITE_PORTS 1 +ICACHE_BANKS 8 +ICACHE_REPL 0 +DCACHE_SIZE (64 * 1024) 32768 +DCACHE_ASSOC 1 4 +DCACHE_LINE_SIZE 64 64 +DCACHE_CYCLES 2 +PERFECT_DCACHE FALSE +DCACHE_READ_PORTS 8 2 +DCACHE_WRITE_PORTS 1 1 +DCACHE_BANKS 1 1 +DCACHE_REPL 0 +DCACHE_REPL_PREF_THRESH 1 +MEM_OOO_STORES TRUE 1 +MEM_OBEY_STORE_DEP TRUE 1 +PREF_INSERT_LRU FALSE +PREF_INSERT_MIDDLE FALSE +PREF_INSERT_LOWQTR FALSE +PREF_INSERT_DYNACC FALSE +MEM_REQ_BUFFER_ENTRIES 32 32 +PRIVATE_MSHR_ON TRUE +MEM_PRIORITY_IFETCH 0 0 +MEM_PRIORITY_DFETCH 0 1 +MEM_PRIORITY_DSTORE 0 2 +MEM_PRIORITY_IPRF 9 3 +MEM_PRIORITY_DPRF 10 4 +MEM_PRIORITY_WB 0 5 +MEM_PRIORITY_WB_NODIRTY 0 5 +PROMOTE_TO_HIGHER_PRIORITY_MEM_REQ_TYPE FALSE 1 +MEM_REQ_BUFFER_PREF_WATERMARK 0 4 +MEM_REQ_BUFFER_WB_VALVE 2 +MEM_L1_FILL_QUEUE_ENTRIES 32 32 +MEM_BUS_OUT_QUEUE_PARTITION_ENABLE FALSE +MEM_MEM_QUEUE_PARTITION_ENABLE FALSE +MEM_BUS_OUT_QUEUE_AS_FIFO TRUE +OLDEST_FIRST_TO_MEM_QUEUE TRUE +ROUND_ROBIN_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE_TH 0 +L1_CYCLE_TIME 312500 +MLCQ_TO_L1Q_TRANSFER_LATENCY 1 +L1Q_TO_FSB_TRANSFER_LATENCY 1 +PRIORITIZE_PREFETCHES_WITH_UNIQUE FALSE +KICKOUT_PREFETCHES FALSE +KICKOUT_LOOK_FOR_OLDEST_FIRST FALSE +KICKOUT_OLDEST_PREFETCH FALSE +KICKOUT_OLDEST_PREFETCH_WITHIN_BANK FALSE +ORDER_BEYOND_BUS FALSE 1 +ALL_FIFO_QUEUES FALSE +QUEUE_MLC_SIZE 0 +QUEUE_L1_SIZE 0 +QUEUE_BUS_OUT_SIZE 0 +QUEUE_CORE_FILL_SIZE 0 +ALLOW_TYPE_MATCHES FALSE +STREAM_PREFETCH_ON FALSE +DC_PREF_CACHE_ENABLE FALSE +DC_PREF_CACHE_CYCLE 0 +PREF_INSERT_DCACHE_IMM TRUE +DC_PREF_CACHE_SIZE (64 * 1024) +DC_PREF_CACHE_ASSOC 4 +DC_PREF_ONLY_L1HIT FALSE +PREF_CACHE_USE_RDY_CYCLE FALSE +IC_PREF_CACHE_ENABLE FALSE +IC_PREF_CACHE_SIZE (64 * 1024) +IC_PREF_CACHE_ASSOC 4 +L1_PREF_CACHE_ENABLE FALSE +L1_PREF_CACHE_SIZE (1024 * 1024) +L1_PREF_CACHE_ASSOC 8 +SET_OFF_PATH_CONFIRMED FALSE 1 +USE_CONFIRMED_OFF FALSE +PREFCACHE_MOVE_OFFPATH FALSE +CACHE_STAT_ENABLE FALSE +PREF_DCACHE_HIT_FILL_L1 TRUE +PREF_ICACHE_HIT_FILL_L1 TRUE +CRITICAL_ACCESS_PLOT_ENABLE FALSE +CRITICAL_ACCESS_PLOT_FILE "critical_access_plot.dat" +ROUND_ROBIN_TO_L1 FALSE +PREF_I_TOGETHER FALSE +ONE_MORE_CACHE_LINE_ENABLE FALSE +L1_STATIC_PARTITION_ENABLE 0 +L1_STATIC_PARTITION NULL +L1_DYNAMIC_PARTITION_ENABLE FALSE +L1_DYNAMIC_PARTITION_POLICY 0 +PARTITION_UMON_DSS_PREF_ENABLE FALSE +L1_CACHE_HIT_POSITION_COLLECT FALSE +L1_PART_ON FALSE +L1_PART_TRIGGER "c:1000000" +L1_PART_START "t:0" +L1_PART_WARMUP FALSE +L1_PART_SHADOW_WARMUP FALSE +L1_PART_METRIC 0 +L1_PART_SEARCH 0 +L1_PART_USE_STALLING TRUE +L1_PART_FILL_DELAY 0 +L1_SHADOW_TAGS_MODULO 1 +HIER_MSHR_ON FALSE +PERF_PRED_ENABLE FALSE +PERF_PRED_MECH PERF_PRED_CP +PERF_PRED_REQ_LATENCY_MECH PERF_PRED_REQ_LATENCY_MECH_REQ_LATENCY +PERF_PRED_COUNT_ALL FALSE +PERF_PRED_COUNT_INST_MISSES TRUE +PERF_PRED_COUNT_PREFETCHES FALSE +PERF_PRED_COUNT_OFFPATH_REQS FALSE +PERF_PRED_COUNT_BW_REQS TRUE +PERF_PRED_UPDATE_MEM_REQ_TYPE FALSE +PERF_PRED_SLACK_PERIOD_SIZE 32 +PERF_PRED_REQS_FINISH_AT_FILL FALSE +PERF_PRED_MEM_UTIL_VIA_BUS_BW FALSE +PERF_PRED_CHIP_UTIL_VIA_MEM_STALL FALSE +DUMB_MODEL_AVG_REQ_DISTANCE 100 +DUMB_MODEL_RANDOMIZE_DISTANCE FALSE +DUMB_MODEL_AVG_REQ_DISTANCE_PER_CORE NULL +DUMB_MODEL_AVG_ROW_HITS 1 +DUMB_MODEL_AVG_ROW_HITS_PER_CORE NULL +DUMB_MODEL_MLP 1 +DUMB_MODEL_MLP_PER_CORE NULL +RAMULATOR_STANDARD "DDR4" DDR4 +RAMULATOR_SPEED "DDR4_2400R" DDR4_2400R +RAMULATOR_ORG "DDR4_8Gb_x8" DDR4_8Gb_x8 +RAMULATOR_CHANNELS 1 1 +RAMULATOR_RANKS 1 1 +RAMULATOR_BANKGROUPS 4 4 +RAMULATOR_BANKS 4 4 +RAMULATOR_CHIP_WIDTH 8 8 +BUS_WIDTH_IN_BYTES 8 8 +RAMULATOR_ROWS 65536 65536 +RAMULATOR_COLS 1024 1024 +RAMULATOR_SCHEDULING_POLICY "FRFCFS_Cap" FRFCFS_Cap +RAMULATOR_READQ_ENTRIES 32 32 +RAMULATOR_WRITEQ_ENTRIES 32 32 +RAMULATOR_REC_CMD_TRACE "off" FALSE +RAMULATOR_PRINT_CMD_TRACE "off" FALSE +RAMULATOR_USE_REST_OF_ADDR_AS_ROW_ADDR "on" +RAMULATOR_TCK 833333 833333 +RAMULATOR_TCL 16 16 +RAMULATOR_TCCD 6 6 +RAMULATOR_TCCDS 4 4 +RAMULATOR_TCCDL 6 6 +RAMULATOR_TCWL 12 12 +RAMULATOR_TBL 4 4 +RAMULATOR_TWTR 9 9 +RAMULATOR_TWTRS 3 3 +RAMULATOR_TWTRL 9 9 +RAMULATOR_TRP 16 16 +RAMULATOR_TRPpb 16 16 +RAMULATOR_TRPab 16 16 +RAMULATOR_TRCD 16 16 +RAMULATOR_TRCDR 16 16 +RAMULATOR_TRCDW 16 16 +RAMULATOR_TRAS 39 39 +DRAM_TECH_IN_NM 32 32 +DVFS_ON FALSE +DVFS_METRIC DVFS_METRIC_NUM_ELEMS +DVFS_CONFIGS NULL +DVFS_CONFIG_FILE NULL +DVFS_START "t:0" +DVFS_PERIOD "t:312500000000" +DVFS_LOG TRUE +DVFS_INDIVIDUAL_CORES FALSE +DVFS_CHIP_LEVEL FALSE +DVFS_STATIC NULL +DVFS_FORCE_CONFIG NULL +DVFS_REPLAY_CONFIG_TRACE NULL +DVFS_USE_ORACLE FALSE +DVFS_USE_BW_SHARING FALSE +DVFS_USE_DRAM_SHARING FALSE +DVFS_USE_STALL_TIME FALSE +DVFS_DRAM_SHARING_SOLVER_BIN NULL +DVFS_DRAM_SHARING_SOLVER_STRICT TRUE +DVFS_BW_SHARING_BUS_UTIL_THRESH 0.95 +DVFS_BW_SHARING_MAX_REQS 28.0 +DVFS_BW_SHARING_MAX_RW_COST 0.25 +DVFS_BW_SHARING_NO_PREF_STALL TRUE +DVFS_BW_SHARING_CRIT_STATS TRUE +DVFS_COUNT_L1_ACCESS_STALL FALSE +NUM_CORES 1 +CHIP_CYCLE_TIME 312500 312500 +CORE_0_CYCLE_TIME 312500 +CORE_1_CYCLE_TIME 312500 +CORE_2_CYCLE_TIME 312500 +CORE_3_CYCLE_TIME 312500 +CORE_4_CYCLE_TIME 312500 +CORE_5_CYCLE_TIME 312500 +CORE_6_CYCLE_TIME 312500 +CORE_7_CYCLE_TIME 312500 +CORE_8_CYCLE_TIME 312500 +CORE_9_CYCLE_TIME 312500 +CORE_10_CYCLE_TIME 312500 +CORE_11_CYCLE_TIME 312500 +CORE_12_CYCLE_TIME 312500 +CORE_13_CYCLE_TIME 312500 +CORE_14_CYCLE_TIME 312500 +CORE_15_CYCLE_TIME 312500 +CORE_16_CYCLE_TIME 312500 +CORE_17_CYCLE_TIME 312500 +CORE_18_CYCLE_TIME 312500 +CORE_19_CYCLE_TIME 312500 +CORE_20_CYCLE_TIME 312500 +CORE_21_CYCLE_TIME 312500 +CORE_22_CYCLE_TIME 312500 +CORE_23_CYCLE_TIME 312500 +CORE_24_CYCLE_TIME 312500 +CORE_25_CYCLE_TIME 312500 +CORE_26_CYCLE_TIME 312500 +CORE_27_CYCLE_TIME 312500 +CORE_28_CYCLE_TIME 312500 +CORE_29_CYCLE_TIME 312500 +CORE_30_CYCLE_TIME 312500 +CORE_31_CYCLE_TIME 312500 +CORE_32_CYCLE_TIME 312500 +CORE_33_CYCLE_TIME 312500 +CORE_34_CYCLE_TIME 312500 +CORE_35_CYCLE_TIME 312500 +CORE_36_CYCLE_TIME 312500 +CORE_37_CYCLE_TIME 312500 +CORE_38_CYCLE_TIME 312500 +CORE_39_CYCLE_TIME 312500 +CORE_40_CYCLE_TIME 312500 +CORE_41_CYCLE_TIME 312500 +CORE_42_CYCLE_TIME 312500 +CORE_43_CYCLE_TIME 312500 +CORE_44_CYCLE_TIME 312500 +CORE_45_CYCLE_TIME 312500 +CORE_46_CYCLE_TIME 312500 +CORE_47_CYCLE_TIME 312500 +CORE_48_CYCLE_TIME 312500 +CORE_49_CYCLE_TIME 312500 +CORE_50_CYCLE_TIME 312500 +CORE_51_CYCLE_TIME 312500 +CORE_52_CYCLE_TIME 312500 +CORE_53_CYCLE_TIME 312500 +CORE_54_CYCLE_TIME 312500 +CORE_55_CYCLE_TIME 312500 +CORE_56_CYCLE_TIME 312500 +CORE_57_CYCLE_TIME 312500 +CORE_58_CYCLE_TIME 312500 +CORE_59_CYCLE_TIME 312500 +CORE_60_CYCLE_TIME 312500 +CORE_61_CYCLE_TIME 312500 +CORE_62_CYCLE_TIME 312500 +CORE_63_CYCLE_TIME 312500 +ISSUE_WIDTH 4 6 +RS_FILL_WIDTH 8 0 +NODE_TABLE_SIZE 256 224 +NODE_RET_WIDTH 4 6 +NODE_RETIRE_RATE 10 +RS_SIZES "256" 97 +RS_CONNECTIONS "xF" 0 +FU_TYPES "0, 0, 0, 0" 0 0 0 0 0 0 0 0 +DECODE_CYCLES 1 5 +MAP_CYCLES 1 5 +EXTRA_RECOVERY_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after recovery. +EXTRA_REDIRECT_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after redirect. +EXTRA_CALLSYS_CYCLES 20 const +DIE_ON_CALLSYS FALSE +DIE_ON_RET_STALL_THRESH 0 +DIE_ON_RET_STALL_CORE 0 +DIE_ON_MEM_BLOCK_THRESH 0 +DIE_ON_MEM_BLOCK_CORE 0 +FETCH_ACROSS_CACHE_LINES FALSE 1 +FETCH_OFF_PATH_OPS TRUE 0 +FETCH_BREAK_ON_TAKEN FALSE 1 +FETCH_TAKEN_BUBBLE_CYCLES 0 0 +WP_COLLECT_STATS FALSE +SWITCH_IC_FETCH_ON_RECOVERY TRUE +OP_INV_DELAY 1 +OP_NOP_DELAY 1 +OP_CF_DELAY 1 +OP_MOV_DELAY 1 +OP_CMOV_DELAY 1 +OP_LDA_DELAY 1 +OP_IMEM_DELAY 1 +OP_IADD_DELAY 1 +OP_IMUL_DELAY 3 +OP_IDIV_DELAY -20 +OP_ICMP_DELAY 1 +OP_LOGIC_DELAY 1 +OP_SHIFT_DELAY 1 +OP_FMEM_DELAY 1 +OP_FCVT_DELAY 3 +OP_FADD_DELAY 3 +OP_FMUL_DELAY 5 +OP_FMA_DELAY 5 +OP_FDIV_DELAY -20 +OP_FCMP_DELAY 3 +OP_FCMOV_DELAY 1 +OP_GATHER_DELAY 12 +OP_SCATTER_DELAY 18 +OP_PIPELINED_FAST_DELAY 2 +OP_PIPELINED_MEDIUM_DELAY 5 +OP_PIPELINED_SLOW_DELAY 10 +OP_NOTPIPELINED_MEDIUM_DELAY -5 +OP_NOTPIPELINED_SLOW_DELAY -20 +OP_NOTPIPELINED_VERY_SLOW_DELAY -100 +UNIFORM_OP_DELAY 0 +STALL_ON_WAIT_MEM TRUE +STORES_DO_NOT_BLOCK_WINDOW FALSE 1 +PREFS_DO_NOT_BLOCK_WINDOW FALSE 1 +OBEY_REG_DEP TRUE +OLDEST_FIRST_SCHED FALSE +FIND_EMPTIEST_RS FALSE +TRACK_L1_MISS_DEPS FALSE +CBP_TRACE_R0 NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir/trace/drmemtrace.x264.555077.8068.trace.gz +CBP_TRACE_R1 NULL +CBP_TRACE_R2 NULL +CBP_TRACE_R3 NULL +CBP_TRACE_R4 NULL +CBP_TRACE_R5 NULL +CBP_TRACE_R6 NULL +CBP_TRACE_R7 NULL +CBP_TRACE_R8 NULL +CBP_TRACE_R9 NULL +CBP_TRACE_R10 NULL +CBP_TRACE_R11 NULL +CBP_TRACE_R12 NULL +CBP_TRACE_R13 NULL +CBP_TRACE_R14 NULL +CBP_TRACE_R15 NULL +CBP_TRACE_R16 NULL +CBP_TRACE_R17 NULL +CBP_TRACE_R18 NULL +CBP_TRACE_R19 NULL +CBP_TRACE_R20 NULL +CBP_TRACE_R21 NULL +CBP_TRACE_R22 NULL +CBP_TRACE_R23 NULL +CBP_TRACE_R24 NULL +CBP_TRACE_R25 NULL +CBP_TRACE_R26 NULL +CBP_TRACE_R27 NULL +CBP_TRACE_R28 NULL +CBP_TRACE_R29 NULL +CBP_TRACE_R30 NULL +CBP_TRACE_R31 NULL +CBP_TRACE_R32 NULL +CBP_TRACE_R33 NULL +CBP_TRACE_R34 NULL +CBP_TRACE_R35 NULL +CBP_TRACE_R36 NULL +CBP_TRACE_R37 NULL +CBP_TRACE_R38 NULL +CBP_TRACE_R39 NULL +CBP_TRACE_R40 NULL +CBP_TRACE_R41 NULL +CBP_TRACE_R42 NULL +CBP_TRACE_R43 NULL +CBP_TRACE_R44 NULL +CBP_TRACE_R45 NULL +CBP_TRACE_R46 NULL +CBP_TRACE_R47 NULL +CBP_TRACE_R48 NULL +CBP_TRACE_R49 NULL +CBP_TRACE_R50 NULL +CBP_TRACE_R51 NULL +CBP_TRACE_R52 NULL +CBP_TRACE_R53 NULL +CBP_TRACE_R54 NULL +CBP_TRACE_R55 NULL +CBP_TRACE_R56 NULL +CBP_TRACE_R57 NULL +CBP_TRACE_R58 NULL +CBP_TRACE_R59 NULL +CBP_TRACE_R60 NULL +CBP_TRACE_R61 NULL +CBP_TRACE_R62 NULL +CBP_TRACE_R63 NULL +MEMTRACE_MODULES_LOG NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir/raw +DUMB_CORE_ON FALSE +DUMB_CORE 1 +DEBUG_CYCLE_START 0 0 +DEBUG_CYCLE_STOP 0 -1 +DEBUG_TIME_START 0 +DEBUG_TIME_STOP 0 +DEBUG_INST_START 0 0 +DEBUG_INST_STOP 0 -1 +DEBUG_OP_START 0 +DEBUG_OP_STOP 0 +DEBUG_CACHE_LIB FALSE +DEBUG_HASH_LIB FALSE +DEBUG_LIST_LIB FALSE +DEBUG_PORT_LIB FALSE +DEBUG_BUS_LIB FALSE +DEBUG_OP_POOL FALSE +DEBUG_ORACLE FALSE +DEBUG_FRONTEND FALSE +DEBUG_ADDR_TRANS FALSE +DEBUG_BP FALSE +DEBUG_BP_DIR FALSE +DEBUG_BTB FALSE +DEBUG_CRS FALSE +DEBUG_MAP FALSE +DEBUG_MEMORY FALSE +DEBUG_REPLAY FALSE +DEBUG_FREQ FALSE +DEBUG_MODEL FALSE +DEBUG_THREAD FALSE +DEBUG_ICACHE_STAGE FALSE +DEBUG_DECODE_STAGE FALSE +DEBUG_MAP_STAGE FALSE +DEBUG_NODE_STAGE FALSE +DEBUG_EXEC_STAGE FALSE +DEBUG_DCACHE_STAGE FALSE +DEBUG_RETIRED_UOPS FALSE +DEBUG_EXC_INSERTS FALSE +DEBUG_BP_CONF FALSE +DEBUG_ONPATH_CONF FALSE +DEBUG_STREAM FALSE +DEBUG_STREAM_MEM FALSE +DEBUG_WAY FALSE +DEBUG_L2MARKV FALSE +DEBUG_L2L1PREF FALSE +DEBUG_PERF_PRED FALSE +DEBUG_POWER_UTILS FALSE +DEBUG_DVFS FALSE +DEBUG_TRACE_READ FALSE +DEBUG_INST_FIELDS FALSE +DEBUG_OP_FIELDS FALSE +DEBUG_PIN_EXEC_DRIVEN FALSE +DEBUG_CACHE_PART FALSE +DEBUG_OPTIMIZER2 FALSE +DEBUG_PREF FALSE +PERFECT_BP FALSE +PERFECT_BTB FALSE +PERFECT_IBP FALSE +PERFECT_CRS FALSE +PERFECT_CBR_BTB FALSE +PERFECT_NT_BTB FALSE +CFS_PER_CYCLE 3 6 # Number of branches that can be predicted in a single cycle +UPDATE_BP_OFF_PATH FALSE 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +BP_UPDATE_AT_RETIRE FALSE 0 # Update the BP at retire. If false, update at the end of exec. +BP_MECH 0 tagescl +LATE_BP_MECH NUM_BP +LATE_BP_LATENCY 5 +HIST_LENGTH 16 +PHT_CTR_BITS 2 const +BHT_ENTRIES (4 * 1024) +BHT_ASSOC 4 +HYBRIDS_INDEX_LENGTH 16 +HYBRIDG_HIST_LENGTH 16 +HYBRIDP_HIST_LENGTH 16 +FILTER_INDEX_LENGTH 16 +USE_FILTER FALSE +INF_HYBRIDGP FALSE +BP_HASH_TOS FALSE +IBTB_HASH_TOS FALSE +BTB_MECH 0 generic +BTB_ENTRIES (4 * 1024) 4096 +BTB_ASSOC 4 4 +BTB_OFF_PATH_WRITES TRUE 1 +ENABLE_CRS TRUE 1 +CRS_ENTRIES 32 32 +CRS_REALISTIC 0 1 +ENABLE_IBP TRUE 1 # Enable the indirect branch predictor +USE_PAT_HIST TRUE +IBTB_MECH 1 tc_tagged +IBTB_HIST_LENGTH 16 +IBTB_OFF_PATH_WRITES TRUE 1 # Allow off path ops to update the ibtb. +TARGETS_IN_HIST 4 +TC_ENTRIES (4 * 1024) 4096 +TC_ASSOC 4 4 +NUM_CORR_BRANCHES 3 +SEL_HIST_BP_ENTRIES 8192 +SEL_HIST_LENGTH 16 +SEL_HIST_DYN_CNT_TH 16 +SEL_HIST_MISPRED_TH 4 +ENABLE_BP_CONF FALSE +CONF_MECH 0 +PERF_BP_CONF_PRED FALSE +BPC_BITS 16 +BPC_MECH 1 +BPC_CTR_RESET TRUE +BPC_CIT_BITS 8 +BPC_CIT_TH 50 +BPC_CTR_BITS 3 +OPC_COUNT_ZEROS FALSE +OPC_COUNT_THRESH 10 +INF_LOOP FALSE +INF_LOOP_BUCKETS 811 +LOOP_ENTRIES (4 * 1024) +LOOP_ASSOC 4 +LOOP_COUNT_MAX 127 +LOOP_REPEAT_MAX 15 +KNOB_PRINT_BRINFO FALSE +BR_MISPRED_FILE NULL +CONF_PERCEPTRON_TH 0 +CONF_PERCEPTRON_CTR_BITS 8 +CONF_PERCEPTRON_ENTRIES 127 +CONF_PERCEPTRON_THRESH_OVRD 0 +CONF_HIST_LENGTH 32 +PERCEPTRON_CONF_USE_CONF FALSE +PERCEPTRON_CONF_TRAIN_HIS FALSE +PERCEPTRON_CONF_TRAIN_CONF FALSE +PERCEPTRON_CONF_TRAIN_OFFSET_CONF FALSE +PERCEPTRON_TRAIN_MISP_FACTOR 1 +PERCEPTRON_TRAIN_CORR_FACTOR 1 +PERCEPTRON_CONF_HIS_BOTH FALSE +PERCEPTRON_CONF_HIS_BOTH_LENGTH 4 +ENABLE_ICACHE_PACKET_BREAKING TRUE +NUM_LOAD_STORE_PER_PACKET 0 +PACKET_BREAK_ON_FUS FALSE +PACKET_BREAK_FU_TYPES "G,G,G,G,G,G,G,G,G,G,G,G" +POWER_INTF_ON FALSE +POWER_INTF_ENABLE_SCALING FALSE +POWER_INTF_EXEC "power/power_intf.py" +POWER_INTF_REF_CHIP_TECH_NM 22 +POWER_INTF_REF_CHIP_FREQ (3.2e9) +POWER_INTF_REF_MEMORY_FREQ (0.8e9) +POWER_OTHER (0.0) +PREF_STREAM_ON FALSE 1 +PREF_STREAM_PER_CORE_ENABLE FALSE 1 +STREAM_BUFFER_N 16 +STREAM_PREFETCH_N 2 4 +STREAM_START_DIS 5 1 +STREAM_LENGTH 16 64 +STREAM_FULL_N 1 +STREAM_TRAIN_LENGTH 16 +STREAM_TRAIN_NUM 1 4 +PREF_ACC_USE_CACHE FALSE +STREAM_STALL_ON_QUEUE_FULL FALSE +PREF_SCHEDULE_NUM 4 +TRAIN_FILTER_SIZE 32 +PREF_REQ_Q_SIZE 64 +STREAM_CREATE_ON_DC_MISS FALSE 0 +STREAM_CREATE_ON_L1_MISS TRUE 1 +STREAM_TRAIN_ON_WRONGPATH TRUE +STREAM_CREATE_ON_WRONGPATH TRUE +STREAM_PREF_INTO_DCACHE FALSE +REMOVE_REDUNDANT_STREAM FALSE +L2HIT_STREAM_SCHEDULE_NUM 4 +PREF_REQ_QUEUE_FILTER_ON FALSE +HW_PREF_HIT_TRAIN_STREAM FALSE +L2HIT_STREAM_BUFFER_N 32 +L2HIT_STREAM_PREFETCH_N 2 +L2HIT_STREAM_START_DIS 2 +L2HIT_STREAM_LENGTH 8 +L2HIT_PREF_REQ_Q_SIZE 128 +L2HIT_L2ACCESS_REQ_Q_SIZE 64 +PREF_STREAM_ACCPERSTREAM FALSE +PREF_ACC_DISTANCE_10 128 +PREF_FRAMEWORK_ON FALSE 1 +PREF_TRACE_ON FALSE +PREF_DL0REQ_QUEUE_SIZE 32 +PREF_UMLC_REQ_QUEUE_SIZE 64 +PREF_UL1REQ_QUEUE_SIZE 128 +PREF_SHARED_QUEUES TRUE 0 +PREF_DL0_MISS_ON TRUE +PREF_DL0_HIT_ON TRUE +PREF_DL0REQ_QUEUE_FILTER_ON TRUE +PREF_UMLC_REQ_QUEUE_FILTER_ON TRUE +PREF_UL1REQ_QUEUE_FILTER_ON TRUE +PREF_DL0REQ_ADD_FILTER_ON TRUE +PREF_UMLC_REQ_ADD_FILTER_ON TRUE +PREF_UL1REQ_ADD_FILTER_ON TRUE +PREF_DL0REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UMLC_REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UL1REQ_QUEUE_OVERWRITE_ON_FULL FALSE 1 +PREF_DL0SCHEDULE_NUM 4 +PREF_UMLC_SCHEDULE_NUM 4 +PREF_UL1SCHEDULE_NUM 4 +PREF_L1Q_DEMAND_RESERVE 0 +PREF_REPORT_PREF_MATCH_AS_MISS FALSE +PREF_REPORT_PREF_MATCH_AS_HIT TRUE +PREF_UPDATE_ON_WRONGPATH TRUE +PREF_TRAIN_ON_PREF_MISSES FALSE 0 +PREF_ORACLE_TRAIN_ON FALSE 0 +PREF_REQ_DROP FALSE +PREF_THROTTLE_ON FALSE +PREF_THROTTLEFB_ON FALSE 1 +PREF_ACC_THRESH_1 0.90 0.75 +PREF_ACC_THRESH_2 0.70 0.4 +PREF_ACC_THRESH_3 0.60 0.4 +PREF_ACC_THRESH_4 0.40 +PREF_UPDATE_INTERVAL 0 8192 +PREF_ANALYZE_LOAD FALSE +PREF_POL_THRESH_1 0.25 +PREF_POL_THRESH_2 0.10 +PREF_POLBV_ON FALSE +PREF_POLBV_SIZE 1024 +PREF_TIMELY_THRESH 0.05 0.01 +PREF_POLPF_THRESH 0.01 0.005 +PREF_DEGFB_USEONLYACC FALSE +PREF_DEGFB_USEONLYPOL FALSE +PREF_DEGFB_USEONLYLATE FALSE +PREF_TIMELY_THRESH_2 0.005 +PREF_DEGFB_STATPHASEFILE FALSE +PREF_MAX_DEGFB 4 +PREF_DHAL FALSE +PREF_DHAL_SENTTHRESH 16 +PREF_DHAL_USETHRESH_MAX 12 +PREF_DHAL_USETHRESH_MIN2 8 +PREF_DHAL_USETHRESH_MIN1 4 +PREF_DHAL_MAXDEG 64 +PREF_HFILTER_ON FALSE +PREF_HFILTER_INDEX_BITS 12 +PREF_HFILTER_USE_PC FALSE +PREF_HFILTER_PRED_USELESS_THRES 2 +PREF_HFILTER_RESET_ENABLE FALSE +PREF_HFILTER_RESET_INTERVAL 100000 +L2L1PREF_ON FALSE +L2WAY_PREF FALSE +L2MARKV_PREF_ON FALSE +L2NEXT_PREF_ON FALSE +L2HIT_STREAM_PREF_ON FALSE +L2L1_DC_HIT_TRAIN FALSE +L1_HIT_DUMP_FILE_ON FALSE +L1_HIT_DUMP_WO_TXT FALSE +L1_HIT_DUMPFILE "l1hit_dump.out" +IDEAL_L2_L1_PREFETCHER FALSE +IDEAL_L2_ICACHE_PREFETCHER FALSE +L1WAY_PREF_SEND_QUEUE 4 +L1PREF_REQ_QUEUE_SIZE 1024 +L1PREF_IMMEDIATE FALSE +L1WAY_PREF_TIMER_DIS 1000 +L1MARKV_PREF_SEND_QUEUE 4 +L1PREF_MARKV_REQ_QUEUE_SIZE 1024 +MARKV_L2ACCESS_REQ_Q_SIZE 64 +L1MARKV_PREF_IMMEDIATE FALSE +L1MARKV_PREF_TIMER_DIS 1 +L2L1_HIT_TRAIN TRUE +L1MARKV_REQ_TH 1 +L2L1_IMMEDIATE_PREF_CACHE FALSE +L2L1_FILL_PREF_CACHE FALSE +L2L1_L2_HIT_STAT FALSE +PREF_GHB_ON FALSE +DEBUG_PREF_GHB FALSE +PREF_GHB_BUFFER_N 1024 +PREF_GHB_INDEX_N 128 +PREF_GHB_CZONE_BITS 12 +PREF_GHB_DEGREE 16 +PREF_GHB_MAX_DEGREE 32 +PREF_STRIDE_ON FALSE +DEBUG_PREF_STRIDE FALSE +PREF_STRIDE_TABLE_N 1024 +PREF_STRIDE_REGION_BITS 16 +PREF_STRIDE_DEGREE 4 +PREF_STRIDE_DISTANCE 16 +PREF_STRIDE_STARTDISTANCE 1 +PREF_STRIDE_SINGLE_THRESH 6 +PREF_STRIDE_MULTI_THRESH 6 +PREF_STRIDE_SINGLE_STRIDE_MODE FALSE +PREF_STRIDEPC_ON FALSE +DEBUG_PREF_STRIDEPC FALSE +PREF_STRIDEPC_TABLE_N 1024 +PREF_STRIDEPC_DEGREE 4 +PREF_STRIDEPC_DISTANCE 16 +PREF_STRIDEPC_USELOADADDR FALSE +PREF_STRIDEPC_TRAINNUM 2 +PREF_STRIDEPC_STARTDIS 4 +PREF_PHASE_ON FALSE +PREF_PHASE_STUDY FALSE +DEBUG_PREF_PHASE FALSE +PREF_PHASE_PRIME_HASH 16381 +PREF_PHASE_INFOSIZE 16384 +PREF_PHASE_LOG2REGIONSIZE 12 +PREF_PHASE_REGIONENTRIES 64 +PREF_PHASE_TRACKEDREGIONS 32 +PREF_PHASE_INTERVAL 100000 +PREF_PHASE_TABLE_SIZE 64 +PREF_PHASE_MAXDIFF_THRESH 64 +PREF_PHASE_MIN_MISSES 64 +PREF_PHASE_MISSPER 0.4 +PREF_2DC_ON FALSE +DEBUG_PREF_2DC FALSE +PREF_2DC_CACHE_SIZE (1 * 1024) +PREF_2DC_CACHE_ASSOC 4 +PREF_2DC_CACHE_LINE_SIZE 1 +PREF_2DC_DEGREE 16 +PREF_2DC_ZONE_SHIFT 10 +PREF_2DC_TAG_SIZE 16 +PREF_2DC_NUM_REGIONS 64 +PREF_2DC_REGION_HASH 61 +PREF_MARKOV_ON FALSE +DEBUG_PREF_MARKOV FALSE +PREF_MARKOV_NUM_ENTRIES 65536 +PREF_MARKOV_NUM_NEXT_STATES 8 +PREF_MARKOV_SEND_ON_PREF_HIT TRUE +PREF_MARKOV_UPDATE_ON_PREF_HIT TRUE +PREF_MARKOV_TABLE_UPDATE_POLICY 0 +PREF_MARKOV_SEND_THRESHOLD 0 +PREF_SMS_ON FALSE 0 +PREF_SMS_AT_SIZE 64 +PREF_SMS_FT_SIZE 64 +PREF_SMS_PHT_SIZE 16384 +PREF_SMS_PRF_SIZE 1024 +PREF_SMS_REGION_SIZE 2048 diff --git a/labs/LAB5/runs/x264-sms0/bp.stat.0.out b/labs/LAB5/runs/x264-sms0/bp.stat.0.out new file mode 100644 index 00000000..278220c3 --- /dev/null +++ b/labs/LAB5/runs/x264-sms0/bp.stat.0.out @@ -0,0 +1,752 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 34067712 Instructions: 100000000 IPC: 2.93533 + +BTB_ON_PATH_MISS 3777 0.083% 3777 0.083% +BTB_ON_PATH_HIT 4522018 99.917% 4522018 99.917% + 4525795 100.000% 4525795 100.000% + 1.00 1.00 1.00 1.00 + +BTB_OFF_PATH_MISS 0 -nan% 0 -nan% +BTB_OFF_PATH_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BTB_ON_PATH_WRITE 3777 100.000% 3777 100.000% +BTB_OFF_PATH_WRITE 0 0.000% 0 0.000% + 3777 100.000% 3777 100.000% + 0.00 0.00 0.00 0.00 + +BP_ON_PATH_CORRECT 4315247 95.348% 4315247 95.348% +BP_ON_PATH_MISPREDICT 67422 1.490% 67422 1.490% +BP_ON_PATH_MISFETCH 143126 3.162% 143126 3.162% + 4525795 100.000% 4525795 100.000% + 0.08 0.36 0.08 0.36 + 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0.000% +RET_STALL_LENGTH_3800 0 0.000% 0 0.000% +RET_STALL_LENGTH_3900 0 0.000% 0 0.000% +RET_STALL_LENGTH_4000 0 0.000% 0 0.000% +RET_STALL_LENGTH_4100 0 0.000% 0 0.000% +RET_STALL_LENGTH_4200 0 0.000% 0 0.000% +RET_STALL_LENGTH_4300 0 0.000% 0 0.000% +RET_STALL_LENGTH_4400 0 0.000% 0 0.000% +RET_STALL_LENGTH_4500 0 0.000% 0 0.000% +RET_STALL_LENGTH_4600 0 0.000% 0 0.000% +RET_STALL_LENGTH_4700 0 0.000% 0 0.000% +RET_STALL_LENGTH_4800 0 0.000% 0 0.000% +RET_STALL_LENGTH_4900 0 0.000% 0 0.000% +RET_STALL_LENGTH_5000 0 0.000% 0 0.000% + 110907477 100.000% 110907477 100.000% + 0.00 0.03 0.00 0.03 + +MEM_BLOCK_LENGTH_0 7127 81.929% 7127 81.929% +MEM_BLOCK_LENGTH_100 327 3.759% 327 3.759% +MEM_BLOCK_LENGTH_200 115 1.322% 115 1.322% +MEM_BLOCK_LENGTH_300 165 1.897% 165 1.897% +MEM_BLOCK_LENGTH_400 212 2.437% 212 2.437% +MEM_BLOCK_LENGTH_500 141 1.621% 141 1.621% +MEM_BLOCK_LENGTH_600 128 1.471% 128 1.471% +MEM_BLOCK_LENGTH_700 112 1.288% 112 1.288% +MEM_BLOCK_LENGTH_800 92 1.058% 92 1.058% +MEM_BLOCK_LENGTH_900 57 0.655% 57 0.655% +MEM_BLOCK_LENGTH_1000 37 0.425% 37 0.425% +MEM_BLOCK_LENGTH_1100 35 0.402% 35 0.402% +MEM_BLOCK_LENGTH_1200 18 0.207% 18 0.207% +MEM_BLOCK_LENGTH_1300 23 0.264% 23 0.264% +MEM_BLOCK_LENGTH_1400 16 0.184% 16 0.184% +MEM_BLOCK_LENGTH_1500 14 0.161% 14 0.161% +MEM_BLOCK_LENGTH_1600 12 0.138% 12 0.138% +MEM_BLOCK_LENGTH_1700 14 0.161% 14 0.161% +MEM_BLOCK_LENGTH_1800 10 0.115% 10 0.115% +MEM_BLOCK_LENGTH_1900 7 0.080% 7 0.080% +MEM_BLOCK_LENGTH_2000 7 0.080% 7 0.080% +MEM_BLOCK_LENGTH_2100 6 0.069% 6 0.069% +MEM_BLOCK_LENGTH_2200 3 0.034% 3 0.034% +MEM_BLOCK_LENGTH_2300 8 0.092% 8 0.092% +MEM_BLOCK_LENGTH_2400 1 0.011% 1 0.011% +MEM_BLOCK_LENGTH_2500 1 0.011% 1 0.011% +MEM_BLOCK_LENGTH_2600 2 0.023% 2 0.023% +MEM_BLOCK_LENGTH_2700 2 0.023% 2 0.023% +MEM_BLOCK_LENGTH_2800 1 0.011% 1 0.011% +MEM_BLOCK_LENGTH_2900 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_3000 1 0.011% 1 0.011% +MEM_BLOCK_LENGTH_3100 2 0.023% 2 0.023% +MEM_BLOCK_LENGTH_3200 1 0.011% 1 0.011% +MEM_BLOCK_LENGTH_3300 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_3400 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_3500 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_3600 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_3700 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_3800 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_3900 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4000 1 0.011% 1 0.011% +MEM_BLOCK_LENGTH_4100 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4200 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4300 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4400 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4500 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4600 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4700 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4800 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4900 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_5000 1 0.011% 1 0.011% + 8699 100.000% 8699 100.000% + 1.01 2.86 1.01 2.86 + +FUS_BUSY_ON_PATH 138607238 4.0686 138607238 4.0686 + +FUS_BUSY_OFF_PATH 0 0.0000 0 0.0000 + +FU_BUSY_MEM_STALL 27698202 0.8130 27698202 0.8130 + +FUS_EMPTY 133934458 3.9314 133934458 3.9314 + +CHIP_UTILIZATION 0 0.0000 0 0.0000 + +CYCLES_UNDER_MEM_REQ 0 0 + +CYCLES_UNDER_NO_MEM_REQ 0 0 + +CYCLES_UNDER_CRITICAL_MEM_REQ 0 0 + +CYCLES_UNDER_NONCRITICAL_MEM_REQ 0 0 + +CHIP_UTILIZATION_UNDER_MEM_REQ 0 -nan 0 -nan + +CHIP_UTILIZATION_UNDER_NO_MEM_REQ 0 -nan 0 -nan + +CHIP_UTILIZATION_UNDER_CRITICAL_MEM_REQ 0 -nan 0 -nan + +CHIP_UTILIZATION_UNDER_NONCRITICAL_MEM_REQ 0 -nan 0 -nan + +CYCLES_NOT_WAITING_FOR_OFF_CHIP 0 0.0000 0 0.0000 + +FUS_BUSY_NOT_WAITING_FOR_OFF_CHIP 0 -nan 0 -nan + +CYCLES_WAITING_FOR_OFF_CHIP 0 0.0000 0 0.0000 + +FUS_BUSY_WAITING_FOR_OFF_CHIP 0 -nan 0 -nan + +TOTAL_OFF_CHIP_DELAYS_LEFT 0 0 + +WRONG_IO_SCHED 0 0 + +DVFS_CONFIG_SWITCH 0 0 + + + diff --git a/labs/LAB5/runs/x264-sms0/fetch.stat.0.out b/labs/LAB5/runs/x264-sms0/fetch.stat.0.out new file mode 100644 index 00000000..0fa34583 --- /dev/null +++ b/labs/LAB5/runs/x264-sms0/fetch.stat.0.out @@ -0,0 +1,248 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 34067712 Instructions: 100000000 IPC: 2.93533 + +ICACHE_CYCLE 34067712 34067712 + +TCACHE_CYCLE 0 0 + +ICACHE_CYCLE_ONPATH 29907084 87.787% 29907084 87.787% +ICACHE_CYCLE_OFFPATH 4160628 12.213% 4160628 12.213% + 34067712 100.000% 34067712 100.000% + 0.12 0.31 0.12 0.31 + +FETCH_ON_PATH 20009166 100.000% 20009166 100.000% +FETCH_OFF_PATH 0 0.000% 0 0.000% + 20009166 100.000% 20009166 100.000% + 0.00 0.00 0.00 0.00 + +FETCHED_OPS_ON_PATH 0 -nan% 0 -nan% +FETCHED_OPS_OFF_PATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +INST_LOST_WAIT_FOR_MISP_RECOVERY 0 0.000% 0 0.000% +INST_LOST_WAIT_FOR_TIMER 0 0.000% 0 0.000% +INST_LOST_WAIT_FOR_EMPTY_ROB 10722 0.006% 10722 0.006% +INST_LOST_WAIT_FOR_REDIRECT 213030 0.118% 213030 0.118% +INST_LOST_FETCH 110907485 61.361% 110907485 61.361% +INST_LOST_OFF_PATH 0 0.000% 0 0.000% +INST_LOST_FULL_WINDOW 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_OTHER 45077214 24.939% 45077214 24.939% +INST_LOST_ROB_STALL_WAIT_FOR_RECOVERY 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_REDIRECT 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_GAP_FILL 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_L1_MISS 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_MEMORY 790044 0.437% 790044 0.437% +INST_LOST_ROB_STALL_WAIT_FOR_DC_MISS 11296308 6.250% 11296308 6.250% +INST_LOST_ROB_BLOCK_ISSUE_FULL 0 0.000% 0 0.000% +INST_LOST_ROB_BLOCK_ISSUE_GAP_TOO_LARGE 0 0.000% 0 0.000% +INST_LOST_BREAK_DONT 0 0.000% 0 0.000% +INST_LOST_BREAK_ISSUE_WIDTH 0 0.000% 0 0.000% +INST_LOST_BREAK_CF 0 0.000% 0 0.000% +INST_LOST_BREAK_BTB_MISS 9691 0.005% 9691 0.005% +INST_LOST_BREAK_ICACHE_MISS 3424254 1.895% 3424254 1.895% +INST_LOST_BREAK_LINE_END 0 0.000% 0 0.000% +INST_LOST_BREAK_STALL 0 0.000% 0 0.000% +INST_LOST_BREAK_BARRIER 56 0.000% 56 0.000% +INST_LOST_BREAK_OFFPATH 99413 0.055% 99413 0.055% +INST_LOST_BREAK_ALIGNMENT 0 0.000% 0 0.000% +INST_LOST_BREAK_TAKEN 8918789 4.934% 8918789 4.934% +INST_LOST_BREAK_MODEL_BEFORE 0 0.000% 0 0.000% +INST_LOST_BREAK_MODEL_AFTER 0 0.000% 0 0.000% + 180747006 100.000% 180747006 100.000% + 6.74 5.39 6.74 5.39 + +INST_LOST_TOTAL 204406272 204406272 + +FETCH_0_OPS 10135170 33.644% 10135170 33.644% +FETCH_1_OPS 692633 2.299% 692633 2.299% +FETCH_2_OPS 358217 1.189% 358217 1.189% +FETCH_3_OPS 883243 2.932% 883243 2.932% +FETCH_4_OPS 446733 1.483% 446733 1.483% +FETCH_5_OPS 589273 1.956% 589273 1.956% +FETCH_6_OPS 17019232 56.496% 17019232 56.496% +FETCH_7_OPS 0 0.000% 0 0.000% +FETCH_8_OPS 0 0.000% 0 0.000% +FETCH_9_OPS 0 0.000% 0 0.000% +FETCH_10_OPS 0 0.000% 0 0.000% +FETCH_11_OPS 0 0.000% 0 0.000% +FETCH_12_OPS 0 0.000% 0 0.000% +FETCH_13_OPS 0 0.000% 0 0.000% +FETCH_14_OPS 0 0.000% 0 0.000% +FETCH_15_OPS 0 0.000% 0 0.000% +FETCH_16_OPS 0 0.000% 0 0.000% + 30124501 100.000% 30124501 100.000% + 3.68 1.81 3.68 1.81 + +ST_BREAK_DONT 0 0.000% 0 0.000% +ST_BREAK_ISSUE_WIDTH 16712616 83.525% 16712616 83.525% +ST_BREAK_CF 0 0.000% 0 0.000% +ST_BREAK_BTB_MISS 3777 0.019% 3777 0.019% +ST_BREAK_ICACHE_MISS 20054 0.100% 20054 0.100% +ST_BREAK_LINE_END 0 0.000% 0 0.000% +ST_BREAK_STALL 0 0.000% 0 0.000% +ST_BREAK_BARRIER 36 0.000% 36 0.000% +ST_BREAK_OFFPATH 35727 0.179% 35727 0.179% +ST_BREAK_ALIGNMENT 0 0.000% 0 0.000% +ST_BREAK_TAKEN 3236956 16.177% 3236956 16.177% + 20009166 100.000% 20009166 100.000% + 2.47 3.47 2.47 3.47 + +ORACLE_ON_PATH_INST 110907485 100.000% 110907485 100.000% +ORACLE_OFF_PATH_INST 0 0.000% 0 0.000% + 110907485 100.000% 110907485 100.000% + 0.00 0.00 0.00 0.00 + +ORACLE_ON_PATH_INST_MEM 34668560 31.259% 34668560 31.259% +ORACLE_ON_PATH_INST_NOTMEM 76238925 68.741% 76238925 68.741% +ORACLE_OFF_PATH_INST_MEM 0 0.000% 0 0.000% +ORACLE_OFF_PATH_INST_NOTMEM 0 0.000% 0 0.000% + 110907485 100.000% 110907485 100.000% + 0.69 0.26 0.69 0.26 + +ICACHE_CYCLE_NONRA_ONPATH 0 -nan% 0 -nan% +ICACHE_CYCLE_NONRA_OFFPATH 0 -nan% 0 -nan% +ICACHE_CYCLE_RA_ONPATH 0 -nan% 0 -nan% +ICACHE_CYCLE_RA_OFFPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ICACHE_CYCLE_ONPATH_NONRA 0 -nan% 0 -nan% +ICACHE_CYCLE_OFFPATH_NONRA 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ICACHE_CYCLE_ONPATH_RA 0 -nan% 0 -nan% +ICACHE_CYCLE_OFFPATH_RA 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +INACCURATE_OFFPATH_CYCLES 0 0.0000 0 0.0000 + +FETCH_ALL_INST 110907485 110907485 + +EXEC_ALL_INST 110907483 110907483 + +RET_ALL_INST 110907477 110907477 + +EXEC_ON_PATH_INST 110907483 100.000% 110907483 100.000% +EXEC_OFF_PATH_INST 0 0.000% 0 0.000% + 110907483 100.000% 110907483 100.000% + 0.00 0.00 0.00 0.00 + +EXEC_ON_PATH_INST_MEM 34668560 31.259% 34668560 31.259% +EXEC_ON_PATH_INST_NOTMEM 76238923 68.741% 76238923 68.741% +EXEC_OFF_PATH_INST_MEM 0 0.000% 0 0.000% +EXEC_OFF_PATH_INST_NOTMEM 0 0.000% 0 0.000% + 110907483 100.000% 110907483 100.000% + 0.69 0.26 0.69 0.26 + +EXEC_RA_INST 0 -nan% 0 -nan% +EXEC_NONRA_INST 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +EXEC_ON_PATH_INST_RA 0 -nan% 0 -nan% +EXEC_OFF_PATH_INST_RA 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +EXEC_ON_PATH_INST_NONRA 0 -nan% 0 -nan% +EXEC_OFF_PATH_INST_NONRA 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +EXEC_RA_ON_PATH_INST 0 -nan% 0 -nan% +EXEC_RA_OFF_PATH_INST 0 -nan% 0 -nan% +EXEC_NONRA_ON_PATH_INST 0 -nan% 0 -nan% +EXEC_NONRA_OFF_PATH_INST 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ICACHE_THROTTLE_CYCLE 0 0 + +FETCH_ENABLE_THROTTLE_OFF_PATH 0 -nan% 0 -nan% +FETCH_ENABLE_THROTTLE_ON_PATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +FETCH_DISABLE_THROTTLE_OFF_PATH 0 -nan% 0 -nan% +FETCH_DISABLE_THROTTLE_ON_PATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +FETCH_TH_ADJUST__0 0 -nan% 0 -nan% +FETCH_TH_ADJUST__1 0 -nan% 0 -nan% +FETCH_TH_ADJUST__2 0 -nan% 0 -nan% +FETCH_TH_ADJUST__3 0 -nan% 0 -nan% +FETCH_TH_ADJUST__4 0 -nan% 0 -nan% +FETCH_TH_ADJUST__5 0 -nan% 0 -nan% +FETCH_TH_ADJUST__6 0 -nan% 0 -nan% +FETCH_TH_ADJUST__7 0 -nan% 0 -nan% +FETCH_TH_ADJUST__8 0 -nan% 0 -nan% +FETCH_TH_ADJUST__9 0 -nan% 0 -nan% +FETCH_TH_ADJUST__MAX 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +FETCH_TH_ADJUST_UP 0 -nan% 0 -nan% +FETCH_TH_ADJUST_DOWN 0 -nan% 0 -nan% +FETCH_TH_ADJUST_SAME 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +THROTTLE_ADJUST_CACHE_MISS_INFO 0 0 + +LOW_CONF_COUNT_BP_MIS_0 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_1 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_2 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_3 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_4 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_5 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_6 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_7 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_8 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_9 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_10 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_11 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_12 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_13 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_14 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_15 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_16 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_17 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_18 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_19 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_20 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +LOW_CONF_COUNT_RET_0 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_1 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_2 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_3 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_4 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_5 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_6 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_7 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_8 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_9 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_10 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_11 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_12 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_13 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_14 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_15 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_16 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_17 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_18 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_19 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_20 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + + + diff --git a/labs/LAB5/runs/x264-sms0/inst.stat.0.out b/labs/LAB5/runs/x264-sms0/inst.stat.0.out new file mode 100644 index 00000000..39cfefd0 --- /dev/null +++ b/labs/LAB5/runs/x264-sms0/inst.stat.0.out @@ -0,0 +1,103 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 34067712 Instructions: 100000000 IPC: 2.93533 + +ST_OP_INV 0 0.000% 0 0.000% +ST_OP_NOP 982303 0.886% 982303 0.886% +ST_OP_CF 4525831 4.081% 4525831 4.081% +ST_OP_MOV 12357707 11.142% 12357707 11.142% +ST_OP_CMOV 362698 0.327% 362698 0.327% +ST_OP_LDA 9857213 8.888% 9857213 8.888% +ST_OP_IMEM 31105341 28.046% 31105341 28.046% +ST_OP_IADD 23442305 21.137% 23442305 21.137% +ST_OP_IMUL 2551445 2.301% 2551445 2.301% +ST_OP_IDIV 10 0.000% 10 0.000% +ST_OP_ICMP 1727044 1.557% 1727044 1.557% +ST_OP_LOGIC 5278766 4.760% 5278766 4.760% +ST_OP_SHIFT 9922262 8.946% 9922262 8.946% +ST_OP_FMEM 3563219 3.213% 3563219 3.213% +ST_OP_FCVT 1532698 1.382% 1532698 1.382% +ST_OP_FADD 1540288 1.389% 1540288 1.389% +ST_OP_FMUL 621017 0.560% 621017 0.560% +ST_OP_FMA 1525450 1.375% 1525450 1.375% +ST_OP_FDIV 21 0.000% 21 0.000% +ST_OP_FCMP 72 0.000% 72 0.000% +ST_OP_FCMOV 0 0.000% 0 0.000% +ST_OP_GATHER 0 0.000% 0 0.000% +ST_OP_SCATTER 0 0.000% 0 0.000% +ST_OP_PIPELINED_FAST 11554 0.010% 11554 0.010% +ST_OP_PIPELINED_MEDIUM 0 0.000% 0 0.000% +ST_OP_PIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_MEDIUM 241 0.000% 241 0.000% +ST_OP_NOTPIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_VERY_SLOW 0 0.000% 0 0.000% + 110907485 100.000% 110907485 100.000% + 7.13 3.39 7.13 3.39 + +ST_NOT_CF 106381654 95.919% 106381654 95.919% +ST_CF_BR 93194 0.084% 93194 0.084% +ST_CF_CBR 2803670 2.528% 2803670 2.528% +ST_CF_CALL 517672 0.467% 517672 0.467% +ST_CF_IBR 307766 0.277% 307766 0.277% +ST_CF_ICALL 142912 0.129% 142912 0.129% +ST_CF_ICO 0 0.000% 0 0.000% +ST_CF_RET 660581 0.596% 660581 0.596% +ST_CF_SYS 36 0.000% 36 0.000% + 110907485 100.000% 110907485 100.000% + 0.12 0.69 0.12 0.69 + +ST_BAR_NONE 110907449 100.000% 110907449 100.000% +ST_BAR_FETCH 36 0.000% 36 0.000% +ST_BAR_ISSUE 0 0.000% 0 0.000% +ST_BAR_BOTH 0 0.000% 0 0.000% + 110907485 100.000% 110907485 100.000% + 0.00 0.00 0.00 0.00 + +ST_NOT_MEM 76238925 68.741% 76238925 68.741% +ST_MEM_LD 25110142 22.641% 25110142 22.641% +ST_MEM_ST 9558303 8.618% 9558303 8.618% +ST_MEM_PF 115 0.000% 115 0.000% +ST_MEM_WH 0 0.000% 0 0.000% +ST_MEM_EVICT 0 0.000% 0 0.000% + 110907485 100.000% 110907485 100.000% + 0.40 0.55 0.40 0.55 + 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b/labs/LAB5/runs/x264-sms0/l2l1pref.stat.0.out new file mode 100644 index 00000000..dafde309 --- /dev/null +++ b/labs/LAB5/runs/x264-sms0/l2l1pref.stat.0.out @@ -0,0 +1,140 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 34067712 Instructions: 100000000 IPC: 2.93533 + +L2WAY_FILL_L1 0 0 + +L2WAY_WAY_HIT 0 -nan% 0 -nan% +L2WAY_WAY_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_PREF_REQ 0 0 + +L2WAY_PREF_HIT_DATA_IN_CACHE 0 -nan% 0 -nan% +L2WAY_PREF_HIT_DATA_REQ 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_TRAIN_HIT 0 -nan% 0 -nan% +L2WAY_TRAIN_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L1_HIT_REQ_TYPE_IFETCH 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DFETCH 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DSTORE 0 -nan% 0 -nan% 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0 -nan% +L2HIT_IP_HIT_COUNT__5 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__6 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__7 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__8 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__9 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + + + diff --git a/labs/LAB5/runs/x264-sms0/memory.stat.0.out b/labs/LAB5/runs/x264-sms0/memory.stat.0.out new file mode 100644 index 00000000..50241f5e --- /dev/null +++ b/labs/LAB5/runs/x264-sms0/memory.stat.0.out @@ -0,0 +1,3416 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 34067712 Instructions: 100000000 IPC: 2.93533 + +ICACHE_MISS 20054 0.095% 20054 0.095% +ICACHE_HIT 21179762 99.905% 21179762 99.905% + 21199816 100.000% 21199816 100.000% + 1.00 1.00 1.00 1.00 + +ICACHE_MISS_ONPATH 20054 100.000% 20054 100.000% +ICACHE_MISS_OFFPATH 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68384 87.942% 68384 87.942% +CORE_PREF_L1_PARTIAL_USED 990 1.273% 990 1.273% +CORE_PREF_L1_NOT_USED 8386 10.784% 8386 10.784% +CORE_PREF_L1_DROPPED 0 0.000% 0 0.000% + 77760 100.000% 77760 100.000% + 0.23 0.59 0.23 0.59 + +TOTAL_MEM_LATENCY 52668374 344.7899 52668374 344.7899 + +TOTAL_MEM_LATENCY_DEMAND 38293297 486.8762 38293297 486.8762 + +TOTAL_MEM_LATENCY_PREF 14375077 193.9852 14375077 193.9852 + +CORE_MEM_LATENCY 52668374 344.7899 52668374 344.7899 + +CORE_MEM_LATENCY_DEMAND 38293297 486.8762 38293297 486.8762 + +CORE_MEM_LATENCY_PREF 14375077 193.9852 14375077 193.9852 + +CORE_MEM_LATENCY_IFETCH 197388 0.375% 197388 0.375% +CORE_MEM_LATENCY_DFETCH 19517761 37.058% 19517761 37.058% +CORE_MEM_LATENCY_DSTORE 19358180 36.755% 19358180 36.755% +CORE_MEM_LATENCY_IPRF 0 0.000% 0 0.000% +CORE_MEM_LATENCY_DPRF 13595045 25.813% 13595045 25.813% +CORE_MEM_LATENCY_WB 0 0.000% 0 0.000% +CORE_MEM_LATENCY_WB_NODIRTY 0 0.000% 0 0.000% + 52668374 100.000% 52668374 100.000% + 2.14 1.18 2.14 1.18 + +CORE_MEM_STALLING_LATENCY_IFETCH 0 -nan% 0 -nan% +CORE_MEM_STALLING_LATENCY_DFETCH 0 -nan% 0 -nan% +CORE_MEM_STALLING_LATENCY_DSTORE 0 -nan% 0 -nan% +CORE_MEM_STALLING_LATENCY_IPRF 0 -nan% 0 -nan% +CORE_MEM_STALLING_LATENCY_DPRF 0 -nan% 0 -nan% +CORE_MEM_STALLING_LATENCY_WB 0 -nan% 0 -nan% +CORE_MEM_STALLING_LATENCY_WB_NODIRTY 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TOTAL_L1_MISS_LATENCY 52668374 344.7899 52668374 344.7899 + +TOTAL_L1_MISS_LATENCY_DEMAND 38293297 486.8762 38293297 486.8762 + +TOTAL_L1_MISS_LATENCY_PREF 14375077 193.9852 14375077 193.9852 + +CORE_L1_MISS_LATENCY 52668374 344.7899 52668374 344.7899 + +CORE_L1_MISS_LATENCY_DEMAND 38293297 486.8762 38293297 486.8762 + +CORE_L1_MISS_LATENCY_PREF 14375077 193.9852 14375077 193.9852 + +CORE_EVICTED_L1_DEMAND 68233 50.030% 68233 50.030% +CORE_EVICTED_L1_PREF_USED 64495 47.289% 64495 47.289% +CORE_EVICTED_L1_PREF_NOT_USED 3656 2.681% 3656 2.681% + 136384 100.000% 136384 100.000% + 0.53 0.41 0.53 0.41 + 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9.664% 6233 9.664% +CORE_PREF_L1_USED_LATENCY600 2888 4.478% 2888 4.478% +CORE_PREF_L1_USED_LATENCY800 2174 3.371% 2174 3.371% +CORE_PREF_L1_USED_LATENCY1000 1212 1.879% 1212 1.879% +CORE_PREF_L1_USED_LATENCY1200 699 1.084% 699 1.084% +CORE_PREF_L1_USED_LATENCY1400 468 0.726% 468 0.726% +CORE_PREF_L1_USED_LATENCY1600 155 0.240% 155 0.240% +CORE_PREF_L1_USED_LATENCY1600MORE 190 0.295% 190 0.295% + 64495 100.000% 64495 100.000% + 0.50 1.13 0.50 1.13 + +CORE_PREF_L1_USED_DISTANCE_1 0 0.000% 0 0.000% +CORE_PREF_L1_USED_DISTANCE_2 2 0.003% 2 0.003% +CORE_PREF_L1_USED_DISTANCE_4 1130 1.752% 1130 1.752% +CORE_PREF_L1_USED_DISTANCE_8 4112 6.376% 4112 6.376% +CORE_PREF_L1_USED_DISTANCE_16 23909 37.071% 23909 37.071% +CORE_PREF_L1_USED_DISTANCE_32 1270 1.969% 1270 1.969% +CORE_PREF_L1_USED_DISTANCE_MORE 34072 52.829% 34072 52.829% + 64495 100.000% 64495 100.000% + 4.98 3.79 4.98 3.79 + +CORE_PREF_L1_DEMAND_LATENCY300 30906 45.295% 30906 45.295% +CORE_PREF_L1_DEMAND_LATENCY400 2186 3.204% 2186 3.204% +CORE_PREF_L1_DEMAND_LATENCY500 4004 5.868% 4004 5.868% +CORE_PREF_L1_DEMAND_LATENCY600 2585 3.788% 2585 3.788% +CORE_PREF_L1_DEMAND_LATENCY700 3208 4.702% 3208 4.702% +CORE_PREF_L1_DEMAND_LATENCY800 6071 8.897% 6071 8.897% +CORE_PREF_L1_DEMAND_LATENCY900 6212 9.104% 6212 9.104% +CORE_PREF_L1_DEMAND_LATENCY1000 3301 4.838% 3301 4.838% +CORE_PREF_L1_DEMAND_LATENCY1000MORE 9760 14.304% 9760 14.304% + 68233 100.000% 68233 100.000% + 2.93 2.68 2.93 2.68 + +CORE_PREF_MLC_NOT_USED_LATENCY200 0 -nan% 0 -nan% +CORE_PREF_MLC_NOT_USED_LATENCY400 0 -nan% 0 -nan% +CORE_PREF_MLC_NOT_USED_LATENCY600 0 -nan% 0 -nan% +CORE_PREF_MLC_NOT_USED_LATENCY800 0 -nan% 0 -nan% +CORE_PREF_MLC_NOT_USED_LATENCY1000 0 -nan% 0 -nan% +CORE_PREF_MLC_NOT_USED_LATENCY1200 0 -nan% 0 -nan% +CORE_PREF_MLC_NOT_USED_LATENCY1400 0 -nan% 0 -nan% +CORE_PREF_MLC_NOT_USED_LATENCY1600 0 -nan% 0 -nan% +CORE_PREF_MLC_NOT_USED_LATENCY1600MORE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + 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8277 30.747% 8277 30.747% +NUM_DCACHE_MISSES_IN_WINDOW_3 9196 34.160% 9196 34.160% +NUM_DCACHE_MISSES_IN_WINDOW_4 2555 9.491% 2555 9.491% +NUM_DCACHE_MISSES_IN_WINDOW_5 386 1.434% 386 1.434% +NUM_DCACHE_MISSES_IN_WINDOW_6 281 1.044% 281 1.044% +NUM_DCACHE_MISSES_IN_WINDOW_7 242 0.899% 242 0.899% +NUM_DCACHE_MISSES_IN_WINDOW_8 619 2.299% 619 2.299% +NUM_DCACHE_MISSES_IN_WINDOW_9 211 0.784% 211 0.784% +NUM_DCACHE_MISSES_IN_WINDOW_10 193 0.717% 193 0.717% +NUM_DCACHE_MISSES_IN_WINDOW_11 109 0.405% 109 0.405% +NUM_DCACHE_MISSES_IN_WINDOW_12 71 0.264% 71 0.264% +NUM_DCACHE_MISSES_IN_WINDOW_13 68 0.253% 68 0.253% +NUM_DCACHE_MISSES_IN_WINDOW_14 85 0.316% 85 0.316% +NUM_DCACHE_MISSES_IN_WINDOW_15 77 0.286% 77 0.286% +NUM_DCACHE_MISSES_IN_WINDOW_16_OR_MORE 1034 3.841% 1034 3.841% + 26920 100.000% 26920 100.000% + 2.48 3.10 2.48 3.10 + +DCACHE_MLP_IN_WINDOW_1_0 6714 24.941% 6714 24.941% +DCACHE_MLP_IN_WINDOW_1_5 1565 5.814% 1565 5.814% +DCACHE_MLP_IN_WINDOW_2_0 8565 31.816% 8565 31.816% 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0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_90 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BUS_100 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DRAM_BOTTLENECK_BANKS_0 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_10 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_20 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_30 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_40 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_50 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_60 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_70 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_80 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_90 0 -nan% 0 -nan% +DRAM_BOTTLENECK_BANKS_100 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DRAM_BOTTLENECK_FAW_0 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_10 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_20 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_30 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_40 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_50 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_60 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_70 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_80 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_90 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_100 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DRAM_ROW_HIT_GEN_AFTER_ROW_OPEN_STALLING 0 0 + +KNOWN_BAD_ADDRESS 0 0.000% 0 0.000% +GOOD_ADDRESS 4961534 100.000% 4961534 100.000% + 4961534 100.000% 4961534 100.000% + 1.00 1.00 1.00 1.00 + + + diff --git a/labs/LAB5/runs/x264-sms0/power.stat.0.out b/labs/LAB5/runs/x264-sms0/power.stat.0.out new file mode 100644 index 00000000..dd47e82e --- /dev/null +++ b/labs/LAB5/runs/x264-sms0/power.stat.0.out @@ -0,0 +1,184 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 34067712 Instructions: 100000000 IPC: 2.93533 + +POWER_STATS_BEGIN 0 0 + +POWER_TIME 10646160000000 10646160000000 + +POWER_CYCLE 34067712 34067712 + +POWER_ITLB_ACCESS 21199816 21199816 + +POWER_DTLB_ACCESS 9558303 9558303 + +POWER_ICACHE_ACCESS 21199816 21199816 + +POWER_ICACHE_MISS 20054 20054 + +POWER_BTB_READ 21199816 21199816 + +POWER_BTB_WRITE 210547 210547 + +POWER_ROB_READ 110907483 110907483 + +POWER_ROB_WRITE 110907483 110907483 + +POWER_RENAME_READ 221814966 221814966 + +POWER_RENAME_WRITE 110907483 110907483 + +POWER_FP_RENAME_READ 0 0 + +POWER_FP_RENAME_WRITE 0 0 + +POWER_FUNCTION_CALL 660583 660583 + +POWER_INST_WINDOW_READ 110907483 110907483 + +POWER_INST_WINDOW_WRITE 110907483 110907483 + +POWER_INT_REGFILE_READ 152748552 152748552 + +POWER_INT_REGFILE_WRITE 131215933 131215933 + +POWER_IALU_ACCESS 108356028 108356028 + +POWER_CDB_IALU_ACCESS 108356028 108356028 + +POWER_MUL_ACCESS 2551455 2551455 + +POWER_CDB_MUL_ACCESS 2551455 2551455 + +POWER_FP_INST_WINDOW_WRITE 0 0 + +POWER_FP_INST_WINDOW_READ 0 0 + +POWER_FP_REGFILE_READ 0 0 + +POWER_FP_REGFILE_WRITE 0 0 + +POWER_FPU_ACCESS 0 0 + +POWER_CDB_FPU_ACCESS 0 0 + +POWER_DCACHE_READ_ACCESS 26436591 26436591 + +POWER_DCACHE_WRITE_ACCESS 10353328 10353328 + +POWER_DCACHE_READ_MISS 2072479 2072479 + +POWER_DCACHE_WRITE_MISS 1001468 1001468 + +POWER_MLC_READ_ACCESS 0 0 + +POWER_MLC_WRITE_ACCESS 0 0 + +POWER_MLC_READ_MISS 0 0 + +POWER_MLC_WRITE_MISS 0 0 + +POWER_LLC_READ_ACCESS 282266 282266 + +POWER_LLC_WRITE_ACCESS 71340 71340 + +POWER_LLC_READ_MISS 152755 152755 + +POWER_LLC_WRITE_MISS 13 13 + +POWER_MEMORY_ACCESS 0 0 + +POWER_MEMORY_READ_ACCESS 0 0 + +POWER_MEMORY_WRITE_ACCESS 0 0 + +POWER_INST_WINDOW_WAKEUP_ACCESS 110907483 110907483 + +POWER_FP_INST_WINDOW_WAKEUP_ACCESS 0 0 + +POWER_L1DIREC_READ_ACCESS 0 0 + +POWER_L1DIREC_WRITE_ACCESS 0 0 + +POWER_L1DIREC_READ_MISS 0 0 + +POWER_L1DIREC_WRITE_MISS 0 0 + +POWER_L2DIREC_READ_ACCESS 0 0 + +POWER_L2DIREC_WRITE_ACCESS 0 0 + +POWER_L2DIREC_READ_MISS 0 0 + +POWER_L2DIREC_WRITE_MISS 0 0 + +POWER_MEMORY_CTRL_ACCESS 216836 216836 + +POWER_MEMORY_CTRL_READ 152755 152755 + +POWER_MEMORY_CTRL_WRITE 64081 64081 + +POWER_OP 110907483 110907483 + +POWER_INT_OP 101130620 101130620 + +POWER_FP_OP 8794560 8794560 + +POWER_LD_OP 25110257 25110257 + +POWER_ST_OP 9558303 9558303 + +POWER_BRANCH_MISPREDICT 210547 210547 + +POWER_COMMITTED_OP 110907483 110907483 + +POWER_COMMITTED_INT_OP 101130620 101130620 + +POWER_COMMITTED_FP_OP 9776863 9776863 + +POWER_BRANCH_OP 4525829 4525829 + +POWER_DRAM_PRECHARGE 24706 24706 + +POWER_DRAM_ACTIVATE 30201 30201 + +POWER_DRAM_READ 152740 152740 + +POWER_DRAM_WRITE 64064 64064 + +POWER_STATS_END 0 0 + +ENERGY 0.000000 0.000000 + +ENERGY_CORE 0.000000 0.000000 + +ENERGY_UNCORE 0.000000 0.000000 + +ENERGY_MEMORY 0.000000 0.000000 + +ENERGY_OTHER 0.000000 0.000000 + +ENERGY_CORE_STATIC 0.000000 0.000000 + +ENERGY_CORE_DYNAMIC 0.000000 0.000000 + +ENERGY_UNCORE_STATIC 0.000000 0.000000 + +ENERGY_UNCORE_DYNAMIC 0.000000 0.000000 + +ENERGY_MEMORY_STATIC 0.000000 0.000000 + +ENERGY_MEMORY_DYNAMIC 0.000000 0.000000 + +ENERGY_OTHER_STATIC 0.000000 0.000000 + +ENERGY_OTHER_DYNAMIC 0.000000 0.000000 + +TIME 0.000000 0.000000 + +ENERGY_STATS_END 0 0 + + + diff --git a/labs/LAB5/runs/x264-sms0/pref.stat.0.out b/labs/LAB5/runs/x264-sms0/pref.stat.0.out new file mode 100644 index 00000000..38b80d7e --- /dev/null +++ b/labs/LAB5/runs/x264-sms0/pref.stat.0.out @@ -0,0 +1,208 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 34067712 Instructions: 100000000 IPC: 2.93533 + +PREF_DL0REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UMLC_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UL1REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_DL0REQ_QUEUE_FULL 0 0 + +PREF_UMLC_REQ_QUEUE_FULL 0 0 + +PREF_UL1REQ_QUEUE_FULL 44003 44003 + +PREF_DC_HIT_NOSEND 0 0 + +PREF_WBQDC_HIT_NOSEND 0 0 + +PREF_MLCQ_STALL 0 0 + +PREF_L1Q_STALL 0 0 + +PREF_UMLC_REQ_SEND_QUEUE_STALL 0 0 + +PREF_UL1REQ_SEND_QUEUE_STALL 1339202 1339202 + +PREF_UMLC_REQ_QUEUE_SENTREQ 0 0 + +PREF_UL1REQ_QUEUE_SENTREQ 111499 111499 + +PREF_NEWREQ_MATCHED 4364 4364 + +PREF_UMLC_REQ_QUEUE_MATCHED_REQ 0 0 + +PREF_UL1REQ_QUEUE_MATCHED_REQ 55493 55493 + +PREF_DL0REQ_QUEUE_MATCHED_REQ 0 0 + +L1_PREF_HIT 73310 73310 + +L1_PREF_UNIQUE_HIT 68384 68384 + +L1_PREF_LATE 1194 1194 + +L1_LATE_PREF_CYCLES 350830 350830 + +L1_LATE_PREF_CYCLES_DIST_0 530 44.389% 530 44.389% +L1_LATE_PREF_CYCLES_DIST_100 146 12.228% 146 12.228% +L1_LATE_PREF_CYCLES_DIST_200 90 7.538% 90 7.538% +L1_LATE_PREF_CYCLES_DIST_300 52 4.355% 52 4.355% +L1_LATE_PREF_CYCLES_DIST_400 60 5.025% 60 5.025% +L1_LATE_PREF_CYCLES_DIST_500 92 7.705% 92 7.705% +L1_LATE_PREF_CYCLES_DIST_600 61 5.109% 61 5.109% +L1_LATE_PREF_CYCLES_DIST_700 45 3.769% 45 3.769% +L1_LATE_PREF_CYCLES_DIST_800 28 2.345% 28 2.345% +L1_LATE_PREF_CYCLES_DIST_900 36 3.015% 36 3.015% +L1_LATE_PREF_CYCLES_DIST_1000 40 3.350% 40 3.350% +L1_LATE_PREF_CYCLES_DIST_1100 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1200 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1300 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1400 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1500 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1600 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1700 3 0.251% 3 0.251% +L1_LATE_PREF_CYCLES_DIST_1800 10 0.838% 10 0.838% +L1_LATE_PREF_CYCLES_DIST_1900 1 0.084% 1 0.084% +L1_LATE_PREF_CYCLES_DIST_2000 0 0.000% 0 0.000% + 1194 100.000% 1194 100.000% + 2.56 2.96 2.56 2.96 + +MLC_PREF_HIT 0 0 + +MLC_PREF_UNIQUE_HIT 0 0 + +MLC_PREF_LATE 0 0 + +PREF_HYBRID_SEL_0 0 -nan% 0 -nan% +PREF_HYBRID_SEL_1 0 -nan% 0 -nan% +PREF_HYBRID_SEL_2 0 -nan% 0 -nan% +PREF_HYBRID_SEL_3 0 -nan% 0 -nan% +PREF_HYBRID_SEL_4 0 -nan% 0 -nan% +PREF_HYBRID_SEL_5 0 -nan% 0 -nan% +PREF_HYBRID_SEL_6 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_DISTANCE_1 0 0.000% 0 0.000% +PREF_DISTANCE_2 0 0.000% 0 0.000% +PREF_DISTANCE_3 1 7.143% 1 7.143% +PREF_DISTANCE_4 1 7.143% 1 7.143% +PREF_DISTANCE_5 12 85.714% 12 85.714% +PREF_DISTANCE_6 0 0.000% 0 0.000% +PREF_DISTANCE_7 0 0.000% 0 0.000% +PREF_DISTANCE_8 0 0.000% 0 0.000% +PREF_DISTANCE_9 0 0.000% 0 0.000% +PREF_DISTANCE_10 0 0.000% 0 0.000% + 14 100.000% 14 100.000% + 3.79 0.58 3.79 0.58 + +PREF_REPL_MRU 0 -nan% 0 -nan% +PREF_REPL_MID 0 -nan% 0 -nan% +PREF_REPL_LOWQTR 0 -nan% 0 -nan% +PREF_REPL_LRU 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_REPL_MOVEDOWN 0 -nan% 0 -nan% +PREF_REPL_MOVEUP 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_COV_1 0 -nan% 0 -nan% +PREF_COV_2 0 -nan% 0 -nan% +PREF_COV_3 0 -nan% 0 -nan% +PREF_COV_4 0 -nan% 0 -nan% +PREF_COV_5 0 -nan% 0 -nan% +PREF_COV_6 0 -nan% 0 -nan% +PREF_COV_7 0 -nan% 0 -nan% +PREF_COV_8 0 -nan% 0 -nan% +PREF_COV_9 0 -nan% 0 -nan% +PREF_COV_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_POL_1 0 0.000% 0 0.000% +PREF_POL_2 0 0.000% 0 0.000% +PREF_POL_3 0 0.000% 0 0.000% +PREF_POL_4 0 0.000% 0 0.000% +PREF_POL_5 0 0.000% 0 0.000% +PREF_POL_6 0 0.000% 0 0.000% +PREF_POL_7 0 0.000% 0 0.000% +PREF_POL_8 0 0.000% 0 0.000% +PREF_POL_9 0 0.000% 0 0.000% +PREF_POL_10 14 100.000% 14 100.000% + 14 100.000% 14 100.000% + 9.00 9.34 9.00 9.34 + +PREF_ACC_1 12 85.714% 12 85.714% +PREF_ACC_2 2 14.286% 2 14.286% +PREF_ACC_3 0 0.000% 0 0.000% +PREF_ACC_4 0 0.000% 0 0.000% +PREF_ACC_5 0 0.000% 0 0.000% +PREF_ACC_6 0 0.000% 0 0.000% +PREF_ACC_7 0 0.000% 0 0.000% +PREF_ACC_8 0 0.000% 0 0.000% +PREF_ACC_9 0 0.000% 0 0.000% +PREF_ACC_10 0 0.000% 0 0.000% + 14 100.000% 14 100.000% + 0.14 0.34 0.14 0.34 + +PREF_TIMELY_1 0 0.000% 0 0.000% +PREF_TIMELY_2 0 0.000% 0 0.000% +PREF_TIMELY_3 0 0.000% 0 0.000% +PREF_TIMELY_4 0 0.000% 0 0.000% +PREF_TIMELY_5 0 0.000% 0 0.000% +PREF_TIMELY_6 0 0.000% 0 0.000% +PREF_TIMELY_7 0 0.000% 0 0.000% +PREF_TIMELY_8 0 0.000% 0 0.000% +PREF_TIMELY_9 1 7.143% 1 7.143% +PREF_TIMELY_10 13 92.857% 13 92.857% + 14 100.000% 14 100.000% + 8.93 8.93 8.93 8.93 + +PREF_UNUSED_EVICT 3656 3656 + +PREF_REGION_SENT 0 0 + +PREF_REGION_USEFUL 0 0 + +PREF_REGION_EVICT 0 0 + +PREF_PFPOL 0 0 + +PREF_PHASE_NEWPHASE_DET 0 0 + +PREF_PHASE_NEWPHASE_NOTVALID 0 0 + +PREF_PHASE_SENTPREF 0 0 + +PREF_PHASE_OVERWRITE_PAGE 0 0 + +PREF_UPDATE_COUNT 14 14 + +PREF_ACC1_HT_HP 0 0.000% 0 0.000% +PREF_ACC1_HT_LP 4 28.571% 4 28.571% +PREF_ACC1_LT_HP 0 0.000% 0 0.000% +PREF_ACC1_LT_LP 10 71.429% 10 71.429% +PREF_ACC2_HT_HP 0 0.000% 0 0.000% +PREF_ACC2_HT_LP 0 0.000% 0 0.000% +PREF_ACC2_LT_HP 0 0.000% 0 0.000% +PREF_ACC2_LT_LP 0 0.000% 0 0.000% +PREF_ACC3_HT_HP 0 0.000% 0 0.000% +PREF_ACC3_HT_LP 0 0.000% 0 0.000% +PREF_ACC3_LT_HP 0 0.000% 0 0.000% +PREF_ACC3_LT_LP 0 0.000% 0 0.000% +PREF_ACC4_HT_HP 0 0.000% 0 0.000% +PREF_ACC4_HT_LP 0 0.000% 0 0.000% +PREF_ACC4_LT_HP 0 0.000% 0 0.000% +PREF_ACC4_LT_LP 0 0.000% 0 0.000% + 14 100.000% 14 100.000% + 2.43 0.94 2.43 0.94 + + + diff --git a/labs/LAB5/runs/x264-sms0/ramulator.stat.out b/labs/LAB5/runs/x264-sms0/ramulator.stat.out new file mode 100644 index 00000000..f0bc675f --- /dev/null +++ b/labs/LAB5/runs/x264-sms0/ramulator.stat.out @@ -0,0 +1,150 @@ + ramulator.active_cycles_0 2239770 # Total active cycles for level _0 + ramulator.busy_cycles_0 2239770 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0 + ramulator.serving_requests_0 4751129 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.average_serving_requests_0 0.371897 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.active_cycles_0_0 2239770 # Total active cycles for level _0_0 + ramulator.busy_cycles_0_0 2779050 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0 + ramulator.serving_requests_0_0 4751129 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.average_serving_requests_0_0 0.371897 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.active_cycles_0_0_0 834557 # Total active cycles for level _0_0_0 + ramulator.busy_cycles_0_0_0 834557 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0 + ramulator.serving_requests_0_0_0 1260316 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 +ramulator.average_serving_requests_0_0_0 0.098652 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 + ramulator.active_cycles_0_0_0_0 217739 # Total active cycles for level _0_0_0_0 + ramulator.busy_cycles_0_0_0_0 217739 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_0 + ramulator.serving_requests_0_0_0_0 290308 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 +ramulator.average_serving_requests_0_0_0_0 0.022724 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 + ramulator.active_cycles_0_0_0_1 246387 # Total active cycles for level _0_0_0_1 + ramulator.busy_cycles_0_0_0_1 246387 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_1 + ramulator.serving_requests_0_0_0_1 331477 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 +ramulator.average_serving_requests_0_0_0_1 0.025947 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 + ramulator.active_cycles_0_0_0_2 213282 # Total active cycles for level _0_0_0_2 + ramulator.busy_cycles_0_0_0_2 213282 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_2 + ramulator.serving_requests_0_0_0_2 285021 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 +ramulator.average_serving_requests_0_0_0_2 0.022310 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 + ramulator.active_cycles_0_0_0_3 261817 # Total active cycles for level _0_0_0_3 + ramulator.busy_cycles_0_0_0_3 261817 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_3 + ramulator.serving_requests_0_0_0_3 353510 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 +ramulator.average_serving_requests_0_0_0_3 0.027671 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 + ramulator.active_cycles_0_0_1 827975 # Total active cycles for level _0_0_1 + ramulator.busy_cycles_0_0_1 827975 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1 + ramulator.serving_requests_0_0_1 1202807 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 +ramulator.average_serving_requests_0_0_1 0.094150 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 + ramulator.active_cycles_0_0_1_0 234833 # Total active cycles for level _0_0_1_0 + ramulator.busy_cycles_0_0_1_0 234833 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_0 + ramulator.serving_requests_0_0_1_0 303689 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 +ramulator.average_serving_requests_0_0_1_0 0.023771 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 + ramulator.active_cycles_0_0_1_1 213261 # Total active cycles for level _0_0_1_1 + ramulator.busy_cycles_0_0_1_1 213261 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_1 + ramulator.serving_requests_0_0_1_1 277229 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 +ramulator.average_serving_requests_0_0_1_1 0.021700 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 + ramulator.active_cycles_0_0_1_2 280474 # Total active cycles for level _0_0_1_2 + ramulator.busy_cycles_0_0_1_2 280474 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_2 + ramulator.serving_requests_0_0_1_2 361018 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 +ramulator.average_serving_requests_0_0_1_2 0.028259 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 + ramulator.active_cycles_0_0_1_3 202101 # Total active cycles for level _0_0_1_3 + ramulator.busy_cycles_0_0_1_3 202101 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_3 + ramulator.serving_requests_0_0_1_3 260871 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 +ramulator.average_serving_requests_0_0_1_3 0.020420 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 + ramulator.active_cycles_0_0_2 816742 # Total active cycles for level _0_0_2 + ramulator.busy_cycles_0_0_2 816742 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2 + ramulator.serving_requests_0_0_2 1198426 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 +ramulator.average_serving_requests_0_0_2 0.093807 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 + ramulator.active_cycles_0_0_2_0 254196 # Total active cycles for level _0_0_2_0 + ramulator.busy_cycles_0_0_2_0 254196 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_0 + ramulator.serving_requests_0_0_2_0 325605 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 +ramulator.average_serving_requests_0_0_2_0 0.025487 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 + ramulator.active_cycles_0_0_2_1 234529 # Total active cycles for level _0_0_2_1 + ramulator.busy_cycles_0_0_2_1 234529 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_1 + ramulator.serving_requests_0_0_2_1 312112 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 +ramulator.average_serving_requests_0_0_2_1 0.024431 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 + ramulator.active_cycles_0_0_2_2 238717 # Total active cycles for level _0_0_2_2 + ramulator.busy_cycles_0_0_2_2 238717 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_2 + ramulator.serving_requests_0_0_2_2 323365 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 +ramulator.average_serving_requests_0_0_2_2 0.025312 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 + ramulator.active_cycles_0_0_2_3 185700 # Total active cycles for level _0_0_2_3 + ramulator.busy_cycles_0_0_2_3 185700 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_3 + ramulator.serving_requests_0_0_2_3 237344 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 +ramulator.average_serving_requests_0_0_2_3 0.018578 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 + ramulator.active_cycles_0_0_3 754798 # Total active cycles for level _0_0_3 + ramulator.busy_cycles_0_0_3 754798 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3 + ramulator.serving_requests_0_0_3 1089580 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 +ramulator.average_serving_requests_0_0_3 0.085287 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 + ramulator.active_cycles_0_0_3_0 223336 # Total active cycles for level _0_0_3_0 + ramulator.busy_cycles_0_0_3_0 223336 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_0 + ramulator.serving_requests_0_0_3_0 288258 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 +ramulator.average_serving_requests_0_0_3_0 0.022564 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 + ramulator.active_cycles_0_0_3_1 244660 # Total active cycles for level _0_0_3_1 + ramulator.busy_cycles_0_0_3_1 244660 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_1 + ramulator.serving_requests_0_0_3_1 312520 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 +ramulator.average_serving_requests_0_0_3_1 0.024463 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 + ramulator.active_cycles_0_0_3_2 205117 # Total active cycles for level _0_0_3_2 + ramulator.busy_cycles_0_0_3_2 205117 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_2 + ramulator.serving_requests_0_0_3_2 262355 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 +ramulator.average_serving_requests_0_0_3_2 0.020536 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 + ramulator.active_cycles_0_0_3_3 165878 # Total active cycles for level _0_0_3_3 + ramulator.busy_cycles_0_0_3_3 165878 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_3 + ramulator.serving_requests_0_0_3_3 226447 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 +ramulator.average_serving_requests_0_0_3_3 0.017725 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 + ramulator.read_transaction_bytes_0 9775360 # The total byte of read transaction per channel + ramulator.write_transaction_bytes_0 4100096 # The total byte of write transaction per channel + ramulator.row_hits_channel_0_core 186680 # Number of row hits per channel per core + ramulator.row_misses_channel_0_core 7825 # Number of row misses per channel per core + ramulator.row_conflicts_channel_0_core 22299 # Number of row conflicts per channel per core + ramulator.read_row_hits_channel_0_core 133969 # Number of row hits for read requests per channel per core + [0] 133969.0 # +ramulator.read_row_misses_channel_0_core 5279 # Number of row misses for read requests per channel per core + [0] 5279.0 # +ramulator.read_row_conflicts_channel_0_core 13492 # Number of row conflicts for read requests per channel per core + [0] 13492.0 # + ramulator.write_row_hits_channel_0_core 52711 # Number of row hits for write requests per channel per core + [0] 52711.0 # +ramulator.write_row_misses_channel_0_core 2546 # Number of row misses for write requests per channel per core + [0] 2546.0 # +ramulator.write_row_conflicts_channel_0_core 8807 # Number of row conflicts for write requests per channel per core + [0] 8807.0 # + ramulator.useless_activates_0_core 80 # Number of useless activations. E.g, ACT -> PRE w/o RD or WR + ramulator.read_latency_avg_0 129.655887 # The average memory latency cycles (in memory time domain) per request for all read requests in this channel + ramulator.read_latency_sum_0 19805585 # The memory latency cycles (in memory time domain) sum for all read requests in this channel + ramulator.req_queue_length_avg_0 13.286134 # Average of read and write queue length per memory cycle per channel. + ramulator.req_queue_length_sum_0 169735634 # Sum of read and write queue length per memory cycle per channel. + ramulator.read_req_queue_length_avg_0 1.525463 # Read queue length average per memory cycle per channel. + ramulator.read_req_queue_length_sum_0 19488390 # Read queue length sum per memory cycle per channel. + ramulator.write_req_queue_length_avg_0 11.760671 # Write queue length average per memory cycle per channel. + ramulator.write_req_queue_length_sum_0 150247244 # Write queue length sum per memory cycle per channel. + ramulator.record_read_hits 0.0 # record read hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_misses 0.0 # record_read_miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_conflicts 0.0 # record read conflict count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_hits 0.0 # record write hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_misses 0.0 # record write miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_conflicts 0.0 # record write conflict for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.dram_capacity 8589934592 # Number of bytes in simulated DRAM + ramulator.dram_cycles 12775397 # Number of DRAM cycles simulated + ramulator.incoming_requests 216836 # Number of incoming requests to DRAM + ramulator.read_requests 152755 # Number of incoming read requests to DRAM per core + [0] 152755.0 # + ramulator.write_requests 64081 # Number of incoming write requests to DRAM per core + [0] 64081.0 # + ramulator.ramulator_active_cycles 2239770 # The total number of cycles that the DRAM part is active (serving R/W) + ramulator.incoming_requests_per_channel 216836.0 # Number of incoming requests to each DRAM channel + [0] 216836.0 # +ramulator.incoming_read_reqs_per_channel 152755.0 # Number of incoming read requests to each DRAM channel + [0] 152755.0 # + ramulator.physical_page_replacement 0 # The number of times that physical page replacement happens. + ramulator.maximum_bandwidth 19200000000 # The theoretical maximum bandwidth (Bps) + ramulator.in_queue_req_num_sum 169735634 # Sum of read/write queue length + ramulator.in_queue_read_req_num_sum 19488390 # Sum of read queue length + ramulator.in_queue_write_req_num_sum 150247244 # Sum of write queue length + ramulator.in_queue_req_num_avg 13.286134 # Average of read/write queue length per memory cycle + ramulator.in_queue_read_req_num_avg 1.525463 # Average of read queue length per memory cycle + ramulator.in_queue_write_req_num_avg 11.760671 # Average of write queue length per memory cycle + ramulator.record_read_requests 0.0 # record read requests for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_requests 0.0 # record write requests for this core when it reaches request limit or to the end + [0] 0.0 # diff --git a/labs/LAB5/runs/x264-sms0/run.err b/labs/LAB5/runs/x264-sms0/run.err new file mode 100644 index 00000000..e69de29b diff --git a/labs/LAB5/runs/x264-sms0/run.out b/labs/LAB5/runs/x264-sms0/run.out new file mode 100644 index 00000000..adbf2e8e --- /dev/null +++ b/labs/LAB5/runs/x264-sms0/run.out @@ -0,0 +1,107 @@ +Scarab gitrev: 7ab9e17 +Scarab started at Sun Jun 11 08:08:38 2023 + +Initialized Ramulator. +** Heartbeat: 1% -- { 1000000 } -- 0.00 KIPS (500.00 KIPS) +** Heartbeat: 2% -- { 2000003 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 3% -- { 3000006 } -- 1000.00 KIPS (600.00 KIPS) +** Heartbeat: 4% -- { 4000009 } -- 500.00 KIPS (571.43 KIPS) +** Heartbeat: 5% -- { 5000010 } -- 500.00 KIPS (555.56 KIPS) +** Heartbeat: 6% -- { 6000012 } -- 1000.00 KIPS (600.00 KIPS) +** Heartbeat: 7% -- { 7000012 } -- 500.00 KIPS (583.33 KIPS) +** Heartbeat: 8% -- { 8000014 } -- 500.00 KIPS (571.43 KIPS) +** Heartbeat: 9% -- { 9000016 } -- 1000.00 KIPS (600.00 KIPS) +** Heartbeat: 10% -- { 10000019 } -- 500.00 KIPS (588.24 KIPS) +** Heartbeat: 11% -- { 11000020 } -- 500.00 KIPS (578.95 KIPS) +** Heartbeat: 12% -- { 12000020 } -- 1000.00 KIPS (600.00 KIPS) +** Heartbeat: 13% -- { 13000021 } -- 500.00 KIPS (590.91 KIPS) +** Heartbeat: 14% -- { 14000022 } -- 500.00 KIPS (583.33 KIPS) +** Heartbeat: 15% -- { 15000023 } -- 1000.00 KIPS (600.00 KIPS) +** Heartbeat: 16% -- { 16000027 } -- 500.00 KIPS (592.59 KIPS) +** Heartbeat: 17% -- { 17000028 } -- 500.00 KIPS (586.21 KIPS) +** Heartbeat: 18% -- { 18000032 } -- 500.00 KIPS (580.65 KIPS) +** Heartbeat: 19% -- { 19000034 } -- 250.00 KIPS (542.86 KIPS) +** Heartbeat: 20% -- { 20000034 } -- 500.00 KIPS (540.54 KIPS) +** Heartbeat: 21% -- { 21000036 } -- 1000.00 KIPS (552.63 KIPS) +** Heartbeat: 22% -- { 22000037 } -- 500.00 KIPS (550.00 KIPS) +** Heartbeat: 23% -- { 23000042 } -- 1000.00 KIPS (560.98 KIPS) +** Heartbeat: 24% -- { 24000046 } -- 500.00 KIPS (558.14 KIPS) +** Heartbeat: 25% -- { 25000049 } -- 1000.00 KIPS (568.18 KIPS) +** Heartbeat: 26% -- { 26000051 } -- 1000.00 KIPS (577.78 KIPS) +** Heartbeat: 27% -- { 27000053 } -- 500.00 KIPS (574.47 KIPS) +** Heartbeat: 28% -- { 28000057 } -- 1000.00 KIPS (583.33 KIPS) +** Heartbeat: 29% -- { 29000060 } -- 1000.00 KIPS (591.84 KIPS) +** Heartbeat: 30% -- { 30000062 } -- 500.00 KIPS (588.24 KIPS) +** Heartbeat: 31% -- { 31000065 } -- 1000.00 KIPS (596.16 KIPS) +** Heartbeat: 32% -- { 32000066 } -- 500.00 KIPS (592.59 KIPS) +** Heartbeat: 33% -- { 33000070 } -- 1000.00 KIPS (600.00 KIPS) +** Heartbeat: 34% -- { 34000073 } -- 500.00 KIPS (596.49 KIPS) +** Heartbeat: 35% -- { 35000074 } -- 1000.00 KIPS (603.45 KIPS) +** Heartbeat: 36% -- { 36000074 } -- 500.00 KIPS (600.00 KIPS) +** Heartbeat: 37% -- { 37000074 } -- 500.00 KIPS (596.78 KIPS) +** Heartbeat: 38% -- { 38000074 } -- 500.00 KIPS (593.75 KIPS) +** Heartbeat: 39% -- { 39000079 } -- 1000.00 KIPS (600.00 KIPS) +** Heartbeat: 40% -- { 40000081 } -- 500.00 KIPS (597.02 KIPS) +** Heartbeat: 41% -- { 41000086 } -- 500.00 KIPS (594.20 KIPS) +** Heartbeat: 42% -- { 42000088 } -- 500.00 KIPS (591.55 KIPS) +** Heartbeat: 43% -- { 43000088 } -- 1000.00 KIPS (597.22 KIPS) +** Heartbeat: 44% -- { 44000093 } -- 500.00 KIPS (594.60 KIPS) +** Heartbeat: 45% -- { 45000094 } -- 1000.00 KIPS (600.00 KIPS) +** Heartbeat: 46% -- { 46000094 } -- 500.00 KIPS (597.40 KIPS) +** Heartbeat: 47% -- { 47000095 } -- 1000.00 KIPS (602.57 KIPS) +** Heartbeat: 48% -- { 48000097 } -- 500.00 KIPS (600.00 KIPS) +** Heartbeat: 49% -- { 49000099 } -- 1000.00 KIPS (604.94 KIPS) +** Heartbeat: 50% -- { 50000099 } -- 500.00 KIPS (602.41 KIPS) +** Heartbeat: 51% -- { 51000100 } -- 500.00 KIPS (600.00 KIPS) +** Heartbeat: 52% -- { 52000102 } -- 1000.00 KIPS (604.65 KIPS) +** Heartbeat: 53% -- { 53000103 } -- 500.00 KIPS (602.27 KIPS) +** Heartbeat: 54% -- { 54000107 } -- 1000.00 KIPS (606.74 KIPS) +** Heartbeat: 55% -- { 55000111 } -- 500.00 KIPS (604.40 KIPS) +** Heartbeat: 56% -- { 56000114 } -- 1000.00 KIPS (608.70 KIPS) +** Heartbeat: 57% -- { 57000116 } -- 500.00 KIPS (606.38 KIPS) +** Heartbeat: 58% -- { 58000118 } -- 1000.00 KIPS (610.53 KIPS) +** Heartbeat: 59% -- { 59000119 } -- 500.00 KIPS (608.25 KIPS) +** Heartbeat: 60% -- { 60000124 } -- 1000.00 KIPS (612.25 KIPS) +** Heartbeat: 61% -- { 61000128 } -- 500.00 KIPS (610.00 KIPS) +** Heartbeat: 62% -- { 62000129 } -- 1000.00 KIPS (613.86 KIPS) +** Heartbeat: 63% -- { 63000129 } -- 500.00 KIPS (611.65 KIPS) +** Heartbeat: 64% -- { 64000132 } -- 500.00 KIPS (609.53 KIPS) +** Heartbeat: 65% -- { 65000133 } -- 1000.00 KIPS (613.21 KIPS) +** Heartbeat: 66% -- { 66000138 } -- 500.00 KIPS (611.11 KIPS) +** Heartbeat: 67% -- { 67000139 } -- 1000.00 KIPS (614.68 KIPS) +** Heartbeat: 68% -- { 68000142 } -- 500.00 KIPS (612.61 KIPS) +** Heartbeat: 69% -- { 69000144 } -- 1000.00 KIPS (616.07 KIPS) +** Heartbeat: 70% -- { 70000145 } -- 500.00 KIPS (614.04 KIPS) +** Heartbeat: 71% -- { 71000148 } -- 1000.00 KIPS (617.39 KIPS) +** Heartbeat: 72% -- { 72000153 } -- 500.00 KIPS (615.39 KIPS) +** Heartbeat: 73% -- { 73000157 } -- 1000.00 KIPS (618.65 KIPS) +** Heartbeat: 74% -- { 74000159 } -- 500.00 KIPS (616.67 KIPS) +** Heartbeat: 75% -- { 75000160 } -- 1000.00 KIPS (619.84 KIPS) +** Heartbeat: 76% -- { 76000160 } -- 500.00 KIPS (617.89 KIPS) +** Heartbeat: 77% -- { 77000161 } -- 500.00 KIPS (616.00 KIPS) +** Heartbeat: 78% -- { 78000163 } -- 1000.00 KIPS (619.05 KIPS) +** Heartbeat: 79% -- { 79000164 } -- 500.00 KIPS (617.19 KIPS) +** Heartbeat: 80% -- { 80000165 } -- 1000.00 KIPS (620.16 KIPS) +** Heartbeat: 81% -- { 81000166 } -- 500.00 KIPS (618.32 KIPS) +** Heartbeat: 82% -- { 82000169 } -- 1000.00 KIPS (621.21 KIPS) +** Heartbeat: 83% -- { 83000170 } -- 500.00 KIPS (619.40 KIPS) +** Heartbeat: 84% -- { 84000170 } -- 1000.00 KIPS (622.22 KIPS) +** Heartbeat: 85% -- { 85000172 } -- 500.00 KIPS (620.44 KIPS) +** Heartbeat: 86% -- { 86000177 } -- 500.00 KIPS (618.71 KIPS) +** Heartbeat: 87% -- { 87000178 } -- 1000.00 KIPS (621.43 KIPS) +** Heartbeat: 88% -- { 88000179 } -- 500.00 KIPS (619.72 KIPS) +** Heartbeat: 89% -- { 89000179 } -- 500.00 KIPS (618.06 KIPS) +** Heartbeat: 90% -- { 90000179 } -- 1000.00 KIPS (620.69 KIPS) +** Heartbeat: 91% -- { 91000179 } -- 500.00 KIPS (619.05 KIPS) +** Heartbeat: 92% -- { 92000184 } -- 1000.00 KIPS (621.62 KIPS) +** Heartbeat: 93% -- { 93000184 } -- 500.00 KIPS (620.00 KIPS) +** Heartbeat: 94% -- { 94000184 } -- 500.00 KIPS (618.42 KIPS) +** Heartbeat: 95% -- { 95000187 } -- 1000.00 KIPS (620.92 KIPS) +** Heartbeat: 96% -- { 96000190 } -- 500.00 KIPS (619.36 KIPS) +** Heartbeat: 97% -- { 97000193 } -- 1000.00 KIPS (621.80 KIPS) +** Heartbeat: 98% -- { 98000198 } -- 500.00 KIPS (620.25 KIPS) +** Heartbeat: 99% -- { 99000201 } -- 500.00 KIPS (618.75 KIPS) +** Core 0 Finished: insts:100000000 cycles:34067712 time:10646160000000 -- 2.94 IPC (2.94 IPC) -- N/A KIPS (621.12 KIPS) +done +Scarab finished at Sun Jun 11 08:11:19 2023 + diff --git a/labs/LAB5/runs/x264-sms0/stream.stat.0.out b/labs/LAB5/runs/x264-sms0/stream.stat.0.out new file mode 100644 index 00000000..5df2a2ca --- /dev/null +++ b/labs/LAB5/runs/x264-sms0/stream.stat.0.out @@ -0,0 +1,188 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 34067712 Instructions: 100000000 IPC: 2.93533 + +DCACHE_PREF_HIT 0 0 + +IFETCH_WB_FIRST_SCHEDULE 0 -nan% 0 -nan% +PREFETCH_LAST_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_PREF_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_LOW_OP_SCHEDULE 0 -nan% 0 -nan% +DEMAND_LAST_SCHEDULE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +SEND_MISS_REQ_QUEUE 152755 152755 + +L1_DATA_EVICT 136384 136384 + +STREAM_BUFFER_REQ 0 0 + +PREF_SEND_TO_MEM_REQ 0 -nan% 0 -nan% +PREF_SEND_TO_MEM_REQ_FAIL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +HIT_TRAIN_STREAM 105291 76.295% 105291 76.295% +MISS_TRAIN_STREAM 32715 23.705% 32715 23.705% + 138006 100.000% 138006 100.000% + 0.24 0.39 0.24 0.39 + +STREAM_TRAIN_CREATE 25609 25609 + +MEM_REQ_MISS_HWP_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_SW_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_IFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DSTORE_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DPRF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_WB_Q 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_BY_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_WB 0 -nan% 0 -nan% +PREF_HIT_BY_PREF 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_WB 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_L1_FILL 0 -nan% 0 -nan% +DEMAND_L1_FILL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TOUCH_L1_REPLACE 0 0.000% 0 0.000% +NO_TOUCH_L1_REPLACE 136384 100.000% 136384 100.000% + 136384 100.000% 136384 100.000% + 1.00 1.00 1.00 1.00 + +PREF_REQ_QUE_FULL 0 0 + +STREAM_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +L2HIT_STREAM_PREF_REQ_QUE_FULL 0 0 + +L2HIT_HIT_TRAIN_STREAM 0 -nan% 0 -nan% +L2HIT_MISS_TRAIN_STREAM 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_TRAIN_CREATE 0 0 + +L2HIT_STREAM_BUFFER_REQ 0 0 + +L2HIT_STREAM_PREF_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_STREAM_PREF_DCACHE_INSERT 0 -nan% 0 -nan% +L2HIT_STREAM_L2_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_DCACHE_PORT_FULL 0 0 + +L2HIT_STREAM_PREF_L1_PORT_FULL 0 0 + +L2HIT_TRAIN_HIT_DEMAND 0 -nan% 0 -nan% +L2HIT_TRAIN_MISS_REQ 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_TRAIN_FILTER_MISS 0 -nan% 0 -nan% +L2HIT_TRAIN_FILTER_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_PREF_REQ_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_PREF_REQ_DCACHE_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_L2SEND_Q_FULL 0 -nan% 0 -nan% +L2HIT_L2SEND_Q_ENTER 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_MEM_REQ 0 0 + +REMOVE_REDUNDANT_STREAM_STAT 0 0 + +REPLACE_OLD_STREAM 25593 25593 + +REQ_SEND_QUEUE_STALL 0 0 + +STREAM_ENTER_RA 0 0 + +CORE_STREAM_LENGTH_0 181 10.735% 181 10.735% +CORE_STREAM_LENGTH_10 489 29.004% 489 29.004% +CORE_STREAM_LENGTH_20 277 16.429% 277 16.429% +CORE_STREAM_LENGTH_30 218 12.930% 218 12.930% +CORE_STREAM_LENGTH_40 109 6.465% 109 6.465% +CORE_STREAM_LENGTH_50 99 5.872% 99 5.872% +CORE_STREAM_LENGTH_60 32 1.898% 32 1.898% +CORE_STREAM_LENGTH_70 33 1.957% 33 1.957% +CORE_STREAM_LENGTH_80 12 0.712% 12 0.712% +CORE_STREAM_LENGTH_90 23 1.364% 23 1.364% +CORE_STREAM_LENGTH_100_P 213 12.633% 213 12.633% + 1686 100.000% 1686 100.000% + 3.25 3.17 3.25 3.17 + +CORE_CUM_STREAM_LENGTH_0 1286 0.573% 1286 0.573% +CORE_CUM_STREAM_LENGTH_10 7557 3.367% 7557 3.367% +CORE_CUM_STREAM_LENGTH_20 6515 2.902% 6515 2.902% +CORE_CUM_STREAM_LENGTH_30 6992 3.115% 6992 3.115% +CORE_CUM_STREAM_LENGTH_40 4850 2.161% 4850 2.161% +CORE_CUM_STREAM_LENGTH_50 5215 2.323% 5215 2.323% +CORE_CUM_STREAM_LENGTH_60 2081 0.927% 2081 0.927% +CORE_CUM_STREAM_LENGTH_70 2385 1.063% 2385 1.063% +CORE_CUM_STREAM_LENGTH_80 1004 0.447% 1004 0.447% +CORE_CUM_STREAM_LENGTH_90 2139 0.953% 2139 0.953% +CORE_CUM_STREAM_LENGTH_100_P 184445 82.169% 184445 82.169% + 224469 100.000% 224469 100.000% + 8.86 8.43 8.86 8.43 + +CORE_STREAM_TRAIN_HITS_0 965 57.236% 965 57.236% +CORE_STREAM_TRAIN_HITS_10 428 25.386% 428 25.386% +CORE_STREAM_TRAIN_HITS_20 75 4.448% 75 4.448% +CORE_STREAM_TRAIN_HITS_30 21 1.246% 21 1.246% +CORE_STREAM_TRAIN_HITS_40 12 0.712% 12 0.712% +CORE_STREAM_TRAIN_HITS_50 13 0.771% 13 0.771% +CORE_STREAM_TRAIN_HITS_60 10 0.593% 10 0.593% +CORE_STREAM_TRAIN_HITS_70 14 0.830% 14 0.830% +CORE_STREAM_TRAIN_HITS_80 10 0.593% 10 0.593% +CORE_STREAM_TRAIN_HITS_90 7 0.415% 7 0.415% +CORE_STREAM_TRAIN_HITS_100_P 131 7.770% 131 7.770% + 1686 100.000% 1686 100.000% + 1.40 2.65 1.40 2.65 + +CORE_CUM_STREAM_TRAIN_HITS_0 6008 5.363% 6008 5.363% +CORE_CUM_STREAM_TRAIN_HITS_10 5519 4.926% 5519 4.926% +CORE_CUM_STREAM_TRAIN_HITS_20 1743 1.556% 1743 1.556% +CORE_CUM_STREAM_TRAIN_HITS_30 681 0.608% 681 0.608% +CORE_CUM_STREAM_TRAIN_HITS_40 522 0.466% 522 0.466% +CORE_CUM_STREAM_TRAIN_HITS_50 729 0.651% 729 0.651% +CORE_CUM_STREAM_TRAIN_HITS_60 631 0.563% 631 0.563% +CORE_CUM_STREAM_TRAIN_HITS_70 1084 0.968% 1084 0.968% +CORE_CUM_STREAM_TRAIN_HITS_80 858 0.766% 858 0.766% +CORE_CUM_STREAM_TRAIN_HITS_90 659 0.588% 659 0.588% +CORE_CUM_STREAM_TRAIN_HITS_100_P 93601 83.546% 93601 83.546% + 112035 100.000% 112035 100.000% + 8.72 8.31 8.72 8.31 + +CORE_STREAM_TRAIN_CREATE 25609 25609 + + + diff --git a/labs/LAB5/runs/x264-sms1/PARAMS.in b/labs/LAB5/runs/x264-sms1/PARAMS.in new file mode 100644 index 00000000..2593c2b8 --- /dev/null +++ b/labs/LAB5/runs/x264-sms1/PARAMS.in @@ -0,0 +1,226 @@ +# File : PARAMS.kaby_lake +# Date : 03/06/19 +# Description : Kaby Lake Configuration +# +# Based on documentation found here: +# https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake + +## Simulation Parameters +--mode full +--model cmp +--sim_limit none + +## Core Parameters + +# Femptoseconds, 3.2GHz, used for energy estimates. +--chip_cycle_time 312500 + + +### Fetch Stage +--fetch_off_path_ops 1 +--fetch_across_cache_lines 1 + +# Will break the packet upon a taken branch. +--fetch_break_on_taken 1 + +# Number of bubble cycles to wait after taken branch. +--fetch_taken_bubble_cycles 0 + + +#### ICache +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 + +### Branch Predictor +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_mech tagescl + + +#### BTB + +# BTB model to use. +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 + +# Allow the BTB to be updated by off path ops. +--btb_off_path_writes 1 + + +#### CRS + +# Enable return stack +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 + +### iBP +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged + # iBTB Model. tc_tagless, tc_tagged, tc_hybrid. +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 + +### Decode Stage +--decode_cycles 5 + + +### Map Stage +--map_cycles 5 + + +### Issue Stage + +# Max number of instructions to be fetched, decoded, renamed, and issued per cycle. +--issue_width 6 + +--rs_fill_width 0 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 + + +### Exec Stage + +### DCache +--dcache_size 32768 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--dcache_assoc 4 +--dcache_line_size 64 + +### Reorder/Retire Stage + +# Max number of instructions to be retired per cycle. +--node_ret_width 6 +--node_table_size 224 + +# Do not keep stores in RSVs on cache misses; TODO: confirm what this knob does +--stores_do_not_block_window 1 + +# TODO: confirm what this knob does +--prefs_do_not_block_window 1 + + +## Uncore + +### Mid-level cache + +# Enable use of a midlevel cache between i/d and L1 +--mlc_present 0 + +### LLC +--l1_size 1048576 +--l1_banks 1 +--l1_cycles 18 +--l1_assoc 8 +--l1_line_size 64 +--l1_interleave_factor 64 + + +### Prefetcher +--pref_framework_on 1 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--pref_shared_queues 0 +--pref_train_on_pref_misses 0 +--pref_oracle_train 0 +--pref_ul1req_queue_overwrite_on_full 1 + +--stream_length 64 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 + +--pref_throttlefb_on=1 +--pref_acc_thresh_1=0.75 +--pref_acc_thresh_2=0.4 +--pref_acc_thresh_3=0.4 +--pref_timely_thresh=0.01 +--pref_polpf_thresh=0.005 +--pref_update_interval=8192 + +--mem_req_buffer_pref_watermark 4 +--promote_to_higher_priority_mem_req_type 1 + +### Memory +--addr_translation random + +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 + +--mem_req_buffer_entries 32 +--mem_l1_fill_queue_entries 32 +--va_page_size_bytes 4096 +--bus_width_in_bytes 8 + +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 + +## Other + + +### Debug +--debug_inst_start 0 +--debug_inst_stop -1 +--debug_cycle_start 0 +--debug_cycle_stop -1 + + +## Stats and Params +--dump_params 1 +--dump_stats 1 +--dump_trace 0 + +#################################### +--set_off_path_confirmed 1 + +--order_beyond_bus 1 + +--mem_ooo_stores 1 +--mem_obey_store_dep 1 diff --git a/labs/LAB5/runs/x264-sms1/PARAMS.out b/labs/LAB5/runs/x264-sms1/PARAMS.out new file mode 100644 index 00000000..196ce7c9 --- /dev/null +++ b/labs/LAB5/runs/x264-sms1/PARAMS.out @@ -0,0 +1,908 @@ +--mode full +--model cmp +--frontend memtrace +--inst_limit 100000000 +--sim_limit none +--dump_params 1 +--dump_stats 1 +--dump_trace 0 +--mlc_present 0 +--l1_size 1048576 +--l1_assoc 8 +--l1_line_size 64 +--l1_cycles 18 +--l1_banks 1 +--l1_interleave_factor 64 +--va_page_size_bytes 4096 +--addr_translation random +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 +--dcache_size 32768 +--dcache_assoc 4 +--dcache_line_size 64 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--mem_ooo_stores 1 +--mem_obey_store_dep 1 +--mem_req_buffer_entries 32 +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 +--promote_to_higher_priority_mem_req_type 1 +--mem_req_buffer_pref_watermark 4 +--mem_l1_fill_queue_entries 32 +--order_beyond_bus 1 +--set_off_path_confirmed 1 +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--bus_width_in_bytes 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 +--chip_cycle_time 312500 +--issue_width 6 +--rs_fill_width 0 +--node_table_size 224 +--node_ret_width 6 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 +--decode_cycles 5 +--map_cycles 5 +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--fetch_across_cache_lines 1 +--fetch_off_path_ops 0 +--fetch_break_on_taken 1 +--fetch_taken_bubble_cycles 0 +--stores_do_not_block_window 1 +--prefs_do_not_block_window 1 +--cbp_trace_r0 /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir/trace/drmemtrace.x264.555077.8068.trace.gz +--memtrace_modules_log /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir/raw +--debug_cycle_start 0 +--debug_cycle_stop -1 +--debug_inst_start 0 +--debug_inst_stop -1 +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--bp_mech tagescl +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 +--btb_off_path_writes 1 +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_length 64 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 +--pref_framework_on 1 +--pref_shared_queues 0 +--pref_ul1req_queue_overwrite_on_full 1 +--pref_train_on_pref_misses 0 +--pref_oracle_train_on 0 +--pref_throttlefb_on 1 +--pref_acc_thresh_1 0.75 +--pref_acc_thresh_2 0.4 +--pref_acc_thresh_3 0.4 +--pref_update_interval 8192 +--pref_timely_thresh 0.01 +--pref_polpf_thresh 0.005 +--pref_sms_on 1 +1 1 1 1 1 1 1 + +--- Cut out everything below to use this file as PARAMS.in --- + +Parameter status at compile time and values supplied on the command line: + +SIM_MODE 0 full +SIM_MODEL 0 cmp +FRONTEND FE_PIN_EXEC_DRIVEN memtrace +INST_LIMIT NULL 100000000 +SIM_LIMIT "none" none +FORWARD_PROGRESS_LIMIT 100000000 +FORWARD_PROGRESS_INTERVAL 10000 +FAST_FORWARD 0 +FAST_FORWARD_UNTIL_ADDR 0 +FAST_FORWARD_TRACE_INS 0 +WARMUP 0 +HEARTBEAT_INTERVAL 1000000 +NUM_HEARTBEATS 0 +FILE_TAG "" +OUTPUT_DIR "." +STATUS_FILE NULL +BINDIR NULL +DUMP_PARAMS TRUE 1 +DUMP_STATS TRUE 1 +DUMP_TRACE FALSE 0 +CLEAR_STATS "never" +STATS_TO_TRACE NULL +STAT_TRACE_FILE "stats.trace" +STAT_TRACE_INTERVAL "i:100000" +PIPEVIEW FALSE +PIPEVIEW_FILE "pipeview" +MEMVIEW FALSE +MEMVIEW_FILE "memview.out" +MEMVIEW_START "never" +INST_HASH_TABLE_SIZE 500021 const +STDOUT_FILE NULL +STDERR_FILE NULL +PIN_EXEC_DRIVEN_FE_SOCKET "./pin_exec_driven_fe_socket.temp" +PRINT_PID FALSE +USE_UNSURE_FREE_LISTS FALSE +OPTIMIZER2_MAX_NUM_SLAVES 64 +OPTIMIZER2_PERFECT_MEMORYLESS FALSE +EXIT_COND 0 +ENABLE_SWPRF FALSE +MLC_PRESENT FALSE 0 +MLC_SIZE (512 * 1024) +MLC_ASSOC 4 +MLC_LINE_SIZE 64 +MLC_CYCLES 12 +PERFECT_MLC FALSE +MLC_READ_PORTS 1 +MLC_WRITE_PORTS 1 +MLC_BANKS 8 +MLC_INTERLEAVE_FACTOR 64 +MLC_CACHE_REPL_POLICY 0 +MLC_WRITE_THROUGH FALSE +PREFETCH_UPDATE_LRU_MLC TRUE +FORCE_L1_MISS FALSE +L1_SIZE (4 * 1024 * 1024) 1048576 +L1_ASSOC 8 8 +L1_LINE_SIZE 64 64 +L1_CYCLES 24 18 +PERFECT_L1 FALSE +PRIVATE_L1 FALSE +L1_READ_PORTS 1 +L1_WRITE_PORTS 1 +L1_BANKS 8 1 +L1_INTERLEAVE_FACTOR 64 64 +L1_CACHE_REPL_POLICY 0 +L1_WRITE_THROUGH FALSE +L1_IGNORE_WB FALSE +L1_USE_CORE_FREQ FALSE +MARK_L1_MISSES TRUE +PREFETCH_UPDATE_LRU_L1 TRUE +MEMORY_RANDOM_ADDR FALSE +VA_PAGE_SIZE_BYTES 4096 4096 +NUM_ADDR_NON_SIGN_EXTEND_BITS 48 +ADDR_TRANSLATION 0 random +CONSTANT_MEMORY_LATENCY FALSE +MEMORY_CYCLES 100 +STALL_MEM_REQS_ONLY FALSE +ICACHE_SIZE (64 * 1024) 32768 +ICACHE_ASSOC 4 4 +ICACHE_LINE_SIZE 64 64 +PERFECT_ICACHE FALSE +ICACHE_READ_PORTS 2 +ICACHE_WRITE_PORTS 1 +ICACHE_BANKS 8 +ICACHE_REPL 0 +DCACHE_SIZE (64 * 1024) 32768 +DCACHE_ASSOC 1 4 +DCACHE_LINE_SIZE 64 64 +DCACHE_CYCLES 2 +PERFECT_DCACHE FALSE +DCACHE_READ_PORTS 8 2 +DCACHE_WRITE_PORTS 1 1 +DCACHE_BANKS 1 1 +DCACHE_REPL 0 +DCACHE_REPL_PREF_THRESH 1 +MEM_OOO_STORES TRUE 1 +MEM_OBEY_STORE_DEP TRUE 1 +PREF_INSERT_LRU FALSE +PREF_INSERT_MIDDLE FALSE +PREF_INSERT_LOWQTR FALSE +PREF_INSERT_DYNACC FALSE +MEM_REQ_BUFFER_ENTRIES 32 32 +PRIVATE_MSHR_ON TRUE +MEM_PRIORITY_IFETCH 0 0 +MEM_PRIORITY_DFETCH 0 1 +MEM_PRIORITY_DSTORE 0 2 +MEM_PRIORITY_IPRF 9 3 +MEM_PRIORITY_DPRF 10 4 +MEM_PRIORITY_WB 0 5 +MEM_PRIORITY_WB_NODIRTY 0 5 +PROMOTE_TO_HIGHER_PRIORITY_MEM_REQ_TYPE FALSE 1 +MEM_REQ_BUFFER_PREF_WATERMARK 0 4 +MEM_REQ_BUFFER_WB_VALVE 2 +MEM_L1_FILL_QUEUE_ENTRIES 32 32 +MEM_BUS_OUT_QUEUE_PARTITION_ENABLE FALSE +MEM_MEM_QUEUE_PARTITION_ENABLE FALSE +MEM_BUS_OUT_QUEUE_AS_FIFO TRUE +OLDEST_FIRST_TO_MEM_QUEUE TRUE +ROUND_ROBIN_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE_TH 0 +L1_CYCLE_TIME 312500 +MLCQ_TO_L1Q_TRANSFER_LATENCY 1 +L1Q_TO_FSB_TRANSFER_LATENCY 1 +PRIORITIZE_PREFETCHES_WITH_UNIQUE FALSE +KICKOUT_PREFETCHES FALSE +KICKOUT_LOOK_FOR_OLDEST_FIRST FALSE +KICKOUT_OLDEST_PREFETCH FALSE +KICKOUT_OLDEST_PREFETCH_WITHIN_BANK FALSE +ORDER_BEYOND_BUS FALSE 1 +ALL_FIFO_QUEUES FALSE +QUEUE_MLC_SIZE 0 +QUEUE_L1_SIZE 0 +QUEUE_BUS_OUT_SIZE 0 +QUEUE_CORE_FILL_SIZE 0 +ALLOW_TYPE_MATCHES FALSE +STREAM_PREFETCH_ON FALSE +DC_PREF_CACHE_ENABLE FALSE +DC_PREF_CACHE_CYCLE 0 +PREF_INSERT_DCACHE_IMM TRUE +DC_PREF_CACHE_SIZE (64 * 1024) +DC_PREF_CACHE_ASSOC 4 +DC_PREF_ONLY_L1HIT FALSE +PREF_CACHE_USE_RDY_CYCLE FALSE +IC_PREF_CACHE_ENABLE FALSE +IC_PREF_CACHE_SIZE (64 * 1024) +IC_PREF_CACHE_ASSOC 4 +L1_PREF_CACHE_ENABLE FALSE +L1_PREF_CACHE_SIZE (1024 * 1024) +L1_PREF_CACHE_ASSOC 8 +SET_OFF_PATH_CONFIRMED FALSE 1 +USE_CONFIRMED_OFF FALSE +PREFCACHE_MOVE_OFFPATH FALSE +CACHE_STAT_ENABLE FALSE +PREF_DCACHE_HIT_FILL_L1 TRUE +PREF_ICACHE_HIT_FILL_L1 TRUE +CRITICAL_ACCESS_PLOT_ENABLE FALSE +CRITICAL_ACCESS_PLOT_FILE "critical_access_plot.dat" +ROUND_ROBIN_TO_L1 FALSE +PREF_I_TOGETHER FALSE +ONE_MORE_CACHE_LINE_ENABLE FALSE +L1_STATIC_PARTITION_ENABLE 0 +L1_STATIC_PARTITION NULL +L1_DYNAMIC_PARTITION_ENABLE FALSE +L1_DYNAMIC_PARTITION_POLICY 0 +PARTITION_UMON_DSS_PREF_ENABLE FALSE +L1_CACHE_HIT_POSITION_COLLECT FALSE +L1_PART_ON FALSE +L1_PART_TRIGGER "c:1000000" +L1_PART_START "t:0" +L1_PART_WARMUP FALSE +L1_PART_SHADOW_WARMUP FALSE +L1_PART_METRIC 0 +L1_PART_SEARCH 0 +L1_PART_USE_STALLING TRUE +L1_PART_FILL_DELAY 0 +L1_SHADOW_TAGS_MODULO 1 +HIER_MSHR_ON FALSE +PERF_PRED_ENABLE FALSE +PERF_PRED_MECH PERF_PRED_CP +PERF_PRED_REQ_LATENCY_MECH PERF_PRED_REQ_LATENCY_MECH_REQ_LATENCY +PERF_PRED_COUNT_ALL FALSE +PERF_PRED_COUNT_INST_MISSES TRUE +PERF_PRED_COUNT_PREFETCHES FALSE +PERF_PRED_COUNT_OFFPATH_REQS FALSE +PERF_PRED_COUNT_BW_REQS TRUE +PERF_PRED_UPDATE_MEM_REQ_TYPE FALSE +PERF_PRED_SLACK_PERIOD_SIZE 32 +PERF_PRED_REQS_FINISH_AT_FILL FALSE +PERF_PRED_MEM_UTIL_VIA_BUS_BW FALSE +PERF_PRED_CHIP_UTIL_VIA_MEM_STALL FALSE +DUMB_MODEL_AVG_REQ_DISTANCE 100 +DUMB_MODEL_RANDOMIZE_DISTANCE FALSE +DUMB_MODEL_AVG_REQ_DISTANCE_PER_CORE NULL +DUMB_MODEL_AVG_ROW_HITS 1 +DUMB_MODEL_AVG_ROW_HITS_PER_CORE NULL +DUMB_MODEL_MLP 1 +DUMB_MODEL_MLP_PER_CORE NULL +RAMULATOR_STANDARD "DDR4" DDR4 +RAMULATOR_SPEED "DDR4_2400R" DDR4_2400R +RAMULATOR_ORG "DDR4_8Gb_x8" DDR4_8Gb_x8 +RAMULATOR_CHANNELS 1 1 +RAMULATOR_RANKS 1 1 +RAMULATOR_BANKGROUPS 4 4 +RAMULATOR_BANKS 4 4 +RAMULATOR_CHIP_WIDTH 8 8 +BUS_WIDTH_IN_BYTES 8 8 +RAMULATOR_ROWS 65536 65536 +RAMULATOR_COLS 1024 1024 +RAMULATOR_SCHEDULING_POLICY "FRFCFS_Cap" FRFCFS_Cap +RAMULATOR_READQ_ENTRIES 32 32 +RAMULATOR_WRITEQ_ENTRIES 32 32 +RAMULATOR_REC_CMD_TRACE "off" FALSE +RAMULATOR_PRINT_CMD_TRACE "off" FALSE +RAMULATOR_USE_REST_OF_ADDR_AS_ROW_ADDR "on" +RAMULATOR_TCK 833333 833333 +RAMULATOR_TCL 16 16 +RAMULATOR_TCCD 6 6 +RAMULATOR_TCCDS 4 4 +RAMULATOR_TCCDL 6 6 +RAMULATOR_TCWL 12 12 +RAMULATOR_TBL 4 4 +RAMULATOR_TWTR 9 9 +RAMULATOR_TWTRS 3 3 +RAMULATOR_TWTRL 9 9 +RAMULATOR_TRP 16 16 +RAMULATOR_TRPpb 16 16 +RAMULATOR_TRPab 16 16 +RAMULATOR_TRCD 16 16 +RAMULATOR_TRCDR 16 16 +RAMULATOR_TRCDW 16 16 +RAMULATOR_TRAS 39 39 +DRAM_TECH_IN_NM 32 32 +DVFS_ON FALSE +DVFS_METRIC DVFS_METRIC_NUM_ELEMS +DVFS_CONFIGS NULL +DVFS_CONFIG_FILE NULL +DVFS_START "t:0" +DVFS_PERIOD "t:312500000000" +DVFS_LOG TRUE +DVFS_INDIVIDUAL_CORES FALSE +DVFS_CHIP_LEVEL FALSE +DVFS_STATIC NULL +DVFS_FORCE_CONFIG NULL +DVFS_REPLAY_CONFIG_TRACE NULL +DVFS_USE_ORACLE FALSE +DVFS_USE_BW_SHARING FALSE +DVFS_USE_DRAM_SHARING FALSE +DVFS_USE_STALL_TIME FALSE +DVFS_DRAM_SHARING_SOLVER_BIN NULL +DVFS_DRAM_SHARING_SOLVER_STRICT TRUE +DVFS_BW_SHARING_BUS_UTIL_THRESH 0.95 +DVFS_BW_SHARING_MAX_REQS 28.0 +DVFS_BW_SHARING_MAX_RW_COST 0.25 +DVFS_BW_SHARING_NO_PREF_STALL TRUE +DVFS_BW_SHARING_CRIT_STATS TRUE +DVFS_COUNT_L1_ACCESS_STALL FALSE +NUM_CORES 1 +CHIP_CYCLE_TIME 312500 312500 +CORE_0_CYCLE_TIME 312500 +CORE_1_CYCLE_TIME 312500 +CORE_2_CYCLE_TIME 312500 +CORE_3_CYCLE_TIME 312500 +CORE_4_CYCLE_TIME 312500 +CORE_5_CYCLE_TIME 312500 +CORE_6_CYCLE_TIME 312500 +CORE_7_CYCLE_TIME 312500 +CORE_8_CYCLE_TIME 312500 +CORE_9_CYCLE_TIME 312500 +CORE_10_CYCLE_TIME 312500 +CORE_11_CYCLE_TIME 312500 +CORE_12_CYCLE_TIME 312500 +CORE_13_CYCLE_TIME 312500 +CORE_14_CYCLE_TIME 312500 +CORE_15_CYCLE_TIME 312500 +CORE_16_CYCLE_TIME 312500 +CORE_17_CYCLE_TIME 312500 +CORE_18_CYCLE_TIME 312500 +CORE_19_CYCLE_TIME 312500 +CORE_20_CYCLE_TIME 312500 +CORE_21_CYCLE_TIME 312500 +CORE_22_CYCLE_TIME 312500 +CORE_23_CYCLE_TIME 312500 +CORE_24_CYCLE_TIME 312500 +CORE_25_CYCLE_TIME 312500 +CORE_26_CYCLE_TIME 312500 +CORE_27_CYCLE_TIME 312500 +CORE_28_CYCLE_TIME 312500 +CORE_29_CYCLE_TIME 312500 +CORE_30_CYCLE_TIME 312500 +CORE_31_CYCLE_TIME 312500 +CORE_32_CYCLE_TIME 312500 +CORE_33_CYCLE_TIME 312500 +CORE_34_CYCLE_TIME 312500 +CORE_35_CYCLE_TIME 312500 +CORE_36_CYCLE_TIME 312500 +CORE_37_CYCLE_TIME 312500 +CORE_38_CYCLE_TIME 312500 +CORE_39_CYCLE_TIME 312500 +CORE_40_CYCLE_TIME 312500 +CORE_41_CYCLE_TIME 312500 +CORE_42_CYCLE_TIME 312500 +CORE_43_CYCLE_TIME 312500 +CORE_44_CYCLE_TIME 312500 +CORE_45_CYCLE_TIME 312500 +CORE_46_CYCLE_TIME 312500 +CORE_47_CYCLE_TIME 312500 +CORE_48_CYCLE_TIME 312500 +CORE_49_CYCLE_TIME 312500 +CORE_50_CYCLE_TIME 312500 +CORE_51_CYCLE_TIME 312500 +CORE_52_CYCLE_TIME 312500 +CORE_53_CYCLE_TIME 312500 +CORE_54_CYCLE_TIME 312500 +CORE_55_CYCLE_TIME 312500 +CORE_56_CYCLE_TIME 312500 +CORE_57_CYCLE_TIME 312500 +CORE_58_CYCLE_TIME 312500 +CORE_59_CYCLE_TIME 312500 +CORE_60_CYCLE_TIME 312500 +CORE_61_CYCLE_TIME 312500 +CORE_62_CYCLE_TIME 312500 +CORE_63_CYCLE_TIME 312500 +ISSUE_WIDTH 4 6 +RS_FILL_WIDTH 8 0 +NODE_TABLE_SIZE 256 224 +NODE_RET_WIDTH 4 6 +NODE_RETIRE_RATE 10 +RS_SIZES "256" 97 +RS_CONNECTIONS "xF" 0 +FU_TYPES "0, 0, 0, 0" 0 0 0 0 0 0 0 0 +DECODE_CYCLES 1 5 +MAP_CYCLES 1 5 +EXTRA_RECOVERY_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after recovery. +EXTRA_REDIRECT_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after redirect. +EXTRA_CALLSYS_CYCLES 20 const +DIE_ON_CALLSYS FALSE +DIE_ON_RET_STALL_THRESH 0 +DIE_ON_RET_STALL_CORE 0 +DIE_ON_MEM_BLOCK_THRESH 0 +DIE_ON_MEM_BLOCK_CORE 0 +FETCH_ACROSS_CACHE_LINES FALSE 1 +FETCH_OFF_PATH_OPS TRUE 0 +FETCH_BREAK_ON_TAKEN FALSE 1 +FETCH_TAKEN_BUBBLE_CYCLES 0 0 +WP_COLLECT_STATS FALSE +SWITCH_IC_FETCH_ON_RECOVERY TRUE +OP_INV_DELAY 1 +OP_NOP_DELAY 1 +OP_CF_DELAY 1 +OP_MOV_DELAY 1 +OP_CMOV_DELAY 1 +OP_LDA_DELAY 1 +OP_IMEM_DELAY 1 +OP_IADD_DELAY 1 +OP_IMUL_DELAY 3 +OP_IDIV_DELAY -20 +OP_ICMP_DELAY 1 +OP_LOGIC_DELAY 1 +OP_SHIFT_DELAY 1 +OP_FMEM_DELAY 1 +OP_FCVT_DELAY 3 +OP_FADD_DELAY 3 +OP_FMUL_DELAY 5 +OP_FMA_DELAY 5 +OP_FDIV_DELAY -20 +OP_FCMP_DELAY 3 +OP_FCMOV_DELAY 1 +OP_GATHER_DELAY 12 +OP_SCATTER_DELAY 18 +OP_PIPELINED_FAST_DELAY 2 +OP_PIPELINED_MEDIUM_DELAY 5 +OP_PIPELINED_SLOW_DELAY 10 +OP_NOTPIPELINED_MEDIUM_DELAY -5 +OP_NOTPIPELINED_SLOW_DELAY -20 +OP_NOTPIPELINED_VERY_SLOW_DELAY -100 +UNIFORM_OP_DELAY 0 +STALL_ON_WAIT_MEM TRUE +STORES_DO_NOT_BLOCK_WINDOW FALSE 1 +PREFS_DO_NOT_BLOCK_WINDOW FALSE 1 +OBEY_REG_DEP TRUE +OLDEST_FIRST_SCHED FALSE +FIND_EMPTIEST_RS FALSE +TRACK_L1_MISS_DEPS FALSE +CBP_TRACE_R0 NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir/trace/drmemtrace.x264.555077.8068.trace.gz +CBP_TRACE_R1 NULL +CBP_TRACE_R2 NULL +CBP_TRACE_R3 NULL +CBP_TRACE_R4 NULL +CBP_TRACE_R5 NULL +CBP_TRACE_R6 NULL +CBP_TRACE_R7 NULL +CBP_TRACE_R8 NULL +CBP_TRACE_R9 NULL +CBP_TRACE_R10 NULL +CBP_TRACE_R11 NULL +CBP_TRACE_R12 NULL +CBP_TRACE_R13 NULL +CBP_TRACE_R14 NULL +CBP_TRACE_R15 NULL +CBP_TRACE_R16 NULL +CBP_TRACE_R17 NULL +CBP_TRACE_R18 NULL +CBP_TRACE_R19 NULL +CBP_TRACE_R20 NULL +CBP_TRACE_R21 NULL +CBP_TRACE_R22 NULL +CBP_TRACE_R23 NULL +CBP_TRACE_R24 NULL +CBP_TRACE_R25 NULL +CBP_TRACE_R26 NULL +CBP_TRACE_R27 NULL +CBP_TRACE_R28 NULL +CBP_TRACE_R29 NULL +CBP_TRACE_R30 NULL +CBP_TRACE_R31 NULL +CBP_TRACE_R32 NULL +CBP_TRACE_R33 NULL +CBP_TRACE_R34 NULL +CBP_TRACE_R35 NULL +CBP_TRACE_R36 NULL +CBP_TRACE_R37 NULL +CBP_TRACE_R38 NULL +CBP_TRACE_R39 NULL +CBP_TRACE_R40 NULL +CBP_TRACE_R41 NULL +CBP_TRACE_R42 NULL +CBP_TRACE_R43 NULL +CBP_TRACE_R44 NULL +CBP_TRACE_R45 NULL +CBP_TRACE_R46 NULL +CBP_TRACE_R47 NULL +CBP_TRACE_R48 NULL +CBP_TRACE_R49 NULL +CBP_TRACE_R50 NULL +CBP_TRACE_R51 NULL +CBP_TRACE_R52 NULL +CBP_TRACE_R53 NULL +CBP_TRACE_R54 NULL +CBP_TRACE_R55 NULL +CBP_TRACE_R56 NULL +CBP_TRACE_R57 NULL +CBP_TRACE_R58 NULL +CBP_TRACE_R59 NULL +CBP_TRACE_R60 NULL +CBP_TRACE_R61 NULL +CBP_TRACE_R62 NULL +CBP_TRACE_R63 NULL +MEMTRACE_MODULES_LOG NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.x264.555077.8155.dir/raw +DUMB_CORE_ON FALSE +DUMB_CORE 1 +DEBUG_CYCLE_START 0 0 +DEBUG_CYCLE_STOP 0 -1 +DEBUG_TIME_START 0 +DEBUG_TIME_STOP 0 +DEBUG_INST_START 0 0 +DEBUG_INST_STOP 0 -1 +DEBUG_OP_START 0 +DEBUG_OP_STOP 0 +DEBUG_CACHE_LIB FALSE +DEBUG_HASH_LIB FALSE +DEBUG_LIST_LIB FALSE +DEBUG_PORT_LIB FALSE +DEBUG_BUS_LIB FALSE +DEBUG_OP_POOL FALSE +DEBUG_ORACLE FALSE +DEBUG_FRONTEND FALSE +DEBUG_ADDR_TRANS FALSE +DEBUG_BP FALSE +DEBUG_BP_DIR FALSE +DEBUG_BTB FALSE +DEBUG_CRS FALSE +DEBUG_MAP FALSE +DEBUG_MEMORY FALSE +DEBUG_REPLAY FALSE +DEBUG_FREQ FALSE +DEBUG_MODEL FALSE +DEBUG_THREAD FALSE +DEBUG_ICACHE_STAGE FALSE +DEBUG_DECODE_STAGE FALSE +DEBUG_MAP_STAGE FALSE +DEBUG_NODE_STAGE FALSE +DEBUG_EXEC_STAGE FALSE +DEBUG_DCACHE_STAGE FALSE +DEBUG_RETIRED_UOPS FALSE +DEBUG_EXC_INSERTS FALSE +DEBUG_BP_CONF FALSE +DEBUG_ONPATH_CONF FALSE +DEBUG_STREAM FALSE +DEBUG_STREAM_MEM FALSE +DEBUG_WAY FALSE +DEBUG_L2MARKV FALSE +DEBUG_L2L1PREF FALSE +DEBUG_PERF_PRED FALSE +DEBUG_POWER_UTILS FALSE +DEBUG_DVFS FALSE +DEBUG_TRACE_READ FALSE +DEBUG_INST_FIELDS FALSE +DEBUG_OP_FIELDS FALSE +DEBUG_PIN_EXEC_DRIVEN FALSE +DEBUG_CACHE_PART FALSE +DEBUG_OPTIMIZER2 FALSE +DEBUG_PREF FALSE +PERFECT_BP FALSE +PERFECT_BTB FALSE +PERFECT_IBP FALSE +PERFECT_CRS FALSE +PERFECT_CBR_BTB FALSE +PERFECT_NT_BTB FALSE +CFS_PER_CYCLE 3 6 # Number of branches that can be predicted in a single cycle +UPDATE_BP_OFF_PATH FALSE 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +BP_UPDATE_AT_RETIRE FALSE 0 # Update the BP at retire. If false, update at the end of exec. +BP_MECH 0 tagescl +LATE_BP_MECH NUM_BP +LATE_BP_LATENCY 5 +HIST_LENGTH 16 +PHT_CTR_BITS 2 const +BHT_ENTRIES (4 * 1024) +BHT_ASSOC 4 +HYBRIDS_INDEX_LENGTH 16 +HYBRIDG_HIST_LENGTH 16 +HYBRIDP_HIST_LENGTH 16 +FILTER_INDEX_LENGTH 16 +USE_FILTER FALSE +INF_HYBRIDGP FALSE +BP_HASH_TOS FALSE +IBTB_HASH_TOS FALSE +BTB_MECH 0 generic +BTB_ENTRIES (4 * 1024) 4096 +BTB_ASSOC 4 4 +BTB_OFF_PATH_WRITES TRUE 1 +ENABLE_CRS TRUE 1 +CRS_ENTRIES 32 32 +CRS_REALISTIC 0 1 +ENABLE_IBP TRUE 1 # Enable the indirect branch predictor +USE_PAT_HIST TRUE +IBTB_MECH 1 tc_tagged +IBTB_HIST_LENGTH 16 +IBTB_OFF_PATH_WRITES TRUE 1 # Allow off path ops to update the ibtb. +TARGETS_IN_HIST 4 +TC_ENTRIES (4 * 1024) 4096 +TC_ASSOC 4 4 +NUM_CORR_BRANCHES 3 +SEL_HIST_BP_ENTRIES 8192 +SEL_HIST_LENGTH 16 +SEL_HIST_DYN_CNT_TH 16 +SEL_HIST_MISPRED_TH 4 +ENABLE_BP_CONF FALSE +CONF_MECH 0 +PERF_BP_CONF_PRED FALSE +BPC_BITS 16 +BPC_MECH 1 +BPC_CTR_RESET TRUE +BPC_CIT_BITS 8 +BPC_CIT_TH 50 +BPC_CTR_BITS 3 +OPC_COUNT_ZEROS FALSE +OPC_COUNT_THRESH 10 +INF_LOOP FALSE +INF_LOOP_BUCKETS 811 +LOOP_ENTRIES (4 * 1024) +LOOP_ASSOC 4 +LOOP_COUNT_MAX 127 +LOOP_REPEAT_MAX 15 +KNOB_PRINT_BRINFO FALSE +BR_MISPRED_FILE NULL +CONF_PERCEPTRON_TH 0 +CONF_PERCEPTRON_CTR_BITS 8 +CONF_PERCEPTRON_ENTRIES 127 +CONF_PERCEPTRON_THRESH_OVRD 0 +CONF_HIST_LENGTH 32 +PERCEPTRON_CONF_USE_CONF FALSE +PERCEPTRON_CONF_TRAIN_HIS FALSE +PERCEPTRON_CONF_TRAIN_CONF FALSE +PERCEPTRON_CONF_TRAIN_OFFSET_CONF FALSE +PERCEPTRON_TRAIN_MISP_FACTOR 1 +PERCEPTRON_TRAIN_CORR_FACTOR 1 +PERCEPTRON_CONF_HIS_BOTH FALSE +PERCEPTRON_CONF_HIS_BOTH_LENGTH 4 +ENABLE_ICACHE_PACKET_BREAKING TRUE +NUM_LOAD_STORE_PER_PACKET 0 +PACKET_BREAK_ON_FUS FALSE +PACKET_BREAK_FU_TYPES "G,G,G,G,G,G,G,G,G,G,G,G" +POWER_INTF_ON FALSE +POWER_INTF_ENABLE_SCALING FALSE +POWER_INTF_EXEC "power/power_intf.py" +POWER_INTF_REF_CHIP_TECH_NM 22 +POWER_INTF_REF_CHIP_FREQ (3.2e9) +POWER_INTF_REF_MEMORY_FREQ (0.8e9) +POWER_OTHER (0.0) +PREF_STREAM_ON FALSE 1 +PREF_STREAM_PER_CORE_ENABLE FALSE 1 +STREAM_BUFFER_N 16 +STREAM_PREFETCH_N 2 4 +STREAM_START_DIS 5 1 +STREAM_LENGTH 16 64 +STREAM_FULL_N 1 +STREAM_TRAIN_LENGTH 16 +STREAM_TRAIN_NUM 1 4 +PREF_ACC_USE_CACHE FALSE +STREAM_STALL_ON_QUEUE_FULL FALSE +PREF_SCHEDULE_NUM 4 +TRAIN_FILTER_SIZE 32 +PREF_REQ_Q_SIZE 64 +STREAM_CREATE_ON_DC_MISS FALSE 0 +STREAM_CREATE_ON_L1_MISS TRUE 1 +STREAM_TRAIN_ON_WRONGPATH TRUE +STREAM_CREATE_ON_WRONGPATH TRUE +STREAM_PREF_INTO_DCACHE FALSE +REMOVE_REDUNDANT_STREAM FALSE +L2HIT_STREAM_SCHEDULE_NUM 4 +PREF_REQ_QUEUE_FILTER_ON FALSE +HW_PREF_HIT_TRAIN_STREAM FALSE +L2HIT_STREAM_BUFFER_N 32 +L2HIT_STREAM_PREFETCH_N 2 +L2HIT_STREAM_START_DIS 2 +L2HIT_STREAM_LENGTH 8 +L2HIT_PREF_REQ_Q_SIZE 128 +L2HIT_L2ACCESS_REQ_Q_SIZE 64 +PREF_STREAM_ACCPERSTREAM FALSE +PREF_ACC_DISTANCE_10 128 +PREF_FRAMEWORK_ON FALSE 1 +PREF_TRACE_ON FALSE +PREF_DL0REQ_QUEUE_SIZE 32 +PREF_UMLC_REQ_QUEUE_SIZE 64 +PREF_UL1REQ_QUEUE_SIZE 128 +PREF_SHARED_QUEUES TRUE 0 +PREF_DL0_MISS_ON TRUE +PREF_DL0_HIT_ON TRUE +PREF_DL0REQ_QUEUE_FILTER_ON TRUE +PREF_UMLC_REQ_QUEUE_FILTER_ON TRUE +PREF_UL1REQ_QUEUE_FILTER_ON TRUE +PREF_DL0REQ_ADD_FILTER_ON TRUE +PREF_UMLC_REQ_ADD_FILTER_ON TRUE +PREF_UL1REQ_ADD_FILTER_ON TRUE +PREF_DL0REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UMLC_REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UL1REQ_QUEUE_OVERWRITE_ON_FULL FALSE 1 +PREF_DL0SCHEDULE_NUM 4 +PREF_UMLC_SCHEDULE_NUM 4 +PREF_UL1SCHEDULE_NUM 4 +PREF_L1Q_DEMAND_RESERVE 0 +PREF_REPORT_PREF_MATCH_AS_MISS FALSE +PREF_REPORT_PREF_MATCH_AS_HIT TRUE +PREF_UPDATE_ON_WRONGPATH TRUE +PREF_TRAIN_ON_PREF_MISSES FALSE 0 +PREF_ORACLE_TRAIN_ON FALSE 0 +PREF_REQ_DROP FALSE +PREF_THROTTLE_ON FALSE +PREF_THROTTLEFB_ON FALSE 1 +PREF_ACC_THRESH_1 0.90 0.75 +PREF_ACC_THRESH_2 0.70 0.4 +PREF_ACC_THRESH_3 0.60 0.4 +PREF_ACC_THRESH_4 0.40 +PREF_UPDATE_INTERVAL 0 8192 +PREF_ANALYZE_LOAD FALSE +PREF_POL_THRESH_1 0.25 +PREF_POL_THRESH_2 0.10 +PREF_POLBV_ON FALSE +PREF_POLBV_SIZE 1024 +PREF_TIMELY_THRESH 0.05 0.01 +PREF_POLPF_THRESH 0.01 0.005 +PREF_DEGFB_USEONLYACC FALSE +PREF_DEGFB_USEONLYPOL FALSE +PREF_DEGFB_USEONLYLATE FALSE +PREF_TIMELY_THRESH_2 0.005 +PREF_DEGFB_STATPHASEFILE FALSE +PREF_MAX_DEGFB 4 +PREF_DHAL FALSE +PREF_DHAL_SENTTHRESH 16 +PREF_DHAL_USETHRESH_MAX 12 +PREF_DHAL_USETHRESH_MIN2 8 +PREF_DHAL_USETHRESH_MIN1 4 +PREF_DHAL_MAXDEG 64 +PREF_HFILTER_ON FALSE +PREF_HFILTER_INDEX_BITS 12 +PREF_HFILTER_USE_PC FALSE +PREF_HFILTER_PRED_USELESS_THRES 2 +PREF_HFILTER_RESET_ENABLE FALSE +PREF_HFILTER_RESET_INTERVAL 100000 +L2L1PREF_ON FALSE +L2WAY_PREF FALSE +L2MARKV_PREF_ON FALSE +L2NEXT_PREF_ON FALSE +L2HIT_STREAM_PREF_ON FALSE +L2L1_DC_HIT_TRAIN FALSE +L1_HIT_DUMP_FILE_ON FALSE +L1_HIT_DUMP_WO_TXT FALSE +L1_HIT_DUMPFILE "l1hit_dump.out" +IDEAL_L2_L1_PREFETCHER FALSE +IDEAL_L2_ICACHE_PREFETCHER FALSE +L1WAY_PREF_SEND_QUEUE 4 +L1PREF_REQ_QUEUE_SIZE 1024 +L1PREF_IMMEDIATE FALSE +L1WAY_PREF_TIMER_DIS 1000 +L1MARKV_PREF_SEND_QUEUE 4 +L1PREF_MARKV_REQ_QUEUE_SIZE 1024 +MARKV_L2ACCESS_REQ_Q_SIZE 64 +L1MARKV_PREF_IMMEDIATE FALSE +L1MARKV_PREF_TIMER_DIS 1 +L2L1_HIT_TRAIN TRUE +L1MARKV_REQ_TH 1 +L2L1_IMMEDIATE_PREF_CACHE FALSE +L2L1_FILL_PREF_CACHE FALSE +L2L1_L2_HIT_STAT FALSE +PREF_GHB_ON FALSE +DEBUG_PREF_GHB FALSE +PREF_GHB_BUFFER_N 1024 +PREF_GHB_INDEX_N 128 +PREF_GHB_CZONE_BITS 12 +PREF_GHB_DEGREE 16 +PREF_GHB_MAX_DEGREE 32 +PREF_STRIDE_ON FALSE +DEBUG_PREF_STRIDE FALSE +PREF_STRIDE_TABLE_N 1024 +PREF_STRIDE_REGION_BITS 16 +PREF_STRIDE_DEGREE 4 +PREF_STRIDE_DISTANCE 16 +PREF_STRIDE_STARTDISTANCE 1 +PREF_STRIDE_SINGLE_THRESH 6 +PREF_STRIDE_MULTI_THRESH 6 +PREF_STRIDE_SINGLE_STRIDE_MODE FALSE +PREF_STRIDEPC_ON FALSE +DEBUG_PREF_STRIDEPC FALSE +PREF_STRIDEPC_TABLE_N 1024 +PREF_STRIDEPC_DEGREE 4 +PREF_STRIDEPC_DISTANCE 16 +PREF_STRIDEPC_USELOADADDR FALSE +PREF_STRIDEPC_TRAINNUM 2 +PREF_STRIDEPC_STARTDIS 4 +PREF_PHASE_ON FALSE +PREF_PHASE_STUDY FALSE +DEBUG_PREF_PHASE FALSE +PREF_PHASE_PRIME_HASH 16381 +PREF_PHASE_INFOSIZE 16384 +PREF_PHASE_LOG2REGIONSIZE 12 +PREF_PHASE_REGIONENTRIES 64 +PREF_PHASE_TRACKEDREGIONS 32 +PREF_PHASE_INTERVAL 100000 +PREF_PHASE_TABLE_SIZE 64 +PREF_PHASE_MAXDIFF_THRESH 64 +PREF_PHASE_MIN_MISSES 64 +PREF_PHASE_MISSPER 0.4 +PREF_2DC_ON FALSE +DEBUG_PREF_2DC FALSE +PREF_2DC_CACHE_SIZE (1 * 1024) +PREF_2DC_CACHE_ASSOC 4 +PREF_2DC_CACHE_LINE_SIZE 1 +PREF_2DC_DEGREE 16 +PREF_2DC_ZONE_SHIFT 10 +PREF_2DC_TAG_SIZE 16 +PREF_2DC_NUM_REGIONS 64 +PREF_2DC_REGION_HASH 61 +PREF_MARKOV_ON FALSE +DEBUG_PREF_MARKOV FALSE +PREF_MARKOV_NUM_ENTRIES 65536 +PREF_MARKOV_NUM_NEXT_STATES 8 +PREF_MARKOV_SEND_ON_PREF_HIT TRUE +PREF_MARKOV_UPDATE_ON_PREF_HIT TRUE +PREF_MARKOV_TABLE_UPDATE_POLICY 0 +PREF_MARKOV_SEND_THRESHOLD 0 +PREF_SMS_ON FALSE 1 +PREF_SMS_AT_SIZE 64 +PREF_SMS_FT_SIZE 64 +PREF_SMS_PHT_SIZE 16384 +PREF_SMS_PRF_SIZE 1024 +PREF_SMS_REGION_SIZE 2048 diff --git a/labs/LAB5/runs/x264-sms1/bp.stat.0.out b/labs/LAB5/runs/x264-sms1/bp.stat.0.out new file mode 100644 index 00000000..278220c3 --- /dev/null +++ b/labs/LAB5/runs/x264-sms1/bp.stat.0.out @@ -0,0 +1,752 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 34067712 Instructions: 100000000 IPC: 2.93533 + +BTB_ON_PATH_MISS 3777 0.083% 3777 0.083% +BTB_ON_PATH_HIT 4522018 99.917% 4522018 99.917% + 4525795 100.000% 4525795 100.000% + 1.00 1.00 1.00 1.00 + +BTB_OFF_PATH_MISS 0 -nan% 0 -nan% +BTB_OFF_PATH_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BTB_ON_PATH_WRITE 3777 100.000% 3777 100.000% +BTB_OFF_PATH_WRITE 0 0.000% 0 0.000% + 3777 100.000% 3777 100.000% + 0.00 0.00 0.00 0.00 + +BP_ON_PATH_CORRECT 4315247 95.348% 4315247 95.348% +BP_ON_PATH_MISPREDICT 67422 1.490% 67422 1.490% +BP_ON_PATH_MISFETCH 143126 3.162% 143126 3.162% + 4525795 100.000% 4525795 100.000% + 0.08 0.36 0.08 0.36 + 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+MEM_BLOCK_LENGTH_900 57 0.655% 57 0.655% +MEM_BLOCK_LENGTH_1000 37 0.425% 37 0.425% +MEM_BLOCK_LENGTH_1100 35 0.402% 35 0.402% +MEM_BLOCK_LENGTH_1200 18 0.207% 18 0.207% +MEM_BLOCK_LENGTH_1300 23 0.264% 23 0.264% +MEM_BLOCK_LENGTH_1400 16 0.184% 16 0.184% +MEM_BLOCK_LENGTH_1500 14 0.161% 14 0.161% +MEM_BLOCK_LENGTH_1600 12 0.138% 12 0.138% +MEM_BLOCK_LENGTH_1700 14 0.161% 14 0.161% +MEM_BLOCK_LENGTH_1800 10 0.115% 10 0.115% +MEM_BLOCK_LENGTH_1900 7 0.080% 7 0.080% +MEM_BLOCK_LENGTH_2000 7 0.080% 7 0.080% +MEM_BLOCK_LENGTH_2100 6 0.069% 6 0.069% +MEM_BLOCK_LENGTH_2200 3 0.034% 3 0.034% +MEM_BLOCK_LENGTH_2300 8 0.092% 8 0.092% +MEM_BLOCK_LENGTH_2400 1 0.011% 1 0.011% +MEM_BLOCK_LENGTH_2500 1 0.011% 1 0.011% +MEM_BLOCK_LENGTH_2600 2 0.023% 2 0.023% +MEM_BLOCK_LENGTH_2700 2 0.023% 2 0.023% +MEM_BLOCK_LENGTH_2800 1 0.011% 1 0.011% +MEM_BLOCK_LENGTH_2900 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_3000 1 0.011% 1 0.011% +MEM_BLOCK_LENGTH_3100 2 0.023% 2 0.023% +MEM_BLOCK_LENGTH_3200 1 0.011% 1 0.011% +MEM_BLOCK_LENGTH_3300 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_3400 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_3500 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_3600 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_3700 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_3800 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_3900 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4000 1 0.011% 1 0.011% +MEM_BLOCK_LENGTH_4100 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4200 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4300 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4400 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4500 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4600 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4700 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4800 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4900 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_5000 1 0.011% 1 0.011% + 8699 100.000% 8699 100.000% + 1.01 2.86 1.01 2.86 + +FUS_BUSY_ON_PATH 138607238 4.0686 138607238 4.0686 + +FUS_BUSY_OFF_PATH 0 0.0000 0 0.0000 + +FU_BUSY_MEM_STALL 27698202 0.8130 27698202 0.8130 + +FUS_EMPTY 133934458 3.9314 133934458 3.9314 + +CHIP_UTILIZATION 0 0.0000 0 0.0000 + +CYCLES_UNDER_MEM_REQ 0 0 + +CYCLES_UNDER_NO_MEM_REQ 0 0 + +CYCLES_UNDER_CRITICAL_MEM_REQ 0 0 + +CYCLES_UNDER_NONCRITICAL_MEM_REQ 0 0 + +CHIP_UTILIZATION_UNDER_MEM_REQ 0 -nan 0 -nan + +CHIP_UTILIZATION_UNDER_NO_MEM_REQ 0 -nan 0 -nan + +CHIP_UTILIZATION_UNDER_CRITICAL_MEM_REQ 0 -nan 0 -nan + +CHIP_UTILIZATION_UNDER_NONCRITICAL_MEM_REQ 0 -nan 0 -nan + +CYCLES_NOT_WAITING_FOR_OFF_CHIP 0 0.0000 0 0.0000 + +FUS_BUSY_NOT_WAITING_FOR_OFF_CHIP 0 -nan 0 -nan + +CYCLES_WAITING_FOR_OFF_CHIP 0 0.0000 0 0.0000 + +FUS_BUSY_WAITING_FOR_OFF_CHIP 0 -nan 0 -nan + +TOTAL_OFF_CHIP_DELAYS_LEFT 0 0 + +WRONG_IO_SCHED 0 0 + +DVFS_CONFIG_SWITCH 0 0 + + + diff --git a/labs/LAB5/runs/x264-sms1/fetch.stat.0.out b/labs/LAB5/runs/x264-sms1/fetch.stat.0.out new file mode 100644 index 00000000..0fa34583 --- /dev/null +++ b/labs/LAB5/runs/x264-sms1/fetch.stat.0.out @@ -0,0 +1,248 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 34067712 Instructions: 100000000 IPC: 2.93533 + +ICACHE_CYCLE 34067712 34067712 + +TCACHE_CYCLE 0 0 + +ICACHE_CYCLE_ONPATH 29907084 87.787% 29907084 87.787% +ICACHE_CYCLE_OFFPATH 4160628 12.213% 4160628 12.213% + 34067712 100.000% 34067712 100.000% + 0.12 0.31 0.12 0.31 + +FETCH_ON_PATH 20009166 100.000% 20009166 100.000% +FETCH_OFF_PATH 0 0.000% 0 0.000% + 20009166 100.000% 20009166 100.000% + 0.00 0.00 0.00 0.00 + +FETCHED_OPS_ON_PATH 0 -nan% 0 -nan% +FETCHED_OPS_OFF_PATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +INST_LOST_WAIT_FOR_MISP_RECOVERY 0 0.000% 0 0.000% +INST_LOST_WAIT_FOR_TIMER 0 0.000% 0 0.000% +INST_LOST_WAIT_FOR_EMPTY_ROB 10722 0.006% 10722 0.006% +INST_LOST_WAIT_FOR_REDIRECT 213030 0.118% 213030 0.118% +INST_LOST_FETCH 110907485 61.361% 110907485 61.361% +INST_LOST_OFF_PATH 0 0.000% 0 0.000% +INST_LOST_FULL_WINDOW 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_OTHER 45077214 24.939% 45077214 24.939% +INST_LOST_ROB_STALL_WAIT_FOR_RECOVERY 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_REDIRECT 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_GAP_FILL 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_L1_MISS 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_MEMORY 790044 0.437% 790044 0.437% +INST_LOST_ROB_STALL_WAIT_FOR_DC_MISS 11296308 6.250% 11296308 6.250% +INST_LOST_ROB_BLOCK_ISSUE_FULL 0 0.000% 0 0.000% +INST_LOST_ROB_BLOCK_ISSUE_GAP_TOO_LARGE 0 0.000% 0 0.000% +INST_LOST_BREAK_DONT 0 0.000% 0 0.000% +INST_LOST_BREAK_ISSUE_WIDTH 0 0.000% 0 0.000% +INST_LOST_BREAK_CF 0 0.000% 0 0.000% +INST_LOST_BREAK_BTB_MISS 9691 0.005% 9691 0.005% +INST_LOST_BREAK_ICACHE_MISS 3424254 1.895% 3424254 1.895% +INST_LOST_BREAK_LINE_END 0 0.000% 0 0.000% +INST_LOST_BREAK_STALL 0 0.000% 0 0.000% +INST_LOST_BREAK_BARRIER 56 0.000% 56 0.000% +INST_LOST_BREAK_OFFPATH 99413 0.055% 99413 0.055% +INST_LOST_BREAK_ALIGNMENT 0 0.000% 0 0.000% +INST_LOST_BREAK_TAKEN 8918789 4.934% 8918789 4.934% +INST_LOST_BREAK_MODEL_BEFORE 0 0.000% 0 0.000% +INST_LOST_BREAK_MODEL_AFTER 0 0.000% 0 0.000% + 180747006 100.000% 180747006 100.000% + 6.74 5.39 6.74 5.39 + +INST_LOST_TOTAL 204406272 204406272 + +FETCH_0_OPS 10135170 33.644% 10135170 33.644% +FETCH_1_OPS 692633 2.299% 692633 2.299% +FETCH_2_OPS 358217 1.189% 358217 1.189% +FETCH_3_OPS 883243 2.932% 883243 2.932% +FETCH_4_OPS 446733 1.483% 446733 1.483% +FETCH_5_OPS 589273 1.956% 589273 1.956% +FETCH_6_OPS 17019232 56.496% 17019232 56.496% +FETCH_7_OPS 0 0.000% 0 0.000% +FETCH_8_OPS 0 0.000% 0 0.000% +FETCH_9_OPS 0 0.000% 0 0.000% +FETCH_10_OPS 0 0.000% 0 0.000% +FETCH_11_OPS 0 0.000% 0 0.000% +FETCH_12_OPS 0 0.000% 0 0.000% +FETCH_13_OPS 0 0.000% 0 0.000% +FETCH_14_OPS 0 0.000% 0 0.000% +FETCH_15_OPS 0 0.000% 0 0.000% +FETCH_16_OPS 0 0.000% 0 0.000% + 30124501 100.000% 30124501 100.000% + 3.68 1.81 3.68 1.81 + +ST_BREAK_DONT 0 0.000% 0 0.000% +ST_BREAK_ISSUE_WIDTH 16712616 83.525% 16712616 83.525% +ST_BREAK_CF 0 0.000% 0 0.000% +ST_BREAK_BTB_MISS 3777 0.019% 3777 0.019% +ST_BREAK_ICACHE_MISS 20054 0.100% 20054 0.100% +ST_BREAK_LINE_END 0 0.000% 0 0.000% +ST_BREAK_STALL 0 0.000% 0 0.000% +ST_BREAK_BARRIER 36 0.000% 36 0.000% +ST_BREAK_OFFPATH 35727 0.179% 35727 0.179% +ST_BREAK_ALIGNMENT 0 0.000% 0 0.000% +ST_BREAK_TAKEN 3236956 16.177% 3236956 16.177% + 20009166 100.000% 20009166 100.000% + 2.47 3.47 2.47 3.47 + +ORACLE_ON_PATH_INST 110907485 100.000% 110907485 100.000% +ORACLE_OFF_PATH_INST 0 0.000% 0 0.000% + 110907485 100.000% 110907485 100.000% + 0.00 0.00 0.00 0.00 + +ORACLE_ON_PATH_INST_MEM 34668560 31.259% 34668560 31.259% +ORACLE_ON_PATH_INST_NOTMEM 76238925 68.741% 76238925 68.741% +ORACLE_OFF_PATH_INST_MEM 0 0.000% 0 0.000% +ORACLE_OFF_PATH_INST_NOTMEM 0 0.000% 0 0.000% + 110907485 100.000% 110907485 100.000% + 0.69 0.26 0.69 0.26 + +ICACHE_CYCLE_NONRA_ONPATH 0 -nan% 0 -nan% +ICACHE_CYCLE_NONRA_OFFPATH 0 -nan% 0 -nan% +ICACHE_CYCLE_RA_ONPATH 0 -nan% 0 -nan% +ICACHE_CYCLE_RA_OFFPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ICACHE_CYCLE_ONPATH_NONRA 0 -nan% 0 -nan% +ICACHE_CYCLE_OFFPATH_NONRA 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ICACHE_CYCLE_ONPATH_RA 0 -nan% 0 -nan% +ICACHE_CYCLE_OFFPATH_RA 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +INACCURATE_OFFPATH_CYCLES 0 0.0000 0 0.0000 + +FETCH_ALL_INST 110907485 110907485 + +EXEC_ALL_INST 110907483 110907483 + +RET_ALL_INST 110907477 110907477 + +EXEC_ON_PATH_INST 110907483 100.000% 110907483 100.000% +EXEC_OFF_PATH_INST 0 0.000% 0 0.000% + 110907483 100.000% 110907483 100.000% + 0.00 0.00 0.00 0.00 + +EXEC_ON_PATH_INST_MEM 34668560 31.259% 34668560 31.259% +EXEC_ON_PATH_INST_NOTMEM 76238923 68.741% 76238923 68.741% +EXEC_OFF_PATH_INST_MEM 0 0.000% 0 0.000% +EXEC_OFF_PATH_INST_NOTMEM 0 0.000% 0 0.000% + 110907483 100.000% 110907483 100.000% + 0.69 0.26 0.69 0.26 + +EXEC_RA_INST 0 -nan% 0 -nan% +EXEC_NONRA_INST 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +EXEC_ON_PATH_INST_RA 0 -nan% 0 -nan% +EXEC_OFF_PATH_INST_RA 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +EXEC_ON_PATH_INST_NONRA 0 -nan% 0 -nan% +EXEC_OFF_PATH_INST_NONRA 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +EXEC_RA_ON_PATH_INST 0 -nan% 0 -nan% +EXEC_RA_OFF_PATH_INST 0 -nan% 0 -nan% +EXEC_NONRA_ON_PATH_INST 0 -nan% 0 -nan% +EXEC_NONRA_OFF_PATH_INST 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ICACHE_THROTTLE_CYCLE 0 0 + +FETCH_ENABLE_THROTTLE_OFF_PATH 0 -nan% 0 -nan% +FETCH_ENABLE_THROTTLE_ON_PATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +FETCH_DISABLE_THROTTLE_OFF_PATH 0 -nan% 0 -nan% +FETCH_DISABLE_THROTTLE_ON_PATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +FETCH_TH_ADJUST__0 0 -nan% 0 -nan% +FETCH_TH_ADJUST__1 0 -nan% 0 -nan% +FETCH_TH_ADJUST__2 0 -nan% 0 -nan% +FETCH_TH_ADJUST__3 0 -nan% 0 -nan% +FETCH_TH_ADJUST__4 0 -nan% 0 -nan% +FETCH_TH_ADJUST__5 0 -nan% 0 -nan% +FETCH_TH_ADJUST__6 0 -nan% 0 -nan% +FETCH_TH_ADJUST__7 0 -nan% 0 -nan% +FETCH_TH_ADJUST__8 0 -nan% 0 -nan% +FETCH_TH_ADJUST__9 0 -nan% 0 -nan% +FETCH_TH_ADJUST__MAX 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +FETCH_TH_ADJUST_UP 0 -nan% 0 -nan% +FETCH_TH_ADJUST_DOWN 0 -nan% 0 -nan% +FETCH_TH_ADJUST_SAME 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +THROTTLE_ADJUST_CACHE_MISS_INFO 0 0 + +LOW_CONF_COUNT_BP_MIS_0 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_1 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_2 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_3 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_4 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_5 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_6 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_7 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_8 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_9 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_10 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_11 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_12 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_13 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_14 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_15 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_16 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_17 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_18 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_19 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_20 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +LOW_CONF_COUNT_RET_0 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_1 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_2 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_3 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_4 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_5 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_6 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_7 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_8 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_9 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_10 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_11 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_12 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_13 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_14 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_15 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_16 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_17 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_18 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_19 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_20 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + + + diff --git a/labs/LAB5/runs/x264-sms1/inst.stat.0.out b/labs/LAB5/runs/x264-sms1/inst.stat.0.out new file mode 100644 index 00000000..39cfefd0 --- /dev/null +++ b/labs/LAB5/runs/x264-sms1/inst.stat.0.out @@ -0,0 +1,103 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 34067712 Instructions: 100000000 IPC: 2.93533 + +ST_OP_INV 0 0.000% 0 0.000% +ST_OP_NOP 982303 0.886% 982303 0.886% +ST_OP_CF 4525831 4.081% 4525831 4.081% +ST_OP_MOV 12357707 11.142% 12357707 11.142% +ST_OP_CMOV 362698 0.327% 362698 0.327% +ST_OP_LDA 9857213 8.888% 9857213 8.888% +ST_OP_IMEM 31105341 28.046% 31105341 28.046% +ST_OP_IADD 23442305 21.137% 23442305 21.137% +ST_OP_IMUL 2551445 2.301% 2551445 2.301% +ST_OP_IDIV 10 0.000% 10 0.000% +ST_OP_ICMP 1727044 1.557% 1727044 1.557% +ST_OP_LOGIC 5278766 4.760% 5278766 4.760% +ST_OP_SHIFT 9922262 8.946% 9922262 8.946% +ST_OP_FMEM 3563219 3.213% 3563219 3.213% +ST_OP_FCVT 1532698 1.382% 1532698 1.382% +ST_OP_FADD 1540288 1.389% 1540288 1.389% +ST_OP_FMUL 621017 0.560% 621017 0.560% +ST_OP_FMA 1525450 1.375% 1525450 1.375% +ST_OP_FDIV 21 0.000% 21 0.000% +ST_OP_FCMP 72 0.000% 72 0.000% +ST_OP_FCMOV 0 0.000% 0 0.000% +ST_OP_GATHER 0 0.000% 0 0.000% +ST_OP_SCATTER 0 0.000% 0 0.000% +ST_OP_PIPELINED_FAST 11554 0.010% 11554 0.010% +ST_OP_PIPELINED_MEDIUM 0 0.000% 0 0.000% +ST_OP_PIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_MEDIUM 241 0.000% 241 0.000% +ST_OP_NOTPIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_VERY_SLOW 0 0.000% 0 0.000% + 110907485 100.000% 110907485 100.000% + 7.13 3.39 7.13 3.39 + +ST_NOT_CF 106381654 95.919% 106381654 95.919% +ST_CF_BR 93194 0.084% 93194 0.084% +ST_CF_CBR 2803670 2.528% 2803670 2.528% +ST_CF_CALL 517672 0.467% 517672 0.467% +ST_CF_IBR 307766 0.277% 307766 0.277% +ST_CF_ICALL 142912 0.129% 142912 0.129% +ST_CF_ICO 0 0.000% 0 0.000% +ST_CF_RET 660581 0.596% 660581 0.596% +ST_CF_SYS 36 0.000% 36 0.000% + 110907485 100.000% 110907485 100.000% + 0.12 0.69 0.12 0.69 + +ST_BAR_NONE 110907449 100.000% 110907449 100.000% +ST_BAR_FETCH 36 0.000% 36 0.000% +ST_BAR_ISSUE 0 0.000% 0 0.000% +ST_BAR_BOTH 0 0.000% 0 0.000% + 110907485 100.000% 110907485 100.000% + 0.00 0.00 0.00 0.00 + +ST_NOT_MEM 76238925 68.741% 76238925 68.741% +ST_MEM_LD 25110142 22.641% 25110142 22.641% +ST_MEM_ST 9558303 8.618% 9558303 8.618% +ST_MEM_PF 115 0.000% 115 0.000% +ST_MEM_WH 0 0.000% 0 0.000% +ST_MEM_EVICT 0 0.000% 0 0.000% + 110907485 100.000% 110907485 100.000% + 0.40 0.55 0.40 0.55 + +ST_NOT_MEM_OFFPATH 0 -nan% 0 -nan% +ST_MEM_LD_OFFPATH 0 -nan% 0 -nan% +ST_MEM_ST_OFFPATH 0 -nan% 0 -nan% +ST_MEM_PF_OFFPATH 0 -nan% 0 -nan% +ST_MEM_WH_OFFPATH 0 -nan% 0 -nan% +ST_MEM_EVIC_OFFPATHT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ST_OP_ONPATH 110907485 110907485 + +ST_OP_OFFPATH 0 0 + +ST_FAKE_OP_OFFPATH 0 -nan% 0 -nan% +ST_NOT_FAKE_OP_OFFPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ST_FAKE_REASON_NOT_FAKE 0 -nan% 0 -nan% +ST_FAKE_REASON_REDIRECT_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_RETURN_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_NONRET_CF_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_NOT_TAKEN_TO_NOT_INSTRUMENTED 0 -nan% 0 -nan% +ST_FAKE_REASON_WRONG_PATH_STORE_TO_NEW_REGION 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ST_INST_ONPATH 100000005 100000005 + +ST_INST_OFFPATH 0 0 + +STATIC_PIN_NOP 0 0 + +DYNAMIC_PIN_REP_GREATER_256 0 0 + + + diff --git a/labs/LAB5/runs/x264-sms1/l2l1pref.stat.0.out b/labs/LAB5/runs/x264-sms1/l2l1pref.stat.0.out new file mode 100644 index 00000000..dafde309 --- /dev/null +++ b/labs/LAB5/runs/x264-sms1/l2l1pref.stat.0.out @@ -0,0 +1,140 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 34067712 Instructions: 100000000 IPC: 2.93533 + +L2WAY_FILL_L1 0 0 + +L2WAY_WAY_HIT 0 -nan% 0 -nan% +L2WAY_WAY_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_PREF_REQ 0 0 + +L2WAY_PREF_HIT_DATA_IN_CACHE 0 -nan% 0 -nan% +L2WAY_PREF_HIT_DATA_REQ 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_TRAIN_HIT 0 -nan% 0 -nan% +L2WAY_TRAIN_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L1_HIT_REQ_TYPE_IFETCH 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DFETCH 0 -nan% 0 -nan% +L1_HIT_REQ_TYPE_DSTORE 0 -nan% 0 -nan% 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0 -nan% +L2HIT_IP_HIT_COUNT__5 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__6 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__7 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__8 0 -nan% 0 -nan% +L2HIT_IP_HIT_COUNT__9 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + + + diff --git a/labs/LAB5/runs/x264-sms1/memory.stat.0.out b/labs/LAB5/runs/x264-sms1/memory.stat.0.out new file mode 100644 index 00000000..50241f5e --- /dev/null +++ b/labs/LAB5/runs/x264-sms1/memory.stat.0.out @@ -0,0 +1,3416 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 34067712 Instructions: 100000000 IPC: 2.93533 + +ICACHE_MISS 20054 0.095% 20054 0.095% +ICACHE_HIT 21179762 99.905% 21179762 99.905% + 21199816 100.000% 21199816 100.000% + 1.00 1.00 1.00 1.00 + +ICACHE_MISS_ONPATH 20054 100.000% 20054 100.000% +ICACHE_MISS_OFFPATH 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+ +CORE_MEM_STALLING_LATENCY_IFETCH 0 -nan% 0 -nan% +CORE_MEM_STALLING_LATENCY_DFETCH 0 -nan% 0 -nan% +CORE_MEM_STALLING_LATENCY_DSTORE 0 -nan% 0 -nan% +CORE_MEM_STALLING_LATENCY_IPRF 0 -nan% 0 -nan% +CORE_MEM_STALLING_LATENCY_DPRF 0 -nan% 0 -nan% +CORE_MEM_STALLING_LATENCY_WB 0 -nan% 0 -nan% +CORE_MEM_STALLING_LATENCY_WB_NODIRTY 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TOTAL_L1_MISS_LATENCY 52668374 344.7899 52668374 344.7899 + +TOTAL_L1_MISS_LATENCY_DEMAND 38293297 486.8762 38293297 486.8762 + +TOTAL_L1_MISS_LATENCY_PREF 14375077 193.9852 14375077 193.9852 + +CORE_L1_MISS_LATENCY 52668374 344.7899 52668374 344.7899 + +CORE_L1_MISS_LATENCY_DEMAND 38293297 486.8762 38293297 486.8762 + +CORE_L1_MISS_LATENCY_PREF 14375077 193.9852 14375077 193.9852 + +CORE_EVICTED_L1_DEMAND 68233 50.030% 68233 50.030% +CORE_EVICTED_L1_PREF_USED 64495 47.289% 64495 47.289% +CORE_EVICTED_L1_PREF_NOT_USED 3656 2.681% 3656 2.681% + 136384 100.000% 136384 100.000% + 0.53 0.41 0.53 0.41 + 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9.664% 6233 9.664% +CORE_PREF_L1_USED_LATENCY600 2888 4.478% 2888 4.478% +CORE_PREF_L1_USED_LATENCY800 2174 3.371% 2174 3.371% +CORE_PREF_L1_USED_LATENCY1000 1212 1.879% 1212 1.879% +CORE_PREF_L1_USED_LATENCY1200 699 1.084% 699 1.084% +CORE_PREF_L1_USED_LATENCY1400 468 0.726% 468 0.726% +CORE_PREF_L1_USED_LATENCY1600 155 0.240% 155 0.240% +CORE_PREF_L1_USED_LATENCY1600MORE 190 0.295% 190 0.295% + 64495 100.000% 64495 100.000% + 0.50 1.13 0.50 1.13 + +CORE_PREF_L1_USED_DISTANCE_1 0 0.000% 0 0.000% +CORE_PREF_L1_USED_DISTANCE_2 2 0.003% 2 0.003% +CORE_PREF_L1_USED_DISTANCE_4 1130 1.752% 1130 1.752% +CORE_PREF_L1_USED_DISTANCE_8 4112 6.376% 4112 6.376% +CORE_PREF_L1_USED_DISTANCE_16 23909 37.071% 23909 37.071% +CORE_PREF_L1_USED_DISTANCE_32 1270 1.969% 1270 1.969% +CORE_PREF_L1_USED_DISTANCE_MORE 34072 52.829% 34072 52.829% + 64495 100.000% 64495 100.000% + 4.98 3.79 4.98 3.79 + +CORE_PREF_L1_DEMAND_LATENCY300 30906 45.295% 30906 45.295% +CORE_PREF_L1_DEMAND_LATENCY400 2186 3.204% 2186 3.204% +CORE_PREF_L1_DEMAND_LATENCY500 4004 5.868% 4004 5.868% +CORE_PREF_L1_DEMAND_LATENCY600 2585 3.788% 2585 3.788% +CORE_PREF_L1_DEMAND_LATENCY700 3208 4.702% 3208 4.702% +CORE_PREF_L1_DEMAND_LATENCY800 6071 8.897% 6071 8.897% +CORE_PREF_L1_DEMAND_LATENCY900 6212 9.104% 6212 9.104% +CORE_PREF_L1_DEMAND_LATENCY1000 3301 4.838% 3301 4.838% +CORE_PREF_L1_DEMAND_LATENCY1000MORE 9760 14.304% 9760 14.304% + 68233 100.000% 68233 100.000% + 2.93 2.68 2.93 2.68 + +CORE_PREF_MLC_NOT_USED_LATENCY200 0 -nan% 0 -nan% +CORE_PREF_MLC_NOT_USED_LATENCY400 0 -nan% 0 -nan% +CORE_PREF_MLC_NOT_USED_LATENCY600 0 -nan% 0 -nan% +CORE_PREF_MLC_NOT_USED_LATENCY800 0 -nan% 0 -nan% +CORE_PREF_MLC_NOT_USED_LATENCY1000 0 -nan% 0 -nan% +CORE_PREF_MLC_NOT_USED_LATENCY1200 0 -nan% 0 -nan% +CORE_PREF_MLC_NOT_USED_LATENCY1400 0 -nan% 0 -nan% +CORE_PREF_MLC_NOT_USED_LATENCY1600 0 -nan% 0 -nan% +CORE_PREF_MLC_NOT_USED_LATENCY1600MORE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + 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8277 30.747% 8277 30.747% +NUM_DCACHE_MISSES_IN_WINDOW_3 9196 34.160% 9196 34.160% +NUM_DCACHE_MISSES_IN_WINDOW_4 2555 9.491% 2555 9.491% +NUM_DCACHE_MISSES_IN_WINDOW_5 386 1.434% 386 1.434% +NUM_DCACHE_MISSES_IN_WINDOW_6 281 1.044% 281 1.044% +NUM_DCACHE_MISSES_IN_WINDOW_7 242 0.899% 242 0.899% +NUM_DCACHE_MISSES_IN_WINDOW_8 619 2.299% 619 2.299% +NUM_DCACHE_MISSES_IN_WINDOW_9 211 0.784% 211 0.784% +NUM_DCACHE_MISSES_IN_WINDOW_10 193 0.717% 193 0.717% +NUM_DCACHE_MISSES_IN_WINDOW_11 109 0.405% 109 0.405% +NUM_DCACHE_MISSES_IN_WINDOW_12 71 0.264% 71 0.264% +NUM_DCACHE_MISSES_IN_WINDOW_13 68 0.253% 68 0.253% +NUM_DCACHE_MISSES_IN_WINDOW_14 85 0.316% 85 0.316% +NUM_DCACHE_MISSES_IN_WINDOW_15 77 0.286% 77 0.286% +NUM_DCACHE_MISSES_IN_WINDOW_16_OR_MORE 1034 3.841% 1034 3.841% + 26920 100.000% 26920 100.000% + 2.48 3.10 2.48 3.10 + +DCACHE_MLP_IN_WINDOW_1_0 6714 24.941% 6714 24.941% +DCACHE_MLP_IN_WINDOW_1_5 1565 5.814% 1565 5.814% +DCACHE_MLP_IN_WINDOW_2_0 8565 31.816% 8565 31.816% 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0.000% +MEM_REQ_DEMANDS_36 0 0.000% 0 0.000% +MEM_REQ_DEMANDS_40 0 0.000% 0 0.000% +MEM_REQ_DEMANDS_44 0 0.000% 0 0.000% +MEM_REQ_DEMANDS_48 0 0.000% 0 0.000% +MEM_REQ_DEMANDS_52 0 0.000% 0 0.000% +MEM_REQ_DEMANDS_56 0 0.000% 0 0.000% +MEM_REQ_DEMANDS_60 0 0.000% 0 0.000% +MEM_REQ_DEMANDS_64 0 0.000% 0 0.000% + 34067712 100.000% 34067712 100.000% + 0.26 1.25 0.26 1.25 + +MEM_REQ_PREFS__0 32659499 95.866% 32659499 95.866% +MEM_REQ_PREFS__4 737168 2.164% 737168 2.164% +MEM_REQ_PREFS__8 300588 0.882% 300588 0.882% +MEM_REQ_PREFS_12 201315 0.591% 201315 0.591% +MEM_REQ_PREFS_16 80590 0.237% 80590 0.237% +MEM_REQ_PREFS_20 38174 0.112% 38174 0.112% +MEM_REQ_PREFS_24 27612 0.081% 27612 0.081% +MEM_REQ_PREFS_28 22766 0.067% 22766 0.067% +MEM_REQ_PREFS_32 0 0.000% 0 0.000% +MEM_REQ_PREFS_36 0 0.000% 0 0.000% +MEM_REQ_PREFS_40 0 0.000% 0 0.000% +MEM_REQ_PREFS_44 0 0.000% 0 0.000% +MEM_REQ_PREFS_48 0 0.000% 0 0.000% +MEM_REQ_PREFS_52 0 0.000% 0 0.000% +MEM_REQ_PREFS_56 0 0.000% 0 0.000% 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-nan% +DRAM_BOTTLENECK_FAW_90 0 -nan% 0 -nan% +DRAM_BOTTLENECK_FAW_100 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +DRAM_ROW_HIT_GEN_AFTER_ROW_OPEN_STALLING 0 0 + +KNOWN_BAD_ADDRESS 0 0.000% 0 0.000% +GOOD_ADDRESS 4961534 100.000% 4961534 100.000% + 4961534 100.000% 4961534 100.000% + 1.00 1.00 1.00 1.00 + + + diff --git a/labs/LAB5/runs/x264-sms1/power.stat.0.out b/labs/LAB5/runs/x264-sms1/power.stat.0.out new file mode 100644 index 00000000..dd47e82e --- /dev/null +++ b/labs/LAB5/runs/x264-sms1/power.stat.0.out @@ -0,0 +1,184 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 34067712 Instructions: 100000000 IPC: 2.93533 + +POWER_STATS_BEGIN 0 0 + +POWER_TIME 10646160000000 10646160000000 + +POWER_CYCLE 34067712 34067712 + +POWER_ITLB_ACCESS 21199816 21199816 + +POWER_DTLB_ACCESS 9558303 9558303 + +POWER_ICACHE_ACCESS 21199816 21199816 + +POWER_ICACHE_MISS 20054 20054 + +POWER_BTB_READ 21199816 21199816 + +POWER_BTB_WRITE 210547 210547 + +POWER_ROB_READ 110907483 110907483 + +POWER_ROB_WRITE 110907483 110907483 + +POWER_RENAME_READ 221814966 221814966 + +POWER_RENAME_WRITE 110907483 110907483 + +POWER_FP_RENAME_READ 0 0 + +POWER_FP_RENAME_WRITE 0 0 + +POWER_FUNCTION_CALL 660583 660583 + +POWER_INST_WINDOW_READ 110907483 110907483 + +POWER_INST_WINDOW_WRITE 110907483 110907483 + +POWER_INT_REGFILE_READ 152748552 152748552 + +POWER_INT_REGFILE_WRITE 131215933 131215933 + +POWER_IALU_ACCESS 108356028 108356028 + +POWER_CDB_IALU_ACCESS 108356028 108356028 + +POWER_MUL_ACCESS 2551455 2551455 + +POWER_CDB_MUL_ACCESS 2551455 2551455 + +POWER_FP_INST_WINDOW_WRITE 0 0 + +POWER_FP_INST_WINDOW_READ 0 0 + +POWER_FP_REGFILE_READ 0 0 + +POWER_FP_REGFILE_WRITE 0 0 + +POWER_FPU_ACCESS 0 0 + +POWER_CDB_FPU_ACCESS 0 0 + +POWER_DCACHE_READ_ACCESS 26436591 26436591 + +POWER_DCACHE_WRITE_ACCESS 10353328 10353328 + +POWER_DCACHE_READ_MISS 2072479 2072479 + +POWER_DCACHE_WRITE_MISS 1001468 1001468 + +POWER_MLC_READ_ACCESS 0 0 + +POWER_MLC_WRITE_ACCESS 0 0 + +POWER_MLC_READ_MISS 0 0 + +POWER_MLC_WRITE_MISS 0 0 + +POWER_LLC_READ_ACCESS 282266 282266 + +POWER_LLC_WRITE_ACCESS 71340 71340 + +POWER_LLC_READ_MISS 152755 152755 + +POWER_LLC_WRITE_MISS 13 13 + +POWER_MEMORY_ACCESS 0 0 + +POWER_MEMORY_READ_ACCESS 0 0 + +POWER_MEMORY_WRITE_ACCESS 0 0 + +POWER_INST_WINDOW_WAKEUP_ACCESS 110907483 110907483 + +POWER_FP_INST_WINDOW_WAKEUP_ACCESS 0 0 + +POWER_L1DIREC_READ_ACCESS 0 0 + +POWER_L1DIREC_WRITE_ACCESS 0 0 + +POWER_L1DIREC_READ_MISS 0 0 + +POWER_L1DIREC_WRITE_MISS 0 0 + +POWER_L2DIREC_READ_ACCESS 0 0 + +POWER_L2DIREC_WRITE_ACCESS 0 0 + +POWER_L2DIREC_READ_MISS 0 0 + +POWER_L2DIREC_WRITE_MISS 0 0 + +POWER_MEMORY_CTRL_ACCESS 216836 216836 + +POWER_MEMORY_CTRL_READ 152755 152755 + +POWER_MEMORY_CTRL_WRITE 64081 64081 + +POWER_OP 110907483 110907483 + +POWER_INT_OP 101130620 101130620 + +POWER_FP_OP 8794560 8794560 + +POWER_LD_OP 25110257 25110257 + +POWER_ST_OP 9558303 9558303 + +POWER_BRANCH_MISPREDICT 210547 210547 + +POWER_COMMITTED_OP 110907483 110907483 + +POWER_COMMITTED_INT_OP 101130620 101130620 + +POWER_COMMITTED_FP_OP 9776863 9776863 + +POWER_BRANCH_OP 4525829 4525829 + +POWER_DRAM_PRECHARGE 24706 24706 + +POWER_DRAM_ACTIVATE 30201 30201 + +POWER_DRAM_READ 152740 152740 + +POWER_DRAM_WRITE 64064 64064 + +POWER_STATS_END 0 0 + +ENERGY 0.000000 0.000000 + +ENERGY_CORE 0.000000 0.000000 + +ENERGY_UNCORE 0.000000 0.000000 + +ENERGY_MEMORY 0.000000 0.000000 + +ENERGY_OTHER 0.000000 0.000000 + +ENERGY_CORE_STATIC 0.000000 0.000000 + +ENERGY_CORE_DYNAMIC 0.000000 0.000000 + +ENERGY_UNCORE_STATIC 0.000000 0.000000 + +ENERGY_UNCORE_DYNAMIC 0.000000 0.000000 + +ENERGY_MEMORY_STATIC 0.000000 0.000000 + +ENERGY_MEMORY_DYNAMIC 0.000000 0.000000 + +ENERGY_OTHER_STATIC 0.000000 0.000000 + +ENERGY_OTHER_DYNAMIC 0.000000 0.000000 + +TIME 0.000000 0.000000 + +ENERGY_STATS_END 0 0 + + + diff --git a/labs/LAB5/runs/x264-sms1/pref.stat.0.out b/labs/LAB5/runs/x264-sms1/pref.stat.0.out new file mode 100644 index 00000000..38b80d7e --- /dev/null +++ b/labs/LAB5/runs/x264-sms1/pref.stat.0.out @@ -0,0 +1,208 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 34067712 Instructions: 100000000 IPC: 2.93533 + +PREF_DL0REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UMLC_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UL1REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_DL0REQ_QUEUE_FULL 0 0 + +PREF_UMLC_REQ_QUEUE_FULL 0 0 + +PREF_UL1REQ_QUEUE_FULL 44003 44003 + +PREF_DC_HIT_NOSEND 0 0 + +PREF_WBQDC_HIT_NOSEND 0 0 + +PREF_MLCQ_STALL 0 0 + +PREF_L1Q_STALL 0 0 + +PREF_UMLC_REQ_SEND_QUEUE_STALL 0 0 + +PREF_UL1REQ_SEND_QUEUE_STALL 1339202 1339202 + +PREF_UMLC_REQ_QUEUE_SENTREQ 0 0 + +PREF_UL1REQ_QUEUE_SENTREQ 111499 111499 + +PREF_NEWREQ_MATCHED 4364 4364 + +PREF_UMLC_REQ_QUEUE_MATCHED_REQ 0 0 + +PREF_UL1REQ_QUEUE_MATCHED_REQ 55493 55493 + +PREF_DL0REQ_QUEUE_MATCHED_REQ 0 0 + +L1_PREF_HIT 73310 73310 + +L1_PREF_UNIQUE_HIT 68384 68384 + +L1_PREF_LATE 1194 1194 + +L1_LATE_PREF_CYCLES 350830 350830 + +L1_LATE_PREF_CYCLES_DIST_0 530 44.389% 530 44.389% +L1_LATE_PREF_CYCLES_DIST_100 146 12.228% 146 12.228% +L1_LATE_PREF_CYCLES_DIST_200 90 7.538% 90 7.538% +L1_LATE_PREF_CYCLES_DIST_300 52 4.355% 52 4.355% +L1_LATE_PREF_CYCLES_DIST_400 60 5.025% 60 5.025% +L1_LATE_PREF_CYCLES_DIST_500 92 7.705% 92 7.705% +L1_LATE_PREF_CYCLES_DIST_600 61 5.109% 61 5.109% +L1_LATE_PREF_CYCLES_DIST_700 45 3.769% 45 3.769% +L1_LATE_PREF_CYCLES_DIST_800 28 2.345% 28 2.345% +L1_LATE_PREF_CYCLES_DIST_900 36 3.015% 36 3.015% +L1_LATE_PREF_CYCLES_DIST_1000 40 3.350% 40 3.350% +L1_LATE_PREF_CYCLES_DIST_1100 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1200 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1300 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1400 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1500 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1600 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1700 3 0.251% 3 0.251% +L1_LATE_PREF_CYCLES_DIST_1800 10 0.838% 10 0.838% +L1_LATE_PREF_CYCLES_DIST_1900 1 0.084% 1 0.084% +L1_LATE_PREF_CYCLES_DIST_2000 0 0.000% 0 0.000% + 1194 100.000% 1194 100.000% + 2.56 2.96 2.56 2.96 + +MLC_PREF_HIT 0 0 + +MLC_PREF_UNIQUE_HIT 0 0 + +MLC_PREF_LATE 0 0 + +PREF_HYBRID_SEL_0 0 -nan% 0 -nan% +PREF_HYBRID_SEL_1 0 -nan% 0 -nan% +PREF_HYBRID_SEL_2 0 -nan% 0 -nan% +PREF_HYBRID_SEL_3 0 -nan% 0 -nan% +PREF_HYBRID_SEL_4 0 -nan% 0 -nan% +PREF_HYBRID_SEL_5 0 -nan% 0 -nan% +PREF_HYBRID_SEL_6 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_DISTANCE_1 0 0.000% 0 0.000% +PREF_DISTANCE_2 0 0.000% 0 0.000% +PREF_DISTANCE_3 1 7.143% 1 7.143% +PREF_DISTANCE_4 1 7.143% 1 7.143% +PREF_DISTANCE_5 12 85.714% 12 85.714% +PREF_DISTANCE_6 0 0.000% 0 0.000% +PREF_DISTANCE_7 0 0.000% 0 0.000% +PREF_DISTANCE_8 0 0.000% 0 0.000% +PREF_DISTANCE_9 0 0.000% 0 0.000% +PREF_DISTANCE_10 0 0.000% 0 0.000% + 14 100.000% 14 100.000% + 3.79 0.58 3.79 0.58 + +PREF_REPL_MRU 0 -nan% 0 -nan% +PREF_REPL_MID 0 -nan% 0 -nan% +PREF_REPL_LOWQTR 0 -nan% 0 -nan% +PREF_REPL_LRU 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_REPL_MOVEDOWN 0 -nan% 0 -nan% +PREF_REPL_MOVEUP 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_COV_1 0 -nan% 0 -nan% +PREF_COV_2 0 -nan% 0 -nan% +PREF_COV_3 0 -nan% 0 -nan% +PREF_COV_4 0 -nan% 0 -nan% +PREF_COV_5 0 -nan% 0 -nan% +PREF_COV_6 0 -nan% 0 -nan% +PREF_COV_7 0 -nan% 0 -nan% +PREF_COV_8 0 -nan% 0 -nan% +PREF_COV_9 0 -nan% 0 -nan% +PREF_COV_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_POL_1 0 0.000% 0 0.000% +PREF_POL_2 0 0.000% 0 0.000% +PREF_POL_3 0 0.000% 0 0.000% +PREF_POL_4 0 0.000% 0 0.000% +PREF_POL_5 0 0.000% 0 0.000% +PREF_POL_6 0 0.000% 0 0.000% +PREF_POL_7 0 0.000% 0 0.000% +PREF_POL_8 0 0.000% 0 0.000% +PREF_POL_9 0 0.000% 0 0.000% +PREF_POL_10 14 100.000% 14 100.000% + 14 100.000% 14 100.000% + 9.00 9.34 9.00 9.34 + +PREF_ACC_1 12 85.714% 12 85.714% +PREF_ACC_2 2 14.286% 2 14.286% +PREF_ACC_3 0 0.000% 0 0.000% +PREF_ACC_4 0 0.000% 0 0.000% +PREF_ACC_5 0 0.000% 0 0.000% +PREF_ACC_6 0 0.000% 0 0.000% +PREF_ACC_7 0 0.000% 0 0.000% +PREF_ACC_8 0 0.000% 0 0.000% +PREF_ACC_9 0 0.000% 0 0.000% +PREF_ACC_10 0 0.000% 0 0.000% + 14 100.000% 14 100.000% + 0.14 0.34 0.14 0.34 + +PREF_TIMELY_1 0 0.000% 0 0.000% +PREF_TIMELY_2 0 0.000% 0 0.000% +PREF_TIMELY_3 0 0.000% 0 0.000% +PREF_TIMELY_4 0 0.000% 0 0.000% +PREF_TIMELY_5 0 0.000% 0 0.000% +PREF_TIMELY_6 0 0.000% 0 0.000% +PREF_TIMELY_7 0 0.000% 0 0.000% +PREF_TIMELY_8 0 0.000% 0 0.000% +PREF_TIMELY_9 1 7.143% 1 7.143% +PREF_TIMELY_10 13 92.857% 13 92.857% + 14 100.000% 14 100.000% + 8.93 8.93 8.93 8.93 + +PREF_UNUSED_EVICT 3656 3656 + +PREF_REGION_SENT 0 0 + +PREF_REGION_USEFUL 0 0 + +PREF_REGION_EVICT 0 0 + +PREF_PFPOL 0 0 + +PREF_PHASE_NEWPHASE_DET 0 0 + +PREF_PHASE_NEWPHASE_NOTVALID 0 0 + +PREF_PHASE_SENTPREF 0 0 + +PREF_PHASE_OVERWRITE_PAGE 0 0 + +PREF_UPDATE_COUNT 14 14 + +PREF_ACC1_HT_HP 0 0.000% 0 0.000% +PREF_ACC1_HT_LP 4 28.571% 4 28.571% +PREF_ACC1_LT_HP 0 0.000% 0 0.000% +PREF_ACC1_LT_LP 10 71.429% 10 71.429% +PREF_ACC2_HT_HP 0 0.000% 0 0.000% +PREF_ACC2_HT_LP 0 0.000% 0 0.000% +PREF_ACC2_LT_HP 0 0.000% 0 0.000% +PREF_ACC2_LT_LP 0 0.000% 0 0.000% +PREF_ACC3_HT_HP 0 0.000% 0 0.000% +PREF_ACC3_HT_LP 0 0.000% 0 0.000% +PREF_ACC3_LT_HP 0 0.000% 0 0.000% +PREF_ACC3_LT_LP 0 0.000% 0 0.000% +PREF_ACC4_HT_HP 0 0.000% 0 0.000% +PREF_ACC4_HT_LP 0 0.000% 0 0.000% +PREF_ACC4_LT_HP 0 0.000% 0 0.000% +PREF_ACC4_LT_LP 0 0.000% 0 0.000% + 14 100.000% 14 100.000% + 2.43 0.94 2.43 0.94 + + + diff --git a/labs/LAB5/runs/x264-sms1/ramulator.stat.out b/labs/LAB5/runs/x264-sms1/ramulator.stat.out new file mode 100644 index 00000000..f0bc675f --- /dev/null +++ b/labs/LAB5/runs/x264-sms1/ramulator.stat.out @@ -0,0 +1,150 @@ + ramulator.active_cycles_0 2239770 # Total active cycles for level _0 + ramulator.busy_cycles_0 2239770 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0 + ramulator.serving_requests_0 4751129 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.average_serving_requests_0 0.371897 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.active_cycles_0_0 2239770 # Total active cycles for level _0_0 + ramulator.busy_cycles_0_0 2779050 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0 + ramulator.serving_requests_0_0 4751129 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.average_serving_requests_0_0 0.371897 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.active_cycles_0_0_0 834557 # Total active cycles for level _0_0_0 + ramulator.busy_cycles_0_0_0 834557 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0 + ramulator.serving_requests_0_0_0 1260316 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 +ramulator.average_serving_requests_0_0_0 0.098652 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 + ramulator.active_cycles_0_0_0_0 217739 # Total active cycles for level _0_0_0_0 + ramulator.busy_cycles_0_0_0_0 217739 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_0 + ramulator.serving_requests_0_0_0_0 290308 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 +ramulator.average_serving_requests_0_0_0_0 0.022724 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 + ramulator.active_cycles_0_0_0_1 246387 # Total active cycles for level _0_0_0_1 + ramulator.busy_cycles_0_0_0_1 246387 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_1 + ramulator.serving_requests_0_0_0_1 331477 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 +ramulator.average_serving_requests_0_0_0_1 0.025947 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 + ramulator.active_cycles_0_0_0_2 213282 # Total active cycles for level _0_0_0_2 + ramulator.busy_cycles_0_0_0_2 213282 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_2 + ramulator.serving_requests_0_0_0_2 285021 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 +ramulator.average_serving_requests_0_0_0_2 0.022310 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 + ramulator.active_cycles_0_0_0_3 261817 # Total active cycles for level _0_0_0_3 + ramulator.busy_cycles_0_0_0_3 261817 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_3 + ramulator.serving_requests_0_0_0_3 353510 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 +ramulator.average_serving_requests_0_0_0_3 0.027671 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 + ramulator.active_cycles_0_0_1 827975 # Total active cycles for level _0_0_1 + ramulator.busy_cycles_0_0_1 827975 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1 + ramulator.serving_requests_0_0_1 1202807 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 +ramulator.average_serving_requests_0_0_1 0.094150 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 + ramulator.active_cycles_0_0_1_0 234833 # Total active cycles for level _0_0_1_0 + ramulator.busy_cycles_0_0_1_0 234833 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_0 + ramulator.serving_requests_0_0_1_0 303689 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 +ramulator.average_serving_requests_0_0_1_0 0.023771 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 + ramulator.active_cycles_0_0_1_1 213261 # Total active cycles for level _0_0_1_1 + ramulator.busy_cycles_0_0_1_1 213261 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_1 + ramulator.serving_requests_0_0_1_1 277229 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 +ramulator.average_serving_requests_0_0_1_1 0.021700 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 + ramulator.active_cycles_0_0_1_2 280474 # Total active cycles for level _0_0_1_2 + ramulator.busy_cycles_0_0_1_2 280474 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_2 + ramulator.serving_requests_0_0_1_2 361018 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 +ramulator.average_serving_requests_0_0_1_2 0.028259 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 + ramulator.active_cycles_0_0_1_3 202101 # Total active cycles for level _0_0_1_3 + ramulator.busy_cycles_0_0_1_3 202101 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_3 + ramulator.serving_requests_0_0_1_3 260871 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 +ramulator.average_serving_requests_0_0_1_3 0.020420 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 + ramulator.active_cycles_0_0_2 816742 # Total active cycles for level _0_0_2 + ramulator.busy_cycles_0_0_2 816742 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2 + ramulator.serving_requests_0_0_2 1198426 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 +ramulator.average_serving_requests_0_0_2 0.093807 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 + ramulator.active_cycles_0_0_2_0 254196 # Total active cycles for level _0_0_2_0 + ramulator.busy_cycles_0_0_2_0 254196 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_0 + ramulator.serving_requests_0_0_2_0 325605 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 +ramulator.average_serving_requests_0_0_2_0 0.025487 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 + ramulator.active_cycles_0_0_2_1 234529 # Total active cycles for level _0_0_2_1 + ramulator.busy_cycles_0_0_2_1 234529 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_1 + ramulator.serving_requests_0_0_2_1 312112 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 +ramulator.average_serving_requests_0_0_2_1 0.024431 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 + ramulator.active_cycles_0_0_2_2 238717 # Total active cycles for level _0_0_2_2 + ramulator.busy_cycles_0_0_2_2 238717 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_2 + ramulator.serving_requests_0_0_2_2 323365 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 +ramulator.average_serving_requests_0_0_2_2 0.025312 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 + ramulator.active_cycles_0_0_2_3 185700 # Total active cycles for level _0_0_2_3 + ramulator.busy_cycles_0_0_2_3 185700 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_3 + ramulator.serving_requests_0_0_2_3 237344 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 +ramulator.average_serving_requests_0_0_2_3 0.018578 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 + ramulator.active_cycles_0_0_3 754798 # Total active cycles for level _0_0_3 + ramulator.busy_cycles_0_0_3 754798 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3 + ramulator.serving_requests_0_0_3 1089580 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 +ramulator.average_serving_requests_0_0_3 0.085287 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 + ramulator.active_cycles_0_0_3_0 223336 # Total active cycles for level _0_0_3_0 + ramulator.busy_cycles_0_0_3_0 223336 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_0 + ramulator.serving_requests_0_0_3_0 288258 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 +ramulator.average_serving_requests_0_0_3_0 0.022564 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 + ramulator.active_cycles_0_0_3_1 244660 # Total active cycles for level _0_0_3_1 + ramulator.busy_cycles_0_0_3_1 244660 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_1 + ramulator.serving_requests_0_0_3_1 312520 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 +ramulator.average_serving_requests_0_0_3_1 0.024463 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 + ramulator.active_cycles_0_0_3_2 205117 # Total active cycles for level _0_0_3_2 + ramulator.busy_cycles_0_0_3_2 205117 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_2 + ramulator.serving_requests_0_0_3_2 262355 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 +ramulator.average_serving_requests_0_0_3_2 0.020536 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 + ramulator.active_cycles_0_0_3_3 165878 # Total active cycles for level _0_0_3_3 + ramulator.busy_cycles_0_0_3_3 165878 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_3 + ramulator.serving_requests_0_0_3_3 226447 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 +ramulator.average_serving_requests_0_0_3_3 0.017725 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 + ramulator.read_transaction_bytes_0 9775360 # The total byte of read transaction per channel + ramulator.write_transaction_bytes_0 4100096 # The total byte of write transaction per channel + ramulator.row_hits_channel_0_core 186680 # Number of row hits per channel per core + ramulator.row_misses_channel_0_core 7825 # Number of row misses per channel per core + ramulator.row_conflicts_channel_0_core 22299 # Number of row conflicts per channel per core + ramulator.read_row_hits_channel_0_core 133969 # Number of row hits for read requests per channel per core + [0] 133969.0 # +ramulator.read_row_misses_channel_0_core 5279 # Number of row misses for read requests per channel per core + [0] 5279.0 # +ramulator.read_row_conflicts_channel_0_core 13492 # Number of row conflicts for read requests per channel per core + [0] 13492.0 # + ramulator.write_row_hits_channel_0_core 52711 # Number of row hits for write requests per channel per core + [0] 52711.0 # +ramulator.write_row_misses_channel_0_core 2546 # Number of row misses for write requests per channel per core + [0] 2546.0 # +ramulator.write_row_conflicts_channel_0_core 8807 # Number of row conflicts for write requests per channel per core + [0] 8807.0 # + ramulator.useless_activates_0_core 80 # Number of useless activations. E.g, ACT -> PRE w/o RD or WR + ramulator.read_latency_avg_0 129.655887 # The average memory latency cycles (in memory time domain) per request for all read requests in this channel + ramulator.read_latency_sum_0 19805585 # The memory latency cycles (in memory time domain) sum for all read requests in this channel + ramulator.req_queue_length_avg_0 13.286134 # Average of read and write queue length per memory cycle per channel. + ramulator.req_queue_length_sum_0 169735634 # Sum of read and write queue length per memory cycle per channel. + ramulator.read_req_queue_length_avg_0 1.525463 # Read queue length average per memory cycle per channel. + ramulator.read_req_queue_length_sum_0 19488390 # Read queue length sum per memory cycle per channel. + ramulator.write_req_queue_length_avg_0 11.760671 # Write queue length average per memory cycle per channel. + ramulator.write_req_queue_length_sum_0 150247244 # Write queue length sum per memory cycle per channel. + ramulator.record_read_hits 0.0 # record read hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_misses 0.0 # record_read_miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_conflicts 0.0 # record read conflict count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_hits 0.0 # record write hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_misses 0.0 # record write miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_conflicts 0.0 # record write conflict for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.dram_capacity 8589934592 # Number of bytes in simulated DRAM + ramulator.dram_cycles 12775397 # Number of DRAM cycles simulated + ramulator.incoming_requests 216836 # Number of incoming requests to DRAM + ramulator.read_requests 152755 # Number of incoming read requests to DRAM per core + [0] 152755.0 # + ramulator.write_requests 64081 # Number of incoming write requests to DRAM per core + [0] 64081.0 # + ramulator.ramulator_active_cycles 2239770 # The total number of cycles that the DRAM part is active (serving R/W) + ramulator.incoming_requests_per_channel 216836.0 # Number of incoming requests to each DRAM channel + [0] 216836.0 # +ramulator.incoming_read_reqs_per_channel 152755.0 # Number of incoming read requests to each DRAM channel + [0] 152755.0 # + ramulator.physical_page_replacement 0 # The number of times that physical page replacement happens. + ramulator.maximum_bandwidth 19200000000 # The theoretical maximum bandwidth (Bps) + ramulator.in_queue_req_num_sum 169735634 # Sum of read/write queue length + ramulator.in_queue_read_req_num_sum 19488390 # Sum of read queue length + ramulator.in_queue_write_req_num_sum 150247244 # Sum of write queue length + ramulator.in_queue_req_num_avg 13.286134 # Average of read/write queue length per memory cycle + ramulator.in_queue_read_req_num_avg 1.525463 # Average of read queue length per memory cycle + ramulator.in_queue_write_req_num_avg 11.760671 # Average of write queue length per memory cycle + ramulator.record_read_requests 0.0 # record read requests for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_requests 0.0 # record write requests for this core when it reaches request limit or to the end + [0] 0.0 # diff --git a/labs/LAB5/runs/x264-sms1/run.err b/labs/LAB5/runs/x264-sms1/run.err new file mode 100644 index 00000000..e69de29b diff --git a/labs/LAB5/runs/x264-sms1/run.out b/labs/LAB5/runs/x264-sms1/run.out new file mode 100644 index 00000000..28a3d318 --- /dev/null +++ b/labs/LAB5/runs/x264-sms1/run.out @@ -0,0 +1,107 @@ +Scarab gitrev: 7ab9e17 +Scarab started at Sun Jun 11 08:08:38 2023 + +Initialized Ramulator. +** Heartbeat: 1% -- { 1000000 } -- 0.00 KIPS (500.00 KIPS) +** Heartbeat: 2% -- { 2000003 } -- 500.00 KIPS (500.00 KIPS) +** Heartbeat: 3% -- { 3000006 } -- 1000.00 KIPS (600.00 KIPS) +** Heartbeat: 4% -- { 4000009 } -- 500.00 KIPS (571.43 KIPS) +** Heartbeat: 5% -- { 5000010 } -- 500.00 KIPS (555.56 KIPS) +** Heartbeat: 6% -- { 6000012 } -- 1000.00 KIPS (600.00 KIPS) +** Heartbeat: 7% -- { 7000012 } -- 500.00 KIPS (583.33 KIPS) +** Heartbeat: 8% -- { 8000014 } -- 500.00 KIPS (571.43 KIPS) +** Heartbeat: 9% -- { 9000016 } -- 500.00 KIPS (562.50 KIPS) +** Heartbeat: 10% -- { 10000019 } -- 1000.00 KIPS (588.24 KIPS) +** Heartbeat: 11% -- { 11000020 } -- 500.00 KIPS (578.95 KIPS) +** Heartbeat: 12% -- { 12000020 } -- 500.00 KIPS (571.43 KIPS) +** Heartbeat: 13% -- { 13000021 } -- 1000.00 KIPS (590.91 KIPS) +** Heartbeat: 14% -- { 14000022 } -- 500.00 KIPS (583.33 KIPS) +** Heartbeat: 15% -- { 15000023 } -- 500.00 KIPS (576.92 KIPS) +** Heartbeat: 16% -- { 16000027 } -- 1000.00 KIPS (592.59 KIPS) +** Heartbeat: 17% -- { 17000028 } -- 500.00 KIPS (586.21 KIPS) +** Heartbeat: 18% -- { 18000032 } -- 333.33 KIPS (562.50 KIPS) +** Heartbeat: 19% -- { 19000034 } -- 333.33 KIPS (542.86 KIPS) +** Heartbeat: 20% -- { 20000034 } -- 500.00 KIPS (540.54 KIPS) +** Heartbeat: 21% -- { 21000036 } -- 500.00 KIPS (538.46 KIPS) +** Heartbeat: 22% -- { 22000037 } -- 500.00 KIPS (536.59 KIPS) +** Heartbeat: 23% -- { 23000042 } -- 1000.00 KIPS (547.62 KIPS) +** Heartbeat: 24% -- { 24000046 } -- 500.00 KIPS (545.46 KIPS) +** Heartbeat: 25% -- { 25000049 } -- 1000.00 KIPS (555.56 KIPS) +** Heartbeat: 26% -- { 26000051 } -- 1000.00 KIPS (565.22 KIPS) +** Heartbeat: 27% -- { 27000053 } -- 500.00 KIPS (562.50 KIPS) +** Heartbeat: 28% -- { 28000057 } -- 1000.00 KIPS (571.43 KIPS) +** Heartbeat: 29% -- { 29000060 } -- 500.00 KIPS (568.63 KIPS) +** Heartbeat: 30% -- { 30000062 } -- 1000.00 KIPS (576.92 KIPS) +** Heartbeat: 31% -- { 31000065 } -- 1000.00 KIPS (584.91 KIPS) +** Heartbeat: 32% -- { 32000066 } -- 500.00 KIPS (581.82 KIPS) +** Heartbeat: 33% -- { 33000070 } -- 1000.00 KIPS (589.29 KIPS) +** Heartbeat: 34% -- { 34000073 } -- 500.00 KIPS (586.21 KIPS) +** Heartbeat: 35% -- { 35000074 } -- 500.00 KIPS (583.33 KIPS) +** Heartbeat: 36% -- { 36000074 } -- 500.00 KIPS (580.65 KIPS) +** Heartbeat: 37% -- { 37000074 } -- 1000.00 KIPS (587.30 KIPS) +** Heartbeat: 38% -- { 38000074 } -- 500.00 KIPS (584.62 KIPS) +** Heartbeat: 39% -- { 39000079 } -- 500.00 KIPS (582.09 KIPS) +** Heartbeat: 40% -- { 40000081 } -- 500.00 KIPS (579.71 KIPS) +** Heartbeat: 41% -- { 41000086 } -- 500.00 KIPS (577.47 KIPS) +** Heartbeat: 42% -- { 42000088 } -- 1000.00 KIPS (583.33 KIPS) +** Heartbeat: 43% -- { 43000088 } -- 500.00 KIPS (581.08 KIPS) +** Heartbeat: 44% -- { 44000093 } -- 500.00 KIPS (578.95 KIPS) +** Heartbeat: 45% -- { 45000094 } -- 1000.00 KIPS (584.42 KIPS) +** Heartbeat: 46% -- { 46000094 } -- 500.00 KIPS (582.28 KIPS) +** Heartbeat: 47% -- { 47000095 } -- 1000.00 KIPS (587.50 KIPS) +** Heartbeat: 48% -- { 48000097 } -- 500.00 KIPS (585.37 KIPS) +** Heartbeat: 49% -- { 49000099 } -- 1000.00 KIPS (590.36 KIPS) +** Heartbeat: 50% -- { 50000099 } -- 500.00 KIPS (588.24 KIPS) +** Heartbeat: 51% -- { 51000100 } -- 500.00 KIPS (586.21 KIPS) +** Heartbeat: 52% -- { 52000102 } -- 1000.00 KIPS (590.91 KIPS) +** Heartbeat: 53% -- { 53000103 } -- 500.00 KIPS (588.89 KIPS) +** Heartbeat: 54% -- { 54000107 } -- 1000.00 KIPS (593.41 KIPS) +** Heartbeat: 55% -- { 55000111 } -- 500.00 KIPS (591.40 KIPS) +** Heartbeat: 56% -- { 56000114 } -- 500.00 KIPS (589.47 KIPS) +** Heartbeat: 57% -- { 57000116 } -- 1000.00 KIPS (593.75 KIPS) +** Heartbeat: 58% -- { 58000118 } -- 500.00 KIPS (591.84 KIPS) +** Heartbeat: 59% -- { 59000119 } -- 1000.00 KIPS (595.96 KIPS) +** Heartbeat: 60% -- { 60000124 } -- 500.00 KIPS (594.06 KIPS) +** Heartbeat: 61% -- { 61000128 } -- 1000.00 KIPS (598.04 KIPS) +** Heartbeat: 62% -- { 62000129 } -- 500.00 KIPS (596.16 KIPS) +** Heartbeat: 63% -- { 63000129 } -- 500.00 KIPS (594.34 KIPS) +** Heartbeat: 64% -- { 64000132 } -- 1000.00 KIPS (598.13 KIPS) +** Heartbeat: 65% -- { 65000133 } -- 500.00 KIPS (596.33 KIPS) +** Heartbeat: 66% -- { 66000138 } -- 1000.00 KIPS (600.00 KIPS) +** Heartbeat: 67% -- { 67000139 } -- 500.00 KIPS (598.22 KIPS) +** Heartbeat: 68% -- { 68000142 } -- 1000.00 KIPS (601.77 KIPS) +** Heartbeat: 69% -- { 69000144 } -- 500.00 KIPS (600.00 KIPS) +** Heartbeat: 70% -- { 70000145 } -- 500.00 KIPS (598.29 KIPS) +** Heartbeat: 71% -- { 71000148 } -- 1000.00 KIPS (601.70 KIPS) +** Heartbeat: 72% -- { 72000153 } -- 500.00 KIPS (600.00 KIPS) +** Heartbeat: 73% -- { 73000157 } -- 1000.00 KIPS (603.31 KIPS) +** Heartbeat: 74% -- { 74000159 } -- 500.00 KIPS (601.63 KIPS) +** Heartbeat: 75% -- { 75000160 } -- 500.00 KIPS (600.00 KIPS) +** Heartbeat: 76% -- { 76000160 } -- 1000.00 KIPS (603.18 KIPS) +** Heartbeat: 77% -- { 77000161 } -- 500.00 KIPS (601.56 KIPS) +** Heartbeat: 78% -- { 78000163 } -- 1000.00 KIPS (604.65 KIPS) +** Heartbeat: 79% -- { 79000164 } -- 500.00 KIPS (603.05 KIPS) +** Heartbeat: 80% -- { 80000165 } -- 1000.00 KIPS (606.06 KIPS) +** Heartbeat: 81% -- { 81000166 } -- 500.00 KIPS (604.48 KIPS) +** Heartbeat: 82% -- { 82000169 } -- 500.00 KIPS (602.94 KIPS) +** Heartbeat: 83% -- { 83000170 } -- 1000.00 KIPS (605.84 KIPS) +** Heartbeat: 84% -- { 84000170 } -- 500.00 KIPS (604.32 KIPS) +** Heartbeat: 85% -- { 85000172 } -- 500.00 KIPS (602.84 KIPS) +** Heartbeat: 86% -- { 86000177 } -- 1000.00 KIPS (605.64 KIPS) +** Heartbeat: 87% -- { 87000178 } -- 500.00 KIPS (604.17 KIPS) +** Heartbeat: 88% -- { 88000179 } -- 500.00 KIPS (602.74 KIPS) +** Heartbeat: 89% -- { 89000179 } -- 1000.00 KIPS (605.44 KIPS) +** Heartbeat: 90% -- { 90000179 } -- 500.00 KIPS (604.03 KIPS) +** Heartbeat: 91% -- { 91000179 } -- 500.00 KIPS (602.65 KIPS) +** Heartbeat: 92% -- { 92000184 } -- 1000.00 KIPS (605.26 KIPS) +** Heartbeat: 93% -- { 93000184 } -- 500.00 KIPS (603.90 KIPS) +** Heartbeat: 94% -- { 94000184 } -- 500.00 KIPS (602.57 KIPS) +** Heartbeat: 95% -- { 95000187 } -- 500.00 KIPS (601.27 KIPS) +** Heartbeat: 96% -- { 96000190 } -- 1000.00 KIPS (603.77 KIPS) +** Heartbeat: 97% -- { 97000193 } -- 500.00 KIPS (602.49 KIPS) +** Heartbeat: 98% -- { 98000198 } -- 1000.00 KIPS (604.94 KIPS) +** Heartbeat: 99% -- { 99000201 } -- 500.00 KIPS (603.66 KIPS) +** Core 0 Finished: insts:100000000 cycles:34067712 time:10646160000000 -- 2.94 IPC (2.94 IPC) -- N/A KIPS (602.41 KIPS) +done +Scarab finished at Sun Jun 11 08:11:24 2023 + diff --git a/labs/LAB5/runs/x264-sms1/stream.stat.0.out b/labs/LAB5/runs/x264-sms1/stream.stat.0.out new file mode 100644 index 00000000..5df2a2ca --- /dev/null +++ b/labs/LAB5/runs/x264-sms1/stream.stat.0.out @@ -0,0 +1,188 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 34067712 Instructions: 100000000 IPC: 2.93533 + +DCACHE_PREF_HIT 0 0 + +IFETCH_WB_FIRST_SCHEDULE 0 -nan% 0 -nan% +PREFETCH_LAST_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_PREF_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_LOW_OP_SCHEDULE 0 -nan% 0 -nan% +DEMAND_LAST_SCHEDULE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +SEND_MISS_REQ_QUEUE 152755 152755 + +L1_DATA_EVICT 136384 136384 + +STREAM_BUFFER_REQ 0 0 + +PREF_SEND_TO_MEM_REQ 0 -nan% 0 -nan% +PREF_SEND_TO_MEM_REQ_FAIL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +HIT_TRAIN_STREAM 105291 76.295% 105291 76.295% +MISS_TRAIN_STREAM 32715 23.705% 32715 23.705% + 138006 100.000% 138006 100.000% + 0.24 0.39 0.24 0.39 + +STREAM_TRAIN_CREATE 25609 25609 + +MEM_REQ_MISS_HWP_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_SW_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_IFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DSTORE_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DPRF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_WB_Q 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_BY_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_WB 0 -nan% 0 -nan% +PREF_HIT_BY_PREF 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_WB 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_L1_FILL 0 -nan% 0 -nan% +DEMAND_L1_FILL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TOUCH_L1_REPLACE 0 0.000% 0 0.000% +NO_TOUCH_L1_REPLACE 136384 100.000% 136384 100.000% + 136384 100.000% 136384 100.000% + 1.00 1.00 1.00 1.00 + +PREF_REQ_QUE_FULL 0 0 + +STREAM_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +L2HIT_STREAM_PREF_REQ_QUE_FULL 0 0 + +L2HIT_HIT_TRAIN_STREAM 0 -nan% 0 -nan% +L2HIT_MISS_TRAIN_STREAM 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_TRAIN_CREATE 0 0 + +L2HIT_STREAM_BUFFER_REQ 0 0 + +L2HIT_STREAM_PREF_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_STREAM_PREF_DCACHE_INSERT 0 -nan% 0 -nan% +L2HIT_STREAM_L2_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_DCACHE_PORT_FULL 0 0 + +L2HIT_STREAM_PREF_L1_PORT_FULL 0 0 + +L2HIT_TRAIN_HIT_DEMAND 0 -nan% 0 -nan% +L2HIT_TRAIN_MISS_REQ 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_TRAIN_FILTER_MISS 0 -nan% 0 -nan% +L2HIT_TRAIN_FILTER_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_PREF_REQ_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_PREF_REQ_DCACHE_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_L2SEND_Q_FULL 0 -nan% 0 -nan% +L2HIT_L2SEND_Q_ENTER 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_MEM_REQ 0 0 + +REMOVE_REDUNDANT_STREAM_STAT 0 0 + +REPLACE_OLD_STREAM 25593 25593 + +REQ_SEND_QUEUE_STALL 0 0 + +STREAM_ENTER_RA 0 0 + +CORE_STREAM_LENGTH_0 181 10.735% 181 10.735% +CORE_STREAM_LENGTH_10 489 29.004% 489 29.004% +CORE_STREAM_LENGTH_20 277 16.429% 277 16.429% +CORE_STREAM_LENGTH_30 218 12.930% 218 12.930% +CORE_STREAM_LENGTH_40 109 6.465% 109 6.465% +CORE_STREAM_LENGTH_50 99 5.872% 99 5.872% +CORE_STREAM_LENGTH_60 32 1.898% 32 1.898% +CORE_STREAM_LENGTH_70 33 1.957% 33 1.957% +CORE_STREAM_LENGTH_80 12 0.712% 12 0.712% +CORE_STREAM_LENGTH_90 23 1.364% 23 1.364% +CORE_STREAM_LENGTH_100_P 213 12.633% 213 12.633% + 1686 100.000% 1686 100.000% + 3.25 3.17 3.25 3.17 + +CORE_CUM_STREAM_LENGTH_0 1286 0.573% 1286 0.573% +CORE_CUM_STREAM_LENGTH_10 7557 3.367% 7557 3.367% +CORE_CUM_STREAM_LENGTH_20 6515 2.902% 6515 2.902% +CORE_CUM_STREAM_LENGTH_30 6992 3.115% 6992 3.115% +CORE_CUM_STREAM_LENGTH_40 4850 2.161% 4850 2.161% +CORE_CUM_STREAM_LENGTH_50 5215 2.323% 5215 2.323% +CORE_CUM_STREAM_LENGTH_60 2081 0.927% 2081 0.927% +CORE_CUM_STREAM_LENGTH_70 2385 1.063% 2385 1.063% +CORE_CUM_STREAM_LENGTH_80 1004 0.447% 1004 0.447% +CORE_CUM_STREAM_LENGTH_90 2139 0.953% 2139 0.953% +CORE_CUM_STREAM_LENGTH_100_P 184445 82.169% 184445 82.169% + 224469 100.000% 224469 100.000% + 8.86 8.43 8.86 8.43 + +CORE_STREAM_TRAIN_HITS_0 965 57.236% 965 57.236% +CORE_STREAM_TRAIN_HITS_10 428 25.386% 428 25.386% +CORE_STREAM_TRAIN_HITS_20 75 4.448% 75 4.448% +CORE_STREAM_TRAIN_HITS_30 21 1.246% 21 1.246% +CORE_STREAM_TRAIN_HITS_40 12 0.712% 12 0.712% +CORE_STREAM_TRAIN_HITS_50 13 0.771% 13 0.771% +CORE_STREAM_TRAIN_HITS_60 10 0.593% 10 0.593% +CORE_STREAM_TRAIN_HITS_70 14 0.830% 14 0.830% +CORE_STREAM_TRAIN_HITS_80 10 0.593% 10 0.593% +CORE_STREAM_TRAIN_HITS_90 7 0.415% 7 0.415% +CORE_STREAM_TRAIN_HITS_100_P 131 7.770% 131 7.770% + 1686 100.000% 1686 100.000% + 1.40 2.65 1.40 2.65 + +CORE_CUM_STREAM_TRAIN_HITS_0 6008 5.363% 6008 5.363% +CORE_CUM_STREAM_TRAIN_HITS_10 5519 4.926% 5519 4.926% +CORE_CUM_STREAM_TRAIN_HITS_20 1743 1.556% 1743 1.556% +CORE_CUM_STREAM_TRAIN_HITS_30 681 0.608% 681 0.608% +CORE_CUM_STREAM_TRAIN_HITS_40 522 0.466% 522 0.466% +CORE_CUM_STREAM_TRAIN_HITS_50 729 0.651% 729 0.651% +CORE_CUM_STREAM_TRAIN_HITS_60 631 0.563% 631 0.563% +CORE_CUM_STREAM_TRAIN_HITS_70 1084 0.968% 1084 0.968% +CORE_CUM_STREAM_TRAIN_HITS_80 858 0.766% 858 0.766% +CORE_CUM_STREAM_TRAIN_HITS_90 659 0.588% 659 0.588% +CORE_CUM_STREAM_TRAIN_HITS_100_P 93601 83.546% 93601 83.546% + 112035 100.000% 112035 100.000% + 8.72 8.31 8.72 8.31 + +CORE_STREAM_TRAIN_CREATE 25609 25609 + + + diff --git a/labs/LAB5/runs/xalancbmk_s_base-sms0/PARAMS.in b/labs/LAB5/runs/xalancbmk_s_base-sms0/PARAMS.in new file mode 100644 index 00000000..2593c2b8 --- /dev/null +++ b/labs/LAB5/runs/xalancbmk_s_base-sms0/PARAMS.in @@ -0,0 +1,226 @@ +# File : PARAMS.kaby_lake +# Date : 03/06/19 +# Description : Kaby Lake Configuration +# +# Based on documentation found here: +# https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake + +## Simulation Parameters +--mode full +--model cmp +--sim_limit none + +## Core Parameters + +# Femptoseconds, 3.2GHz, used for energy estimates. +--chip_cycle_time 312500 + + +### Fetch Stage +--fetch_off_path_ops 1 +--fetch_across_cache_lines 1 + +# Will break the packet upon a taken branch. +--fetch_break_on_taken 1 + +# Number of bubble cycles to wait after taken branch. +--fetch_taken_bubble_cycles 0 + + +#### ICache +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 + +### Branch Predictor +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_mech tagescl + + +#### BTB + +# BTB model to use. +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 + +# Allow the BTB to be updated by off path ops. +--btb_off_path_writes 1 + + +#### CRS + +# Enable return stack +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 + +### iBP +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged + # iBTB Model. tc_tagless, tc_tagged, tc_hybrid. +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 + +### Decode Stage +--decode_cycles 5 + + +### Map Stage +--map_cycles 5 + + +### Issue Stage + +# Max number of instructions to be fetched, decoded, renamed, and issued per cycle. +--issue_width 6 + +--rs_fill_width 0 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 + + +### Exec Stage + +### DCache +--dcache_size 32768 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--dcache_assoc 4 +--dcache_line_size 64 + +### Reorder/Retire Stage + +# Max number of instructions to be retired per cycle. +--node_ret_width 6 +--node_table_size 224 + +# Do not keep stores in RSVs on cache misses; TODO: confirm what this knob does +--stores_do_not_block_window 1 + +# TODO: confirm what this knob does +--prefs_do_not_block_window 1 + + +## Uncore + +### Mid-level cache + +# Enable use of a midlevel cache between i/d and L1 +--mlc_present 0 + +### LLC +--l1_size 1048576 +--l1_banks 1 +--l1_cycles 18 +--l1_assoc 8 +--l1_line_size 64 +--l1_interleave_factor 64 + + +### Prefetcher +--pref_framework_on 1 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--pref_shared_queues 0 +--pref_train_on_pref_misses 0 +--pref_oracle_train 0 +--pref_ul1req_queue_overwrite_on_full 1 + +--stream_length 64 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 + +--pref_throttlefb_on=1 +--pref_acc_thresh_1=0.75 +--pref_acc_thresh_2=0.4 +--pref_acc_thresh_3=0.4 +--pref_timely_thresh=0.01 +--pref_polpf_thresh=0.005 +--pref_update_interval=8192 + +--mem_req_buffer_pref_watermark 4 +--promote_to_higher_priority_mem_req_type 1 + +### Memory +--addr_translation random + +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 + +--mem_req_buffer_entries 32 +--mem_l1_fill_queue_entries 32 +--va_page_size_bytes 4096 +--bus_width_in_bytes 8 + +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 + +## Other + + +### Debug +--debug_inst_start 0 +--debug_inst_stop -1 +--debug_cycle_start 0 +--debug_cycle_stop -1 + + +## Stats and Params +--dump_params 1 +--dump_stats 1 +--dump_trace 0 + +#################################### +--set_off_path_confirmed 1 + +--order_beyond_bus 1 + +--mem_ooo_stores 1 +--mem_obey_store_dep 1 diff --git a/labs/LAB5/runs/xalancbmk_s_base-sms0/PARAMS.out b/labs/LAB5/runs/xalancbmk_s_base-sms0/PARAMS.out new file mode 100644 index 00000000..26527fe4 --- /dev/null +++ b/labs/LAB5/runs/xalancbmk_s_base-sms0/PARAMS.out @@ -0,0 +1,908 @@ +--mode full +--model cmp +--frontend memtrace +--inst_limit 100000000 +--sim_limit none +--dump_params 1 +--dump_stats 1 +--dump_trace 0 +--mlc_present 0 +--l1_size 1048576 +--l1_assoc 8 +--l1_line_size 64 +--l1_cycles 18 +--l1_banks 1 +--l1_interleave_factor 64 +--va_page_size_bytes 4096 +--addr_translation random +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 +--dcache_size 32768 +--dcache_assoc 4 +--dcache_line_size 64 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--mem_ooo_stores 1 +--mem_obey_store_dep 1 +--mem_req_buffer_entries 32 +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 +--promote_to_higher_priority_mem_req_type 1 +--mem_req_buffer_pref_watermark 4 +--mem_l1_fill_queue_entries 32 +--order_beyond_bus 1 +--set_off_path_confirmed 1 +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--bus_width_in_bytes 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 +--chip_cycle_time 312500 +--issue_width 6 +--rs_fill_width 0 +--node_table_size 224 +--node_ret_width 6 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 +--decode_cycles 5 +--map_cycles 5 +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--fetch_across_cache_lines 1 +--fetch_off_path_ops 0 +--fetch_break_on_taken 1 +--fetch_taken_bubble_cycles 0 +--stores_do_not_block_window 1 +--prefs_do_not_block_window 1 +--cbp_trace_r0 /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir/trace/drmemtrace.xalancbmk_s_base.mytest-m64.555084.7482.trace.gz +--memtrace_modules_log /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir/raw +--debug_cycle_start 0 +--debug_cycle_stop -1 +--debug_inst_start 0 +--debug_inst_stop -1 +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--bp_mech tagescl +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 +--btb_off_path_writes 1 +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_length 64 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 +--pref_framework_on 1 +--pref_shared_queues 0 +--pref_ul1req_queue_overwrite_on_full 1 +--pref_train_on_pref_misses 0 +--pref_oracle_train_on 0 +--pref_throttlefb_on 1 +--pref_acc_thresh_1 0.75 +--pref_acc_thresh_2 0.4 +--pref_acc_thresh_3 0.4 +--pref_update_interval 8192 +--pref_timely_thresh 0.01 +--pref_polpf_thresh 0.005 +--pref_sms_on 0 +1 1 1 1 1 1 1 + +--- Cut out everything below to use this file as PARAMS.in --- + +Parameter status at compile time and values supplied on the command line: + +SIM_MODE 0 full +SIM_MODEL 0 cmp +FRONTEND FE_PIN_EXEC_DRIVEN memtrace +INST_LIMIT NULL 100000000 +SIM_LIMIT "none" none +FORWARD_PROGRESS_LIMIT 100000000 +FORWARD_PROGRESS_INTERVAL 10000 +FAST_FORWARD 0 +FAST_FORWARD_UNTIL_ADDR 0 +FAST_FORWARD_TRACE_INS 0 +WARMUP 0 +HEARTBEAT_INTERVAL 1000000 +NUM_HEARTBEATS 0 +FILE_TAG "" +OUTPUT_DIR "." +STATUS_FILE NULL +BINDIR NULL +DUMP_PARAMS TRUE 1 +DUMP_STATS TRUE 1 +DUMP_TRACE FALSE 0 +CLEAR_STATS "never" +STATS_TO_TRACE NULL +STAT_TRACE_FILE "stats.trace" +STAT_TRACE_INTERVAL "i:100000" +PIPEVIEW FALSE +PIPEVIEW_FILE "pipeview" +MEMVIEW FALSE +MEMVIEW_FILE "memview.out" +MEMVIEW_START "never" +INST_HASH_TABLE_SIZE 500021 const +STDOUT_FILE NULL +STDERR_FILE NULL +PIN_EXEC_DRIVEN_FE_SOCKET "./pin_exec_driven_fe_socket.temp" +PRINT_PID FALSE +USE_UNSURE_FREE_LISTS FALSE +OPTIMIZER2_MAX_NUM_SLAVES 64 +OPTIMIZER2_PERFECT_MEMORYLESS FALSE +EXIT_COND 0 +ENABLE_SWPRF FALSE +MLC_PRESENT FALSE 0 +MLC_SIZE (512 * 1024) +MLC_ASSOC 4 +MLC_LINE_SIZE 64 +MLC_CYCLES 12 +PERFECT_MLC FALSE +MLC_READ_PORTS 1 +MLC_WRITE_PORTS 1 +MLC_BANKS 8 +MLC_INTERLEAVE_FACTOR 64 +MLC_CACHE_REPL_POLICY 0 +MLC_WRITE_THROUGH FALSE +PREFETCH_UPDATE_LRU_MLC TRUE +FORCE_L1_MISS FALSE +L1_SIZE (4 * 1024 * 1024) 1048576 +L1_ASSOC 8 8 +L1_LINE_SIZE 64 64 +L1_CYCLES 24 18 +PERFECT_L1 FALSE +PRIVATE_L1 FALSE +L1_READ_PORTS 1 +L1_WRITE_PORTS 1 +L1_BANKS 8 1 +L1_INTERLEAVE_FACTOR 64 64 +L1_CACHE_REPL_POLICY 0 +L1_WRITE_THROUGH FALSE +L1_IGNORE_WB FALSE +L1_USE_CORE_FREQ FALSE +MARK_L1_MISSES TRUE +PREFETCH_UPDATE_LRU_L1 TRUE +MEMORY_RANDOM_ADDR FALSE +VA_PAGE_SIZE_BYTES 4096 4096 +NUM_ADDR_NON_SIGN_EXTEND_BITS 48 +ADDR_TRANSLATION 0 random +CONSTANT_MEMORY_LATENCY FALSE +MEMORY_CYCLES 100 +STALL_MEM_REQS_ONLY FALSE +ICACHE_SIZE (64 * 1024) 32768 +ICACHE_ASSOC 4 4 +ICACHE_LINE_SIZE 64 64 +PERFECT_ICACHE FALSE +ICACHE_READ_PORTS 2 +ICACHE_WRITE_PORTS 1 +ICACHE_BANKS 8 +ICACHE_REPL 0 +DCACHE_SIZE (64 * 1024) 32768 +DCACHE_ASSOC 1 4 +DCACHE_LINE_SIZE 64 64 +DCACHE_CYCLES 2 +PERFECT_DCACHE FALSE +DCACHE_READ_PORTS 8 2 +DCACHE_WRITE_PORTS 1 1 +DCACHE_BANKS 1 1 +DCACHE_REPL 0 +DCACHE_REPL_PREF_THRESH 1 +MEM_OOO_STORES TRUE 1 +MEM_OBEY_STORE_DEP TRUE 1 +PREF_INSERT_LRU FALSE +PREF_INSERT_MIDDLE FALSE +PREF_INSERT_LOWQTR FALSE +PREF_INSERT_DYNACC FALSE +MEM_REQ_BUFFER_ENTRIES 32 32 +PRIVATE_MSHR_ON TRUE +MEM_PRIORITY_IFETCH 0 0 +MEM_PRIORITY_DFETCH 0 1 +MEM_PRIORITY_DSTORE 0 2 +MEM_PRIORITY_IPRF 9 3 +MEM_PRIORITY_DPRF 10 4 +MEM_PRIORITY_WB 0 5 +MEM_PRIORITY_WB_NODIRTY 0 5 +PROMOTE_TO_HIGHER_PRIORITY_MEM_REQ_TYPE FALSE 1 +MEM_REQ_BUFFER_PREF_WATERMARK 0 4 +MEM_REQ_BUFFER_WB_VALVE 2 +MEM_L1_FILL_QUEUE_ENTRIES 32 32 +MEM_BUS_OUT_QUEUE_PARTITION_ENABLE FALSE +MEM_MEM_QUEUE_PARTITION_ENABLE FALSE +MEM_BUS_OUT_QUEUE_AS_FIFO TRUE +OLDEST_FIRST_TO_MEM_QUEUE TRUE +ROUND_ROBIN_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE_TH 0 +L1_CYCLE_TIME 312500 +MLCQ_TO_L1Q_TRANSFER_LATENCY 1 +L1Q_TO_FSB_TRANSFER_LATENCY 1 +PRIORITIZE_PREFETCHES_WITH_UNIQUE FALSE +KICKOUT_PREFETCHES FALSE +KICKOUT_LOOK_FOR_OLDEST_FIRST FALSE +KICKOUT_OLDEST_PREFETCH FALSE +KICKOUT_OLDEST_PREFETCH_WITHIN_BANK FALSE +ORDER_BEYOND_BUS FALSE 1 +ALL_FIFO_QUEUES FALSE +QUEUE_MLC_SIZE 0 +QUEUE_L1_SIZE 0 +QUEUE_BUS_OUT_SIZE 0 +QUEUE_CORE_FILL_SIZE 0 +ALLOW_TYPE_MATCHES FALSE +STREAM_PREFETCH_ON FALSE +DC_PREF_CACHE_ENABLE FALSE +DC_PREF_CACHE_CYCLE 0 +PREF_INSERT_DCACHE_IMM TRUE +DC_PREF_CACHE_SIZE (64 * 1024) +DC_PREF_CACHE_ASSOC 4 +DC_PREF_ONLY_L1HIT FALSE +PREF_CACHE_USE_RDY_CYCLE FALSE +IC_PREF_CACHE_ENABLE FALSE +IC_PREF_CACHE_SIZE (64 * 1024) +IC_PREF_CACHE_ASSOC 4 +L1_PREF_CACHE_ENABLE FALSE +L1_PREF_CACHE_SIZE (1024 * 1024) +L1_PREF_CACHE_ASSOC 8 +SET_OFF_PATH_CONFIRMED FALSE 1 +USE_CONFIRMED_OFF FALSE +PREFCACHE_MOVE_OFFPATH FALSE +CACHE_STAT_ENABLE FALSE +PREF_DCACHE_HIT_FILL_L1 TRUE +PREF_ICACHE_HIT_FILL_L1 TRUE +CRITICAL_ACCESS_PLOT_ENABLE FALSE +CRITICAL_ACCESS_PLOT_FILE "critical_access_plot.dat" +ROUND_ROBIN_TO_L1 FALSE +PREF_I_TOGETHER FALSE +ONE_MORE_CACHE_LINE_ENABLE FALSE +L1_STATIC_PARTITION_ENABLE 0 +L1_STATIC_PARTITION NULL +L1_DYNAMIC_PARTITION_ENABLE FALSE +L1_DYNAMIC_PARTITION_POLICY 0 +PARTITION_UMON_DSS_PREF_ENABLE FALSE +L1_CACHE_HIT_POSITION_COLLECT FALSE +L1_PART_ON FALSE +L1_PART_TRIGGER "c:1000000" +L1_PART_START "t:0" +L1_PART_WARMUP FALSE +L1_PART_SHADOW_WARMUP FALSE +L1_PART_METRIC 0 +L1_PART_SEARCH 0 +L1_PART_USE_STALLING TRUE +L1_PART_FILL_DELAY 0 +L1_SHADOW_TAGS_MODULO 1 +HIER_MSHR_ON FALSE +PERF_PRED_ENABLE FALSE +PERF_PRED_MECH PERF_PRED_CP +PERF_PRED_REQ_LATENCY_MECH PERF_PRED_REQ_LATENCY_MECH_REQ_LATENCY +PERF_PRED_COUNT_ALL FALSE +PERF_PRED_COUNT_INST_MISSES TRUE +PERF_PRED_COUNT_PREFETCHES FALSE +PERF_PRED_COUNT_OFFPATH_REQS FALSE +PERF_PRED_COUNT_BW_REQS TRUE +PERF_PRED_UPDATE_MEM_REQ_TYPE FALSE +PERF_PRED_SLACK_PERIOD_SIZE 32 +PERF_PRED_REQS_FINISH_AT_FILL FALSE +PERF_PRED_MEM_UTIL_VIA_BUS_BW FALSE +PERF_PRED_CHIP_UTIL_VIA_MEM_STALL FALSE +DUMB_MODEL_AVG_REQ_DISTANCE 100 +DUMB_MODEL_RANDOMIZE_DISTANCE FALSE +DUMB_MODEL_AVG_REQ_DISTANCE_PER_CORE NULL +DUMB_MODEL_AVG_ROW_HITS 1 +DUMB_MODEL_AVG_ROW_HITS_PER_CORE NULL +DUMB_MODEL_MLP 1 +DUMB_MODEL_MLP_PER_CORE NULL +RAMULATOR_STANDARD "DDR4" DDR4 +RAMULATOR_SPEED "DDR4_2400R" DDR4_2400R +RAMULATOR_ORG "DDR4_8Gb_x8" DDR4_8Gb_x8 +RAMULATOR_CHANNELS 1 1 +RAMULATOR_RANKS 1 1 +RAMULATOR_BANKGROUPS 4 4 +RAMULATOR_BANKS 4 4 +RAMULATOR_CHIP_WIDTH 8 8 +BUS_WIDTH_IN_BYTES 8 8 +RAMULATOR_ROWS 65536 65536 +RAMULATOR_COLS 1024 1024 +RAMULATOR_SCHEDULING_POLICY "FRFCFS_Cap" FRFCFS_Cap +RAMULATOR_READQ_ENTRIES 32 32 +RAMULATOR_WRITEQ_ENTRIES 32 32 +RAMULATOR_REC_CMD_TRACE "off" FALSE +RAMULATOR_PRINT_CMD_TRACE "off" FALSE +RAMULATOR_USE_REST_OF_ADDR_AS_ROW_ADDR "on" +RAMULATOR_TCK 833333 833333 +RAMULATOR_TCL 16 16 +RAMULATOR_TCCD 6 6 +RAMULATOR_TCCDS 4 4 +RAMULATOR_TCCDL 6 6 +RAMULATOR_TCWL 12 12 +RAMULATOR_TBL 4 4 +RAMULATOR_TWTR 9 9 +RAMULATOR_TWTRS 3 3 +RAMULATOR_TWTRL 9 9 +RAMULATOR_TRP 16 16 +RAMULATOR_TRPpb 16 16 +RAMULATOR_TRPab 16 16 +RAMULATOR_TRCD 16 16 +RAMULATOR_TRCDR 16 16 +RAMULATOR_TRCDW 16 16 +RAMULATOR_TRAS 39 39 +DRAM_TECH_IN_NM 32 32 +DVFS_ON FALSE +DVFS_METRIC DVFS_METRIC_NUM_ELEMS +DVFS_CONFIGS NULL +DVFS_CONFIG_FILE NULL +DVFS_START "t:0" +DVFS_PERIOD "t:312500000000" +DVFS_LOG TRUE +DVFS_INDIVIDUAL_CORES FALSE +DVFS_CHIP_LEVEL FALSE +DVFS_STATIC NULL +DVFS_FORCE_CONFIG NULL +DVFS_REPLAY_CONFIG_TRACE NULL +DVFS_USE_ORACLE FALSE +DVFS_USE_BW_SHARING FALSE +DVFS_USE_DRAM_SHARING FALSE +DVFS_USE_STALL_TIME FALSE +DVFS_DRAM_SHARING_SOLVER_BIN NULL +DVFS_DRAM_SHARING_SOLVER_STRICT TRUE +DVFS_BW_SHARING_BUS_UTIL_THRESH 0.95 +DVFS_BW_SHARING_MAX_REQS 28.0 +DVFS_BW_SHARING_MAX_RW_COST 0.25 +DVFS_BW_SHARING_NO_PREF_STALL TRUE +DVFS_BW_SHARING_CRIT_STATS TRUE +DVFS_COUNT_L1_ACCESS_STALL FALSE +NUM_CORES 1 +CHIP_CYCLE_TIME 312500 312500 +CORE_0_CYCLE_TIME 312500 +CORE_1_CYCLE_TIME 312500 +CORE_2_CYCLE_TIME 312500 +CORE_3_CYCLE_TIME 312500 +CORE_4_CYCLE_TIME 312500 +CORE_5_CYCLE_TIME 312500 +CORE_6_CYCLE_TIME 312500 +CORE_7_CYCLE_TIME 312500 +CORE_8_CYCLE_TIME 312500 +CORE_9_CYCLE_TIME 312500 +CORE_10_CYCLE_TIME 312500 +CORE_11_CYCLE_TIME 312500 +CORE_12_CYCLE_TIME 312500 +CORE_13_CYCLE_TIME 312500 +CORE_14_CYCLE_TIME 312500 +CORE_15_CYCLE_TIME 312500 +CORE_16_CYCLE_TIME 312500 +CORE_17_CYCLE_TIME 312500 +CORE_18_CYCLE_TIME 312500 +CORE_19_CYCLE_TIME 312500 +CORE_20_CYCLE_TIME 312500 +CORE_21_CYCLE_TIME 312500 +CORE_22_CYCLE_TIME 312500 +CORE_23_CYCLE_TIME 312500 +CORE_24_CYCLE_TIME 312500 +CORE_25_CYCLE_TIME 312500 +CORE_26_CYCLE_TIME 312500 +CORE_27_CYCLE_TIME 312500 +CORE_28_CYCLE_TIME 312500 +CORE_29_CYCLE_TIME 312500 +CORE_30_CYCLE_TIME 312500 +CORE_31_CYCLE_TIME 312500 +CORE_32_CYCLE_TIME 312500 +CORE_33_CYCLE_TIME 312500 +CORE_34_CYCLE_TIME 312500 +CORE_35_CYCLE_TIME 312500 +CORE_36_CYCLE_TIME 312500 +CORE_37_CYCLE_TIME 312500 +CORE_38_CYCLE_TIME 312500 +CORE_39_CYCLE_TIME 312500 +CORE_40_CYCLE_TIME 312500 +CORE_41_CYCLE_TIME 312500 +CORE_42_CYCLE_TIME 312500 +CORE_43_CYCLE_TIME 312500 +CORE_44_CYCLE_TIME 312500 +CORE_45_CYCLE_TIME 312500 +CORE_46_CYCLE_TIME 312500 +CORE_47_CYCLE_TIME 312500 +CORE_48_CYCLE_TIME 312500 +CORE_49_CYCLE_TIME 312500 +CORE_50_CYCLE_TIME 312500 +CORE_51_CYCLE_TIME 312500 +CORE_52_CYCLE_TIME 312500 +CORE_53_CYCLE_TIME 312500 +CORE_54_CYCLE_TIME 312500 +CORE_55_CYCLE_TIME 312500 +CORE_56_CYCLE_TIME 312500 +CORE_57_CYCLE_TIME 312500 +CORE_58_CYCLE_TIME 312500 +CORE_59_CYCLE_TIME 312500 +CORE_60_CYCLE_TIME 312500 +CORE_61_CYCLE_TIME 312500 +CORE_62_CYCLE_TIME 312500 +CORE_63_CYCLE_TIME 312500 +ISSUE_WIDTH 4 6 +RS_FILL_WIDTH 8 0 +NODE_TABLE_SIZE 256 224 +NODE_RET_WIDTH 4 6 +NODE_RETIRE_RATE 10 +RS_SIZES "256" 97 +RS_CONNECTIONS "xF" 0 +FU_TYPES "0, 0, 0, 0" 0 0 0 0 0 0 0 0 +DECODE_CYCLES 1 5 +MAP_CYCLES 1 5 +EXTRA_RECOVERY_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after recovery. +EXTRA_REDIRECT_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after redirect. +EXTRA_CALLSYS_CYCLES 20 const +DIE_ON_CALLSYS FALSE +DIE_ON_RET_STALL_THRESH 0 +DIE_ON_RET_STALL_CORE 0 +DIE_ON_MEM_BLOCK_THRESH 0 +DIE_ON_MEM_BLOCK_CORE 0 +FETCH_ACROSS_CACHE_LINES FALSE 1 +FETCH_OFF_PATH_OPS TRUE 0 +FETCH_BREAK_ON_TAKEN FALSE 1 +FETCH_TAKEN_BUBBLE_CYCLES 0 0 +WP_COLLECT_STATS FALSE +SWITCH_IC_FETCH_ON_RECOVERY TRUE +OP_INV_DELAY 1 +OP_NOP_DELAY 1 +OP_CF_DELAY 1 +OP_MOV_DELAY 1 +OP_CMOV_DELAY 1 +OP_LDA_DELAY 1 +OP_IMEM_DELAY 1 +OP_IADD_DELAY 1 +OP_IMUL_DELAY 3 +OP_IDIV_DELAY -20 +OP_ICMP_DELAY 1 +OP_LOGIC_DELAY 1 +OP_SHIFT_DELAY 1 +OP_FMEM_DELAY 1 +OP_FCVT_DELAY 3 +OP_FADD_DELAY 3 +OP_FMUL_DELAY 5 +OP_FMA_DELAY 5 +OP_FDIV_DELAY -20 +OP_FCMP_DELAY 3 +OP_FCMOV_DELAY 1 +OP_GATHER_DELAY 12 +OP_SCATTER_DELAY 18 +OP_PIPELINED_FAST_DELAY 2 +OP_PIPELINED_MEDIUM_DELAY 5 +OP_PIPELINED_SLOW_DELAY 10 +OP_NOTPIPELINED_MEDIUM_DELAY -5 +OP_NOTPIPELINED_SLOW_DELAY -20 +OP_NOTPIPELINED_VERY_SLOW_DELAY -100 +UNIFORM_OP_DELAY 0 +STALL_ON_WAIT_MEM TRUE +STORES_DO_NOT_BLOCK_WINDOW FALSE 1 +PREFS_DO_NOT_BLOCK_WINDOW FALSE 1 +OBEY_REG_DEP TRUE +OLDEST_FIRST_SCHED FALSE +FIND_EMPTIEST_RS FALSE +TRACK_L1_MISS_DEPS FALSE +CBP_TRACE_R0 NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir/trace/drmemtrace.xalancbmk_s_base.mytest-m64.555084.7482.trace.gz +CBP_TRACE_R1 NULL +CBP_TRACE_R2 NULL +CBP_TRACE_R3 NULL +CBP_TRACE_R4 NULL +CBP_TRACE_R5 NULL +CBP_TRACE_R6 NULL +CBP_TRACE_R7 NULL +CBP_TRACE_R8 NULL +CBP_TRACE_R9 NULL +CBP_TRACE_R10 NULL +CBP_TRACE_R11 NULL +CBP_TRACE_R12 NULL +CBP_TRACE_R13 NULL +CBP_TRACE_R14 NULL +CBP_TRACE_R15 NULL +CBP_TRACE_R16 NULL +CBP_TRACE_R17 NULL +CBP_TRACE_R18 NULL +CBP_TRACE_R19 NULL +CBP_TRACE_R20 NULL +CBP_TRACE_R21 NULL +CBP_TRACE_R22 NULL +CBP_TRACE_R23 NULL +CBP_TRACE_R24 NULL +CBP_TRACE_R25 NULL +CBP_TRACE_R26 NULL +CBP_TRACE_R27 NULL +CBP_TRACE_R28 NULL +CBP_TRACE_R29 NULL +CBP_TRACE_R30 NULL +CBP_TRACE_R31 NULL +CBP_TRACE_R32 NULL +CBP_TRACE_R33 NULL +CBP_TRACE_R34 NULL +CBP_TRACE_R35 NULL +CBP_TRACE_R36 NULL +CBP_TRACE_R37 NULL +CBP_TRACE_R38 NULL +CBP_TRACE_R39 NULL +CBP_TRACE_R40 NULL +CBP_TRACE_R41 NULL +CBP_TRACE_R42 NULL +CBP_TRACE_R43 NULL +CBP_TRACE_R44 NULL +CBP_TRACE_R45 NULL +CBP_TRACE_R46 NULL +CBP_TRACE_R47 NULL +CBP_TRACE_R48 NULL +CBP_TRACE_R49 NULL +CBP_TRACE_R50 NULL +CBP_TRACE_R51 NULL +CBP_TRACE_R52 NULL +CBP_TRACE_R53 NULL +CBP_TRACE_R54 NULL +CBP_TRACE_R55 NULL +CBP_TRACE_R56 NULL +CBP_TRACE_R57 NULL +CBP_TRACE_R58 NULL +CBP_TRACE_R59 NULL +CBP_TRACE_R60 NULL +CBP_TRACE_R61 NULL +CBP_TRACE_R62 NULL +CBP_TRACE_R63 NULL +MEMTRACE_MODULES_LOG NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir/raw +DUMB_CORE_ON FALSE +DUMB_CORE 1 +DEBUG_CYCLE_START 0 0 +DEBUG_CYCLE_STOP 0 -1 +DEBUG_TIME_START 0 +DEBUG_TIME_STOP 0 +DEBUG_INST_START 0 0 +DEBUG_INST_STOP 0 -1 +DEBUG_OP_START 0 +DEBUG_OP_STOP 0 +DEBUG_CACHE_LIB FALSE +DEBUG_HASH_LIB FALSE +DEBUG_LIST_LIB FALSE +DEBUG_PORT_LIB FALSE +DEBUG_BUS_LIB FALSE +DEBUG_OP_POOL FALSE +DEBUG_ORACLE FALSE +DEBUG_FRONTEND FALSE +DEBUG_ADDR_TRANS FALSE +DEBUG_BP FALSE +DEBUG_BP_DIR FALSE +DEBUG_BTB FALSE +DEBUG_CRS FALSE +DEBUG_MAP FALSE +DEBUG_MEMORY FALSE +DEBUG_REPLAY FALSE +DEBUG_FREQ FALSE +DEBUG_MODEL FALSE +DEBUG_THREAD FALSE +DEBUG_ICACHE_STAGE FALSE +DEBUG_DECODE_STAGE FALSE +DEBUG_MAP_STAGE FALSE +DEBUG_NODE_STAGE FALSE +DEBUG_EXEC_STAGE FALSE +DEBUG_DCACHE_STAGE FALSE +DEBUG_RETIRED_UOPS FALSE +DEBUG_EXC_INSERTS FALSE +DEBUG_BP_CONF FALSE +DEBUG_ONPATH_CONF FALSE +DEBUG_STREAM FALSE +DEBUG_STREAM_MEM FALSE +DEBUG_WAY FALSE +DEBUG_L2MARKV FALSE +DEBUG_L2L1PREF FALSE +DEBUG_PERF_PRED FALSE +DEBUG_POWER_UTILS FALSE +DEBUG_DVFS FALSE +DEBUG_TRACE_READ FALSE +DEBUG_INST_FIELDS FALSE +DEBUG_OP_FIELDS FALSE +DEBUG_PIN_EXEC_DRIVEN FALSE +DEBUG_CACHE_PART FALSE +DEBUG_OPTIMIZER2 FALSE +DEBUG_PREF FALSE +PERFECT_BP FALSE +PERFECT_BTB FALSE +PERFECT_IBP FALSE +PERFECT_CRS FALSE +PERFECT_CBR_BTB FALSE +PERFECT_NT_BTB FALSE +CFS_PER_CYCLE 3 6 # Number of branches that can be predicted in a single cycle +UPDATE_BP_OFF_PATH FALSE 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +BP_UPDATE_AT_RETIRE FALSE 0 # Update the BP at retire. If false, update at the end of exec. +BP_MECH 0 tagescl +LATE_BP_MECH NUM_BP +LATE_BP_LATENCY 5 +HIST_LENGTH 16 +PHT_CTR_BITS 2 const +BHT_ENTRIES (4 * 1024) +BHT_ASSOC 4 +HYBRIDS_INDEX_LENGTH 16 +HYBRIDG_HIST_LENGTH 16 +HYBRIDP_HIST_LENGTH 16 +FILTER_INDEX_LENGTH 16 +USE_FILTER FALSE +INF_HYBRIDGP FALSE +BP_HASH_TOS FALSE +IBTB_HASH_TOS FALSE +BTB_MECH 0 generic +BTB_ENTRIES (4 * 1024) 4096 +BTB_ASSOC 4 4 +BTB_OFF_PATH_WRITES TRUE 1 +ENABLE_CRS TRUE 1 +CRS_ENTRIES 32 32 +CRS_REALISTIC 0 1 +ENABLE_IBP TRUE 1 # Enable the indirect branch predictor +USE_PAT_HIST TRUE +IBTB_MECH 1 tc_tagged +IBTB_HIST_LENGTH 16 +IBTB_OFF_PATH_WRITES TRUE 1 # Allow off path ops to update the ibtb. +TARGETS_IN_HIST 4 +TC_ENTRIES (4 * 1024) 4096 +TC_ASSOC 4 4 +NUM_CORR_BRANCHES 3 +SEL_HIST_BP_ENTRIES 8192 +SEL_HIST_LENGTH 16 +SEL_HIST_DYN_CNT_TH 16 +SEL_HIST_MISPRED_TH 4 +ENABLE_BP_CONF FALSE +CONF_MECH 0 +PERF_BP_CONF_PRED FALSE +BPC_BITS 16 +BPC_MECH 1 +BPC_CTR_RESET TRUE +BPC_CIT_BITS 8 +BPC_CIT_TH 50 +BPC_CTR_BITS 3 +OPC_COUNT_ZEROS FALSE +OPC_COUNT_THRESH 10 +INF_LOOP FALSE +INF_LOOP_BUCKETS 811 +LOOP_ENTRIES (4 * 1024) +LOOP_ASSOC 4 +LOOP_COUNT_MAX 127 +LOOP_REPEAT_MAX 15 +KNOB_PRINT_BRINFO FALSE +BR_MISPRED_FILE NULL +CONF_PERCEPTRON_TH 0 +CONF_PERCEPTRON_CTR_BITS 8 +CONF_PERCEPTRON_ENTRIES 127 +CONF_PERCEPTRON_THRESH_OVRD 0 +CONF_HIST_LENGTH 32 +PERCEPTRON_CONF_USE_CONF FALSE +PERCEPTRON_CONF_TRAIN_HIS FALSE +PERCEPTRON_CONF_TRAIN_CONF FALSE +PERCEPTRON_CONF_TRAIN_OFFSET_CONF FALSE +PERCEPTRON_TRAIN_MISP_FACTOR 1 +PERCEPTRON_TRAIN_CORR_FACTOR 1 +PERCEPTRON_CONF_HIS_BOTH FALSE +PERCEPTRON_CONF_HIS_BOTH_LENGTH 4 +ENABLE_ICACHE_PACKET_BREAKING TRUE +NUM_LOAD_STORE_PER_PACKET 0 +PACKET_BREAK_ON_FUS FALSE +PACKET_BREAK_FU_TYPES "G,G,G,G,G,G,G,G,G,G,G,G" +POWER_INTF_ON FALSE +POWER_INTF_ENABLE_SCALING FALSE +POWER_INTF_EXEC "power/power_intf.py" +POWER_INTF_REF_CHIP_TECH_NM 22 +POWER_INTF_REF_CHIP_FREQ (3.2e9) +POWER_INTF_REF_MEMORY_FREQ (0.8e9) +POWER_OTHER (0.0) +PREF_STREAM_ON FALSE 1 +PREF_STREAM_PER_CORE_ENABLE FALSE 1 +STREAM_BUFFER_N 16 +STREAM_PREFETCH_N 2 4 +STREAM_START_DIS 5 1 +STREAM_LENGTH 16 64 +STREAM_FULL_N 1 +STREAM_TRAIN_LENGTH 16 +STREAM_TRAIN_NUM 1 4 +PREF_ACC_USE_CACHE FALSE +STREAM_STALL_ON_QUEUE_FULL FALSE +PREF_SCHEDULE_NUM 4 +TRAIN_FILTER_SIZE 32 +PREF_REQ_Q_SIZE 64 +STREAM_CREATE_ON_DC_MISS FALSE 0 +STREAM_CREATE_ON_L1_MISS TRUE 1 +STREAM_TRAIN_ON_WRONGPATH TRUE +STREAM_CREATE_ON_WRONGPATH TRUE +STREAM_PREF_INTO_DCACHE FALSE +REMOVE_REDUNDANT_STREAM FALSE +L2HIT_STREAM_SCHEDULE_NUM 4 +PREF_REQ_QUEUE_FILTER_ON FALSE +HW_PREF_HIT_TRAIN_STREAM FALSE +L2HIT_STREAM_BUFFER_N 32 +L2HIT_STREAM_PREFETCH_N 2 +L2HIT_STREAM_START_DIS 2 +L2HIT_STREAM_LENGTH 8 +L2HIT_PREF_REQ_Q_SIZE 128 +L2HIT_L2ACCESS_REQ_Q_SIZE 64 +PREF_STREAM_ACCPERSTREAM FALSE +PREF_ACC_DISTANCE_10 128 +PREF_FRAMEWORK_ON FALSE 1 +PREF_TRACE_ON FALSE +PREF_DL0REQ_QUEUE_SIZE 32 +PREF_UMLC_REQ_QUEUE_SIZE 64 +PREF_UL1REQ_QUEUE_SIZE 128 +PREF_SHARED_QUEUES TRUE 0 +PREF_DL0_MISS_ON TRUE +PREF_DL0_HIT_ON TRUE +PREF_DL0REQ_QUEUE_FILTER_ON TRUE +PREF_UMLC_REQ_QUEUE_FILTER_ON TRUE +PREF_UL1REQ_QUEUE_FILTER_ON TRUE +PREF_DL0REQ_ADD_FILTER_ON TRUE +PREF_UMLC_REQ_ADD_FILTER_ON TRUE +PREF_UL1REQ_ADD_FILTER_ON TRUE +PREF_DL0REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UMLC_REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UL1REQ_QUEUE_OVERWRITE_ON_FULL FALSE 1 +PREF_DL0SCHEDULE_NUM 4 +PREF_UMLC_SCHEDULE_NUM 4 +PREF_UL1SCHEDULE_NUM 4 +PREF_L1Q_DEMAND_RESERVE 0 +PREF_REPORT_PREF_MATCH_AS_MISS FALSE +PREF_REPORT_PREF_MATCH_AS_HIT TRUE +PREF_UPDATE_ON_WRONGPATH TRUE +PREF_TRAIN_ON_PREF_MISSES FALSE 0 +PREF_ORACLE_TRAIN_ON FALSE 0 +PREF_REQ_DROP FALSE +PREF_THROTTLE_ON FALSE +PREF_THROTTLEFB_ON FALSE 1 +PREF_ACC_THRESH_1 0.90 0.75 +PREF_ACC_THRESH_2 0.70 0.4 +PREF_ACC_THRESH_3 0.60 0.4 +PREF_ACC_THRESH_4 0.40 +PREF_UPDATE_INTERVAL 0 8192 +PREF_ANALYZE_LOAD FALSE +PREF_POL_THRESH_1 0.25 +PREF_POL_THRESH_2 0.10 +PREF_POLBV_ON FALSE +PREF_POLBV_SIZE 1024 +PREF_TIMELY_THRESH 0.05 0.01 +PREF_POLPF_THRESH 0.01 0.005 +PREF_DEGFB_USEONLYACC FALSE +PREF_DEGFB_USEONLYPOL FALSE +PREF_DEGFB_USEONLYLATE FALSE +PREF_TIMELY_THRESH_2 0.005 +PREF_DEGFB_STATPHASEFILE FALSE +PREF_MAX_DEGFB 4 +PREF_DHAL FALSE +PREF_DHAL_SENTTHRESH 16 +PREF_DHAL_USETHRESH_MAX 12 +PREF_DHAL_USETHRESH_MIN2 8 +PREF_DHAL_USETHRESH_MIN1 4 +PREF_DHAL_MAXDEG 64 +PREF_HFILTER_ON FALSE +PREF_HFILTER_INDEX_BITS 12 +PREF_HFILTER_USE_PC FALSE +PREF_HFILTER_PRED_USELESS_THRES 2 +PREF_HFILTER_RESET_ENABLE FALSE +PREF_HFILTER_RESET_INTERVAL 100000 +L2L1PREF_ON FALSE +L2WAY_PREF FALSE +L2MARKV_PREF_ON FALSE +L2NEXT_PREF_ON FALSE +L2HIT_STREAM_PREF_ON FALSE +L2L1_DC_HIT_TRAIN FALSE +L1_HIT_DUMP_FILE_ON FALSE +L1_HIT_DUMP_WO_TXT FALSE +L1_HIT_DUMPFILE "l1hit_dump.out" +IDEAL_L2_L1_PREFETCHER FALSE +IDEAL_L2_ICACHE_PREFETCHER FALSE +L1WAY_PREF_SEND_QUEUE 4 +L1PREF_REQ_QUEUE_SIZE 1024 +L1PREF_IMMEDIATE FALSE +L1WAY_PREF_TIMER_DIS 1000 +L1MARKV_PREF_SEND_QUEUE 4 +L1PREF_MARKV_REQ_QUEUE_SIZE 1024 +MARKV_L2ACCESS_REQ_Q_SIZE 64 +L1MARKV_PREF_IMMEDIATE FALSE +L1MARKV_PREF_TIMER_DIS 1 +L2L1_HIT_TRAIN TRUE +L1MARKV_REQ_TH 1 +L2L1_IMMEDIATE_PREF_CACHE FALSE +L2L1_FILL_PREF_CACHE FALSE +L2L1_L2_HIT_STAT FALSE +PREF_GHB_ON FALSE +DEBUG_PREF_GHB FALSE +PREF_GHB_BUFFER_N 1024 +PREF_GHB_INDEX_N 128 +PREF_GHB_CZONE_BITS 12 +PREF_GHB_DEGREE 16 +PREF_GHB_MAX_DEGREE 32 +PREF_STRIDE_ON FALSE +DEBUG_PREF_STRIDE FALSE +PREF_STRIDE_TABLE_N 1024 +PREF_STRIDE_REGION_BITS 16 +PREF_STRIDE_DEGREE 4 +PREF_STRIDE_DISTANCE 16 +PREF_STRIDE_STARTDISTANCE 1 +PREF_STRIDE_SINGLE_THRESH 6 +PREF_STRIDE_MULTI_THRESH 6 +PREF_STRIDE_SINGLE_STRIDE_MODE FALSE +PREF_STRIDEPC_ON FALSE +DEBUG_PREF_STRIDEPC FALSE +PREF_STRIDEPC_TABLE_N 1024 +PREF_STRIDEPC_DEGREE 4 +PREF_STRIDEPC_DISTANCE 16 +PREF_STRIDEPC_USELOADADDR FALSE +PREF_STRIDEPC_TRAINNUM 2 +PREF_STRIDEPC_STARTDIS 4 +PREF_PHASE_ON FALSE +PREF_PHASE_STUDY FALSE +DEBUG_PREF_PHASE FALSE +PREF_PHASE_PRIME_HASH 16381 +PREF_PHASE_INFOSIZE 16384 +PREF_PHASE_LOG2REGIONSIZE 12 +PREF_PHASE_REGIONENTRIES 64 +PREF_PHASE_TRACKEDREGIONS 32 +PREF_PHASE_INTERVAL 100000 +PREF_PHASE_TABLE_SIZE 64 +PREF_PHASE_MAXDIFF_THRESH 64 +PREF_PHASE_MIN_MISSES 64 +PREF_PHASE_MISSPER 0.4 +PREF_2DC_ON FALSE +DEBUG_PREF_2DC FALSE +PREF_2DC_CACHE_SIZE (1 * 1024) +PREF_2DC_CACHE_ASSOC 4 +PREF_2DC_CACHE_LINE_SIZE 1 +PREF_2DC_DEGREE 16 +PREF_2DC_ZONE_SHIFT 10 +PREF_2DC_TAG_SIZE 16 +PREF_2DC_NUM_REGIONS 64 +PREF_2DC_REGION_HASH 61 +PREF_MARKOV_ON FALSE +DEBUG_PREF_MARKOV FALSE +PREF_MARKOV_NUM_ENTRIES 65536 +PREF_MARKOV_NUM_NEXT_STATES 8 +PREF_MARKOV_SEND_ON_PREF_HIT TRUE +PREF_MARKOV_UPDATE_ON_PREF_HIT TRUE +PREF_MARKOV_TABLE_UPDATE_POLICY 0 +PREF_MARKOV_SEND_THRESHOLD 0 +PREF_SMS_ON FALSE 0 +PREF_SMS_AT_SIZE 64 +PREF_SMS_FT_SIZE 64 +PREF_SMS_PHT_SIZE 16384 +PREF_SMS_PRF_SIZE 1024 +PREF_SMS_REGION_SIZE 2048 diff --git a/labs/LAB5/runs/xalancbmk_s_base-sms0/bp.stat.0.out b/labs/LAB5/runs/xalancbmk_s_base-sms0/bp.stat.0.out new file mode 100644 index 00000000..d52e0292 --- /dev/null +++ b/labs/LAB5/runs/xalancbmk_s_base-sms0/bp.stat.0.out @@ -0,0 +1,752 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 99495664 Instructions: 100000000 IPC: 1.00507 + +BTB_ON_PATH_MISS 260260 1.012% 260260 1.012% +BTB_ON_PATH_HIT 25446980 98.988% 25446980 98.988% + 25707240 100.000% 25707240 100.000% + 0.99 0.98 0.99 0.98 + +BTB_OFF_PATH_MISS 0 -nan% 0 -nan% +BTB_OFF_PATH_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BTB_ON_PATH_WRITE 260260 100.000% 260260 100.000% +BTB_OFF_PATH_WRITE 0 0.000% 0 0.000% + 260260 100.000% 260260 100.000% + 0.00 0.00 0.00 0.00 + +BP_ON_PATH_CORRECT 25275249 98.320% 25275249 98.320% +BP_ON_PATH_MISPREDICT 45002 0.175% 45002 0.175% +BP_ON_PATH_MISFETCH 386989 1.505% 386989 1.505% + 25707240 100.000% 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0.000% +MEM_BLOCK_LENGTH_900 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_1000 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_1100 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_1200 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_1300 1 0.361% 1 0.361% +MEM_BLOCK_LENGTH_1400 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_1500 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_1600 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_1700 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_1800 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_1900 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_2000 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_2100 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_2200 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_2300 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_2400 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_2500 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_2600 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_2700 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_2800 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_2900 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_3000 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_3100 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_3200 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_3300 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_3400 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_3500 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_3600 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_3700 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_3800 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_3900 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4000 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4100 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4200 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4300 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4400 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4500 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4600 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4700 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4800 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4900 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_5000 0 0.000% 0 0.000% + 277 100.000% 277 100.000% + 0.18 0.97 0.18 0.97 + +FUS_BUSY_ON_PATH 127858991 1.2851 127858991 1.2851 + +FUS_BUSY_OFF_PATH 0 0.0000 0 0.0000 + +FU_BUSY_MEM_STALL 4718840 0.0474 4718840 0.0474 + +FUS_EMPTY 668106321 6.7149 668106321 6.7149 + +CHIP_UTILIZATION 0 0.0000 0 0.0000 + +CYCLES_UNDER_MEM_REQ 0 0 + +CYCLES_UNDER_NO_MEM_REQ 0 0 + +CYCLES_UNDER_CRITICAL_MEM_REQ 0 0 + +CYCLES_UNDER_NONCRITICAL_MEM_REQ 0 0 + +CHIP_UTILIZATION_UNDER_MEM_REQ 0 -nan 0 -nan + +CHIP_UTILIZATION_UNDER_NO_MEM_REQ 0 -nan 0 -nan + +CHIP_UTILIZATION_UNDER_CRITICAL_MEM_REQ 0 -nan 0 -nan + +CHIP_UTILIZATION_UNDER_NONCRITICAL_MEM_REQ 0 -nan 0 -nan + +CYCLES_NOT_WAITING_FOR_OFF_CHIP 0 0.0000 0 0.0000 + +FUS_BUSY_NOT_WAITING_FOR_OFF_CHIP 0 -nan 0 -nan + +CYCLES_WAITING_FOR_OFF_CHIP 0 0.0000 0 0.0000 + +FUS_BUSY_WAITING_FOR_OFF_CHIP 0 -nan 0 -nan + +TOTAL_OFF_CHIP_DELAYS_LEFT 0 0 + +WRONG_IO_SCHED 0 0 + +DVFS_CONFIG_SWITCH 0 0 + + + diff --git a/labs/LAB5/runs/xalancbmk_s_base-sms0/fetch.stat.0.out b/labs/LAB5/runs/xalancbmk_s_base-sms0/fetch.stat.0.out new file mode 100644 index 00000000..3ed79d66 --- /dev/null +++ b/labs/LAB5/runs/xalancbmk_s_base-sms0/fetch.stat.0.out @@ -0,0 +1,248 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 99495664 Instructions: 100000000 IPC: 1.00507 + +ICACHE_CYCLE 99495664 99495664 + +TCACHE_CYCLE 0 0 + +ICACHE_CYCLE_ONPATH 47518383 47.759% 47518383 47.759% +ICACHE_CYCLE_OFFPATH 51977281 52.241% 51977281 52.241% + 99495664 100.000% 99495664 100.000% + 0.52 0.51 0.52 0.51 + +FETCH_ON_PATH 26945093 100.000% 26945093 100.000% +FETCH_OFF_PATH 0 0.000% 0 0.000% + 26945093 100.000% 26945093 100.000% + 0.00 0.00 0.00 0.00 + +FETCHED_OPS_ON_PATH 0 -nan% 0 -nan% +FETCHED_OPS_OFF_PATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +INST_LOST_WAIT_FOR_MISP_RECOVERY 0 0.000% 0 0.000% +INST_LOST_WAIT_FOR_TIMER 0 0.000% 0 0.000% +INST_LOST_WAIT_FOR_EMPTY_ROB 1950 0.001% 1950 0.001% +INST_LOST_WAIT_FOR_REDIRECT 10946916 3.763% 10946916 3.763% +INST_LOST_FETCH 122678521 42.174% 122678521 42.174% +INST_LOST_OFF_PATH 0 0.000% 0 0.000% +INST_LOST_FULL_WINDOW 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_OTHER 3110622 1.069% 3110622 1.069% +INST_LOST_ROB_STALL_WAIT_FOR_RECOVERY 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_REDIRECT 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_GAP_FILL 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_L1_MISS 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_MEMORY 25356 0.009% 25356 0.009% +INST_LOST_ROB_STALL_WAIT_FOR_DC_MISS 21388332 7.353% 21388332 7.353% +INST_LOST_ROB_BLOCK_ISSUE_FULL 0 0.000% 0 0.000% +INST_LOST_ROB_BLOCK_ISSUE_GAP_TOO_LARGE 0 0.000% 0 0.000% +INST_LOST_BREAK_DONT 0 0.000% 0 0.000% +INST_LOST_BREAK_ISSUE_WIDTH 0 0.000% 0 0.000% +INST_LOST_BREAK_CF 0 0.000% 0 0.000% +INST_LOST_BREAK_BTB_MISS 573056 0.197% 573056 0.197% +INST_LOST_BREAK_ICACHE_MISS 97876681 33.648% 97876681 33.648% +INST_LOST_BREAK_LINE_END 0 0.000% 0 0.000% +INST_LOST_BREAK_STALL 0 0.000% 0 0.000% +INST_LOST_BREAK_BARRIER 34 0.000% 34 0.000% +INST_LOST_BREAK_OFFPATH 25353 0.009% 25353 0.009% +INST_LOST_BREAK_ALIGNMENT 0 0.000% 0 0.000% +INST_LOST_BREAK_TAKEN 34258015 11.777% 34258015 11.777% +INST_LOST_BREAK_MODEL_BEFORE 0 0.000% 0 0.000% +INST_LOST_BREAK_MODEL_AFTER 0 0.000% 0 0.000% + 290884836 100.000% 290884836 100.000% + 12.66 8.64 12.66 8.64 + +INST_LOST_TOTAL 596973984 596973984 + +FETCH_0_OPS 22205819 45.803% 22205819 45.803% +FETCH_1_OPS 2378508 4.906% 2378508 4.906% +FETCH_2_OPS 1555709 3.209% 1555709 3.209% +FETCH_3_OPS 1451870 2.995% 1451870 2.995% +FETCH_4_OPS 5260469 10.851% 5260469 10.851% +FETCH_5_OPS 1979477 4.083% 1979477 4.083% +FETCH_6_OPS 13648954 28.153% 13648954 28.153% +FETCH_7_OPS 0 0.000% 0 0.000% +FETCH_8_OPS 0 0.000% 0 0.000% +FETCH_9_OPS 0 0.000% 0 0.000% +FETCH_10_OPS 0 0.000% 0 0.000% +FETCH_11_OPS 0 0.000% 0 0.000% +FETCH_12_OPS 0 0.000% 0 0.000% +FETCH_13_OPS 0 0.000% 0 0.000% +FETCH_14_OPS 0 0.000% 0 0.000% +FETCH_15_OPS 0 0.000% 0 0.000% +FETCH_16_OPS 0 0.000% 0 0.000% + 48480806 100.000% 48480806 100.000% + 2.53 2.00 2.53 2.00 + +ST_BREAK_DONT 0 0.000% 0 0.000% +ST_BREAK_ISSUE_WIDTH 11779773 43.718% 11779773 43.718% +ST_BREAK_CF 0 0.000% 0 0.000% +ST_BREAK_BTB_MISS 260260 0.966% 260260 0.966% +ST_BREAK_ICACHE_MISS 720333 2.673% 720333 2.673% +ST_BREAK_LINE_END 0 0.000% 0 0.000% +ST_BREAK_STALL 0 0.000% 0 0.000% +ST_BREAK_BARRIER 17 0.000% 17 0.000% +ST_BREAK_OFFPATH 13286 0.049% 13286 0.049% +ST_BREAK_ALIGNMENT 0 0.000% 0 0.000% +ST_BREAK_TAKEN 14171424 52.594% 14171424 52.594% + 26945093 100.000% 26945093 100.000% + 5.84 6.12 5.84 6.12 + +ORACLE_ON_PATH_INST 122678521 100.000% 122678521 100.000% +ORACLE_OFF_PATH_INST 0 0.000% 0 0.000% + 122678521 100.000% 122678521 100.000% + 0.00 0.00 0.00 0.00 + +ORACLE_ON_PATH_INST_MEM 36394722 29.667% 36394722 29.667% +ORACLE_ON_PATH_INST_NOTMEM 86283799 70.333% 86283799 70.333% +ORACLE_OFF_PATH_INST_MEM 0 0.000% 0 0.000% +ORACLE_OFF_PATH_INST_NOTMEM 0 0.000% 0 0.000% + 122678521 100.000% 122678521 100.000% + 0.70 0.25 0.70 0.25 + +ICACHE_CYCLE_NONRA_ONPATH 0 -nan% 0 -nan% +ICACHE_CYCLE_NONRA_OFFPATH 0 -nan% 0 -nan% +ICACHE_CYCLE_RA_ONPATH 0 -nan% 0 -nan% +ICACHE_CYCLE_RA_OFFPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ICACHE_CYCLE_ONPATH_NONRA 0 -nan% 0 -nan% +ICACHE_CYCLE_OFFPATH_NONRA 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ICACHE_CYCLE_ONPATH_RA 0 -nan% 0 -nan% +ICACHE_CYCLE_OFFPATH_RA 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +INACCURATE_OFFPATH_CYCLES 0 0.0000 0 0.0000 + +FETCH_ALL_INST 122678521 122678521 + +EXEC_ALL_INST 122678470 122678470 + +RET_ALL_INST 122678423 122678423 + +EXEC_ON_PATH_INST 122678470 100.000% 122678470 100.000% +EXEC_OFF_PATH_INST 0 0.000% 0 0.000% + 122678470 100.000% 122678470 100.000% + 0.00 0.00 0.00 0.00 + +EXEC_ON_PATH_INST_MEM 36394712 29.667% 36394712 29.667% +EXEC_ON_PATH_INST_NOTMEM 86283758 70.333% 86283758 70.333% +EXEC_OFF_PATH_INST_MEM 0 0.000% 0 0.000% +EXEC_OFF_PATH_INST_NOTMEM 0 0.000% 0 0.000% + 122678470 100.000% 122678470 100.000% + 0.70 0.25 0.70 0.25 + +EXEC_RA_INST 0 -nan% 0 -nan% +EXEC_NONRA_INST 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +EXEC_ON_PATH_INST_RA 0 -nan% 0 -nan% +EXEC_OFF_PATH_INST_RA 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +EXEC_ON_PATH_INST_NONRA 0 -nan% 0 -nan% +EXEC_OFF_PATH_INST_NONRA 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +EXEC_RA_ON_PATH_INST 0 -nan% 0 -nan% +EXEC_RA_OFF_PATH_INST 0 -nan% 0 -nan% +EXEC_NONRA_ON_PATH_INST 0 -nan% 0 -nan% +EXEC_NONRA_OFF_PATH_INST 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ICACHE_THROTTLE_CYCLE 0 0 + +FETCH_ENABLE_THROTTLE_OFF_PATH 0 -nan% 0 -nan% +FETCH_ENABLE_THROTTLE_ON_PATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +FETCH_DISABLE_THROTTLE_OFF_PATH 0 -nan% 0 -nan% +FETCH_DISABLE_THROTTLE_ON_PATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +FETCH_TH_ADJUST__0 0 -nan% 0 -nan% +FETCH_TH_ADJUST__1 0 -nan% 0 -nan% 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-nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_11 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_12 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_13 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_14 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_15 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_16 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_17 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_18 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_19 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_20 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +LOW_CONF_COUNT_RET_0 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_1 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_2 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_3 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_4 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_5 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_6 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_7 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_8 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_9 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_10 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_11 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_12 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_13 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_14 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_15 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_16 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_17 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_18 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_19 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_20 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + + + diff --git a/labs/LAB5/runs/xalancbmk_s_base-sms0/inst.stat.0.out b/labs/LAB5/runs/xalancbmk_s_base-sms0/inst.stat.0.out new file mode 100644 index 00000000..d7586819 --- /dev/null +++ b/labs/LAB5/runs/xalancbmk_s_base-sms0/inst.stat.0.out @@ -0,0 +1,103 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 99495664 Instructions: 100000000 IPC: 1.00507 + +ST_OP_INV 0 0.000% 0 0.000% +ST_OP_NOP 2194493 1.789% 2194493 1.789% +ST_OP_CF 25707257 20.955% 25707257 20.955% +ST_OP_MOV 9609563 7.833% 9609563 7.833% +ST_OP_CMOV 37882 0.031% 37882 0.031% +ST_OP_LDA 3328200 2.713% 3328200 2.713% +ST_OP_IMEM 36242566 29.543% 36242566 29.543% +ST_OP_IADD 20326400 16.569% 20326400 16.569% +ST_OP_IMUL 148805 0.121% 148805 0.121% +ST_OP_IDIV 24299 0.020% 24299 0.020% +ST_OP_ICMP 13665531 11.139% 13665531 11.139% +ST_OP_LOGIC 10291006 8.389% 10291006 8.389% +ST_OP_SHIFT 950333 0.775% 950333 0.775% +ST_OP_FMEM 152156 0.124% 152156 0.124% +ST_OP_FCVT 20 0.000% 20 0.000% +ST_OP_FADD 0 0.000% 0 0.000% +ST_OP_FMUL 10 0.000% 10 0.000% +ST_OP_FMA 0 0.000% 0 0.000% +ST_OP_FDIV 0 0.000% 0 0.000% +ST_OP_FCMP 0 0.000% 0 0.000% +ST_OP_FCMOV 0 0.000% 0 0.000% +ST_OP_GATHER 0 0.000% 0 0.000% +ST_OP_SCATTER 0 0.000% 0 0.000% +ST_OP_PIPELINED_FAST 0 0.000% 0 0.000% +ST_OP_PIPELINED_MEDIUM 0 0.000% 0 0.000% +ST_OP_PIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_MEDIUM 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_VERY_SLOW 0 0.000% 0 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a/labs/LAB5/runs/xalancbmk_s_base-sms0/l2l1pref.stat.0.out b/labs/LAB5/runs/xalancbmk_s_base-sms0/l2l1pref.stat.0.out new file mode 100644 index 00000000..515a9e6b --- /dev/null +++ b/labs/LAB5/runs/xalancbmk_s_base-sms0/l2l1pref.stat.0.out @@ -0,0 +1,140 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 99495664 Instructions: 100000000 IPC: 1.00507 + +L2WAY_FILL_L1 0 0 + +L2WAY_WAY_HIT 0 -nan% 0 -nan% +L2WAY_WAY_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_PREF_REQ 0 0 + +L2WAY_PREF_HIT_DATA_IN_CACHE 0 -nan% 0 -nan% +L2WAY_PREF_HIT_DATA_REQ 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_TRAIN_HIT 0 -nan% 0 -nan% +L2WAY_TRAIN_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L1_HIT_REQ_TYPE_IFETCH 0 -nan% 0 -nan% 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108.4075 + +CORE_L1_MISS_LATENCY_PREF 23896077 106.0314 23896077 106.0314 + +CORE_EVICTED_L1_DEMAND 676787 75.290% 676787 75.290% +CORE_EVICTED_L1_PREF_USED 83701 9.311% 83701 9.311% +CORE_EVICTED_L1_PREF_NOT_USED 138417 15.398% 138417 15.398% + 898905 100.000% 898905 100.000% + 0.40 0.67 0.40 0.67 + +CORE_EVICTED_MLC_DEMAND 0 -nan% 0 -nan% +CORE_EVICTED_MLC_PREF_USED 0 -nan% 0 -nan% +CORE_EVICTED_MLC_PREF_NOT_USED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CORE_MEM_LATENCY_AVE_DEMAND 73340875 108.3663 73340875 108.3663 + +CORE_MEM_LATENCY_AVE_PREF_USED 8603759 102.7916 8603759 102.7916 + +CORE_MEM_LATENCY_AVE_PREF_NOT_USED 14943958 107.9633 14943958 107.9633 + +DRAM_LATENCY 0 0 + +TOTAL_DRAM_LATENCY 0 0 + +DRAM_CLOSED_PAGE_POLICY_CMD 0 0 + +DRAM_ACTIVATE_STALLING 0 0 + +DRAM_PRECHARGE_STALLING 0 0 + +DRAM_PRECHARGE_STALLING_WAIT_CYCLES 0 0 + +L1_STAY_DEMAND 1158011274045 1711042.4314 1158011274045 1711042.4314 + +L1_STAY_PREF_USED 165455431941 1976743.7897 165455431941 1976743.7897 + +L1_STAY_PREF_NOT_USED 211417385097 1527394.6488 211417385097 1527394.6488 + +TOTAL_DATA_MISS_LATENCY 73879827 73879827 + +TOTAL_DATA_MISS_COUNT 680673 680673 + +CORE_PREF_L1_NOT_USED_LATENCY200 128724 92.997% 128724 92.997% +CORE_PREF_L1_NOT_USED_LATENCY400 6666 4.816% 6666 4.816% +CORE_PREF_L1_NOT_USED_LATENCY600 1320 0.954% 1320 0.954% +CORE_PREF_L1_NOT_USED_LATENCY800 312 0.225% 312 0.225% +CORE_PREF_L1_NOT_USED_LATENCY1000 151 0.109% 151 0.109% +CORE_PREF_L1_NOT_USED_LATENCY1200 268 0.194% 268 0.194% +CORE_PREF_L1_NOT_USED_LATENCY1400 750 0.542% 750 0.542% +CORE_PREF_L1_NOT_USED_LATENCY1600 190 0.137% 190 0.137% +CORE_PREF_L1_NOT_USED_LATENCY1600MORE 36 0.026% 36 0.026% + 138417 100.000% 138417 100.000% + 0.13 0.65 0.13 0.65 + +CORE_PREF_L1_NOT_USED_DISTANCE_1 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_DISTANCE_2 11821 8.540% 11821 8.540% +CORE_PREF_L1_NOT_USED_DISTANCE_4 26357 19.042% 26357 19.042% +CORE_PREF_L1_NOT_USED_DISTANCE_8 56267 40.650% 56267 40.650% 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+PERF_PRED_NUM_STAT_RESETS 0 0 + +PERF_PRED_RESET_STATS_CYCLE 0 0 + +PERF_PRED_CYCLE 99495664 99495664 + +ESTIMATED_ALONE_CYCLES 0 0.0000 0 0.0000 + +NUM_WINDOWS_WITH_DCACHE_MISS 384032 384032 + +LONGEST_DCACHE_MISS_CHAIN 1776047 1776047 + +NUM_DCACHE_MISSES_IN_WINDOW_1 15314 3.988% 15314 3.988% +NUM_DCACHE_MISSES_IN_WINDOW_2 14533 3.784% 14533 3.784% +NUM_DCACHE_MISSES_IN_WINDOW_3 16774 4.368% 16774 4.368% +NUM_DCACHE_MISSES_IN_WINDOW_4 19932 5.190% 19932 5.190% +NUM_DCACHE_MISSES_IN_WINDOW_5 37220 9.692% 37220 9.692% +NUM_DCACHE_MISSES_IN_WINDOW_6 64204 16.718% 64204 16.718% +NUM_DCACHE_MISSES_IN_WINDOW_7 64616 16.826% 64616 16.826% +NUM_DCACHE_MISSES_IN_WINDOW_8 47216 12.295% 47216 12.295% +NUM_DCACHE_MISSES_IN_WINDOW_9 24663 6.422% 24663 6.422% +NUM_DCACHE_MISSES_IN_WINDOW_10 15927 4.147% 15927 4.147% +NUM_DCACHE_MISSES_IN_WINDOW_11 16578 4.317% 16578 4.317% +NUM_DCACHE_MISSES_IN_WINDOW_12 12468 3.247% 12468 3.247% +NUM_DCACHE_MISSES_IN_WINDOW_13 8208 2.137% 8208 2.137% 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-nan -nan + +MEM_REQ_DEMANDS__0 94191253 94.669% 94191253 94.669% +MEM_REQ_DEMANDS__4 5255902 5.283% 5255902 5.283% +MEM_REQ_DEMANDS__8 19285 0.019% 19285 0.019% +MEM_REQ_DEMANDS_12 8609 0.009% 8609 0.009% +MEM_REQ_DEMANDS_16 5228 0.005% 5228 0.005% +MEM_REQ_DEMANDS_20 2455 0.002% 2455 0.002% +MEM_REQ_DEMANDS_24 1290 0.001% 1290 0.001% +MEM_REQ_DEMANDS_28 11642 0.012% 11642 0.012% +MEM_REQ_DEMANDS_32 0 0.000% 0 0.000% +MEM_REQ_DEMANDS_36 0 0.000% 0 0.000% +MEM_REQ_DEMANDS_40 0 0.000% 0 0.000% +MEM_REQ_DEMANDS_44 0 0.000% 0 0.000% +MEM_REQ_DEMANDS_48 0 0.000% 0 0.000% +MEM_REQ_DEMANDS_52 0 0.000% 0 0.000% +MEM_REQ_DEMANDS_56 0 0.000% 0 0.000% +MEM_REQ_DEMANDS_60 0 0.000% 0 0.000% +MEM_REQ_DEMANDS_64 0 0.000% 0 0.000% + 99495664 100.000% 99495664 100.000% + 0.05 0.24 0.05 0.24 + +MEM_REQ_PREFS__0 97674168 98.169% 97674168 98.169% +MEM_REQ_PREFS__4 1313415 1.320% 1313415 1.320% +MEM_REQ_PREFS__8 334176 0.336% 334176 0.336% +MEM_REQ_PREFS_12 97961 0.098% 97961 0.098% +MEM_REQ_PREFS_16 40034 0.040% 40034 0.040% +MEM_REQ_PREFS_20 18173 0.018% 18173 0.018% +MEM_REQ_PREFS_24 15378 0.015% 15378 0.015% +MEM_REQ_PREFS_28 2359 0.002% 2359 0.002% +MEM_REQ_PREFS_32 0 0.000% 0 0.000% +MEM_REQ_PREFS_36 0 0.000% 0 0.000% +MEM_REQ_PREFS_40 0 0.000% 0 0.000% +MEM_REQ_PREFS_44 0 0.000% 0 0.000% +MEM_REQ_PREFS_48 0 0.000% 0 0.000% +MEM_REQ_PREFS_52 0 0.000% 0 0.000% +MEM_REQ_PREFS_56 0 0.000% 0 0.000% +MEM_REQ_PREFS_60 0 0.000% 0 0.000% +MEM_REQ_PREFS_64 0 0.000% 0 0.000% + 99495664 100.000% 99495664 100.000% + 0.03 0.23 0.03 0.23 + +MEM_REQ_WRITEBACKS__0 99486818 99.991% 99486818 99.991% +MEM_REQ_WRITEBACKS__4 8792 0.009% 8792 0.009% +MEM_REQ_WRITEBACKS__8 54 0.000% 54 0.000% +MEM_REQ_WRITEBACKS_12 0 0.000% 0 0.000% +MEM_REQ_WRITEBACKS_16 0 0.000% 0 0.000% +MEM_REQ_WRITEBACKS_20 0 0.000% 0 0.000% +MEM_REQ_WRITEBACKS_24 0 0.000% 0 0.000% +MEM_REQ_WRITEBACKS_28 0 0.000% 0 0.000% +MEM_REQ_WRITEBACKS_32 0 0.000% 0 0.000% +MEM_REQ_WRITEBACKS_36 0 0.000% 0 0.000% +MEM_REQ_WRITEBACKS_40 0 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b/labs/LAB5/runs/xalancbmk_s_base-sms0/power.stat.0.out @@ -0,0 +1,184 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 99495664 Instructions: 100000000 IPC: 1.00507 + +POWER_STATS_BEGIN 0 0 + +POWER_TIME 31092395000000 31092395000000 + +POWER_CYCLE 99495664 99495664 + +POWER_ITLB_ACCESS 37311449 37311449 + +POWER_DTLB_ACCESS 7518274 7518274 + +POWER_ICACHE_ACCESS 37311449 37311449 + +POWER_ICACHE_MISS 720333 720333 + +POWER_BTB_READ 37311449 37311449 + +POWER_BTB_WRITE 431991 431991 + +POWER_ROB_READ 122678470 122678470 + +POWER_ROB_WRITE 122678470 122678470 + +POWER_RENAME_READ 245356940 245356940 + +POWER_RENAME_WRITE 122678470 122678470 + +POWER_FP_RENAME_READ 0 0 + +POWER_FP_RENAME_WRITE 0 0 + +POWER_FUNCTION_CALL 1375050 1375050 + +POWER_INST_WINDOW_READ 122678470 122678470 + +POWER_INST_WINDOW_WRITE 122678470 122678470 + +POWER_INT_REGFILE_READ 138776099 138776099 + +POWER_INT_REGFILE_WRITE 102427755 102427755 + +POWER_IALU_ACCESS 122505366 122505366 + +POWER_CDB_IALU_ACCESS 122505366 122505366 + +POWER_MUL_ACCESS 173104 173104 + +POWER_CDB_MUL_ACCESS 173104 173104 + +POWER_FP_INST_WINDOW_WRITE 0 0 + +POWER_FP_INST_WINDOW_READ 0 0 + +POWER_FP_REGFILE_READ 0 0 + +POWER_FP_REGFILE_WRITE 0 0 + +POWER_FPU_ACCESS 0 0 + +POWER_CDB_FPU_ACCESS 0 0 + +POWER_DCACHE_READ_ACCESS 28884559 28884559 + +POWER_DCACHE_WRITE_ACCESS 7526468 7526468 + +POWER_DCACHE_READ_MISS 6334529 6334529 + +POWER_DCACHE_WRITE_MISS 607011 607011 + +POWER_MLC_READ_ACCESS 0 0 + +POWER_MLC_WRITE_ACCESS 0 0 + +POWER_MLC_READ_MISS 0 0 + +POWER_MLC_WRITE_MISS 0 0 + +POWER_LLC_READ_ACCESS 3321957 3321957 + +POWER_LLC_WRITE_ACCESS 265168 265168 + +POWER_LLC_READ_MISS 914973 914973 + +POWER_LLC_WRITE_MISS 316 316 + +POWER_MEMORY_ACCESS 0 0 + +POWER_MEMORY_READ_ACCESS 0 0 + +POWER_MEMORY_WRITE_ACCESS 0 0 + +POWER_INST_WINDOW_WAKEUP_ACCESS 122678470 122678470 + +POWER_FP_INST_WINDOW_WAKEUP_ACCESS 0 0 + +POWER_L1DIREC_READ_ACCESS 0 0 + +POWER_L1DIREC_WRITE_ACCESS 0 0 + +POWER_L1DIREC_READ_MISS 0 0 + +POWER_L1DIREC_WRITE_MISS 0 0 + +POWER_L2DIREC_READ_ACCESS 0 0 + +POWER_L2DIREC_WRITE_ACCESS 0 0 + +POWER_L2DIREC_READ_MISS 0 0 + +POWER_L2DIREC_WRITE_MISS 0 0 + +POWER_MEMORY_CTRL_ACCESS 951475 951475 + +POWER_MEMORY_CTRL_READ 914973 914973 + +POWER_MEMORY_CTRL_WRITE 36502 36502 + +POWER_OP 122678470 122678470 + +POWER_INT_OP 120331793 120331793 + +POWER_FP_OP 152184 152184 + +POWER_LD_OP 28876438 28876438 + +POWER_ST_OP 7518274 7518274 + +POWER_BRANCH_MISPREDICT 431991 431991 + +POWER_COMMITTED_OP 122678470 122678470 + +POWER_COMMITTED_INT_OP 120331793 120331793 + +POWER_COMMITTED_FP_OP 2346677 2346677 + +POWER_BRANCH_OP 25707245 25707245 + +POWER_DRAM_PRECHARGE 207813 207813 + +POWER_DRAM_ACTIVATE 256691 256691 + +POWER_DRAM_READ 913949 913949 + +POWER_DRAM_WRITE 36497 36497 + +POWER_STATS_END 0 0 + +ENERGY 0.000000 0.000000 + +ENERGY_CORE 0.000000 0.000000 + +ENERGY_UNCORE 0.000000 0.000000 + +ENERGY_MEMORY 0.000000 0.000000 + +ENERGY_OTHER 0.000000 0.000000 + +ENERGY_CORE_STATIC 0.000000 0.000000 + +ENERGY_CORE_DYNAMIC 0.000000 0.000000 + +ENERGY_UNCORE_STATIC 0.000000 0.000000 + +ENERGY_UNCORE_DYNAMIC 0.000000 0.000000 + +ENERGY_MEMORY_STATIC 0.000000 0.000000 + +ENERGY_MEMORY_DYNAMIC 0.000000 0.000000 + +ENERGY_OTHER_STATIC 0.000000 0.000000 + +ENERGY_OTHER_DYNAMIC 0.000000 0.000000 + +TIME 0.000000 0.000000 + +ENERGY_STATS_END 0 0 + + + diff --git a/labs/LAB5/runs/xalancbmk_s_base-sms0/pref.stat.0.out b/labs/LAB5/runs/xalancbmk_s_base-sms0/pref.stat.0.out new file mode 100644 index 00000000..7e4c3462 --- /dev/null +++ b/labs/LAB5/runs/xalancbmk_s_base-sms0/pref.stat.0.out @@ -0,0 +1,208 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 99495664 Instructions: 100000000 IPC: 1.00507 + +PREF_DL0REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UMLC_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UL1REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_DL0REQ_QUEUE_FULL 0 0 + +PREF_UMLC_REQ_QUEUE_FULL 0 0 + +PREF_UL1REQ_QUEUE_FULL 0 0 + +PREF_DC_HIT_NOSEND 0 0 + +PREF_WBQDC_HIT_NOSEND 0 0 + +PREF_MLCQ_STALL 0 0 + +PREF_L1Q_STALL 0 0 + +PREF_UMLC_REQ_SEND_QUEUE_STALL 0 0 + +PREF_UL1REQ_SEND_QUEUE_STALL 20623 20623 + +PREF_UMLC_REQ_QUEUE_SENTREQ 0 0 + +PREF_UL1REQ_QUEUE_SENTREQ 368011 368011 + +PREF_NEWREQ_MATCHED 19721 19721 + +PREF_UMLC_REQ_QUEUE_MATCHED_REQ 0 0 + +PREF_UL1REQ_QUEUE_MATCHED_REQ 3540 3540 + +PREF_DL0REQ_QUEUE_MATCHED_REQ 0 0 + +L1_PREF_HIT 231140 231140 + +L1_PREF_UNIQUE_HIT 69299 69299 + +L1_PREF_LATE 16896 16896 + +L1_LATE_PREF_CYCLES 1072621 1072621 + +L1_LATE_PREF_CYCLES_DIST_0 14686 86.920% 14686 86.920% +L1_LATE_PREF_CYCLES_DIST_100 1784 10.559% 1784 10.559% +L1_LATE_PREF_CYCLES_DIST_200 188 1.113% 188 1.113% +L1_LATE_PREF_CYCLES_DIST_300 97 0.574% 97 0.574% +L1_LATE_PREF_CYCLES_DIST_400 29 0.172% 29 0.172% +L1_LATE_PREF_CYCLES_DIST_500 16 0.095% 16 0.095% +L1_LATE_PREF_CYCLES_DIST_600 7 0.041% 7 0.041% +L1_LATE_PREF_CYCLES_DIST_700 2 0.012% 2 0.012% +L1_LATE_PREF_CYCLES_DIST_800 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_900 12 0.071% 12 0.071% +L1_LATE_PREF_CYCLES_DIST_1000 13 0.077% 13 0.077% +L1_LATE_PREF_CYCLES_DIST_1100 18 0.107% 18 0.107% +L1_LATE_PREF_CYCLES_DIST_1200 37 0.219% 37 0.219% +L1_LATE_PREF_CYCLES_DIST_1300 4 0.024% 4 0.024% +L1_LATE_PREF_CYCLES_DIST_1400 3 0.018% 3 0.018% +L1_LATE_PREF_CYCLES_DIST_1500 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1600 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1700 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1800 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1900 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_2000 0 0.000% 0 0.000% + 16896 100.000% 16896 100.000% + 0.22 0.92 0.22 0.92 + +MLC_PREF_HIT 0 0 + +MLC_PREF_UNIQUE_HIT 0 0 + +MLC_PREF_LATE 0 0 + +PREF_HYBRID_SEL_0 0 -nan% 0 -nan% +PREF_HYBRID_SEL_1 0 -nan% 0 -nan% +PREF_HYBRID_SEL_2 0 -nan% 0 -nan% +PREF_HYBRID_SEL_3 0 -nan% 0 -nan% +PREF_HYBRID_SEL_4 0 -nan% 0 -nan% +PREF_HYBRID_SEL_5 0 -nan% 0 -nan% +PREF_HYBRID_SEL_6 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_DISTANCE_1 43 39.450% 43 39.450% +PREF_DISTANCE_2 35 32.110% 35 32.110% +PREF_DISTANCE_3 24 22.018% 24 22.018% +PREF_DISTANCE_4 7 6.422% 7 6.422% +PREF_DISTANCE_5 0 0.000% 0 0.000% +PREF_DISTANCE_6 0 0.000% 0 0.000% +PREF_DISTANCE_7 0 0.000% 0 0.000% +PREF_DISTANCE_8 0 0.000% 0 0.000% +PREF_DISTANCE_9 0 0.000% 0 0.000% +PREF_DISTANCE_10 0 0.000% 0 0.000% + 109 100.000% 109 100.000% + 0.95 0.72 0.95 0.72 + +PREF_REPL_MRU 0 -nan% 0 -nan% +PREF_REPL_MID 0 -nan% 0 -nan% +PREF_REPL_LOWQTR 0 -nan% 0 -nan% +PREF_REPL_LRU 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_REPL_MOVEDOWN 0 -nan% 0 -nan% +PREF_REPL_MOVEUP 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_COV_1 0 -nan% 0 -nan% +PREF_COV_2 0 -nan% 0 -nan% +PREF_COV_3 0 -nan% 0 -nan% +PREF_COV_4 0 -nan% 0 -nan% +PREF_COV_5 0 -nan% 0 -nan% +PREF_COV_6 0 -nan% 0 -nan% +PREF_COV_7 0 -nan% 0 -nan% +PREF_COV_8 0 -nan% 0 -nan% +PREF_COV_9 0 -nan% 0 -nan% +PREF_COV_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_POL_1 0 0.000% 0 0.000% +PREF_POL_2 0 0.000% 0 0.000% +PREF_POL_3 0 0.000% 0 0.000% +PREF_POL_4 0 0.000% 0 0.000% +PREF_POL_5 0 0.000% 0 0.000% +PREF_POL_6 0 0.000% 0 0.000% +PREF_POL_7 0 0.000% 0 0.000% +PREF_POL_8 0 0.000% 0 0.000% +PREF_POL_9 0 0.000% 0 0.000% +PREF_POL_10 109 100.000% 109 100.000% + 109 100.000% 109 100.000% + 9.00 9.04 9.00 9.04 + +PREF_ACC_1 0 0.000% 0 0.000% +PREF_ACC_2 0 0.000% 0 0.000% +PREF_ACC_3 0 0.000% 0 0.000% +PREF_ACC_4 0 0.000% 0 0.000% +PREF_ACC_5 10 9.174% 10 9.174% +PREF_ACC_6 31 28.440% 31 28.440% +PREF_ACC_7 59 54.128% 59 54.128% +PREF_ACC_8 9 8.257% 9 8.257% +PREF_ACC_9 0 0.000% 0 0.000% +PREF_ACC_10 0 0.000% 0 0.000% + 109 100.000% 109 100.000% + 5.61 0.77 5.61 0.77 + +PREF_TIMELY_1 0 0.000% 0 0.000% +PREF_TIMELY_2 0 0.000% 0 0.000% +PREF_TIMELY_3 0 0.000% 0 0.000% +PREF_TIMELY_4 0 0.000% 0 0.000% +PREF_TIMELY_5 0 0.000% 0 0.000% +PREF_TIMELY_6 0 0.000% 0 0.000% +PREF_TIMELY_7 0 0.000% 0 0.000% +PREF_TIMELY_8 57 52.294% 57 52.294% +PREF_TIMELY_9 49 44.954% 49 44.954% +PREF_TIMELY_10 3 2.752% 3 2.752% + 109 100.000% 109 100.000% + 7.50 1.37 7.50 1.37 + +PREF_UNUSED_EVICT 138417 138417 + +PREF_REGION_SENT 0 0 + +PREF_REGION_USEFUL 0 0 + +PREF_REGION_EVICT 0 0 + +PREF_PFPOL 0 0 + +PREF_PHASE_NEWPHASE_DET 0 0 + +PREF_PHASE_NEWPHASE_NOTVALID 0 0 + +PREF_PHASE_SENTPREF 0 0 + +PREF_PHASE_OVERWRITE_PAGE 0 0 + +PREF_UPDATE_COUNT 109 109 + +PREF_ACC1_HT_HP 0 0.000% 0 0.000% +PREF_ACC1_HT_LP 0 0.000% 0 0.000% +PREF_ACC1_LT_HP 0 0.000% 0 0.000% +PREF_ACC1_LT_LP 0 0.000% 0 0.000% +PREF_ACC2_HT_HP 0 0.000% 0 0.000% +PREF_ACC2_HT_LP 0 0.000% 0 0.000% +PREF_ACC2_LT_HP 0 0.000% 0 0.000% +PREF_ACC2_LT_LP 41 37.615% 41 37.615% +PREF_ACC3_HT_HP 0 0.000% 0 0.000% +PREF_ACC3_HT_LP 0 0.000% 0 0.000% +PREF_ACC3_LT_HP 0 0.000% 0 0.000% +PREF_ACC3_LT_LP 0 0.000% 0 0.000% +PREF_ACC4_HT_HP 0 0.000% 0 0.000% +PREF_ACC4_HT_LP 0 0.000% 0 0.000% +PREF_ACC4_LT_HP 0 0.000% 0 0.000% +PREF_ACC4_LT_LP 68 62.385% 68 62.385% + 109 100.000% 109 100.000% + 11.99 10.28 11.99 10.28 + + + diff --git a/labs/LAB5/runs/xalancbmk_s_base-sms0/ramulator.stat.out b/labs/LAB5/runs/xalancbmk_s_base-sms0/ramulator.stat.out new file mode 100644 index 00000000..1d7e183c --- /dev/null +++ b/labs/LAB5/runs/xalancbmk_s_base-sms0/ramulator.stat.out @@ -0,0 +1,150 @@ + ramulator.active_cycles_0 23913117 # Total active cycles for level _0 + ramulator.busy_cycles_0 23913117 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0 + ramulator.serving_requests_0 41709667 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.average_serving_requests_0 1.117895 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.active_cycles_0_0 23913117 # Total active cycles for level _0_0 + ramulator.busy_cycles_0_0 24884577 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0 + ramulator.serving_requests_0_0 41709667 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.average_serving_requests_0_0 1.117895 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.active_cycles_0_0_0 7363395 # Total active cycles for level _0_0_0 + ramulator.busy_cycles_0_0_0 7363395 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0 + ramulator.serving_requests_0_0_0 9316991 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 +ramulator.average_serving_requests_0_0_0 0.249712 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 + ramulator.active_cycles_0_0_0_0 1781818 # Total active cycles for level _0_0_0_0 + ramulator.busy_cycles_0_0_0_0 1781818 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_0 + ramulator.serving_requests_0_0_0_0 2065605 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 +ramulator.average_serving_requests_0_0_0_0 0.055362 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 + ramulator.active_cycles_0_0_0_1 2807535 # Total active cycles for level _0_0_0_1 + ramulator.busy_cycles_0_0_0_1 2807535 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_1 + ramulator.serving_requests_0_0_0_1 3228424 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 +ramulator.average_serving_requests_0_0_0_1 0.086528 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 + ramulator.active_cycles_0_0_0_2 1941937 # Total active cycles for level _0_0_0_2 + ramulator.busy_cycles_0_0_0_2 1941937 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_2 + ramulator.serving_requests_0_0_0_2 2286753 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 +ramulator.average_serving_requests_0_0_0_2 0.061289 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 + ramulator.active_cycles_0_0_0_3 1454008 # Total active cycles for level _0_0_0_3 + ramulator.busy_cycles_0_0_0_3 1454008 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_3 + ramulator.serving_requests_0_0_0_3 1736209 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 +ramulator.average_serving_requests_0_0_0_3 0.046534 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 + ramulator.active_cycles_0_0_1 8351344 # Total active cycles for level _0_0_1 + ramulator.busy_cycles_0_0_1 8351344 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1 + ramulator.serving_requests_0_0_1 10671013 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 +ramulator.average_serving_requests_0_0_1 0.286003 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 + ramulator.active_cycles_0_0_1_0 2207064 # Total active cycles for level _0_0_1_0 + ramulator.busy_cycles_0_0_1_0 2207064 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_0 + ramulator.serving_requests_0_0_1_0 2565844 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 +ramulator.average_serving_requests_0_0_1_0 0.068769 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 + ramulator.active_cycles_0_0_1_1 2391610 # Total active cycles for level _0_0_1_1 + ramulator.busy_cycles_0_0_1_1 2391610 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_1 + ramulator.serving_requests_0_0_1_1 2738079 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 +ramulator.average_serving_requests_0_0_1_1 0.073386 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 + ramulator.active_cycles_0_0_1_2 2631364 # Total active cycles for level _0_0_1_2 + ramulator.busy_cycles_0_0_1_2 2631364 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_2 + ramulator.serving_requests_0_0_1_2 2944330 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 +ramulator.average_serving_requests_0_0_1_2 0.078913 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 + ramulator.active_cycles_0_0_1_3 2058463 # Total active cycles for level _0_0_1_3 + ramulator.busy_cycles_0_0_1_3 2058463 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_3 + ramulator.serving_requests_0_0_1_3 2422760 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 +ramulator.average_serving_requests_0_0_1_3 0.064934 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 + ramulator.active_cycles_0_0_2 8569361 # Total active cycles for level _0_0_2 + ramulator.busy_cycles_0_0_2 8569361 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2 + ramulator.serving_requests_0_0_2 10864525 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 +ramulator.average_serving_requests_0_0_2 0.291189 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 + ramulator.active_cycles_0_0_2_0 1905683 # Total active cycles for level _0_0_2_0 + ramulator.busy_cycles_0_0_2_0 1905683 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_0 + ramulator.serving_requests_0_0_2_0 2174011 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 +ramulator.average_serving_requests_0_0_2_0 0.058267 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 + ramulator.active_cycles_0_0_2_1 2929103 # Total active cycles for level _0_0_2_1 + ramulator.busy_cycles_0_0_2_1 2929103 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_1 + ramulator.serving_requests_0_0_2_1 3278148 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 +ramulator.average_serving_requests_0_0_2_1 0.087860 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 + ramulator.active_cycles_0_0_2_2 1824409 # Total active cycles for level _0_0_2_2 + ramulator.busy_cycles_0_0_2_2 1824409 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_2 + ramulator.serving_requests_0_0_2_2 2069362 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 +ramulator.average_serving_requests_0_0_2_2 0.055463 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 + ramulator.active_cycles_0_0_2_3 2926354 # Total active cycles for level _0_0_2_3 + ramulator.busy_cycles_0_0_2_3 2926354 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_3 + ramulator.serving_requests_0_0_2_3 3343004 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 +ramulator.average_serving_requests_0_0_2_3 0.089599 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 + ramulator.active_cycles_0_0_3 8633093 # Total active cycles for level _0_0_3 + ramulator.busy_cycles_0_0_3 8633093 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3 + ramulator.serving_requests_0_0_3 10856398 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 +ramulator.average_serving_requests_0_0_3 0.290971 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 + ramulator.active_cycles_0_0_3_0 2421107 # Total active cycles for level _0_0_3_0 + ramulator.busy_cycles_0_0_3_0 2421107 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_0 + ramulator.serving_requests_0_0_3_0 2778574 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 +ramulator.average_serving_requests_0_0_3_0 0.074471 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 + ramulator.active_cycles_0_0_3_1 1313825 # Total active cycles for level _0_0_3_1 + ramulator.busy_cycles_0_0_3_1 1313825 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_1 + ramulator.serving_requests_0_0_3_1 1571863 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 +ramulator.average_serving_requests_0_0_3_1 0.042129 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 + ramulator.active_cycles_0_0_3_2 3403729 # Total active cycles for level _0_0_3_2 + ramulator.busy_cycles_0_0_3_2 3403729 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_2 + ramulator.serving_requests_0_0_3_2 3872777 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 +ramulator.average_serving_requests_0_0_3_2 0.103798 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 + ramulator.active_cycles_0_0_3_3 2259234 # Total active cycles for level _0_0_3_3 + ramulator.busy_cycles_0_0_3_3 2259234 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_3 + ramulator.serving_requests_0_0_3_3 2621782 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 +ramulator.average_serving_requests_0_0_3_3 0.070269 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 + ramulator.read_transaction_bytes_0 58492736 # The total byte of read transaction per channel + ramulator.write_transaction_bytes_0 2335872 # The total byte of write transaction per channel + ramulator.row_hits_channel_0_core 693760 # Number of row hits per channel per core + ramulator.row_misses_channel_0_core 53726 # Number of row misses per channel per core + ramulator.row_conflicts_channel_0_core 202961 # Number of row conflicts per channel per core + ramulator.read_row_hits_channel_0_core 676206 # Number of row hits for read requests per channel per core + [0] 676206.0 # +ramulator.read_row_misses_channel_0_core 50175 # Number of row misses for read requests per channel per core + [0] 50175.0 # +ramulator.read_row_conflicts_channel_0_core 187568 # Number of row conflicts for read requests per channel per core + [0] 187568.0 # + ramulator.write_row_hits_channel_0_core 17554 # Number of row hits for write requests per channel per core + [0] 17554.0 # +ramulator.write_row_misses_channel_0_core 3551 # Number of row misses for write requests per channel per core + [0] 3551.0 # +ramulator.write_row_conflicts_channel_0_core 15393 # Number of row conflicts for write requests per channel per core + [0] 15393.0 # + ramulator.useless_activates_0_core 8 # Number of useless activations. E.g, ACT -> PRE w/o RD or WR + ramulator.read_latency_avg_0 40.759840 # The average memory latency cycles (in memory time domain) per request for all read requests in this channel + ramulator.read_latency_sum_0 37294153 # The memory latency cycles (in memory time domain) sum for all read requests in this channel + ramulator.req_queue_length_avg_0 15.288103 # Average of read and write queue length per memory cycle per channel. + ramulator.req_queue_length_sum_0 570412716 # Sum of read and write queue length per memory cycle per channel. + ramulator.read_req_queue_length_avg_0 0.897305 # Read queue length average per memory cycle per channel. + ramulator.read_req_queue_length_sum_0 33479232 # Read queue length sum per memory cycle per channel. + ramulator.write_req_queue_length_avg_0 14.390799 # Write queue length average per memory cycle per channel. + ramulator.write_req_queue_length_sum_0 536933484 # Write queue length sum per memory cycle per channel. + ramulator.record_read_hits 0.0 # record read hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_misses 0.0 # record_read_miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_conflicts 0.0 # record read conflict count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_hits 0.0 # record write hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_misses 0.0 # record write miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_conflicts 0.0 # record write conflict for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.dram_capacity 8589934592 # Number of bytes in simulated DRAM + ramulator.dram_cycles 37310888 # Number of DRAM cycles simulated + ramulator.incoming_requests 951475 # Number of incoming requests to DRAM + ramulator.read_requests 914973 # Number of incoming read requests to DRAM per core + [0] 914973.0 # + ramulator.write_requests 36502 # Number of incoming write requests to DRAM per core + [0] 36502.0 # + ramulator.ramulator_active_cycles 23913177 # The total number of cycles that the DRAM part is active (serving R/W) + ramulator.incoming_requests_per_channel 951475.0 # Number of incoming requests to each DRAM channel + [0] 951475.0 # +ramulator.incoming_read_reqs_per_channel 914973.0 # Number of incoming read requests to each DRAM channel + [0] 914973.0 # + ramulator.physical_page_replacement 0 # The number of times that physical page replacement happens. + ramulator.maximum_bandwidth 19200000000 # The theoretical maximum bandwidth (Bps) + ramulator.in_queue_req_num_sum 570412716 # Sum of read/write queue length + ramulator.in_queue_read_req_num_sum 33479232 # Sum of read queue length + ramulator.in_queue_write_req_num_sum 536933484 # Sum of write queue length + ramulator.in_queue_req_num_avg 15.288103 # Average of read/write queue length per memory cycle + ramulator.in_queue_read_req_num_avg 0.897305 # Average of read queue length per memory cycle + ramulator.in_queue_write_req_num_avg 14.390799 # Average of write queue length per memory cycle + ramulator.record_read_requests 0.0 # record read requests for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_requests 0.0 # record write requests for this core when it reaches request limit or to the end + [0] 0.0 # diff --git a/labs/LAB5/runs/xalancbmk_s_base-sms0/run.err b/labs/LAB5/runs/xalancbmk_s_base-sms0/run.err new file mode 100644 index 00000000..e69de29b diff --git a/labs/LAB5/runs/xalancbmk_s_base-sms0/run.out b/labs/LAB5/runs/xalancbmk_s_base-sms0/run.out new file mode 100644 index 00000000..22494acc --- /dev/null +++ b/labs/LAB5/runs/xalancbmk_s_base-sms0/run.out @@ -0,0 +1,107 @@ +Scarab gitrev: 7ab9e17 +Scarab started at Sun Jun 11 08:08:38 2023 + +Initialized Ramulator. +** Heartbeat: 1% -- { 1000005 } -- 0.00 KIPS (333.33 KIPS) +** Heartbeat: 2% -- { 2000007 } -- 500.00 KIPS (400.00 KIPS) +** Heartbeat: 3% -- { 3000007 } -- 500.00 KIPS (428.57 KIPS) +** Heartbeat: 4% -- { 4000009 } -- 500.00 KIPS (444.45 KIPS) +** Heartbeat: 5% -- { 5000009 } -- 333.33 KIPS (416.67 KIPS) +** Heartbeat: 6% -- { 6000010 } -- 500.00 KIPS (428.57 KIPS) +** Heartbeat: 7% -- { 7000015 } -- 500.00 KIPS (437.50 KIPS) +** Heartbeat: 8% -- { 8000018 } -- 500.00 KIPS (444.45 KIPS) +** Heartbeat: 9% -- { 9000018 } -- 500.00 KIPS (450.00 KIPS) +** Heartbeat: 10% -- { 10000021 } -- 333.33 KIPS (434.78 KIPS) +** Heartbeat: 11% -- { 11000022 } -- 500.00 KIPS (440.00 KIPS) +** Heartbeat: 12% -- { 12000022 } -- 500.00 KIPS (444.45 KIPS) +** Heartbeat: 13% -- { 13000026 } -- 500.00 KIPS (448.28 KIPS) +** Heartbeat: 14% -- { 14000028 } -- 500.00 KIPS (451.61 KIPS) +** Heartbeat: 15% -- { 15000028 } -- 500.00 KIPS (454.55 KIPS) +** Heartbeat: 16% -- { 16000030 } -- 500.00 KIPS (457.14 KIPS) +** Heartbeat: 17% -- { 17000034 } -- 333.33 KIPS (447.37 KIPS) +** Heartbeat: 18% -- { 18000039 } -- 500.00 KIPS (450.00 KIPS) +** Heartbeat: 19% -- { 19000043 } -- 500.00 KIPS (452.38 KIPS) +** Heartbeat: 20% -- { 20000043 } -- 500.00 KIPS (454.55 KIPS) +** Heartbeat: 21% -- { 21000043 } -- 333.33 KIPS (446.81 KIPS) +** Heartbeat: 22% -- { 22000043 } -- 500.00 KIPS (448.98 KIPS) +** Heartbeat: 23% -- { 23000045 } -- 500.00 KIPS (450.98 KIPS) +** Heartbeat: 24% -- { 24000045 } -- 500.00 KIPS (452.83 KIPS) +** Heartbeat: 25% -- { 25000047 } -- 500.00 KIPS (454.55 KIPS) +** Heartbeat: 26% -- { 26000049 } -- 500.00 KIPS (456.14 KIPS) +** Heartbeat: 27% -- { 27000052 } -- 500.00 KIPS (457.63 KIPS) +** Heartbeat: 28% -- { 28000052 } -- 333.33 KIPS (451.61 KIPS) +** Heartbeat: 29% -- { 29000054 } -- 500.00 KIPS (453.13 KIPS) +** Heartbeat: 30% -- { 30000054 } -- 500.00 KIPS (454.55 KIPS) +** Heartbeat: 31% -- { 31000055 } -- 500.00 KIPS (455.88 KIPS) +** Heartbeat: 32% -- { 32000058 } -- 500.00 KIPS (457.14 KIPS) +** Heartbeat: 33% -- { 33000059 } -- 333.33 KIPS (452.06 KIPS) +** Heartbeat: 34% -- { 34000061 } -- 500.00 KIPS (453.33 KIPS) +** Heartbeat: 35% -- { 35000061 } -- 500.00 KIPS (454.55 KIPS) +** Heartbeat: 36% -- { 36000061 } -- 500.00 KIPS (455.70 KIPS) +** Heartbeat: 37% -- { 37000063 } -- 500.00 KIPS (456.79 KIPS) +** Heartbeat: 38% -- { 38000063 } -- 500.00 KIPS (457.83 KIPS) +** Heartbeat: 39% -- { 39000064 } -- 333.33 KIPS (453.49 KIPS) +** Heartbeat: 40% -- { 40000065 } -- 500.00 KIPS (454.55 KIPS) +** Heartbeat: 41% -- { 41000065 } -- 500.00 KIPS (455.56 KIPS) +** Heartbeat: 42% -- { 42000066 } -- 333.33 KIPS (451.61 KIPS) +** Heartbeat: 43% -- { 43000071 } -- 500.00 KIPS (452.63 KIPS) +** Heartbeat: 44% -- { 44000071 } -- 500.00 KIPS (453.61 KIPS) +** Heartbeat: 45% -- { 45000075 } -- 500.00 KIPS (454.55 KIPS) +** Heartbeat: 46% -- { 46000079 } -- 500.00 KIPS (455.45 KIPS) +** Heartbeat: 47% -- { 47000079 } -- 333.33 KIPS (451.92 KIPS) +** Heartbeat: 48% -- { 48000082 } -- 500.00 KIPS (452.83 KIPS) +** Heartbeat: 49% -- { 49000082 } -- 500.00 KIPS (453.70 KIPS) +** Heartbeat: 50% -- { 50000082 } -- 500.00 KIPS (454.55 KIPS) +** Heartbeat: 51% -- { 51000082 } -- 500.00 KIPS (455.36 KIPS) +** Heartbeat: 52% -- { 52000082 } -- 333.33 KIPS (452.17 KIPS) +** Heartbeat: 53% -- { 53000085 } -- 500.00 KIPS (452.99 KIPS) +** Heartbeat: 54% -- { 54000087 } -- 500.00 KIPS (453.78 KIPS) +** Heartbeat: 55% -- { 55000090 } -- 500.00 KIPS (454.55 KIPS) +** Heartbeat: 56% -- { 56000090 } -- 500.00 KIPS (455.29 KIPS) +** Heartbeat: 57% -- { 57000095 } -- 333.33 KIPS (452.38 KIPS) +** Heartbeat: 58% -- { 58000099 } -- 500.00 KIPS (453.13 KIPS) +** Heartbeat: 59% -- { 59000099 } -- 500.00 KIPS (453.85 KIPS) +** Heartbeat: 60% -- { 60000100 } -- 500.00 KIPS (454.55 KIPS) +** Heartbeat: 61% -- { 61000104 } -- 500.00 KIPS (455.22 KIPS) +** Heartbeat: 62% -- { 62000108 } -- 333.33 KIPS (452.56 KIPS) +** Heartbeat: 63% -- { 63000109 } -- 500.00 KIPS (453.24 KIPS) +** Heartbeat: 64% -- { 64000114 } -- 500.00 KIPS (453.90 KIPS) +** Heartbeat: 65% -- { 65000117 } -- 500.00 KIPS (454.55 KIPS) +** Heartbeat: 66% -- { 66000117 } -- 333.33 KIPS (452.06 KIPS) +** Heartbeat: 67% -- { 67000121 } -- 500.00 KIPS (452.70 KIPS) +** Heartbeat: 68% -- { 68000121 } -- 500.00 KIPS (453.33 KIPS) +** Heartbeat: 69% -- { 69000125 } -- 500.00 KIPS (453.95 KIPS) +** Heartbeat: 70% -- { 70000129 } -- 500.00 KIPS (454.55 KIPS) +** Heartbeat: 71% -- { 71000129 } -- 500.00 KIPS (455.13 KIPS) +** Heartbeat: 72% -- { 72000132 } -- 333.33 KIPS (452.83 KIPS) +** Heartbeat: 73% -- { 73000132 } -- 500.00 KIPS (453.42 KIPS) +** Heartbeat: 74% -- { 74000133 } -- 500.00 KIPS (453.99 KIPS) +** Heartbeat: 75% -- { 75000135 } -- 500.00 KIPS (454.55 KIPS) +** Heartbeat: 76% -- { 76000140 } -- 500.00 KIPS (455.09 KIPS) +** Heartbeat: 77% -- { 77000144 } -- 333.33 KIPS (452.94 KIPS) +** Heartbeat: 78% -- { 78000147 } -- 500.00 KIPS (453.49 KIPS) +** Heartbeat: 79% -- { 79000150 } -- 500.00 KIPS (454.02 KIPS) +** Heartbeat: 80% -- { 80000153 } -- 500.00 KIPS (454.55 KIPS) +** Heartbeat: 81% -- { 81000156 } -- 500.00 KIPS (455.06 KIPS) +** Heartbeat: 82% -- { 82000158 } -- 500.00 KIPS (455.56 KIPS) +** Heartbeat: 83% -- { 83000161 } -- 333.33 KIPS (453.55 KIPS) +** Heartbeat: 84% -- { 84000165 } -- 500.00 KIPS (454.05 KIPS) +** Heartbeat: 85% -- { 85000165 } -- 500.00 KIPS (454.55 KIPS) +** Heartbeat: 86% -- { 86000165 } -- 500.00 KIPS (455.03 KIPS) +** Heartbeat: 87% -- { 87000169 } -- 333.33 KIPS (453.13 KIPS) +** Heartbeat: 88% -- { 88000173 } -- 500.00 KIPS (453.61 KIPS) +** Heartbeat: 89% -- { 89000177 } -- 500.00 KIPS (454.08 KIPS) +** Heartbeat: 90% -- { 90000178 } -- 500.00 KIPS (454.55 KIPS) +** Heartbeat: 91% -- { 91000178 } -- 500.00 KIPS (455.00 KIPS) +** Heartbeat: 92% -- { 92000179 } -- 500.00 KIPS (455.45 KIPS) +** Heartbeat: 93% -- { 93000179 } -- 333.33 KIPS (453.66 KIPS) +** Heartbeat: 94% -- { 94000181 } -- 500.00 KIPS (454.11 KIPS) +** Heartbeat: 95% -- { 95000182 } -- 500.00 KIPS (454.55 KIPS) +** Heartbeat: 96% -- { 96000185 } -- 500.00 KIPS (454.98 KIPS) +** Heartbeat: 97% -- { 97000188 } -- 333.33 KIPS (453.27 KIPS) +** Heartbeat: 98% -- { 98000191 } -- 500.00 KIPS (453.70 KIPS) +** Heartbeat: 99% -- { 99000192 } -- 500.00 KIPS (454.13 KIPS) +** Core 0 Finished: insts:100000000 cycles:99495664 time:31092395000000 -- 1.01 IPC (1.01 IPC) -- N/A KIPS (454.55 KIPS) +done +Scarab finished at Sun Jun 11 08:12:18 2023 + diff --git a/labs/LAB5/runs/xalancbmk_s_base-sms0/stream.stat.0.out b/labs/LAB5/runs/xalancbmk_s_base-sms0/stream.stat.0.out new file mode 100644 index 00000000..f4e19eb2 --- /dev/null +++ b/labs/LAB5/runs/xalancbmk_s_base-sms0/stream.stat.0.out @@ -0,0 +1,188 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 99495664 Instructions: 100000000 IPC: 1.00507 + +DCACHE_PREF_HIT 0 0 + +IFETCH_WB_FIRST_SCHEDULE 0 -nan% 0 -nan% +PREFETCH_LAST_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_PREF_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_LOW_OP_SCHEDULE 0 -nan% 0 -nan% +DEMAND_LAST_SCHEDULE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +SEND_MISS_REQ_QUEUE 914973 914973 + +L1_DATA_EVICT 898905 898905 + +STREAM_BUFFER_REQ 0 0 + +PREF_SEND_TO_MEM_REQ 0 -nan% 0 -nan% +PREF_SEND_TO_MEM_REQ_FAIL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +HIT_TRAIN_STREAM 296720 30.457% 296720 30.457% +MISS_TRAIN_STREAM 677502 69.543% 677502 69.543% + 974222 100.000% 974222 100.000% + 0.70 0.63 0.70 0.63 + +STREAM_TRAIN_CREATE 243237 243237 + +MEM_REQ_MISS_HWP_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_SW_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_IFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DSTORE_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DPRF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_WB_Q 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_BY_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_WB 0 -nan% 0 -nan% +PREF_HIT_BY_PREF 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_WB 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_L1_FILL 0 -nan% 0 -nan% +DEMAND_L1_FILL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TOUCH_L1_REPLACE 0 0.000% 0 0.000% +NO_TOUCH_L1_REPLACE 898905 100.000% 898905 100.000% + 898905 100.000% 898905 100.000% + 1.00 1.00 1.00 1.00 + +PREF_REQ_QUE_FULL 0 0 + +STREAM_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +L2HIT_STREAM_PREF_REQ_QUE_FULL 0 0 + +L2HIT_HIT_TRAIN_STREAM 0 -nan% 0 -nan% +L2HIT_MISS_TRAIN_STREAM 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_TRAIN_CREATE 0 0 + +L2HIT_STREAM_BUFFER_REQ 0 0 + +L2HIT_STREAM_PREF_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_STREAM_PREF_DCACHE_INSERT 0 -nan% 0 -nan% +L2HIT_STREAM_L2_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_DCACHE_PORT_FULL 0 0 + +L2HIT_STREAM_PREF_L1_PORT_FULL 0 0 + +L2HIT_TRAIN_HIT_DEMAND 0 -nan% 0 -nan% +L2HIT_TRAIN_MISS_REQ 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_TRAIN_FILTER_MISS 0 -nan% 0 -nan% +L2HIT_TRAIN_FILTER_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_PREF_REQ_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_PREF_REQ_DCACHE_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_L2SEND_Q_FULL 0 -nan% 0 -nan% +L2HIT_L2SEND_Q_ENTER 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_MEM_REQ 0 0 + +REMOVE_REDUNDANT_STREAM_STAT 0 0 + +REPLACE_OLD_STREAM 243221 243221 + +REQ_SEND_QUEUE_STALL 0 0 + +STREAM_ENTER_RA 0 0 + +CORE_STREAM_LENGTH_0 42125 46.839% 42125 46.839% +CORE_STREAM_LENGTH_10 40821 45.389% 40821 45.389% +CORE_STREAM_LENGTH_20 4519 5.025% 4519 5.025% +CORE_STREAM_LENGTH_30 1040 1.156% 1040 1.156% +CORE_STREAM_LENGTH_40 512 0.569% 512 0.569% +CORE_STREAM_LENGTH_50 338 0.376% 338 0.376% +CORE_STREAM_LENGTH_60 232 0.258% 232 0.258% +CORE_STREAM_LENGTH_70 144 0.160% 144 0.160% +CORE_STREAM_LENGTH_80 77 0.086% 77 0.086% +CORE_STREAM_LENGTH_90 37 0.041% 37 0.041% +CORE_STREAM_LENGTH_100_P 91 0.101% 91 0.101% + 89936 100.000% 89936 100.000% + 0.68 0.79 0.68 0.79 + +CORE_CUM_STREAM_LENGTH_0 244125 23.320% 244125 23.320% +CORE_CUM_STREAM_LENGTH_10 567219 54.183% 567219 54.183% +CORE_CUM_STREAM_LENGTH_20 102163 9.759% 102163 9.759% +CORE_CUM_STREAM_LENGTH_30 34857 3.330% 34857 3.330% +CORE_CUM_STREAM_LENGTH_40 22797 2.178% 22797 2.178% +CORE_CUM_STREAM_LENGTH_50 18358 1.754% 18358 1.754% +CORE_CUM_STREAM_LENGTH_60 14981 1.431% 14981 1.431% +CORE_CUM_STREAM_LENGTH_70 10758 1.028% 10758 1.028% +CORE_CUM_STREAM_LENGTH_80 6369 0.608% 6369 0.608% +CORE_CUM_STREAM_LENGTH_90 3476 0.332% 3476 0.332% +CORE_CUM_STREAM_LENGTH_100_P 21751 2.078% 21751 2.078% + 1046854 100.000% 1046854 100.000% + 1.46 1.79 1.46 1.79 + +CORE_STREAM_TRAIN_HITS_0 76154 84.676% 76154 84.676% +CORE_STREAM_TRAIN_HITS_10 12005 13.348% 12005 13.348% +CORE_STREAM_TRAIN_HITS_20 1109 1.233% 1109 1.233% +CORE_STREAM_TRAIN_HITS_30 353 0.393% 353 0.393% +CORE_STREAM_TRAIN_HITS_40 148 0.165% 148 0.165% +CORE_STREAM_TRAIN_HITS_50 48 0.053% 48 0.053% +CORE_STREAM_TRAIN_HITS_60 32 0.036% 32 0.036% +CORE_STREAM_TRAIN_HITS_70 18 0.020% 18 0.020% +CORE_STREAM_TRAIN_HITS_80 7 0.008% 7 0.008% +CORE_STREAM_TRAIN_HITS_90 6 0.007% 6 0.007% +CORE_STREAM_TRAIN_HITS_100_P 56 0.062% 56 0.062% + 89936 100.000% 89936 100.000% + 0.19 0.54 0.19 0.54 + +CORE_CUM_STREAM_TRAIN_HITS_0 442688 67.435% 442688 67.435% +CORE_CUM_STREAM_TRAIN_HITS_10 144996 22.087% 144996 22.087% +CORE_CUM_STREAM_TRAIN_HITS_20 25961 3.955% 25961 3.955% +CORE_CUM_STREAM_TRAIN_HITS_30 11837 1.803% 11837 1.803% +CORE_CUM_STREAM_TRAIN_HITS_40 6356 0.968% 6356 0.968% +CORE_CUM_STREAM_TRAIN_HITS_50 2573 0.392% 2573 0.392% +CORE_CUM_STREAM_TRAIN_HITS_60 2038 0.310% 2038 0.310% +CORE_CUM_STREAM_TRAIN_HITS_70 1331 0.203% 1331 0.203% +CORE_CUM_STREAM_TRAIN_HITS_80 601 0.092% 601 0.092% +CORE_CUM_STREAM_TRAIN_HITS_90 566 0.086% 566 0.086% +CORE_CUM_STREAM_TRAIN_HITS_100_P 17517 2.668% 17517 2.668% + 656464 100.000% 656464 100.000% + 0.73 1.71 0.73 1.71 + +CORE_STREAM_TRAIN_CREATE 243237 243237 + + + diff --git a/labs/LAB5/runs/xalancbmk_s_base-sms1/PARAMS.in b/labs/LAB5/runs/xalancbmk_s_base-sms1/PARAMS.in new file mode 100644 index 00000000..2593c2b8 --- /dev/null +++ b/labs/LAB5/runs/xalancbmk_s_base-sms1/PARAMS.in @@ -0,0 +1,226 @@ +# File : PARAMS.kaby_lake +# Date : 03/06/19 +# Description : Kaby Lake Configuration +# +# Based on documentation found here: +# https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake + +## Simulation Parameters +--mode full +--model cmp +--sim_limit none + +## Core Parameters + +# Femptoseconds, 3.2GHz, used for energy estimates. +--chip_cycle_time 312500 + + +### Fetch Stage +--fetch_off_path_ops 1 +--fetch_across_cache_lines 1 + +# Will break the packet upon a taken branch. +--fetch_break_on_taken 1 + +# Number of bubble cycles to wait after taken branch. +--fetch_taken_bubble_cycles 0 + + +#### ICache +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 + +### Branch Predictor +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_mech tagescl + + +#### BTB + +# BTB model to use. +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 + +# Allow the BTB to be updated by off path ops. +--btb_off_path_writes 1 + + +#### CRS + +# Enable return stack +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 + +### iBP +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged + # iBTB Model. tc_tagless, tc_tagged, tc_hybrid. +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 + +### Decode Stage +--decode_cycles 5 + + +### Map Stage +--map_cycles 5 + + +### Issue Stage + +# Max number of instructions to be fetched, decoded, renamed, and issued per cycle. +--issue_width 6 + +--rs_fill_width 0 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 + + +### Exec Stage + +### DCache +--dcache_size 32768 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--dcache_assoc 4 +--dcache_line_size 64 + +### Reorder/Retire Stage + +# Max number of instructions to be retired per cycle. +--node_ret_width 6 +--node_table_size 224 + +# Do not keep stores in RSVs on cache misses; TODO: confirm what this knob does +--stores_do_not_block_window 1 + +# TODO: confirm what this knob does +--prefs_do_not_block_window 1 + + +## Uncore + +### Mid-level cache + +# Enable use of a midlevel cache between i/d and L1 +--mlc_present 0 + +### LLC +--l1_size 1048576 +--l1_banks 1 +--l1_cycles 18 +--l1_assoc 8 +--l1_line_size 64 +--l1_interleave_factor 64 + + +### Prefetcher +--pref_framework_on 1 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--pref_shared_queues 0 +--pref_train_on_pref_misses 0 +--pref_oracle_train 0 +--pref_ul1req_queue_overwrite_on_full 1 + +--stream_length 64 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 + +--pref_throttlefb_on=1 +--pref_acc_thresh_1=0.75 +--pref_acc_thresh_2=0.4 +--pref_acc_thresh_3=0.4 +--pref_timely_thresh=0.01 +--pref_polpf_thresh=0.005 +--pref_update_interval=8192 + +--mem_req_buffer_pref_watermark 4 +--promote_to_higher_priority_mem_req_type 1 + +### Memory +--addr_translation random + +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 + +--mem_req_buffer_entries 32 +--mem_l1_fill_queue_entries 32 +--va_page_size_bytes 4096 +--bus_width_in_bytes 8 + +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 + +## Other + + +### Debug +--debug_inst_start 0 +--debug_inst_stop -1 +--debug_cycle_start 0 +--debug_cycle_stop -1 + + +## Stats and Params +--dump_params 1 +--dump_stats 1 +--dump_trace 0 + +#################################### +--set_off_path_confirmed 1 + +--order_beyond_bus 1 + +--mem_ooo_stores 1 +--mem_obey_store_dep 1 diff --git a/labs/LAB5/runs/xalancbmk_s_base-sms1/PARAMS.out b/labs/LAB5/runs/xalancbmk_s_base-sms1/PARAMS.out new file mode 100644 index 00000000..dc9dff16 --- /dev/null +++ b/labs/LAB5/runs/xalancbmk_s_base-sms1/PARAMS.out @@ -0,0 +1,908 @@ +--mode full +--model cmp +--frontend memtrace +--inst_limit 100000000 +--sim_limit none +--dump_params 1 +--dump_stats 1 +--dump_trace 0 +--mlc_present 0 +--l1_size 1048576 +--l1_assoc 8 +--l1_line_size 64 +--l1_cycles 18 +--l1_banks 1 +--l1_interleave_factor 64 +--va_page_size_bytes 4096 +--addr_translation random +--icache_size 32768 +--icache_assoc 4 +--icache_line_size 64 +--dcache_size 32768 +--dcache_assoc 4 +--dcache_line_size 64 +--dcache_read_ports 2 +--dcache_write_ports 1 +--dcache_banks 1 +--mem_ooo_stores 1 +--mem_obey_store_dep 1 +--mem_req_buffer_entries 32 +--mem_priority_ifetch 0 +--mem_priority_dfetch 1 +--mem_priority_dstore 2 +--mem_priority_iprf 3 +--mem_priority_dprf 4 +--mem_priority_wb 5 +--mem_priority_wb_nodirty 5 +--promote_to_higher_priority_mem_req_type 1 +--mem_req_buffer_pref_watermark 4 +--mem_l1_fill_queue_entries 32 +--order_beyond_bus 1 +--set_off_path_confirmed 1 +--ramulator_standard DDR4 +--ramulator_speed DDR4_2400R +--ramulator_org DDR4_8Gb_x8 +--ramulator_channels 1 +--ramulator_ranks 1 +--ramulator_bankgroups 4 +--ramulator_banks 4 +--ramulator_chip_width 8 +--bus_width_in_bytes 8 +--ramulator_rows 65536 +--ramulator_cols 1024 +--ramulator_scheduling_policy FRFCFS_Cap +--ramulator_readq_entries 32 +--ramulator_writeq_entries 32 +--ramulator_record_cmd_trace FALSE +--ramulator_print_cmd_trace FALSE +--ramulator_tCK 833333 +--ramulator_tCL 16 +--ramulator_tCCD 6 +--ramulator_tCCDS 4 +--ramulator_tCCDL 6 +--ramulator_tCWL 12 +--ramulator_tBL 4 +--ramulator_tWTR 9 +--ramulator_tWTRS 3 +--ramulator_tWTRL 9 +--ramulator_tRP 16 +--ramulator_tRPpb 16 +--ramulator_tRPab 16 +--ramulator_tRCD 16 +--ramulator_tRCDR 16 +--ramulator_tRCDW 16 +--ramulator_tRAS 39 +--dram_tech_in_nm 32 +--chip_cycle_time 312500 +--issue_width 6 +--rs_fill_width 0 +--node_table_size 224 +--node_ret_width 6 +--rs_sizes 97 +--rs_connections 0 +--fu_types 0 0 0 0 0 0 0 0 +--decode_cycles 5 +--map_cycles 5 +--extra_recovery_cycles 0 # Number of cycles before the fetching of the first instructions after recovery. +--extra_redirect_cycles 0 # Number of cycles before the fetching of the first instructions after redirect. +--fetch_across_cache_lines 1 +--fetch_off_path_ops 0 +--fetch_break_on_taken 1 +--fetch_taken_bubble_cycles 0 +--stores_do_not_block_window 1 +--prefs_do_not_block_window 1 +--cbp_trace_r0 /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir/trace/drmemtrace.xalancbmk_s_base.mytest-m64.555084.7482.trace.gz +--memtrace_modules_log /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir/raw +--debug_cycle_start 0 +--debug_cycle_stop -1 +--debug_inst_start 0 +--debug_inst_stop -1 +--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle +--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. +--bp_mech tagescl +--btb_mech generic +--btb_entries 4096 +--btb_assoc 4 +--btb_off_path_writes 1 +--enable_crs 1 +--crs_entries 32 +--crs_realistic 1 +--enable_ibp 1 # Enable the indirect branch predictor +--ibtb_mech tc_tagged +--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. +--tc_entries 4096 +--tc_assoc 4 +--pref_stream_on 1 +--pref_stream_per_core_enable 1 +--stream_prefetch_n 4 +--stream_start_dis 1 +--stream_length 64 +--stream_train_num 4 +--stream_create_on_dc_miss 0 +--stream_create_on_l1_miss 1 +--pref_framework_on 1 +--pref_shared_queues 0 +--pref_ul1req_queue_overwrite_on_full 1 +--pref_train_on_pref_misses 0 +--pref_oracle_train_on 0 +--pref_throttlefb_on 1 +--pref_acc_thresh_1 0.75 +--pref_acc_thresh_2 0.4 +--pref_acc_thresh_3 0.4 +--pref_update_interval 8192 +--pref_timely_thresh 0.01 +--pref_polpf_thresh 0.005 +--pref_sms_on 1 +1 1 1 1 1 1 1 + +--- Cut out everything below to use this file as PARAMS.in --- + +Parameter status at compile time and values supplied on the command line: + +SIM_MODE 0 full +SIM_MODEL 0 cmp +FRONTEND FE_PIN_EXEC_DRIVEN memtrace +INST_LIMIT NULL 100000000 +SIM_LIMIT "none" none +FORWARD_PROGRESS_LIMIT 100000000 +FORWARD_PROGRESS_INTERVAL 10000 +FAST_FORWARD 0 +FAST_FORWARD_UNTIL_ADDR 0 +FAST_FORWARD_TRACE_INS 0 +WARMUP 0 +HEARTBEAT_INTERVAL 1000000 +NUM_HEARTBEATS 0 +FILE_TAG "" +OUTPUT_DIR "." +STATUS_FILE NULL +BINDIR NULL +DUMP_PARAMS TRUE 1 +DUMP_STATS TRUE 1 +DUMP_TRACE FALSE 0 +CLEAR_STATS "never" +STATS_TO_TRACE NULL +STAT_TRACE_FILE "stats.trace" +STAT_TRACE_INTERVAL "i:100000" +PIPEVIEW FALSE +PIPEVIEW_FILE "pipeview" +MEMVIEW FALSE +MEMVIEW_FILE "memview.out" +MEMVIEW_START "never" +INST_HASH_TABLE_SIZE 500021 const +STDOUT_FILE NULL +STDERR_FILE NULL +PIN_EXEC_DRIVEN_FE_SOCKET "./pin_exec_driven_fe_socket.temp" +PRINT_PID FALSE +USE_UNSURE_FREE_LISTS FALSE +OPTIMIZER2_MAX_NUM_SLAVES 64 +OPTIMIZER2_PERFECT_MEMORYLESS FALSE +EXIT_COND 0 +ENABLE_SWPRF FALSE +MLC_PRESENT FALSE 0 +MLC_SIZE (512 * 1024) +MLC_ASSOC 4 +MLC_LINE_SIZE 64 +MLC_CYCLES 12 +PERFECT_MLC FALSE +MLC_READ_PORTS 1 +MLC_WRITE_PORTS 1 +MLC_BANKS 8 +MLC_INTERLEAVE_FACTOR 64 +MLC_CACHE_REPL_POLICY 0 +MLC_WRITE_THROUGH FALSE +PREFETCH_UPDATE_LRU_MLC TRUE +FORCE_L1_MISS FALSE +L1_SIZE (4 * 1024 * 1024) 1048576 +L1_ASSOC 8 8 +L1_LINE_SIZE 64 64 +L1_CYCLES 24 18 +PERFECT_L1 FALSE +PRIVATE_L1 FALSE +L1_READ_PORTS 1 +L1_WRITE_PORTS 1 +L1_BANKS 8 1 +L1_INTERLEAVE_FACTOR 64 64 +L1_CACHE_REPL_POLICY 0 +L1_WRITE_THROUGH FALSE +L1_IGNORE_WB FALSE +L1_USE_CORE_FREQ FALSE +MARK_L1_MISSES TRUE +PREFETCH_UPDATE_LRU_L1 TRUE +MEMORY_RANDOM_ADDR FALSE +VA_PAGE_SIZE_BYTES 4096 4096 +NUM_ADDR_NON_SIGN_EXTEND_BITS 48 +ADDR_TRANSLATION 0 random +CONSTANT_MEMORY_LATENCY FALSE +MEMORY_CYCLES 100 +STALL_MEM_REQS_ONLY FALSE +ICACHE_SIZE (64 * 1024) 32768 +ICACHE_ASSOC 4 4 +ICACHE_LINE_SIZE 64 64 +PERFECT_ICACHE FALSE +ICACHE_READ_PORTS 2 +ICACHE_WRITE_PORTS 1 +ICACHE_BANKS 8 +ICACHE_REPL 0 +DCACHE_SIZE (64 * 1024) 32768 +DCACHE_ASSOC 1 4 +DCACHE_LINE_SIZE 64 64 +DCACHE_CYCLES 2 +PERFECT_DCACHE FALSE +DCACHE_READ_PORTS 8 2 +DCACHE_WRITE_PORTS 1 1 +DCACHE_BANKS 1 1 +DCACHE_REPL 0 +DCACHE_REPL_PREF_THRESH 1 +MEM_OOO_STORES TRUE 1 +MEM_OBEY_STORE_DEP TRUE 1 +PREF_INSERT_LRU FALSE +PREF_INSERT_MIDDLE FALSE +PREF_INSERT_LOWQTR FALSE +PREF_INSERT_DYNACC FALSE +MEM_REQ_BUFFER_ENTRIES 32 32 +PRIVATE_MSHR_ON TRUE +MEM_PRIORITY_IFETCH 0 0 +MEM_PRIORITY_DFETCH 0 1 +MEM_PRIORITY_DSTORE 0 2 +MEM_PRIORITY_IPRF 9 3 +MEM_PRIORITY_DPRF 10 4 +MEM_PRIORITY_WB 0 5 +MEM_PRIORITY_WB_NODIRTY 0 5 +PROMOTE_TO_HIGHER_PRIORITY_MEM_REQ_TYPE FALSE 1 +MEM_REQ_BUFFER_PREF_WATERMARK 0 4 +MEM_REQ_BUFFER_WB_VALVE 2 +MEM_L1_FILL_QUEUE_ENTRIES 32 32 +MEM_BUS_OUT_QUEUE_PARTITION_ENABLE FALSE +MEM_MEM_QUEUE_PARTITION_ENABLE FALSE +MEM_BUS_OUT_QUEUE_AS_FIFO TRUE +OLDEST_FIRST_TO_MEM_QUEUE TRUE +ROUND_ROBIN_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE FALSE +ONE_CORE_FIRST_TO_MEM_QUEUE_TH 0 +L1_CYCLE_TIME 312500 +MLCQ_TO_L1Q_TRANSFER_LATENCY 1 +L1Q_TO_FSB_TRANSFER_LATENCY 1 +PRIORITIZE_PREFETCHES_WITH_UNIQUE FALSE +KICKOUT_PREFETCHES FALSE +KICKOUT_LOOK_FOR_OLDEST_FIRST FALSE +KICKOUT_OLDEST_PREFETCH FALSE +KICKOUT_OLDEST_PREFETCH_WITHIN_BANK FALSE +ORDER_BEYOND_BUS FALSE 1 +ALL_FIFO_QUEUES FALSE +QUEUE_MLC_SIZE 0 +QUEUE_L1_SIZE 0 +QUEUE_BUS_OUT_SIZE 0 +QUEUE_CORE_FILL_SIZE 0 +ALLOW_TYPE_MATCHES FALSE +STREAM_PREFETCH_ON FALSE +DC_PREF_CACHE_ENABLE FALSE +DC_PREF_CACHE_CYCLE 0 +PREF_INSERT_DCACHE_IMM TRUE +DC_PREF_CACHE_SIZE (64 * 1024) +DC_PREF_CACHE_ASSOC 4 +DC_PREF_ONLY_L1HIT FALSE +PREF_CACHE_USE_RDY_CYCLE FALSE +IC_PREF_CACHE_ENABLE FALSE +IC_PREF_CACHE_SIZE (64 * 1024) +IC_PREF_CACHE_ASSOC 4 +L1_PREF_CACHE_ENABLE FALSE +L1_PREF_CACHE_SIZE (1024 * 1024) +L1_PREF_CACHE_ASSOC 8 +SET_OFF_PATH_CONFIRMED FALSE 1 +USE_CONFIRMED_OFF FALSE +PREFCACHE_MOVE_OFFPATH FALSE +CACHE_STAT_ENABLE FALSE +PREF_DCACHE_HIT_FILL_L1 TRUE +PREF_ICACHE_HIT_FILL_L1 TRUE +CRITICAL_ACCESS_PLOT_ENABLE FALSE +CRITICAL_ACCESS_PLOT_FILE "critical_access_plot.dat" +ROUND_ROBIN_TO_L1 FALSE +PREF_I_TOGETHER FALSE +ONE_MORE_CACHE_LINE_ENABLE FALSE +L1_STATIC_PARTITION_ENABLE 0 +L1_STATIC_PARTITION NULL +L1_DYNAMIC_PARTITION_ENABLE FALSE +L1_DYNAMIC_PARTITION_POLICY 0 +PARTITION_UMON_DSS_PREF_ENABLE FALSE +L1_CACHE_HIT_POSITION_COLLECT FALSE +L1_PART_ON FALSE +L1_PART_TRIGGER "c:1000000" +L1_PART_START "t:0" +L1_PART_WARMUP FALSE +L1_PART_SHADOW_WARMUP FALSE +L1_PART_METRIC 0 +L1_PART_SEARCH 0 +L1_PART_USE_STALLING TRUE +L1_PART_FILL_DELAY 0 +L1_SHADOW_TAGS_MODULO 1 +HIER_MSHR_ON FALSE +PERF_PRED_ENABLE FALSE +PERF_PRED_MECH PERF_PRED_CP +PERF_PRED_REQ_LATENCY_MECH PERF_PRED_REQ_LATENCY_MECH_REQ_LATENCY +PERF_PRED_COUNT_ALL FALSE +PERF_PRED_COUNT_INST_MISSES TRUE +PERF_PRED_COUNT_PREFETCHES FALSE +PERF_PRED_COUNT_OFFPATH_REQS FALSE +PERF_PRED_COUNT_BW_REQS TRUE +PERF_PRED_UPDATE_MEM_REQ_TYPE FALSE +PERF_PRED_SLACK_PERIOD_SIZE 32 +PERF_PRED_REQS_FINISH_AT_FILL FALSE +PERF_PRED_MEM_UTIL_VIA_BUS_BW FALSE +PERF_PRED_CHIP_UTIL_VIA_MEM_STALL FALSE +DUMB_MODEL_AVG_REQ_DISTANCE 100 +DUMB_MODEL_RANDOMIZE_DISTANCE FALSE +DUMB_MODEL_AVG_REQ_DISTANCE_PER_CORE NULL +DUMB_MODEL_AVG_ROW_HITS 1 +DUMB_MODEL_AVG_ROW_HITS_PER_CORE NULL +DUMB_MODEL_MLP 1 +DUMB_MODEL_MLP_PER_CORE NULL +RAMULATOR_STANDARD "DDR4" DDR4 +RAMULATOR_SPEED "DDR4_2400R" DDR4_2400R +RAMULATOR_ORG "DDR4_8Gb_x8" DDR4_8Gb_x8 +RAMULATOR_CHANNELS 1 1 +RAMULATOR_RANKS 1 1 +RAMULATOR_BANKGROUPS 4 4 +RAMULATOR_BANKS 4 4 +RAMULATOR_CHIP_WIDTH 8 8 +BUS_WIDTH_IN_BYTES 8 8 +RAMULATOR_ROWS 65536 65536 +RAMULATOR_COLS 1024 1024 +RAMULATOR_SCHEDULING_POLICY "FRFCFS_Cap" FRFCFS_Cap +RAMULATOR_READQ_ENTRIES 32 32 +RAMULATOR_WRITEQ_ENTRIES 32 32 +RAMULATOR_REC_CMD_TRACE "off" FALSE +RAMULATOR_PRINT_CMD_TRACE "off" FALSE +RAMULATOR_USE_REST_OF_ADDR_AS_ROW_ADDR "on" +RAMULATOR_TCK 833333 833333 +RAMULATOR_TCL 16 16 +RAMULATOR_TCCD 6 6 +RAMULATOR_TCCDS 4 4 +RAMULATOR_TCCDL 6 6 +RAMULATOR_TCWL 12 12 +RAMULATOR_TBL 4 4 +RAMULATOR_TWTR 9 9 +RAMULATOR_TWTRS 3 3 +RAMULATOR_TWTRL 9 9 +RAMULATOR_TRP 16 16 +RAMULATOR_TRPpb 16 16 +RAMULATOR_TRPab 16 16 +RAMULATOR_TRCD 16 16 +RAMULATOR_TRCDR 16 16 +RAMULATOR_TRCDW 16 16 +RAMULATOR_TRAS 39 39 +DRAM_TECH_IN_NM 32 32 +DVFS_ON FALSE +DVFS_METRIC DVFS_METRIC_NUM_ELEMS +DVFS_CONFIGS NULL +DVFS_CONFIG_FILE NULL +DVFS_START "t:0" +DVFS_PERIOD "t:312500000000" +DVFS_LOG TRUE +DVFS_INDIVIDUAL_CORES FALSE +DVFS_CHIP_LEVEL FALSE +DVFS_STATIC NULL +DVFS_FORCE_CONFIG NULL +DVFS_REPLAY_CONFIG_TRACE NULL +DVFS_USE_ORACLE FALSE +DVFS_USE_BW_SHARING FALSE +DVFS_USE_DRAM_SHARING FALSE +DVFS_USE_STALL_TIME FALSE +DVFS_DRAM_SHARING_SOLVER_BIN NULL +DVFS_DRAM_SHARING_SOLVER_STRICT TRUE +DVFS_BW_SHARING_BUS_UTIL_THRESH 0.95 +DVFS_BW_SHARING_MAX_REQS 28.0 +DVFS_BW_SHARING_MAX_RW_COST 0.25 +DVFS_BW_SHARING_NO_PREF_STALL TRUE +DVFS_BW_SHARING_CRIT_STATS TRUE +DVFS_COUNT_L1_ACCESS_STALL FALSE +NUM_CORES 1 +CHIP_CYCLE_TIME 312500 312500 +CORE_0_CYCLE_TIME 312500 +CORE_1_CYCLE_TIME 312500 +CORE_2_CYCLE_TIME 312500 +CORE_3_CYCLE_TIME 312500 +CORE_4_CYCLE_TIME 312500 +CORE_5_CYCLE_TIME 312500 +CORE_6_CYCLE_TIME 312500 +CORE_7_CYCLE_TIME 312500 +CORE_8_CYCLE_TIME 312500 +CORE_9_CYCLE_TIME 312500 +CORE_10_CYCLE_TIME 312500 +CORE_11_CYCLE_TIME 312500 +CORE_12_CYCLE_TIME 312500 +CORE_13_CYCLE_TIME 312500 +CORE_14_CYCLE_TIME 312500 +CORE_15_CYCLE_TIME 312500 +CORE_16_CYCLE_TIME 312500 +CORE_17_CYCLE_TIME 312500 +CORE_18_CYCLE_TIME 312500 +CORE_19_CYCLE_TIME 312500 +CORE_20_CYCLE_TIME 312500 +CORE_21_CYCLE_TIME 312500 +CORE_22_CYCLE_TIME 312500 +CORE_23_CYCLE_TIME 312500 +CORE_24_CYCLE_TIME 312500 +CORE_25_CYCLE_TIME 312500 +CORE_26_CYCLE_TIME 312500 +CORE_27_CYCLE_TIME 312500 +CORE_28_CYCLE_TIME 312500 +CORE_29_CYCLE_TIME 312500 +CORE_30_CYCLE_TIME 312500 +CORE_31_CYCLE_TIME 312500 +CORE_32_CYCLE_TIME 312500 +CORE_33_CYCLE_TIME 312500 +CORE_34_CYCLE_TIME 312500 +CORE_35_CYCLE_TIME 312500 +CORE_36_CYCLE_TIME 312500 +CORE_37_CYCLE_TIME 312500 +CORE_38_CYCLE_TIME 312500 +CORE_39_CYCLE_TIME 312500 +CORE_40_CYCLE_TIME 312500 +CORE_41_CYCLE_TIME 312500 +CORE_42_CYCLE_TIME 312500 +CORE_43_CYCLE_TIME 312500 +CORE_44_CYCLE_TIME 312500 +CORE_45_CYCLE_TIME 312500 +CORE_46_CYCLE_TIME 312500 +CORE_47_CYCLE_TIME 312500 +CORE_48_CYCLE_TIME 312500 +CORE_49_CYCLE_TIME 312500 +CORE_50_CYCLE_TIME 312500 +CORE_51_CYCLE_TIME 312500 +CORE_52_CYCLE_TIME 312500 +CORE_53_CYCLE_TIME 312500 +CORE_54_CYCLE_TIME 312500 +CORE_55_CYCLE_TIME 312500 +CORE_56_CYCLE_TIME 312500 +CORE_57_CYCLE_TIME 312500 +CORE_58_CYCLE_TIME 312500 +CORE_59_CYCLE_TIME 312500 +CORE_60_CYCLE_TIME 312500 +CORE_61_CYCLE_TIME 312500 +CORE_62_CYCLE_TIME 312500 +CORE_63_CYCLE_TIME 312500 +ISSUE_WIDTH 4 6 +RS_FILL_WIDTH 8 0 +NODE_TABLE_SIZE 256 224 +NODE_RET_WIDTH 4 6 +NODE_RETIRE_RATE 10 +RS_SIZES "256" 97 +RS_CONNECTIONS "xF" 0 +FU_TYPES "0, 0, 0, 0" 0 0 0 0 0 0 0 0 +DECODE_CYCLES 1 5 +MAP_CYCLES 1 5 +EXTRA_RECOVERY_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after recovery. +EXTRA_REDIRECT_CYCLES 0 0 # Number of cycles before the fetching of the first instructions after redirect. +EXTRA_CALLSYS_CYCLES 20 const +DIE_ON_CALLSYS FALSE +DIE_ON_RET_STALL_THRESH 0 +DIE_ON_RET_STALL_CORE 0 +DIE_ON_MEM_BLOCK_THRESH 0 +DIE_ON_MEM_BLOCK_CORE 0 +FETCH_ACROSS_CACHE_LINES FALSE 1 +FETCH_OFF_PATH_OPS TRUE 0 +FETCH_BREAK_ON_TAKEN FALSE 1 +FETCH_TAKEN_BUBBLE_CYCLES 0 0 +WP_COLLECT_STATS FALSE +SWITCH_IC_FETCH_ON_RECOVERY TRUE +OP_INV_DELAY 1 +OP_NOP_DELAY 1 +OP_CF_DELAY 1 +OP_MOV_DELAY 1 +OP_CMOV_DELAY 1 +OP_LDA_DELAY 1 +OP_IMEM_DELAY 1 +OP_IADD_DELAY 1 +OP_IMUL_DELAY 3 +OP_IDIV_DELAY -20 +OP_ICMP_DELAY 1 +OP_LOGIC_DELAY 1 +OP_SHIFT_DELAY 1 +OP_FMEM_DELAY 1 +OP_FCVT_DELAY 3 +OP_FADD_DELAY 3 +OP_FMUL_DELAY 5 +OP_FMA_DELAY 5 +OP_FDIV_DELAY -20 +OP_FCMP_DELAY 3 +OP_FCMOV_DELAY 1 +OP_GATHER_DELAY 12 +OP_SCATTER_DELAY 18 +OP_PIPELINED_FAST_DELAY 2 +OP_PIPELINED_MEDIUM_DELAY 5 +OP_PIPELINED_SLOW_DELAY 10 +OP_NOTPIPELINED_MEDIUM_DELAY -5 +OP_NOTPIPELINED_SLOW_DELAY -20 +OP_NOTPIPELINED_VERY_SLOW_DELAY -100 +UNIFORM_OP_DELAY 0 +STALL_ON_WAIT_MEM TRUE +STORES_DO_NOT_BLOCK_WINDOW FALSE 1 +PREFS_DO_NOT_BLOCK_WINDOW FALSE 1 +OBEY_REG_DEP TRUE +OLDEST_FIRST_SCHED FALSE +FIND_EMPTIEST_RS FALSE +TRACK_L1_MISS_DEPS FALSE +CBP_TRACE_R0 NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir/trace/drmemtrace.xalancbmk_s_base.mytest-m64.555084.7482.trace.gz +CBP_TRACE_R1 NULL +CBP_TRACE_R2 NULL +CBP_TRACE_R3 NULL +CBP_TRACE_R4 NULL +CBP_TRACE_R5 NULL +CBP_TRACE_R6 NULL +CBP_TRACE_R7 NULL +CBP_TRACE_R8 NULL +CBP_TRACE_R9 NULL +CBP_TRACE_R10 NULL +CBP_TRACE_R11 NULL +CBP_TRACE_R12 NULL +CBP_TRACE_R13 NULL +CBP_TRACE_R14 NULL +CBP_TRACE_R15 NULL +CBP_TRACE_R16 NULL +CBP_TRACE_R17 NULL +CBP_TRACE_R18 NULL +CBP_TRACE_R19 NULL +CBP_TRACE_R20 NULL +CBP_TRACE_R21 NULL +CBP_TRACE_R22 NULL +CBP_TRACE_R23 NULL +CBP_TRACE_R24 NULL +CBP_TRACE_R25 NULL +CBP_TRACE_R26 NULL +CBP_TRACE_R27 NULL +CBP_TRACE_R28 NULL +CBP_TRACE_R29 NULL +CBP_TRACE_R30 NULL +CBP_TRACE_R31 NULL +CBP_TRACE_R32 NULL +CBP_TRACE_R33 NULL +CBP_TRACE_R34 NULL +CBP_TRACE_R35 NULL +CBP_TRACE_R36 NULL +CBP_TRACE_R37 NULL +CBP_TRACE_R38 NULL +CBP_TRACE_R39 NULL +CBP_TRACE_R40 NULL +CBP_TRACE_R41 NULL +CBP_TRACE_R42 NULL +CBP_TRACE_R43 NULL +CBP_TRACE_R44 NULL +CBP_TRACE_R45 NULL +CBP_TRACE_R46 NULL +CBP_TRACE_R47 NULL +CBP_TRACE_R48 NULL +CBP_TRACE_R49 NULL +CBP_TRACE_R50 NULL +CBP_TRACE_R51 NULL +CBP_TRACE_R52 NULL +CBP_TRACE_R53 NULL +CBP_TRACE_R54 NULL +CBP_TRACE_R55 NULL +CBP_TRACE_R56 NULL +CBP_TRACE_R57 NULL +CBP_TRACE_R58 NULL +CBP_TRACE_R59 NULL +CBP_TRACE_R60 NULL +CBP_TRACE_R61 NULL +CBP_TRACE_R62 NULL +CBP_TRACE_R63 NULL +MEMTRACE_MODULES_LOG NULL /outside/Development/ucsc/coursework/S23_CSE220/cse220-traces/drmemtrace.xalancbmk_s_base.mytest-m64.555084.9837.dir/raw +DUMB_CORE_ON FALSE +DUMB_CORE 1 +DEBUG_CYCLE_START 0 0 +DEBUG_CYCLE_STOP 0 -1 +DEBUG_TIME_START 0 +DEBUG_TIME_STOP 0 +DEBUG_INST_START 0 0 +DEBUG_INST_STOP 0 -1 +DEBUG_OP_START 0 +DEBUG_OP_STOP 0 +DEBUG_CACHE_LIB FALSE +DEBUG_HASH_LIB FALSE +DEBUG_LIST_LIB FALSE +DEBUG_PORT_LIB FALSE +DEBUG_BUS_LIB FALSE +DEBUG_OP_POOL FALSE +DEBUG_ORACLE FALSE +DEBUG_FRONTEND FALSE +DEBUG_ADDR_TRANS FALSE +DEBUG_BP FALSE +DEBUG_BP_DIR FALSE +DEBUG_BTB FALSE +DEBUG_CRS FALSE +DEBUG_MAP FALSE +DEBUG_MEMORY FALSE +DEBUG_REPLAY FALSE +DEBUG_FREQ FALSE +DEBUG_MODEL FALSE +DEBUG_THREAD FALSE +DEBUG_ICACHE_STAGE FALSE +DEBUG_DECODE_STAGE FALSE +DEBUG_MAP_STAGE FALSE +DEBUG_NODE_STAGE FALSE +DEBUG_EXEC_STAGE FALSE +DEBUG_DCACHE_STAGE FALSE +DEBUG_RETIRED_UOPS FALSE +DEBUG_EXC_INSERTS FALSE +DEBUG_BP_CONF FALSE +DEBUG_ONPATH_CONF FALSE +DEBUG_STREAM FALSE +DEBUG_STREAM_MEM FALSE +DEBUG_WAY FALSE +DEBUG_L2MARKV FALSE +DEBUG_L2L1PREF FALSE +DEBUG_PERF_PRED FALSE +DEBUG_POWER_UTILS FALSE +DEBUG_DVFS FALSE +DEBUG_TRACE_READ FALSE +DEBUG_INST_FIELDS FALSE +DEBUG_OP_FIELDS FALSE +DEBUG_PIN_EXEC_DRIVEN FALSE +DEBUG_CACHE_PART FALSE +DEBUG_OPTIMIZER2 FALSE +DEBUG_PREF FALSE +PERFECT_BP FALSE +PERFECT_BTB FALSE +PERFECT_IBP FALSE +PERFECT_CRS FALSE +PERFECT_CBR_BTB FALSE +PERFECT_NT_BTB FALSE +CFS_PER_CYCLE 3 6 # Number of branches that can be predicted in a single cycle +UPDATE_BP_OFF_PATH FALSE 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). +BP_UPDATE_AT_RETIRE FALSE 0 # Update the BP at retire. If false, update at the end of exec. +BP_MECH 0 tagescl +LATE_BP_MECH NUM_BP +LATE_BP_LATENCY 5 +HIST_LENGTH 16 +PHT_CTR_BITS 2 const +BHT_ENTRIES (4 * 1024) +BHT_ASSOC 4 +HYBRIDS_INDEX_LENGTH 16 +HYBRIDG_HIST_LENGTH 16 +HYBRIDP_HIST_LENGTH 16 +FILTER_INDEX_LENGTH 16 +USE_FILTER FALSE +INF_HYBRIDGP FALSE +BP_HASH_TOS FALSE +IBTB_HASH_TOS FALSE +BTB_MECH 0 generic +BTB_ENTRIES (4 * 1024) 4096 +BTB_ASSOC 4 4 +BTB_OFF_PATH_WRITES TRUE 1 +ENABLE_CRS TRUE 1 +CRS_ENTRIES 32 32 +CRS_REALISTIC 0 1 +ENABLE_IBP TRUE 1 # Enable the indirect branch predictor +USE_PAT_HIST TRUE +IBTB_MECH 1 tc_tagged +IBTB_HIST_LENGTH 16 +IBTB_OFF_PATH_WRITES TRUE 1 # Allow off path ops to update the ibtb. +TARGETS_IN_HIST 4 +TC_ENTRIES (4 * 1024) 4096 +TC_ASSOC 4 4 +NUM_CORR_BRANCHES 3 +SEL_HIST_BP_ENTRIES 8192 +SEL_HIST_LENGTH 16 +SEL_HIST_DYN_CNT_TH 16 +SEL_HIST_MISPRED_TH 4 +ENABLE_BP_CONF FALSE +CONF_MECH 0 +PERF_BP_CONF_PRED FALSE +BPC_BITS 16 +BPC_MECH 1 +BPC_CTR_RESET TRUE +BPC_CIT_BITS 8 +BPC_CIT_TH 50 +BPC_CTR_BITS 3 +OPC_COUNT_ZEROS FALSE +OPC_COUNT_THRESH 10 +INF_LOOP FALSE +INF_LOOP_BUCKETS 811 +LOOP_ENTRIES (4 * 1024) +LOOP_ASSOC 4 +LOOP_COUNT_MAX 127 +LOOP_REPEAT_MAX 15 +KNOB_PRINT_BRINFO FALSE +BR_MISPRED_FILE NULL +CONF_PERCEPTRON_TH 0 +CONF_PERCEPTRON_CTR_BITS 8 +CONF_PERCEPTRON_ENTRIES 127 +CONF_PERCEPTRON_THRESH_OVRD 0 +CONF_HIST_LENGTH 32 +PERCEPTRON_CONF_USE_CONF FALSE +PERCEPTRON_CONF_TRAIN_HIS FALSE +PERCEPTRON_CONF_TRAIN_CONF FALSE +PERCEPTRON_CONF_TRAIN_OFFSET_CONF FALSE +PERCEPTRON_TRAIN_MISP_FACTOR 1 +PERCEPTRON_TRAIN_CORR_FACTOR 1 +PERCEPTRON_CONF_HIS_BOTH FALSE +PERCEPTRON_CONF_HIS_BOTH_LENGTH 4 +ENABLE_ICACHE_PACKET_BREAKING TRUE +NUM_LOAD_STORE_PER_PACKET 0 +PACKET_BREAK_ON_FUS FALSE +PACKET_BREAK_FU_TYPES "G,G,G,G,G,G,G,G,G,G,G,G" +POWER_INTF_ON FALSE +POWER_INTF_ENABLE_SCALING FALSE +POWER_INTF_EXEC "power/power_intf.py" +POWER_INTF_REF_CHIP_TECH_NM 22 +POWER_INTF_REF_CHIP_FREQ (3.2e9) +POWER_INTF_REF_MEMORY_FREQ (0.8e9) +POWER_OTHER (0.0) +PREF_STREAM_ON FALSE 1 +PREF_STREAM_PER_CORE_ENABLE FALSE 1 +STREAM_BUFFER_N 16 +STREAM_PREFETCH_N 2 4 +STREAM_START_DIS 5 1 +STREAM_LENGTH 16 64 +STREAM_FULL_N 1 +STREAM_TRAIN_LENGTH 16 +STREAM_TRAIN_NUM 1 4 +PREF_ACC_USE_CACHE FALSE +STREAM_STALL_ON_QUEUE_FULL FALSE +PREF_SCHEDULE_NUM 4 +TRAIN_FILTER_SIZE 32 +PREF_REQ_Q_SIZE 64 +STREAM_CREATE_ON_DC_MISS FALSE 0 +STREAM_CREATE_ON_L1_MISS TRUE 1 +STREAM_TRAIN_ON_WRONGPATH TRUE +STREAM_CREATE_ON_WRONGPATH TRUE +STREAM_PREF_INTO_DCACHE FALSE +REMOVE_REDUNDANT_STREAM FALSE +L2HIT_STREAM_SCHEDULE_NUM 4 +PREF_REQ_QUEUE_FILTER_ON FALSE +HW_PREF_HIT_TRAIN_STREAM FALSE +L2HIT_STREAM_BUFFER_N 32 +L2HIT_STREAM_PREFETCH_N 2 +L2HIT_STREAM_START_DIS 2 +L2HIT_STREAM_LENGTH 8 +L2HIT_PREF_REQ_Q_SIZE 128 +L2HIT_L2ACCESS_REQ_Q_SIZE 64 +PREF_STREAM_ACCPERSTREAM FALSE +PREF_ACC_DISTANCE_10 128 +PREF_FRAMEWORK_ON FALSE 1 +PREF_TRACE_ON FALSE +PREF_DL0REQ_QUEUE_SIZE 32 +PREF_UMLC_REQ_QUEUE_SIZE 64 +PREF_UL1REQ_QUEUE_SIZE 128 +PREF_SHARED_QUEUES TRUE 0 +PREF_DL0_MISS_ON TRUE +PREF_DL0_HIT_ON TRUE +PREF_DL0REQ_QUEUE_FILTER_ON TRUE +PREF_UMLC_REQ_QUEUE_FILTER_ON TRUE +PREF_UL1REQ_QUEUE_FILTER_ON TRUE +PREF_DL0REQ_ADD_FILTER_ON TRUE +PREF_UMLC_REQ_ADD_FILTER_ON TRUE +PREF_UL1REQ_ADD_FILTER_ON TRUE +PREF_DL0REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UMLC_REQ_QUEUE_OVERWRITE_ON_FULL FALSE +PREF_UL1REQ_QUEUE_OVERWRITE_ON_FULL FALSE 1 +PREF_DL0SCHEDULE_NUM 4 +PREF_UMLC_SCHEDULE_NUM 4 +PREF_UL1SCHEDULE_NUM 4 +PREF_L1Q_DEMAND_RESERVE 0 +PREF_REPORT_PREF_MATCH_AS_MISS FALSE +PREF_REPORT_PREF_MATCH_AS_HIT TRUE +PREF_UPDATE_ON_WRONGPATH TRUE +PREF_TRAIN_ON_PREF_MISSES FALSE 0 +PREF_ORACLE_TRAIN_ON FALSE 0 +PREF_REQ_DROP FALSE +PREF_THROTTLE_ON FALSE +PREF_THROTTLEFB_ON FALSE 1 +PREF_ACC_THRESH_1 0.90 0.75 +PREF_ACC_THRESH_2 0.70 0.4 +PREF_ACC_THRESH_3 0.60 0.4 +PREF_ACC_THRESH_4 0.40 +PREF_UPDATE_INTERVAL 0 8192 +PREF_ANALYZE_LOAD FALSE +PREF_POL_THRESH_1 0.25 +PREF_POL_THRESH_2 0.10 +PREF_POLBV_ON FALSE +PREF_POLBV_SIZE 1024 +PREF_TIMELY_THRESH 0.05 0.01 +PREF_POLPF_THRESH 0.01 0.005 +PREF_DEGFB_USEONLYACC FALSE +PREF_DEGFB_USEONLYPOL FALSE +PREF_DEGFB_USEONLYLATE FALSE +PREF_TIMELY_THRESH_2 0.005 +PREF_DEGFB_STATPHASEFILE FALSE +PREF_MAX_DEGFB 4 +PREF_DHAL FALSE +PREF_DHAL_SENTTHRESH 16 +PREF_DHAL_USETHRESH_MAX 12 +PREF_DHAL_USETHRESH_MIN2 8 +PREF_DHAL_USETHRESH_MIN1 4 +PREF_DHAL_MAXDEG 64 +PREF_HFILTER_ON FALSE +PREF_HFILTER_INDEX_BITS 12 +PREF_HFILTER_USE_PC FALSE +PREF_HFILTER_PRED_USELESS_THRES 2 +PREF_HFILTER_RESET_ENABLE FALSE +PREF_HFILTER_RESET_INTERVAL 100000 +L2L1PREF_ON FALSE +L2WAY_PREF FALSE +L2MARKV_PREF_ON FALSE +L2NEXT_PREF_ON FALSE +L2HIT_STREAM_PREF_ON FALSE +L2L1_DC_HIT_TRAIN FALSE +L1_HIT_DUMP_FILE_ON FALSE +L1_HIT_DUMP_WO_TXT FALSE +L1_HIT_DUMPFILE "l1hit_dump.out" +IDEAL_L2_L1_PREFETCHER FALSE +IDEAL_L2_ICACHE_PREFETCHER FALSE +L1WAY_PREF_SEND_QUEUE 4 +L1PREF_REQ_QUEUE_SIZE 1024 +L1PREF_IMMEDIATE FALSE +L1WAY_PREF_TIMER_DIS 1000 +L1MARKV_PREF_SEND_QUEUE 4 +L1PREF_MARKV_REQ_QUEUE_SIZE 1024 +MARKV_L2ACCESS_REQ_Q_SIZE 64 +L1MARKV_PREF_IMMEDIATE FALSE +L1MARKV_PREF_TIMER_DIS 1 +L2L1_HIT_TRAIN TRUE +L1MARKV_REQ_TH 1 +L2L1_IMMEDIATE_PREF_CACHE FALSE +L2L1_FILL_PREF_CACHE FALSE +L2L1_L2_HIT_STAT FALSE +PREF_GHB_ON FALSE +DEBUG_PREF_GHB FALSE +PREF_GHB_BUFFER_N 1024 +PREF_GHB_INDEX_N 128 +PREF_GHB_CZONE_BITS 12 +PREF_GHB_DEGREE 16 +PREF_GHB_MAX_DEGREE 32 +PREF_STRIDE_ON FALSE +DEBUG_PREF_STRIDE FALSE +PREF_STRIDE_TABLE_N 1024 +PREF_STRIDE_REGION_BITS 16 +PREF_STRIDE_DEGREE 4 +PREF_STRIDE_DISTANCE 16 +PREF_STRIDE_STARTDISTANCE 1 +PREF_STRIDE_SINGLE_THRESH 6 +PREF_STRIDE_MULTI_THRESH 6 +PREF_STRIDE_SINGLE_STRIDE_MODE FALSE +PREF_STRIDEPC_ON FALSE +DEBUG_PREF_STRIDEPC FALSE +PREF_STRIDEPC_TABLE_N 1024 +PREF_STRIDEPC_DEGREE 4 +PREF_STRIDEPC_DISTANCE 16 +PREF_STRIDEPC_USELOADADDR FALSE +PREF_STRIDEPC_TRAINNUM 2 +PREF_STRIDEPC_STARTDIS 4 +PREF_PHASE_ON FALSE +PREF_PHASE_STUDY FALSE +DEBUG_PREF_PHASE FALSE +PREF_PHASE_PRIME_HASH 16381 +PREF_PHASE_INFOSIZE 16384 +PREF_PHASE_LOG2REGIONSIZE 12 +PREF_PHASE_REGIONENTRIES 64 +PREF_PHASE_TRACKEDREGIONS 32 +PREF_PHASE_INTERVAL 100000 +PREF_PHASE_TABLE_SIZE 64 +PREF_PHASE_MAXDIFF_THRESH 64 +PREF_PHASE_MIN_MISSES 64 +PREF_PHASE_MISSPER 0.4 +PREF_2DC_ON FALSE +DEBUG_PREF_2DC FALSE +PREF_2DC_CACHE_SIZE (1 * 1024) +PREF_2DC_CACHE_ASSOC 4 +PREF_2DC_CACHE_LINE_SIZE 1 +PREF_2DC_DEGREE 16 +PREF_2DC_ZONE_SHIFT 10 +PREF_2DC_TAG_SIZE 16 +PREF_2DC_NUM_REGIONS 64 +PREF_2DC_REGION_HASH 61 +PREF_MARKOV_ON FALSE +DEBUG_PREF_MARKOV FALSE +PREF_MARKOV_NUM_ENTRIES 65536 +PREF_MARKOV_NUM_NEXT_STATES 8 +PREF_MARKOV_SEND_ON_PREF_HIT TRUE +PREF_MARKOV_UPDATE_ON_PREF_HIT TRUE +PREF_MARKOV_TABLE_UPDATE_POLICY 0 +PREF_MARKOV_SEND_THRESHOLD 0 +PREF_SMS_ON FALSE 1 +PREF_SMS_AT_SIZE 64 +PREF_SMS_FT_SIZE 64 +PREF_SMS_PHT_SIZE 16384 +PREF_SMS_PRF_SIZE 1024 +PREF_SMS_REGION_SIZE 2048 diff --git a/labs/LAB5/runs/xalancbmk_s_base-sms1/bp.stat.0.out b/labs/LAB5/runs/xalancbmk_s_base-sms1/bp.stat.0.out new file mode 100644 index 00000000..d52e0292 --- /dev/null +++ b/labs/LAB5/runs/xalancbmk_s_base-sms1/bp.stat.0.out @@ -0,0 +1,752 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 99495664 Instructions: 100000000 IPC: 1.00507 + +BTB_ON_PATH_MISS 260260 1.012% 260260 1.012% +BTB_ON_PATH_HIT 25446980 98.988% 25446980 98.988% + 25707240 100.000% 25707240 100.000% + 0.99 0.98 0.99 0.98 + +BTB_OFF_PATH_MISS 0 -nan% 0 -nan% +BTB_OFF_PATH_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +BTB_ON_PATH_WRITE 260260 100.000% 260260 100.000% +BTB_OFF_PATH_WRITE 0 0.000% 0 0.000% + 260260 100.000% 260260 100.000% + 0.00 0.00 0.00 0.00 + +BP_ON_PATH_CORRECT 25275249 98.320% 25275249 98.320% +BP_ON_PATH_MISPREDICT 45002 0.175% 45002 0.175% +BP_ON_PATH_MISFETCH 386989 1.505% 386989 1.505% + 25707240 100.000% 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0.000% +MEM_BLOCK_LENGTH_900 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_1000 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_1100 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_1200 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_1300 1 0.361% 1 0.361% +MEM_BLOCK_LENGTH_1400 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_1500 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_1600 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_1700 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_1800 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_1900 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_2000 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_2100 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_2200 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_2300 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_2400 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_2500 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_2600 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_2700 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_2800 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_2900 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_3000 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_3100 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_3200 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_3300 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_3400 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_3500 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_3600 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_3700 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_3800 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_3900 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4000 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4100 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4200 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4300 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4400 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4500 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4600 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4700 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4800 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_4900 0 0.000% 0 0.000% +MEM_BLOCK_LENGTH_5000 0 0.000% 0 0.000% + 277 100.000% 277 100.000% + 0.18 0.97 0.18 0.97 + +FUS_BUSY_ON_PATH 127858991 1.2851 127858991 1.2851 + +FUS_BUSY_OFF_PATH 0 0.0000 0 0.0000 + +FU_BUSY_MEM_STALL 4718840 0.0474 4718840 0.0474 + +FUS_EMPTY 668106321 6.7149 668106321 6.7149 + +CHIP_UTILIZATION 0 0.0000 0 0.0000 + +CYCLES_UNDER_MEM_REQ 0 0 + +CYCLES_UNDER_NO_MEM_REQ 0 0 + +CYCLES_UNDER_CRITICAL_MEM_REQ 0 0 + +CYCLES_UNDER_NONCRITICAL_MEM_REQ 0 0 + +CHIP_UTILIZATION_UNDER_MEM_REQ 0 -nan 0 -nan + +CHIP_UTILIZATION_UNDER_NO_MEM_REQ 0 -nan 0 -nan + +CHIP_UTILIZATION_UNDER_CRITICAL_MEM_REQ 0 -nan 0 -nan + +CHIP_UTILIZATION_UNDER_NONCRITICAL_MEM_REQ 0 -nan 0 -nan + +CYCLES_NOT_WAITING_FOR_OFF_CHIP 0 0.0000 0 0.0000 + +FUS_BUSY_NOT_WAITING_FOR_OFF_CHIP 0 -nan 0 -nan + +CYCLES_WAITING_FOR_OFF_CHIP 0 0.0000 0 0.0000 + +FUS_BUSY_WAITING_FOR_OFF_CHIP 0 -nan 0 -nan + +TOTAL_OFF_CHIP_DELAYS_LEFT 0 0 + +WRONG_IO_SCHED 0 0 + +DVFS_CONFIG_SWITCH 0 0 + + + diff --git a/labs/LAB5/runs/xalancbmk_s_base-sms1/fetch.stat.0.out b/labs/LAB5/runs/xalancbmk_s_base-sms1/fetch.stat.0.out new file mode 100644 index 00000000..3ed79d66 --- /dev/null +++ b/labs/LAB5/runs/xalancbmk_s_base-sms1/fetch.stat.0.out @@ -0,0 +1,248 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 99495664 Instructions: 100000000 IPC: 1.00507 + +ICACHE_CYCLE 99495664 99495664 + +TCACHE_CYCLE 0 0 + +ICACHE_CYCLE_ONPATH 47518383 47.759% 47518383 47.759% +ICACHE_CYCLE_OFFPATH 51977281 52.241% 51977281 52.241% + 99495664 100.000% 99495664 100.000% + 0.52 0.51 0.52 0.51 + +FETCH_ON_PATH 26945093 100.000% 26945093 100.000% +FETCH_OFF_PATH 0 0.000% 0 0.000% + 26945093 100.000% 26945093 100.000% + 0.00 0.00 0.00 0.00 + +FETCHED_OPS_ON_PATH 0 -nan% 0 -nan% +FETCHED_OPS_OFF_PATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +INST_LOST_WAIT_FOR_MISP_RECOVERY 0 0.000% 0 0.000% +INST_LOST_WAIT_FOR_TIMER 0 0.000% 0 0.000% +INST_LOST_WAIT_FOR_EMPTY_ROB 1950 0.001% 1950 0.001% +INST_LOST_WAIT_FOR_REDIRECT 10946916 3.763% 10946916 3.763% +INST_LOST_FETCH 122678521 42.174% 122678521 42.174% +INST_LOST_OFF_PATH 0 0.000% 0 0.000% +INST_LOST_FULL_WINDOW 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_OTHER 3110622 1.069% 3110622 1.069% +INST_LOST_ROB_STALL_WAIT_FOR_RECOVERY 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_REDIRECT 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_GAP_FILL 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_L1_MISS 0 0.000% 0 0.000% +INST_LOST_ROB_STALL_WAIT_FOR_MEMORY 25356 0.009% 25356 0.009% +INST_LOST_ROB_STALL_WAIT_FOR_DC_MISS 21388332 7.353% 21388332 7.353% +INST_LOST_ROB_BLOCK_ISSUE_FULL 0 0.000% 0 0.000% +INST_LOST_ROB_BLOCK_ISSUE_GAP_TOO_LARGE 0 0.000% 0 0.000% +INST_LOST_BREAK_DONT 0 0.000% 0 0.000% +INST_LOST_BREAK_ISSUE_WIDTH 0 0.000% 0 0.000% +INST_LOST_BREAK_CF 0 0.000% 0 0.000% +INST_LOST_BREAK_BTB_MISS 573056 0.197% 573056 0.197% +INST_LOST_BREAK_ICACHE_MISS 97876681 33.648% 97876681 33.648% +INST_LOST_BREAK_LINE_END 0 0.000% 0 0.000% +INST_LOST_BREAK_STALL 0 0.000% 0 0.000% +INST_LOST_BREAK_BARRIER 34 0.000% 34 0.000% +INST_LOST_BREAK_OFFPATH 25353 0.009% 25353 0.009% +INST_LOST_BREAK_ALIGNMENT 0 0.000% 0 0.000% +INST_LOST_BREAK_TAKEN 34258015 11.777% 34258015 11.777% +INST_LOST_BREAK_MODEL_BEFORE 0 0.000% 0 0.000% +INST_LOST_BREAK_MODEL_AFTER 0 0.000% 0 0.000% + 290884836 100.000% 290884836 100.000% + 12.66 8.64 12.66 8.64 + +INST_LOST_TOTAL 596973984 596973984 + +FETCH_0_OPS 22205819 45.803% 22205819 45.803% +FETCH_1_OPS 2378508 4.906% 2378508 4.906% +FETCH_2_OPS 1555709 3.209% 1555709 3.209% +FETCH_3_OPS 1451870 2.995% 1451870 2.995% +FETCH_4_OPS 5260469 10.851% 5260469 10.851% +FETCH_5_OPS 1979477 4.083% 1979477 4.083% +FETCH_6_OPS 13648954 28.153% 13648954 28.153% +FETCH_7_OPS 0 0.000% 0 0.000% +FETCH_8_OPS 0 0.000% 0 0.000% +FETCH_9_OPS 0 0.000% 0 0.000% +FETCH_10_OPS 0 0.000% 0 0.000% +FETCH_11_OPS 0 0.000% 0 0.000% +FETCH_12_OPS 0 0.000% 0 0.000% +FETCH_13_OPS 0 0.000% 0 0.000% +FETCH_14_OPS 0 0.000% 0 0.000% +FETCH_15_OPS 0 0.000% 0 0.000% +FETCH_16_OPS 0 0.000% 0 0.000% + 48480806 100.000% 48480806 100.000% + 2.53 2.00 2.53 2.00 + +ST_BREAK_DONT 0 0.000% 0 0.000% +ST_BREAK_ISSUE_WIDTH 11779773 43.718% 11779773 43.718% +ST_BREAK_CF 0 0.000% 0 0.000% +ST_BREAK_BTB_MISS 260260 0.966% 260260 0.966% +ST_BREAK_ICACHE_MISS 720333 2.673% 720333 2.673% +ST_BREAK_LINE_END 0 0.000% 0 0.000% +ST_BREAK_STALL 0 0.000% 0 0.000% +ST_BREAK_BARRIER 17 0.000% 17 0.000% +ST_BREAK_OFFPATH 13286 0.049% 13286 0.049% +ST_BREAK_ALIGNMENT 0 0.000% 0 0.000% +ST_BREAK_TAKEN 14171424 52.594% 14171424 52.594% + 26945093 100.000% 26945093 100.000% + 5.84 6.12 5.84 6.12 + +ORACLE_ON_PATH_INST 122678521 100.000% 122678521 100.000% +ORACLE_OFF_PATH_INST 0 0.000% 0 0.000% + 122678521 100.000% 122678521 100.000% + 0.00 0.00 0.00 0.00 + +ORACLE_ON_PATH_INST_MEM 36394722 29.667% 36394722 29.667% +ORACLE_ON_PATH_INST_NOTMEM 86283799 70.333% 86283799 70.333% +ORACLE_OFF_PATH_INST_MEM 0 0.000% 0 0.000% +ORACLE_OFF_PATH_INST_NOTMEM 0 0.000% 0 0.000% + 122678521 100.000% 122678521 100.000% + 0.70 0.25 0.70 0.25 + +ICACHE_CYCLE_NONRA_ONPATH 0 -nan% 0 -nan% +ICACHE_CYCLE_NONRA_OFFPATH 0 -nan% 0 -nan% +ICACHE_CYCLE_RA_ONPATH 0 -nan% 0 -nan% +ICACHE_CYCLE_RA_OFFPATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ICACHE_CYCLE_ONPATH_NONRA 0 -nan% 0 -nan% +ICACHE_CYCLE_OFFPATH_NONRA 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ICACHE_CYCLE_ONPATH_RA 0 -nan% 0 -nan% +ICACHE_CYCLE_OFFPATH_RA 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +INACCURATE_OFFPATH_CYCLES 0 0.0000 0 0.0000 + +FETCH_ALL_INST 122678521 122678521 + +EXEC_ALL_INST 122678470 122678470 + +RET_ALL_INST 122678423 122678423 + +EXEC_ON_PATH_INST 122678470 100.000% 122678470 100.000% +EXEC_OFF_PATH_INST 0 0.000% 0 0.000% + 122678470 100.000% 122678470 100.000% + 0.00 0.00 0.00 0.00 + +EXEC_ON_PATH_INST_MEM 36394712 29.667% 36394712 29.667% +EXEC_ON_PATH_INST_NOTMEM 86283758 70.333% 86283758 70.333% +EXEC_OFF_PATH_INST_MEM 0 0.000% 0 0.000% +EXEC_OFF_PATH_INST_NOTMEM 0 0.000% 0 0.000% + 122678470 100.000% 122678470 100.000% + 0.70 0.25 0.70 0.25 + +EXEC_RA_INST 0 -nan% 0 -nan% +EXEC_NONRA_INST 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +EXEC_ON_PATH_INST_RA 0 -nan% 0 -nan% +EXEC_OFF_PATH_INST_RA 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +EXEC_ON_PATH_INST_NONRA 0 -nan% 0 -nan% +EXEC_OFF_PATH_INST_NONRA 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +EXEC_RA_ON_PATH_INST 0 -nan% 0 -nan% +EXEC_RA_OFF_PATH_INST 0 -nan% 0 -nan% +EXEC_NONRA_ON_PATH_INST 0 -nan% 0 -nan% +EXEC_NONRA_OFF_PATH_INST 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +ICACHE_THROTTLE_CYCLE 0 0 + +FETCH_ENABLE_THROTTLE_OFF_PATH 0 -nan% 0 -nan% +FETCH_ENABLE_THROTTLE_ON_PATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +FETCH_DISABLE_THROTTLE_OFF_PATH 0 -nan% 0 -nan% +FETCH_DISABLE_THROTTLE_ON_PATH 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +FETCH_TH_ADJUST__0 0 -nan% 0 -nan% +FETCH_TH_ADJUST__1 0 -nan% 0 -nan% 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-nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_11 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_12 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_13 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_14 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_15 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_16 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_17 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_18 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_19 0 -nan% 0 -nan% +LOW_CONF_COUNT_BP_MIS_20 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +LOW_CONF_COUNT_RET_0 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_1 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_2 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_3 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_4 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_5 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_6 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_7 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_8 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_9 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_10 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_11 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_12 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_13 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_14 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_15 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_16 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_17 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_18 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_19 0 -nan% 0 -nan% +LOW_CONF_COUNT_RET_20 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + + + diff --git a/labs/LAB5/runs/xalancbmk_s_base-sms1/inst.stat.0.out b/labs/LAB5/runs/xalancbmk_s_base-sms1/inst.stat.0.out new file mode 100644 index 00000000..d7586819 --- /dev/null +++ b/labs/LAB5/runs/xalancbmk_s_base-sms1/inst.stat.0.out @@ -0,0 +1,103 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 99495664 Instructions: 100000000 IPC: 1.00507 + +ST_OP_INV 0 0.000% 0 0.000% +ST_OP_NOP 2194493 1.789% 2194493 1.789% +ST_OP_CF 25707257 20.955% 25707257 20.955% +ST_OP_MOV 9609563 7.833% 9609563 7.833% +ST_OP_CMOV 37882 0.031% 37882 0.031% +ST_OP_LDA 3328200 2.713% 3328200 2.713% +ST_OP_IMEM 36242566 29.543% 36242566 29.543% +ST_OP_IADD 20326400 16.569% 20326400 16.569% +ST_OP_IMUL 148805 0.121% 148805 0.121% +ST_OP_IDIV 24299 0.020% 24299 0.020% +ST_OP_ICMP 13665531 11.139% 13665531 11.139% +ST_OP_LOGIC 10291006 8.389% 10291006 8.389% +ST_OP_SHIFT 950333 0.775% 950333 0.775% +ST_OP_FMEM 152156 0.124% 152156 0.124% +ST_OP_FCVT 20 0.000% 20 0.000% +ST_OP_FADD 0 0.000% 0 0.000% +ST_OP_FMUL 10 0.000% 10 0.000% +ST_OP_FMA 0 0.000% 0 0.000% +ST_OP_FDIV 0 0.000% 0 0.000% +ST_OP_FCMP 0 0.000% 0 0.000% +ST_OP_FCMOV 0 0.000% 0 0.000% +ST_OP_GATHER 0 0.000% 0 0.000% +ST_OP_SCATTER 0 0.000% 0 0.000% +ST_OP_PIPELINED_FAST 0 0.000% 0 0.000% +ST_OP_PIPELINED_MEDIUM 0 0.000% 0 0.000% +ST_OP_PIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_MEDIUM 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_SLOW 0 0.000% 0 0.000% +ST_OP_NOTPIPELINED_VERY_SLOW 0 0.000% 0 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a/labs/LAB5/runs/xalancbmk_s_base-sms1/l2l1pref.stat.0.out b/labs/LAB5/runs/xalancbmk_s_base-sms1/l2l1pref.stat.0.out new file mode 100644 index 00000000..515a9e6b --- /dev/null +++ b/labs/LAB5/runs/xalancbmk_s_base-sms1/l2l1pref.stat.0.out @@ -0,0 +1,140 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 99495664 Instructions: 100000000 IPC: 1.00507 + +L2WAY_FILL_L1 0 0 + +L2WAY_WAY_HIT 0 -nan% 0 -nan% +L2WAY_WAY_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_PREF_REQ 0 0 + +L2WAY_PREF_HIT_DATA_IN_CACHE 0 -nan% 0 -nan% +L2WAY_PREF_HIT_DATA_REQ 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2WAY_TRAIN_HIT 0 -nan% 0 -nan% +L2WAY_TRAIN_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L1_HIT_REQ_TYPE_IFETCH 0 -nan% 0 -nan% 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108.4075 + +CORE_L1_MISS_LATENCY_PREF 23896077 106.0314 23896077 106.0314 + +CORE_EVICTED_L1_DEMAND 676787 75.290% 676787 75.290% +CORE_EVICTED_L1_PREF_USED 83701 9.311% 83701 9.311% +CORE_EVICTED_L1_PREF_NOT_USED 138417 15.398% 138417 15.398% + 898905 100.000% 898905 100.000% + 0.40 0.67 0.40 0.67 + +CORE_EVICTED_MLC_DEMAND 0 -nan% 0 -nan% +CORE_EVICTED_MLC_PREF_USED 0 -nan% 0 -nan% +CORE_EVICTED_MLC_PREF_NOT_USED 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +CORE_MEM_LATENCY_AVE_DEMAND 73340875 108.3663 73340875 108.3663 + +CORE_MEM_LATENCY_AVE_PREF_USED 8603759 102.7916 8603759 102.7916 + +CORE_MEM_LATENCY_AVE_PREF_NOT_USED 14943958 107.9633 14943958 107.9633 + +DRAM_LATENCY 0 0 + +TOTAL_DRAM_LATENCY 0 0 + +DRAM_CLOSED_PAGE_POLICY_CMD 0 0 + +DRAM_ACTIVATE_STALLING 0 0 + +DRAM_PRECHARGE_STALLING 0 0 + +DRAM_PRECHARGE_STALLING_WAIT_CYCLES 0 0 + +L1_STAY_DEMAND 1158011274045 1711042.4314 1158011274045 1711042.4314 + +L1_STAY_PREF_USED 165455431941 1976743.7897 165455431941 1976743.7897 + +L1_STAY_PREF_NOT_USED 211417385097 1527394.6488 211417385097 1527394.6488 + +TOTAL_DATA_MISS_LATENCY 73879827 73879827 + +TOTAL_DATA_MISS_COUNT 680673 680673 + +CORE_PREF_L1_NOT_USED_LATENCY200 128724 92.997% 128724 92.997% +CORE_PREF_L1_NOT_USED_LATENCY400 6666 4.816% 6666 4.816% +CORE_PREF_L1_NOT_USED_LATENCY600 1320 0.954% 1320 0.954% +CORE_PREF_L1_NOT_USED_LATENCY800 312 0.225% 312 0.225% +CORE_PREF_L1_NOT_USED_LATENCY1000 151 0.109% 151 0.109% +CORE_PREF_L1_NOT_USED_LATENCY1200 268 0.194% 268 0.194% +CORE_PREF_L1_NOT_USED_LATENCY1400 750 0.542% 750 0.542% +CORE_PREF_L1_NOT_USED_LATENCY1600 190 0.137% 190 0.137% +CORE_PREF_L1_NOT_USED_LATENCY1600MORE 36 0.026% 36 0.026% + 138417 100.000% 138417 100.000% + 0.13 0.65 0.13 0.65 + +CORE_PREF_L1_NOT_USED_DISTANCE_1 0 0.000% 0 0.000% +CORE_PREF_L1_NOT_USED_DISTANCE_2 11821 8.540% 11821 8.540% +CORE_PREF_L1_NOT_USED_DISTANCE_4 26357 19.042% 26357 19.042% +CORE_PREF_L1_NOT_USED_DISTANCE_8 56267 40.650% 56267 40.650% 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+PERF_PRED_NUM_STAT_RESETS 0 0 + +PERF_PRED_RESET_STATS_CYCLE 0 0 + +PERF_PRED_CYCLE 99495664 99495664 + +ESTIMATED_ALONE_CYCLES 0 0.0000 0 0.0000 + +NUM_WINDOWS_WITH_DCACHE_MISS 384032 384032 + +LONGEST_DCACHE_MISS_CHAIN 1776047 1776047 + +NUM_DCACHE_MISSES_IN_WINDOW_1 15314 3.988% 15314 3.988% +NUM_DCACHE_MISSES_IN_WINDOW_2 14533 3.784% 14533 3.784% +NUM_DCACHE_MISSES_IN_WINDOW_3 16774 4.368% 16774 4.368% +NUM_DCACHE_MISSES_IN_WINDOW_4 19932 5.190% 19932 5.190% +NUM_DCACHE_MISSES_IN_WINDOW_5 37220 9.692% 37220 9.692% +NUM_DCACHE_MISSES_IN_WINDOW_6 64204 16.718% 64204 16.718% +NUM_DCACHE_MISSES_IN_WINDOW_7 64616 16.826% 64616 16.826% +NUM_DCACHE_MISSES_IN_WINDOW_8 47216 12.295% 47216 12.295% +NUM_DCACHE_MISSES_IN_WINDOW_9 24663 6.422% 24663 6.422% +NUM_DCACHE_MISSES_IN_WINDOW_10 15927 4.147% 15927 4.147% +NUM_DCACHE_MISSES_IN_WINDOW_11 16578 4.317% 16578 4.317% +NUM_DCACHE_MISSES_IN_WINDOW_12 12468 3.247% 12468 3.247% +NUM_DCACHE_MISSES_IN_WINDOW_13 8208 2.137% 8208 2.137% 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-nan -nan + +MEM_REQ_DEMANDS__0 94191253 94.669% 94191253 94.669% +MEM_REQ_DEMANDS__4 5255902 5.283% 5255902 5.283% +MEM_REQ_DEMANDS__8 19285 0.019% 19285 0.019% +MEM_REQ_DEMANDS_12 8609 0.009% 8609 0.009% +MEM_REQ_DEMANDS_16 5228 0.005% 5228 0.005% +MEM_REQ_DEMANDS_20 2455 0.002% 2455 0.002% +MEM_REQ_DEMANDS_24 1290 0.001% 1290 0.001% +MEM_REQ_DEMANDS_28 11642 0.012% 11642 0.012% +MEM_REQ_DEMANDS_32 0 0.000% 0 0.000% +MEM_REQ_DEMANDS_36 0 0.000% 0 0.000% +MEM_REQ_DEMANDS_40 0 0.000% 0 0.000% +MEM_REQ_DEMANDS_44 0 0.000% 0 0.000% +MEM_REQ_DEMANDS_48 0 0.000% 0 0.000% +MEM_REQ_DEMANDS_52 0 0.000% 0 0.000% +MEM_REQ_DEMANDS_56 0 0.000% 0 0.000% +MEM_REQ_DEMANDS_60 0 0.000% 0 0.000% +MEM_REQ_DEMANDS_64 0 0.000% 0 0.000% + 99495664 100.000% 99495664 100.000% + 0.05 0.24 0.05 0.24 + +MEM_REQ_PREFS__0 97674168 98.169% 97674168 98.169% +MEM_REQ_PREFS__4 1313415 1.320% 1313415 1.320% +MEM_REQ_PREFS__8 334176 0.336% 334176 0.336% +MEM_REQ_PREFS_12 97961 0.098% 97961 0.098% +MEM_REQ_PREFS_16 40034 0.040% 40034 0.040% +MEM_REQ_PREFS_20 18173 0.018% 18173 0.018% +MEM_REQ_PREFS_24 15378 0.015% 15378 0.015% +MEM_REQ_PREFS_28 2359 0.002% 2359 0.002% +MEM_REQ_PREFS_32 0 0.000% 0 0.000% +MEM_REQ_PREFS_36 0 0.000% 0 0.000% +MEM_REQ_PREFS_40 0 0.000% 0 0.000% +MEM_REQ_PREFS_44 0 0.000% 0 0.000% +MEM_REQ_PREFS_48 0 0.000% 0 0.000% +MEM_REQ_PREFS_52 0 0.000% 0 0.000% +MEM_REQ_PREFS_56 0 0.000% 0 0.000% +MEM_REQ_PREFS_60 0 0.000% 0 0.000% +MEM_REQ_PREFS_64 0 0.000% 0 0.000% + 99495664 100.000% 99495664 100.000% + 0.03 0.23 0.03 0.23 + +MEM_REQ_WRITEBACKS__0 99486818 99.991% 99486818 99.991% +MEM_REQ_WRITEBACKS__4 8792 0.009% 8792 0.009% +MEM_REQ_WRITEBACKS__8 54 0.000% 54 0.000% +MEM_REQ_WRITEBACKS_12 0 0.000% 0 0.000% +MEM_REQ_WRITEBACKS_16 0 0.000% 0 0.000% +MEM_REQ_WRITEBACKS_20 0 0.000% 0 0.000% +MEM_REQ_WRITEBACKS_24 0 0.000% 0 0.000% +MEM_REQ_WRITEBACKS_28 0 0.000% 0 0.000% +MEM_REQ_WRITEBACKS_32 0 0.000% 0 0.000% +MEM_REQ_WRITEBACKS_36 0 0.000% 0 0.000% +MEM_REQ_WRITEBACKS_40 0 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b/labs/LAB5/runs/xalancbmk_s_base-sms1/power.stat.0.out @@ -0,0 +1,184 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 99495664 Instructions: 100000000 IPC: 1.00507 + +POWER_STATS_BEGIN 0 0 + +POWER_TIME 31092395000000 31092395000000 + +POWER_CYCLE 99495664 99495664 + +POWER_ITLB_ACCESS 37311449 37311449 + +POWER_DTLB_ACCESS 7518274 7518274 + +POWER_ICACHE_ACCESS 37311449 37311449 + +POWER_ICACHE_MISS 720333 720333 + +POWER_BTB_READ 37311449 37311449 + +POWER_BTB_WRITE 431991 431991 + +POWER_ROB_READ 122678470 122678470 + +POWER_ROB_WRITE 122678470 122678470 + +POWER_RENAME_READ 245356940 245356940 + +POWER_RENAME_WRITE 122678470 122678470 + +POWER_FP_RENAME_READ 0 0 + +POWER_FP_RENAME_WRITE 0 0 + +POWER_FUNCTION_CALL 1375050 1375050 + +POWER_INST_WINDOW_READ 122678470 122678470 + +POWER_INST_WINDOW_WRITE 122678470 122678470 + +POWER_INT_REGFILE_READ 138776099 138776099 + +POWER_INT_REGFILE_WRITE 102427755 102427755 + +POWER_IALU_ACCESS 122505366 122505366 + +POWER_CDB_IALU_ACCESS 122505366 122505366 + +POWER_MUL_ACCESS 173104 173104 + +POWER_CDB_MUL_ACCESS 173104 173104 + +POWER_FP_INST_WINDOW_WRITE 0 0 + +POWER_FP_INST_WINDOW_READ 0 0 + +POWER_FP_REGFILE_READ 0 0 + +POWER_FP_REGFILE_WRITE 0 0 + +POWER_FPU_ACCESS 0 0 + +POWER_CDB_FPU_ACCESS 0 0 + +POWER_DCACHE_READ_ACCESS 28884559 28884559 + +POWER_DCACHE_WRITE_ACCESS 7526468 7526468 + +POWER_DCACHE_READ_MISS 6334529 6334529 + +POWER_DCACHE_WRITE_MISS 607011 607011 + +POWER_MLC_READ_ACCESS 0 0 + +POWER_MLC_WRITE_ACCESS 0 0 + +POWER_MLC_READ_MISS 0 0 + +POWER_MLC_WRITE_MISS 0 0 + +POWER_LLC_READ_ACCESS 3321957 3321957 + +POWER_LLC_WRITE_ACCESS 265168 265168 + +POWER_LLC_READ_MISS 914973 914973 + +POWER_LLC_WRITE_MISS 316 316 + +POWER_MEMORY_ACCESS 0 0 + +POWER_MEMORY_READ_ACCESS 0 0 + +POWER_MEMORY_WRITE_ACCESS 0 0 + +POWER_INST_WINDOW_WAKEUP_ACCESS 122678470 122678470 + +POWER_FP_INST_WINDOW_WAKEUP_ACCESS 0 0 + +POWER_L1DIREC_READ_ACCESS 0 0 + +POWER_L1DIREC_WRITE_ACCESS 0 0 + +POWER_L1DIREC_READ_MISS 0 0 + +POWER_L1DIREC_WRITE_MISS 0 0 + +POWER_L2DIREC_READ_ACCESS 0 0 + +POWER_L2DIREC_WRITE_ACCESS 0 0 + +POWER_L2DIREC_READ_MISS 0 0 + +POWER_L2DIREC_WRITE_MISS 0 0 + +POWER_MEMORY_CTRL_ACCESS 951475 951475 + +POWER_MEMORY_CTRL_READ 914973 914973 + +POWER_MEMORY_CTRL_WRITE 36502 36502 + +POWER_OP 122678470 122678470 + +POWER_INT_OP 120331793 120331793 + +POWER_FP_OP 152184 152184 + +POWER_LD_OP 28876438 28876438 + +POWER_ST_OP 7518274 7518274 + +POWER_BRANCH_MISPREDICT 431991 431991 + +POWER_COMMITTED_OP 122678470 122678470 + +POWER_COMMITTED_INT_OP 120331793 120331793 + +POWER_COMMITTED_FP_OP 2346677 2346677 + +POWER_BRANCH_OP 25707245 25707245 + +POWER_DRAM_PRECHARGE 207813 207813 + +POWER_DRAM_ACTIVATE 256691 256691 + +POWER_DRAM_READ 913949 913949 + +POWER_DRAM_WRITE 36497 36497 + +POWER_STATS_END 0 0 + +ENERGY 0.000000 0.000000 + +ENERGY_CORE 0.000000 0.000000 + +ENERGY_UNCORE 0.000000 0.000000 + +ENERGY_MEMORY 0.000000 0.000000 + +ENERGY_OTHER 0.000000 0.000000 + +ENERGY_CORE_STATIC 0.000000 0.000000 + +ENERGY_CORE_DYNAMIC 0.000000 0.000000 + +ENERGY_UNCORE_STATIC 0.000000 0.000000 + +ENERGY_UNCORE_DYNAMIC 0.000000 0.000000 + +ENERGY_MEMORY_STATIC 0.000000 0.000000 + +ENERGY_MEMORY_DYNAMIC 0.000000 0.000000 + +ENERGY_OTHER_STATIC 0.000000 0.000000 + +ENERGY_OTHER_DYNAMIC 0.000000 0.000000 + +TIME 0.000000 0.000000 + +ENERGY_STATS_END 0 0 + + + diff --git a/labs/LAB5/runs/xalancbmk_s_base-sms1/pref.stat.0.out b/labs/LAB5/runs/xalancbmk_s_base-sms1/pref.stat.0.out new file mode 100644 index 00000000..7e4c3462 --- /dev/null +++ b/labs/LAB5/runs/xalancbmk_s_base-sms1/pref.stat.0.out @@ -0,0 +1,208 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 99495664 Instructions: 100000000 IPC: 1.00507 + +PREF_DL0REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UMLC_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_UL1REQ_QUEUE_HIT_BY_DEMAND 0 0 + +PREF_DL0REQ_QUEUE_FULL 0 0 + +PREF_UMLC_REQ_QUEUE_FULL 0 0 + +PREF_UL1REQ_QUEUE_FULL 0 0 + +PREF_DC_HIT_NOSEND 0 0 + +PREF_WBQDC_HIT_NOSEND 0 0 + +PREF_MLCQ_STALL 0 0 + +PREF_L1Q_STALL 0 0 + +PREF_UMLC_REQ_SEND_QUEUE_STALL 0 0 + +PREF_UL1REQ_SEND_QUEUE_STALL 20623 20623 + +PREF_UMLC_REQ_QUEUE_SENTREQ 0 0 + +PREF_UL1REQ_QUEUE_SENTREQ 368011 368011 + +PREF_NEWREQ_MATCHED 19721 19721 + +PREF_UMLC_REQ_QUEUE_MATCHED_REQ 0 0 + +PREF_UL1REQ_QUEUE_MATCHED_REQ 3540 3540 + +PREF_DL0REQ_QUEUE_MATCHED_REQ 0 0 + +L1_PREF_HIT 231140 231140 + +L1_PREF_UNIQUE_HIT 69299 69299 + +L1_PREF_LATE 16896 16896 + +L1_LATE_PREF_CYCLES 1072621 1072621 + +L1_LATE_PREF_CYCLES_DIST_0 14686 86.920% 14686 86.920% +L1_LATE_PREF_CYCLES_DIST_100 1784 10.559% 1784 10.559% +L1_LATE_PREF_CYCLES_DIST_200 188 1.113% 188 1.113% +L1_LATE_PREF_CYCLES_DIST_300 97 0.574% 97 0.574% +L1_LATE_PREF_CYCLES_DIST_400 29 0.172% 29 0.172% +L1_LATE_PREF_CYCLES_DIST_500 16 0.095% 16 0.095% +L1_LATE_PREF_CYCLES_DIST_600 7 0.041% 7 0.041% +L1_LATE_PREF_CYCLES_DIST_700 2 0.012% 2 0.012% +L1_LATE_PREF_CYCLES_DIST_800 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_900 12 0.071% 12 0.071% +L1_LATE_PREF_CYCLES_DIST_1000 13 0.077% 13 0.077% +L1_LATE_PREF_CYCLES_DIST_1100 18 0.107% 18 0.107% +L1_LATE_PREF_CYCLES_DIST_1200 37 0.219% 37 0.219% +L1_LATE_PREF_CYCLES_DIST_1300 4 0.024% 4 0.024% +L1_LATE_PREF_CYCLES_DIST_1400 3 0.018% 3 0.018% +L1_LATE_PREF_CYCLES_DIST_1500 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1600 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1700 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1800 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_1900 0 0.000% 0 0.000% +L1_LATE_PREF_CYCLES_DIST_2000 0 0.000% 0 0.000% + 16896 100.000% 16896 100.000% + 0.22 0.92 0.22 0.92 + +MLC_PREF_HIT 0 0 + +MLC_PREF_UNIQUE_HIT 0 0 + +MLC_PREF_LATE 0 0 + +PREF_HYBRID_SEL_0 0 -nan% 0 -nan% +PREF_HYBRID_SEL_1 0 -nan% 0 -nan% +PREF_HYBRID_SEL_2 0 -nan% 0 -nan% +PREF_HYBRID_SEL_3 0 -nan% 0 -nan% +PREF_HYBRID_SEL_4 0 -nan% 0 -nan% +PREF_HYBRID_SEL_5 0 -nan% 0 -nan% +PREF_HYBRID_SEL_6 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_DISTANCE_1 43 39.450% 43 39.450% +PREF_DISTANCE_2 35 32.110% 35 32.110% +PREF_DISTANCE_3 24 22.018% 24 22.018% +PREF_DISTANCE_4 7 6.422% 7 6.422% +PREF_DISTANCE_5 0 0.000% 0 0.000% +PREF_DISTANCE_6 0 0.000% 0 0.000% +PREF_DISTANCE_7 0 0.000% 0 0.000% +PREF_DISTANCE_8 0 0.000% 0 0.000% +PREF_DISTANCE_9 0 0.000% 0 0.000% +PREF_DISTANCE_10 0 0.000% 0 0.000% + 109 100.000% 109 100.000% + 0.95 0.72 0.95 0.72 + +PREF_REPL_MRU 0 -nan% 0 -nan% +PREF_REPL_MID 0 -nan% 0 -nan% +PREF_REPL_LOWQTR 0 -nan% 0 -nan% +PREF_REPL_LRU 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_REPL_MOVEDOWN 0 -nan% 0 -nan% +PREF_REPL_MOVEUP 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_COV_1 0 -nan% 0 -nan% +PREF_COV_2 0 -nan% 0 -nan% +PREF_COV_3 0 -nan% 0 -nan% +PREF_COV_4 0 -nan% 0 -nan% +PREF_COV_5 0 -nan% 0 -nan% +PREF_COV_6 0 -nan% 0 -nan% +PREF_COV_7 0 -nan% 0 -nan% +PREF_COV_8 0 -nan% 0 -nan% +PREF_COV_9 0 -nan% 0 -nan% +PREF_COV_10 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_POL_1 0 0.000% 0 0.000% +PREF_POL_2 0 0.000% 0 0.000% +PREF_POL_3 0 0.000% 0 0.000% +PREF_POL_4 0 0.000% 0 0.000% +PREF_POL_5 0 0.000% 0 0.000% +PREF_POL_6 0 0.000% 0 0.000% +PREF_POL_7 0 0.000% 0 0.000% +PREF_POL_8 0 0.000% 0 0.000% +PREF_POL_9 0 0.000% 0 0.000% +PREF_POL_10 109 100.000% 109 100.000% + 109 100.000% 109 100.000% + 9.00 9.04 9.00 9.04 + +PREF_ACC_1 0 0.000% 0 0.000% +PREF_ACC_2 0 0.000% 0 0.000% +PREF_ACC_3 0 0.000% 0 0.000% +PREF_ACC_4 0 0.000% 0 0.000% +PREF_ACC_5 10 9.174% 10 9.174% +PREF_ACC_6 31 28.440% 31 28.440% +PREF_ACC_7 59 54.128% 59 54.128% +PREF_ACC_8 9 8.257% 9 8.257% +PREF_ACC_9 0 0.000% 0 0.000% +PREF_ACC_10 0 0.000% 0 0.000% + 109 100.000% 109 100.000% + 5.61 0.77 5.61 0.77 + +PREF_TIMELY_1 0 0.000% 0 0.000% +PREF_TIMELY_2 0 0.000% 0 0.000% +PREF_TIMELY_3 0 0.000% 0 0.000% +PREF_TIMELY_4 0 0.000% 0 0.000% +PREF_TIMELY_5 0 0.000% 0 0.000% +PREF_TIMELY_6 0 0.000% 0 0.000% +PREF_TIMELY_7 0 0.000% 0 0.000% +PREF_TIMELY_8 57 52.294% 57 52.294% +PREF_TIMELY_9 49 44.954% 49 44.954% +PREF_TIMELY_10 3 2.752% 3 2.752% + 109 100.000% 109 100.000% + 7.50 1.37 7.50 1.37 + +PREF_UNUSED_EVICT 138417 138417 + +PREF_REGION_SENT 0 0 + +PREF_REGION_USEFUL 0 0 + +PREF_REGION_EVICT 0 0 + +PREF_PFPOL 0 0 + +PREF_PHASE_NEWPHASE_DET 0 0 + +PREF_PHASE_NEWPHASE_NOTVALID 0 0 + +PREF_PHASE_SENTPREF 0 0 + +PREF_PHASE_OVERWRITE_PAGE 0 0 + +PREF_UPDATE_COUNT 109 109 + +PREF_ACC1_HT_HP 0 0.000% 0 0.000% +PREF_ACC1_HT_LP 0 0.000% 0 0.000% +PREF_ACC1_LT_HP 0 0.000% 0 0.000% +PREF_ACC1_LT_LP 0 0.000% 0 0.000% +PREF_ACC2_HT_HP 0 0.000% 0 0.000% +PREF_ACC2_HT_LP 0 0.000% 0 0.000% +PREF_ACC2_LT_HP 0 0.000% 0 0.000% +PREF_ACC2_LT_LP 41 37.615% 41 37.615% +PREF_ACC3_HT_HP 0 0.000% 0 0.000% +PREF_ACC3_HT_LP 0 0.000% 0 0.000% +PREF_ACC3_LT_HP 0 0.000% 0 0.000% +PREF_ACC3_LT_LP 0 0.000% 0 0.000% +PREF_ACC4_HT_HP 0 0.000% 0 0.000% +PREF_ACC4_HT_LP 0 0.000% 0 0.000% +PREF_ACC4_LT_HP 0 0.000% 0 0.000% +PREF_ACC4_LT_LP 68 62.385% 68 62.385% + 109 100.000% 109 100.000% + 11.99 10.28 11.99 10.28 + + + diff --git a/labs/LAB5/runs/xalancbmk_s_base-sms1/ramulator.stat.out b/labs/LAB5/runs/xalancbmk_s_base-sms1/ramulator.stat.out new file mode 100644 index 00000000..1d7e183c --- /dev/null +++ b/labs/LAB5/runs/xalancbmk_s_base-sms1/ramulator.stat.out @@ -0,0 +1,150 @@ + ramulator.active_cycles_0 23913117 # Total active cycles for level _0 + ramulator.busy_cycles_0 23913117 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0 + ramulator.serving_requests_0 41709667 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.average_serving_requests_0 1.117895 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0 + ramulator.active_cycles_0_0 23913117 # Total active cycles for level _0_0 + ramulator.busy_cycles_0_0 24884577 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0 + ramulator.serving_requests_0_0 41709667 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.average_serving_requests_0_0 1.117895 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0 + ramulator.active_cycles_0_0_0 7363395 # Total active cycles for level _0_0_0 + ramulator.busy_cycles_0_0_0 7363395 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0 + ramulator.serving_requests_0_0_0 9316991 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 +ramulator.average_serving_requests_0_0_0 0.249712 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0 + ramulator.active_cycles_0_0_0_0 1781818 # Total active cycles for level _0_0_0_0 + ramulator.busy_cycles_0_0_0_0 1781818 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_0 + ramulator.serving_requests_0_0_0_0 2065605 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 +ramulator.average_serving_requests_0_0_0_0 0.055362 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_0 + ramulator.active_cycles_0_0_0_1 2807535 # Total active cycles for level _0_0_0_1 + ramulator.busy_cycles_0_0_0_1 2807535 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_1 + ramulator.serving_requests_0_0_0_1 3228424 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 +ramulator.average_serving_requests_0_0_0_1 0.086528 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_1 + ramulator.active_cycles_0_0_0_2 1941937 # Total active cycles for level _0_0_0_2 + ramulator.busy_cycles_0_0_0_2 1941937 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_2 + ramulator.serving_requests_0_0_0_2 2286753 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 +ramulator.average_serving_requests_0_0_0_2 0.061289 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_2 + ramulator.active_cycles_0_0_0_3 1454008 # Total active cycles for level _0_0_0_3 + ramulator.busy_cycles_0_0_0_3 1454008 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_0_3 + ramulator.serving_requests_0_0_0_3 1736209 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 +ramulator.average_serving_requests_0_0_0_3 0.046534 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_0_3 + ramulator.active_cycles_0_0_1 8351344 # Total active cycles for level _0_0_1 + ramulator.busy_cycles_0_0_1 8351344 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1 + ramulator.serving_requests_0_0_1 10671013 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 +ramulator.average_serving_requests_0_0_1 0.286003 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1 + ramulator.active_cycles_0_0_1_0 2207064 # Total active cycles for level _0_0_1_0 + ramulator.busy_cycles_0_0_1_0 2207064 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_0 + ramulator.serving_requests_0_0_1_0 2565844 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 +ramulator.average_serving_requests_0_0_1_0 0.068769 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_0 + ramulator.active_cycles_0_0_1_1 2391610 # Total active cycles for level _0_0_1_1 + ramulator.busy_cycles_0_0_1_1 2391610 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_1 + ramulator.serving_requests_0_0_1_1 2738079 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 +ramulator.average_serving_requests_0_0_1_1 0.073386 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_1 + ramulator.active_cycles_0_0_1_2 2631364 # Total active cycles for level _0_0_1_2 + ramulator.busy_cycles_0_0_1_2 2631364 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_2 + ramulator.serving_requests_0_0_1_2 2944330 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 +ramulator.average_serving_requests_0_0_1_2 0.078913 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_2 + ramulator.active_cycles_0_0_1_3 2058463 # Total active cycles for level _0_0_1_3 + ramulator.busy_cycles_0_0_1_3 2058463 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_1_3 + ramulator.serving_requests_0_0_1_3 2422760 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 +ramulator.average_serving_requests_0_0_1_3 0.064934 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_1_3 + ramulator.active_cycles_0_0_2 8569361 # Total active cycles for level _0_0_2 + ramulator.busy_cycles_0_0_2 8569361 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2 + ramulator.serving_requests_0_0_2 10864525 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 +ramulator.average_serving_requests_0_0_2 0.291189 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2 + ramulator.active_cycles_0_0_2_0 1905683 # Total active cycles for level _0_0_2_0 + ramulator.busy_cycles_0_0_2_0 1905683 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_0 + ramulator.serving_requests_0_0_2_0 2174011 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 +ramulator.average_serving_requests_0_0_2_0 0.058267 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_0 + ramulator.active_cycles_0_0_2_1 2929103 # Total active cycles for level _0_0_2_1 + ramulator.busy_cycles_0_0_2_1 2929103 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_1 + ramulator.serving_requests_0_0_2_1 3278148 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 +ramulator.average_serving_requests_0_0_2_1 0.087860 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_1 + ramulator.active_cycles_0_0_2_2 1824409 # Total active cycles for level _0_0_2_2 + ramulator.busy_cycles_0_0_2_2 1824409 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_2 + ramulator.serving_requests_0_0_2_2 2069362 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 +ramulator.average_serving_requests_0_0_2_2 0.055463 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_2 + ramulator.active_cycles_0_0_2_3 2926354 # Total active cycles for level _0_0_2_3 + ramulator.busy_cycles_0_0_2_3 2926354 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_2_3 + ramulator.serving_requests_0_0_2_3 3343004 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 +ramulator.average_serving_requests_0_0_2_3 0.089599 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_2_3 + ramulator.active_cycles_0_0_3 8633093 # Total active cycles for level _0_0_3 + ramulator.busy_cycles_0_0_3 8633093 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3 + ramulator.serving_requests_0_0_3 10856398 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 +ramulator.average_serving_requests_0_0_3 0.290971 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3 + ramulator.active_cycles_0_0_3_0 2421107 # Total active cycles for level _0_0_3_0 + ramulator.busy_cycles_0_0_3_0 2421107 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_0 + ramulator.serving_requests_0_0_3_0 2778574 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 +ramulator.average_serving_requests_0_0_3_0 0.074471 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_0 + ramulator.active_cycles_0_0_3_1 1313825 # Total active cycles for level _0_0_3_1 + ramulator.busy_cycles_0_0_3_1 1313825 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_1 + ramulator.serving_requests_0_0_3_1 1571863 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 +ramulator.average_serving_requests_0_0_3_1 0.042129 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_1 + ramulator.active_cycles_0_0_3_2 3403729 # Total active cycles for level _0_0_3_2 + ramulator.busy_cycles_0_0_3_2 3403729 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_2 + ramulator.serving_requests_0_0_3_2 3872777 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 +ramulator.average_serving_requests_0_0_3_2 0.103798 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_2 + ramulator.active_cycles_0_0_3_3 2259234 # Total active cycles for level _0_0_3_3 + ramulator.busy_cycles_0_0_3_3 2259234 # (All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level _0_0_3_3 + ramulator.serving_requests_0_0_3_3 2621782 # The sum of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 +ramulator.average_serving_requests_0_0_3_3 0.070269 # The average of read and write requests that are served in this DRAM element per memory cycle for level _0_0_3_3 + ramulator.read_transaction_bytes_0 58492736 # The total byte of read transaction per channel + ramulator.write_transaction_bytes_0 2335872 # The total byte of write transaction per channel + ramulator.row_hits_channel_0_core 693760 # Number of row hits per channel per core + ramulator.row_misses_channel_0_core 53726 # Number of row misses per channel per core + ramulator.row_conflicts_channel_0_core 202961 # Number of row conflicts per channel per core + ramulator.read_row_hits_channel_0_core 676206 # Number of row hits for read requests per channel per core + [0] 676206.0 # +ramulator.read_row_misses_channel_0_core 50175 # Number of row misses for read requests per channel per core + [0] 50175.0 # +ramulator.read_row_conflicts_channel_0_core 187568 # Number of row conflicts for read requests per channel per core + [0] 187568.0 # + ramulator.write_row_hits_channel_0_core 17554 # Number of row hits for write requests per channel per core + [0] 17554.0 # +ramulator.write_row_misses_channel_0_core 3551 # Number of row misses for write requests per channel per core + [0] 3551.0 # +ramulator.write_row_conflicts_channel_0_core 15393 # Number of row conflicts for write requests per channel per core + [0] 15393.0 # + ramulator.useless_activates_0_core 8 # Number of useless activations. E.g, ACT -> PRE w/o RD or WR + ramulator.read_latency_avg_0 40.759840 # The average memory latency cycles (in memory time domain) per request for all read requests in this channel + ramulator.read_latency_sum_0 37294153 # The memory latency cycles (in memory time domain) sum for all read requests in this channel + ramulator.req_queue_length_avg_0 15.288103 # Average of read and write queue length per memory cycle per channel. + ramulator.req_queue_length_sum_0 570412716 # Sum of read and write queue length per memory cycle per channel. + ramulator.read_req_queue_length_avg_0 0.897305 # Read queue length average per memory cycle per channel. + ramulator.read_req_queue_length_sum_0 33479232 # Read queue length sum per memory cycle per channel. + ramulator.write_req_queue_length_avg_0 14.390799 # Write queue length average per memory cycle per channel. + ramulator.write_req_queue_length_sum_0 536933484 # Write queue length sum per memory cycle per channel. + ramulator.record_read_hits 0.0 # record read hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_misses 0.0 # record_read_miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_read_conflicts 0.0 # record read conflict count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_hits 0.0 # record write hit count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_misses 0.0 # record write miss count for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_conflicts 0.0 # record write conflict for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.dram_capacity 8589934592 # Number of bytes in simulated DRAM + ramulator.dram_cycles 37310888 # Number of DRAM cycles simulated + ramulator.incoming_requests 951475 # Number of incoming requests to DRAM + ramulator.read_requests 914973 # Number of incoming read requests to DRAM per core + [0] 914973.0 # + ramulator.write_requests 36502 # Number of incoming write requests to DRAM per core + [0] 36502.0 # + ramulator.ramulator_active_cycles 23913177 # The total number of cycles that the DRAM part is active (serving R/W) + ramulator.incoming_requests_per_channel 951475.0 # Number of incoming requests to each DRAM channel + [0] 951475.0 # +ramulator.incoming_read_reqs_per_channel 914973.0 # Number of incoming read requests to each DRAM channel + [0] 914973.0 # + ramulator.physical_page_replacement 0 # The number of times that physical page replacement happens. + ramulator.maximum_bandwidth 19200000000 # The theoretical maximum bandwidth (Bps) + ramulator.in_queue_req_num_sum 570412716 # Sum of read/write queue length + ramulator.in_queue_read_req_num_sum 33479232 # Sum of read queue length + ramulator.in_queue_write_req_num_sum 536933484 # Sum of write queue length + ramulator.in_queue_req_num_avg 15.288103 # Average of read/write queue length per memory cycle + ramulator.in_queue_read_req_num_avg 0.897305 # Average of read queue length per memory cycle + ramulator.in_queue_write_req_num_avg 14.390799 # Average of write queue length per memory cycle + ramulator.record_read_requests 0.0 # record read requests for this core when it reaches request limit or to the end + [0] 0.0 # + ramulator.record_write_requests 0.0 # record write requests for this core when it reaches request limit or to the end + [0] 0.0 # diff --git a/labs/LAB5/runs/xalancbmk_s_base-sms1/run.err b/labs/LAB5/runs/xalancbmk_s_base-sms1/run.err new file mode 100644 index 00000000..e69de29b diff --git a/labs/LAB5/runs/xalancbmk_s_base-sms1/run.out b/labs/LAB5/runs/xalancbmk_s_base-sms1/run.out new file mode 100644 index 00000000..4797806a --- /dev/null +++ b/labs/LAB5/runs/xalancbmk_s_base-sms1/run.out @@ -0,0 +1,107 @@ +Scarab gitrev: 7ab9e17 +Scarab started at Sun Jun 11 08:08:38 2023 + +Initialized Ramulator. +** Heartbeat: 1% -- { 1000005 } -- 0.00 KIPS (333.33 KIPS) +** Heartbeat: 2% -- { 2000007 } -- 500.00 KIPS (400.00 KIPS) +** Heartbeat: 3% -- { 3000007 } -- 333.33 KIPS (375.00 KIPS) +** Heartbeat: 4% -- { 4000009 } -- 500.00 KIPS (400.00 KIPS) +** Heartbeat: 5% -- { 5000009 } -- 500.00 KIPS (416.67 KIPS) +** Heartbeat: 6% -- { 6000010 } -- 500.00 KIPS (428.57 KIPS) +** Heartbeat: 7% -- { 7000015 } -- 333.33 KIPS (411.77 KIPS) +** Heartbeat: 8% -- { 8000018 } -- 500.00 KIPS (421.05 KIPS) +** Heartbeat: 9% -- { 9000018 } -- 500.00 KIPS (428.57 KIPS) +** Heartbeat: 10% -- { 10000021 } -- 333.33 KIPS (416.67 KIPS) +** Heartbeat: 11% -- { 11000022 } -- 500.00 KIPS (423.08 KIPS) +** Heartbeat: 12% -- { 12000022 } -- 500.00 KIPS (428.57 KIPS) +** Heartbeat: 13% -- { 13000026 } -- 333.33 KIPS (419.36 KIPS) +** Heartbeat: 14% -- { 14000028 } -- 500.00 KIPS (424.24 KIPS) +** Heartbeat: 15% -- { 15000028 } -- 500.00 KIPS (428.57 KIPS) +** Heartbeat: 16% -- { 16000030 } -- 500.00 KIPS (432.43 KIPS) +** Heartbeat: 17% -- { 17000034 } -- 333.33 KIPS (425.00 KIPS) +** Heartbeat: 18% -- { 18000039 } -- 500.00 KIPS (428.57 KIPS) +** Heartbeat: 19% -- { 19000043 } -- 500.00 KIPS (431.82 KIPS) +** Heartbeat: 20% -- { 20000043 } -- 333.33 KIPS (425.53 KIPS) +** Heartbeat: 21% -- { 21000043 } -- 500.00 KIPS (428.57 KIPS) +** Heartbeat: 22% -- { 22000043 } -- 333.33 KIPS (423.08 KIPS) +** Heartbeat: 23% -- { 23000045 } -- 500.00 KIPS (425.93 KIPS) +** Heartbeat: 24% -- { 24000045 } -- 500.00 KIPS (428.57 KIPS) +** Heartbeat: 25% -- { 25000047 } -- 500.00 KIPS (431.04 KIPS) +** Heartbeat: 26% -- { 26000049 } -- 500.00 KIPS (433.33 KIPS) +** Heartbeat: 27% -- { 27000052 } -- 333.33 KIPS (428.57 KIPS) +** Heartbeat: 28% -- { 28000052 } -- 500.00 KIPS (430.77 KIPS) +** Heartbeat: 29% -- { 29000054 } -- 500.00 KIPS (432.84 KIPS) +** Heartbeat: 30% -- { 30000054 } -- 500.00 KIPS (434.78 KIPS) +** Heartbeat: 31% -- { 31000055 } -- 333.33 KIPS (430.56 KIPS) +** Heartbeat: 32% -- { 32000058 } -- 500.00 KIPS (432.43 KIPS) +** Heartbeat: 33% -- { 33000059 } -- 333.33 KIPS (428.57 KIPS) +** Heartbeat: 34% -- { 34000061 } -- 500.00 KIPS (430.38 KIPS) +** Heartbeat: 35% -- { 35000061 } -- 500.00 KIPS (432.10 KIPS) +** Heartbeat: 36% -- { 36000061 } -- 333.33 KIPS (428.57 KIPS) +** Heartbeat: 37% -- { 37000063 } -- 500.00 KIPS (430.23 KIPS) +** Heartbeat: 38% -- { 38000063 } -- 500.00 KIPS (431.82 KIPS) +** Heartbeat: 39% -- { 39000064 } -- 500.00 KIPS (433.33 KIPS) +** Heartbeat: 40% -- { 40000065 } -- 333.33 KIPS (430.11 KIPS) +** Heartbeat: 41% -- { 41000065 } -- 500.00 KIPS (431.58 KIPS) +** Heartbeat: 42% -- { 42000066 } -- 333.33 KIPS (428.57 KIPS) +** Heartbeat: 43% -- { 43000071 } -- 500.00 KIPS (430.00 KIPS) +** Heartbeat: 44% -- { 44000071 } -- 500.00 KIPS (431.37 KIPS) +** Heartbeat: 45% -- { 45000075 } -- 333.33 KIPS (428.57 KIPS) +** Heartbeat: 46% -- { 46000079 } -- 500.00 KIPS (429.91 KIPS) +** Heartbeat: 47% -- { 47000079 } -- 500.00 KIPS (431.19 KIPS) +** Heartbeat: 48% -- { 48000082 } -- 333.33 KIPS (428.57 KIPS) +** Heartbeat: 49% -- { 49000082 } -- 500.00 KIPS (429.83 KIPS) +** Heartbeat: 50% -- { 50000082 } -- 500.00 KIPS (431.04 KIPS) +** Heartbeat: 51% -- { 51000082 } -- 500.00 KIPS (432.20 KIPS) +** Heartbeat: 52% -- { 52000082 } -- 333.33 KIPS (429.75 KIPS) +** Heartbeat: 53% -- { 53000085 } -- 500.00 KIPS (430.89 KIPS) +** Heartbeat: 54% -- { 54000087 } -- 500.00 KIPS (432.00 KIPS) +** Heartbeat: 55% -- { 55000090 } -- 333.33 KIPS (429.69 KIPS) +** Heartbeat: 56% -- { 56000090 } -- 500.00 KIPS (430.77 KIPS) +** Heartbeat: 57% -- { 57000095 } -- 500.00 KIPS (431.82 KIPS) +** Heartbeat: 58% -- { 58000099 } -- 333.33 KIPS (429.63 KIPS) +** Heartbeat: 59% -- { 59000099 } -- 500.00 KIPS (430.66 KIPS) +** Heartbeat: 60% -- { 60000100 } -- 500.00 KIPS (431.66 KIPS) +** Heartbeat: 61% -- { 61000104 } -- 333.33 KIPS (429.58 KIPS) +** Heartbeat: 62% -- { 62000108 } -- 500.00 KIPS (430.56 KIPS) +** Heartbeat: 63% -- { 63000109 } -- 500.00 KIPS (431.51 KIPS) +** Heartbeat: 64% -- { 64000114 } -- 500.00 KIPS (432.43 KIPS) +** Heartbeat: 65% -- { 65000117 } -- 333.33 KIPS (430.46 KIPS) +** Heartbeat: 66% -- { 66000117 } -- 500.00 KIPS (431.37 KIPS) +** Heartbeat: 67% -- { 67000121 } -- 333.33 KIPS (429.49 KIPS) +** Heartbeat: 68% -- { 68000121 } -- 500.00 KIPS (430.38 KIPS) +** Heartbeat: 69% -- { 69000125 } -- 500.00 KIPS (431.25 KIPS) +** Heartbeat: 70% -- { 70000129 } -- 333.33 KIPS (429.45 KIPS) +** Heartbeat: 71% -- { 71000129 } -- 500.00 KIPS (430.30 KIPS) +** Heartbeat: 72% -- { 72000132 } -- 500.00 KIPS (431.14 KIPS) +** Heartbeat: 73% -- { 73000132 } -- 333.33 KIPS (429.41 KIPS) +** Heartbeat: 74% -- { 74000133 } -- 500.00 KIPS (430.23 KIPS) +** Heartbeat: 75% -- { 75000135 } -- 500.00 KIPS (431.04 KIPS) +** Heartbeat: 76% -- { 76000140 } -- 500.00 KIPS (431.82 KIPS) +** Heartbeat: 77% -- { 77000144 } -- 333.33 KIPS (430.17 KIPS) +** Heartbeat: 78% -- { 78000147 } -- 500.00 KIPS (430.94 KIPS) +** Heartbeat: 79% -- { 79000150 } -- 500.00 KIPS (431.69 KIPS) +** Heartbeat: 80% -- { 80000153 } -- 333.33 KIPS (430.11 KIPS) +** Heartbeat: 81% -- { 81000156 } -- 500.00 KIPS (430.85 KIPS) +** Heartbeat: 82% -- { 82000158 } -- 500.00 KIPS (431.58 KIPS) +** Heartbeat: 83% -- { 83000161 } -- 500.00 KIPS (432.29 KIPS) +** Heartbeat: 84% -- { 84000165 } -- 333.33 KIPS (430.77 KIPS) +** Heartbeat: 85% -- { 85000165 } -- 500.00 KIPS (431.47 KIPS) +** Heartbeat: 86% -- { 86000165 } -- 500.00 KIPS (432.16 KIPS) +** Heartbeat: 87% -- { 87000169 } -- 333.33 KIPS (430.69 KIPS) +** Heartbeat: 88% -- { 88000173 } -- 500.00 KIPS (431.37 KIPS) +** Heartbeat: 89% -- { 89000177 } -- 500.00 KIPS (432.04 KIPS) +** Heartbeat: 90% -- { 90000178 } -- 500.00 KIPS (432.69 KIPS) +** Heartbeat: 91% -- { 91000178 } -- 333.33 KIPS (431.28 KIPS) +** Heartbeat: 92% -- { 92000179 } -- 500.00 KIPS (431.93 KIPS) +** Heartbeat: 93% -- { 93000179 } -- 333.33 KIPS (430.56 KIPS) +** Heartbeat: 94% -- { 94000181 } -- 500.00 KIPS (431.19 KIPS) +** Heartbeat: 95% -- { 95000182 } -- 500.00 KIPS (431.82 KIPS) +** Heartbeat: 96% -- { 96000185 } -- 500.00 KIPS (432.43 KIPS) +** Heartbeat: 97% -- { 97000188 } -- 333.33 KIPS (431.11 KIPS) +** Heartbeat: 98% -- { 98000191 } -- 500.00 KIPS (431.72 KIPS) +** Heartbeat: 99% -- { 99000192 } -- 500.00 KIPS (432.32 KIPS) +** Core 0 Finished: insts:100000000 cycles:99495664 time:31092395000000 -- 1.01 IPC (1.01 IPC) -- N/A KIPS (431.03 KIPS) +done +Scarab finished at Sun Jun 11 08:12:30 2023 + diff --git a/labs/LAB5/runs/xalancbmk_s_base-sms1/stream.stat.0.out b/labs/LAB5/runs/xalancbmk_s_base-sms1/stream.stat.0.out new file mode 100644 index 00000000..f4e19eb2 --- /dev/null +++ b/labs/LAB5/runs/xalancbmk_s_base-sms1/stream.stat.0.out @@ -0,0 +1,188 @@ +/* -*- Mode: c -*- */ +#################################################################################################### +Core 0 +#################################################################################################### +Cumulative: Cycles: 99495664 Instructions: 100000000 IPC: 1.00507 + +DCACHE_PREF_HIT 0 0 + +IFETCH_WB_FIRST_SCHEDULE 0 -nan% 0 -nan% +PREFETCH_LAST_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_PREF_SCHEDULE 0 -nan% 0 -nan% +DEMAND_PASS_LOW_OP_SCHEDULE 0 -nan% 0 -nan% +DEMAND_LAST_SCHEDULE 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +SEND_MISS_REQ_QUEUE 914973 914973 + +L1_DATA_EVICT 898905 898905 + +STREAM_BUFFER_REQ 0 0 + +PREF_SEND_TO_MEM_REQ 0 -nan% 0 -nan% +PREF_SEND_TO_MEM_REQ_FAIL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +HIT_TRAIN_STREAM 296720 30.457% 296720 30.457% +MISS_TRAIN_STREAM 677502 69.543% 677502 69.543% + 974222 100.000% 974222 100.000% + 0.70 0.63 0.70 0.63 + +STREAM_TRAIN_CREATE 243237 243237 + +MEM_REQ_MISS_HWP_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_SW_PREF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_IFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DFETCH_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DSTORE_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_DPRF_Q 0 -nan% 0 -nan% +MEM_REQ_MISS_WB_Q 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_BY_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_BY_DEMAND_WB 0 -nan% 0 -nan% +PREF_HIT_BY_PREF 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_HIT_DEMAND_IFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DFETCH 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DSTORE 0 -nan% 0 -nan% +PREF_HIT_DEMAND_IPREF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_DPRF 0 -nan% 0 -nan% +PREF_HIT_DEMAND_WB 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +PREF_L1_FILL 0 -nan% 0 -nan% +DEMAND_L1_FILL 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +TOUCH_L1_REPLACE 0 0.000% 0 0.000% +NO_TOUCH_L1_REPLACE 898905 100.000% 898905 100.000% + 898905 100.000% 898905 100.000% + 1.00 1.00 1.00 1.00 + +PREF_REQ_QUE_FULL 0 0 + +STREAM_REQ_QUEUE_HIT_BY_DEMAND 0 0 + +L2HIT_STREAM_PREF_REQ_QUE_FULL 0 0 + +L2HIT_HIT_TRAIN_STREAM 0 -nan% 0 -nan% +L2HIT_MISS_TRAIN_STREAM 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_TRAIN_CREATE 0 0 + +L2HIT_STREAM_BUFFER_REQ 0 0 + +L2HIT_STREAM_PREF_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_STREAM_PREF_DCACHE_INSERT 0 -nan% 0 -nan% +L2HIT_STREAM_L2_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_STREAM_DCACHE_PORT_FULL 0 0 + +L2HIT_STREAM_PREF_L1_PORT_FULL 0 0 + +L2HIT_TRAIN_HIT_DEMAND 0 -nan% 0 -nan% +L2HIT_TRAIN_MISS_REQ 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_TRAIN_FILTER_MISS 0 -nan% 0 -nan% +L2HIT_TRAIN_FILTER_HIT 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_PREF_REQ_DCACHE_HIT 0 -nan% 0 -nan% +L2HIT_PREF_REQ_DCACHE_MISS 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_L2SEND_Q_FULL 0 -nan% 0 -nan% +L2HIT_L2SEND_Q_ENTER 0 -nan% 0 -nan% + 0 -nan% 0 -nan% + -nan -nan -nan -nan + +L2HIT_MEM_REQ 0 0 + +REMOVE_REDUNDANT_STREAM_STAT 0 0 + +REPLACE_OLD_STREAM 243221 243221 + +REQ_SEND_QUEUE_STALL 0 0 + +STREAM_ENTER_RA 0 0 + +CORE_STREAM_LENGTH_0 42125 46.839% 42125 46.839% +CORE_STREAM_LENGTH_10 40821 45.389% 40821 45.389% +CORE_STREAM_LENGTH_20 4519 5.025% 4519 5.025% +CORE_STREAM_LENGTH_30 1040 1.156% 1040 1.156% +CORE_STREAM_LENGTH_40 512 0.569% 512 0.569% +CORE_STREAM_LENGTH_50 338 0.376% 338 0.376% +CORE_STREAM_LENGTH_60 232 0.258% 232 0.258% +CORE_STREAM_LENGTH_70 144 0.160% 144 0.160% +CORE_STREAM_LENGTH_80 77 0.086% 77 0.086% +CORE_STREAM_LENGTH_90 37 0.041% 37 0.041% +CORE_STREAM_LENGTH_100_P 91 0.101% 91 0.101% + 89936 100.000% 89936 100.000% + 0.68 0.79 0.68 0.79 + +CORE_CUM_STREAM_LENGTH_0 244125 23.320% 244125 23.320% +CORE_CUM_STREAM_LENGTH_10 567219 54.183% 567219 54.183% +CORE_CUM_STREAM_LENGTH_20 102163 9.759% 102163 9.759% +CORE_CUM_STREAM_LENGTH_30 34857 3.330% 34857 3.330% +CORE_CUM_STREAM_LENGTH_40 22797 2.178% 22797 2.178% +CORE_CUM_STREAM_LENGTH_50 18358 1.754% 18358 1.754% +CORE_CUM_STREAM_LENGTH_60 14981 1.431% 14981 1.431% +CORE_CUM_STREAM_LENGTH_70 10758 1.028% 10758 1.028% +CORE_CUM_STREAM_LENGTH_80 6369 0.608% 6369 0.608% +CORE_CUM_STREAM_LENGTH_90 3476 0.332% 3476 0.332% +CORE_CUM_STREAM_LENGTH_100_P 21751 2.078% 21751 2.078% + 1046854 100.000% 1046854 100.000% + 1.46 1.79 1.46 1.79 + +CORE_STREAM_TRAIN_HITS_0 76154 84.676% 76154 84.676% +CORE_STREAM_TRAIN_HITS_10 12005 13.348% 12005 13.348% +CORE_STREAM_TRAIN_HITS_20 1109 1.233% 1109 1.233% +CORE_STREAM_TRAIN_HITS_30 353 0.393% 353 0.393% +CORE_STREAM_TRAIN_HITS_40 148 0.165% 148 0.165% +CORE_STREAM_TRAIN_HITS_50 48 0.053% 48 0.053% +CORE_STREAM_TRAIN_HITS_60 32 0.036% 32 0.036% +CORE_STREAM_TRAIN_HITS_70 18 0.020% 18 0.020% +CORE_STREAM_TRAIN_HITS_80 7 0.008% 7 0.008% +CORE_STREAM_TRAIN_HITS_90 6 0.007% 6 0.007% +CORE_STREAM_TRAIN_HITS_100_P 56 0.062% 56 0.062% + 89936 100.000% 89936 100.000% + 0.19 0.54 0.19 0.54 + +CORE_CUM_STREAM_TRAIN_HITS_0 442688 67.435% 442688 67.435% +CORE_CUM_STREAM_TRAIN_HITS_10 144996 22.087% 144996 22.087% +CORE_CUM_STREAM_TRAIN_HITS_20 25961 3.955% 25961 3.955% +CORE_CUM_STREAM_TRAIN_HITS_30 11837 1.803% 11837 1.803% +CORE_CUM_STREAM_TRAIN_HITS_40 6356 0.968% 6356 0.968% +CORE_CUM_STREAM_TRAIN_HITS_50 2573 0.392% 2573 0.392% +CORE_CUM_STREAM_TRAIN_HITS_60 2038 0.310% 2038 0.310% +CORE_CUM_STREAM_TRAIN_HITS_70 1331 0.203% 1331 0.203% +CORE_CUM_STREAM_TRAIN_HITS_80 601 0.092% 601 0.092% +CORE_CUM_STREAM_TRAIN_HITS_90 566 0.086% 566 0.086% +CORE_CUM_STREAM_TRAIN_HITS_100_P 17517 2.668% 17517 2.668% + 656464 100.000% 656464 100.000% + 0.73 1.71 0.73 1.71 + +CORE_STREAM_TRAIN_CREATE 243237 243237 + + + diff --git a/labs/LAB5/scarab_run.sh b/labs/LAB5/scarab_run.sh index 72d450c2..6cb7796a 100755 --- a/labs/LAB5/scarab_run.sh +++ b/labs/LAB5/scarab_run.sh @@ -4,16 +4,16 @@ set -eEuxo pipefail . vars.env TRACE_NAME=$1 -VICTIM_CACHE_SIZE=$2 +SMS_ON=$2 TRACE_DIR=$(find "${ALL_TRACES_DIR}" -type d -iname "*${TRACE_NAME}*.dir") TRACE_FILE=$(find "${TRACE_DIR}" -type f -iname "*${TRACE_NAME}*.trace*") TRACE_RAW_DIR=${TRACE_DIR}/raw -RUN_DIR="$(pwd)/runs/${TRACE_NAME}-${VICTIM_CACHE_SIZE}" +RUN_DIR="$(pwd)/runs/${TRACE_NAME}-sms${SMS_ON}" EXTRA_ARGS="" -EXTRA_ARGS="${EXTRA_ARGS} --victim_cache_size=${VICTIM_CACHE_SIZE}" EXTRA_ARGS="${EXTRA_ARGS} --fetch_off_path_ops=0" EXTRA_ARGS="${EXTRA_ARGS} --inst_limit=100000000" # 100M +EXTRA_ARGS="${EXTRA_ARGS} --pref_sms_on=${SMS_ON}" START_DIR=$(pwd) mkdir -p "${RUN_DIR}"