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Update RISC-V tests #1823

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Update RISC-V tests #1823

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f3550b7
update: RISC-V tests files
matthiasgoergens Aug 18, 2024
9f9dab9
Merge branch 'main' into github/actions/update-riscv-tests
matthiasgoergens Sep 26, 2024
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2 changes: 1 addition & 1 deletion riscv-testdata/testdata/.testdata_generated_from_this_commit
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Original file line number Diff line number Diff line change
@@ -1 +1 @@
68c70f52115267097bc1381f3e85a18df15bbad4
e2cdf460d248925b43b9085a3470102ce8a0a83b
12 changes: 6 additions & 6 deletions riscv-testdata/testdata/rv64mi/illegal.S
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Original file line number Diff line number Diff line change
Expand Up @@ -72,19 +72,19 @@ msip:
beqz t2, bare_s_1
csrc sstatus, t0

# Make sure SFENCE.VMA and sptbr don't trap when TVM=0.
# Make sure SFENCE.VMA and satp don't trap when TVM=0.
sfence.vma
csrr t0, sptbr
csrr t0, satp
bad5:
.word 0
j fail

bad6:
# Make sure SFENCE.VMA and sptbr do trap when TVM=1.
# Make sure SFENCE.VMA and satp do trap when TVM=1.
sfence.vma
j fail
bad7:
csrr t0, sptbr
csrr t0, satp
j fail

test_tsr:
Expand Down Expand Up @@ -120,7 +120,7 @@ bare_s_2:
j fail

# And access to satp should not trap
csrr t0, sptbr
csrr t0, satp
bare_s_3:
.word 0
j fail
Expand Down Expand Up @@ -156,7 +156,7 @@ synchronous_exception:
csrr t0, mepc

# Make sure mtval contains either 0 or the instruction word.
csrr t2, mbadaddr
csrr t2, mtval
beqz t2, 1f
lhu t1, 0(t0)
xor t2, t2, t1
Expand Down
2 changes: 1 addition & 1 deletion riscv-testdata/testdata/rv64mi/ma_addr.S
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Expand Up @@ -103,7 +103,7 @@ mtvec_handler:
j fail
1:

csrr t0, mbadaddr
csrr t0, mtval
beqz t0, 1f
bne t0, t1, fail

Expand Down
2 changes: 1 addition & 1 deletion riscv-testdata/testdata/rv64si/dirty.S
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Expand Up @@ -22,7 +22,7 @@ RVTEST_CODE_BEGIN
la a1, page_table_1
srl a1, a1, RISCV_PGSHIFT
or a1, a1, a0
csrw sptbr, a1
csrw satp, a1
sfence.vma

# Set up MPRV with MPP=S, so loads and stores use S-mode
Expand Down
2 changes: 1 addition & 1 deletion riscv-testdata/testdata/rv64si/icache-alias.S
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Expand Up @@ -48,7 +48,7 @@ RVTEST_CODE_BEGIN
la a1, page_table_1
srl a1, a1, RISCV_PGSHIFT
or a1, a1, a0
csrw sptbr, a1
csrw satp, a1
sfence.vma

# Enter supervisor mode and make sure correct page is accessed
Expand Down
6 changes: 3 additions & 3 deletions riscv-testdata/testdata/rv64si/ma_fetch.S
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Expand Up @@ -17,7 +17,7 @@ RVTEST_CODE_BEGIN
#define sscratch mscratch
#define sstatus mstatus
#define scause mcause
#define sbadaddr mbadaddr
#define stval mtval
#define sepc mepc
#define sret mret
#define stvec_handler mtvec_handler
Expand Down Expand Up @@ -205,8 +205,8 @@ stvec_handler:
addi a1, a1, 4
bne t0, a1, fail

# verify that badaddr == 0 or badaddr == t0+2.
csrr a0, sbadaddr
# verify that tval == 0 or tval == t0+2.
csrr a0, stval
beqz a0, 1f
addi a0, a0, -2
bne a0, t0, fail
Expand Down